1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services_types.h" 28 #include "dc.h" 29 #include "dc/dc_dmub_srv.h" 30 #include "dc/dc_edid_parser.h" 31 #include "dc/dc_stat.h" 32 #include "dc/dc_state.h" 33 #include "dc/dc_stream.h" 34 #include "dc/inc/core_types.h" 35 #include "link_enc_cfg.h" 36 #include "link/protocols/link_dpcd.h" 37 #include "link_service_types.h" 38 #include "link/protocols/link_dp_capability.h" 39 #include "link/protocols/link_ddc.h" 40 41 #include "amdgpu.h" 42 #include "amdgpu_display.h" 43 #include "amdgpu_dm.h" 44 #include "amdgpu_dm_connector.h" 45 #include "amdgpu_dm_plane.h" 46 #include "amdgpu_dm_crtc.h" 47 #include "amdgpu_dm_wb.h" 48 #include "amdgpu_dm_mst_types.h" 49 #if defined(CONFIG_DEBUG_FS) 50 #include "amdgpu_dm_debugfs.h" 51 #endif 52 #include "amdgpu_dm_backlight.h" 53 #include "amdgpu_dm_audio.h" 54 #include "amdgpu_dm_irq.h" 55 #include "amdgpu_dm_psr.h" 56 #include "dm_helpers.h" 57 58 #include <drm/drm_atomic.h> 59 #include <drm/drm_atomic_uapi.h> 60 #include <drm/drm_atomic_helper.h> 61 #include <drm/drm_edid.h> 62 #include <drm/drm_eld.h> 63 #include <drm/drm_fixed.h> 64 #include <drm/drm_mode.h> 65 #include <drm/drm_probe_helper.h> 66 #include <drm/drm_utils.h> 67 #include <drm/display/drm_dp_mst_helper.h> 68 #include <drm/display/drm_hdmi_helper.h> 69 #include <drm/drm_privacy_screen_consumer.h> 70 #include <drm/display/drm_hdcp_helper.h> 71 72 #include <linux/backlight.h> 73 74 #include <media/cec-notifier.h> 75 76 #include "modules/inc/mod_freesync.h" 77 #include "modules/inc/mod_power.h" 78 79 #include "amdgpu_dm_trace.h" 80 81 /* Encoder functions */ 82 83 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 84 { 85 drm_encoder_cleanup(encoder); 86 kfree(encoder); 87 } 88 89 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 90 .destroy = amdgpu_dm_encoder_destroy, 91 }; 92 93 STATIC_IFN_KUNIT void dm_encoder_helper_disable(struct drm_encoder *encoder) 94 { 95 } 96 EXPORT_IF_KUNIT(dm_encoder_helper_disable); 97 98 STATIC_IFN_KUNIT int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 99 struct drm_crtc_state *crtc_state, 100 struct drm_connector_state *conn_state) 101 { 102 struct drm_atomic_commit *state = crtc_state->state; 103 struct drm_connector *connector = conn_state->connector; 104 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 105 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 106 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 107 struct drm_dp_mst_topology_mgr *mst_mgr; 108 struct drm_dp_mst_port *mst_port; 109 struct drm_dp_mst_topology_state *mst_state; 110 enum dc_color_depth color_depth; 111 int clock, bpp = 0; 112 bool is_y420 = false; 113 114 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 115 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 116 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 117 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 118 enum drm_mode_status result; 119 120 result = drm_crtc_helper_mode_valid_fixed(encoder->crtc, adjusted_mode, native_mode); 121 if (result != MODE_OK && dm_new_connector_state->scaling == RMX_OFF) { 122 drm_dbg_driver(encoder->dev, 123 "mode %dx%d@%dHz is not native, enabling scaling\n", 124 adjusted_mode->hdisplay, adjusted_mode->vdisplay, 125 drm_mode_vrefresh(adjusted_mode)); 126 dm_new_connector_state->scaling = RMX_ASPECT; 127 } 128 return 0; 129 } 130 131 if (!aconnector->mst_output_port) 132 return 0; 133 134 mst_port = aconnector->mst_output_port; 135 mst_mgr = &aconnector->mst_root->mst_mgr; 136 137 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 138 return 0; 139 140 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 141 if (IS_ERR(mst_state)) 142 return PTR_ERR(mst_state); 143 144 mst_state->pbn_div.full = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); 145 146 if (!state->duplicated) { 147 int max_bpc = conn_state->max_requested_bpc; 148 149 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 150 aconnector->force_yuv_pixel_format == PIXEL_ENCODING_YCBCR420; 151 color_depth = amdgpu_dm_convert_color_depth_from_display_info(connector, 152 is_y420, 153 max_bpc); 154 bpp = amdgpu_dm_convert_dc_color_depth_into_bpc(color_depth) * 3; 155 clock = adjusted_mode->clock; 156 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); 157 } 158 159 dm_new_connector_state->vcpi_slots = 160 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 161 dm_new_connector_state->pbn); 162 if (dm_new_connector_state->vcpi_slots < 0) { 163 drm_dbg_atomic(connector->dev, "failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 164 return dm_new_connector_state->vcpi_slots; 165 } 166 return 0; 167 } 168 EXPORT_IF_KUNIT(dm_encoder_helper_atomic_check); 169 170 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 171 .disable = dm_encoder_helper_disable, 172 .atomic_check = dm_encoder_helper_atomic_check 173 }; 174 175 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 176 { 177 switch (adev->mode_info.num_crtc) { 178 case 1: 179 return 0x1; 180 case 2: 181 return 0x3; 182 case 3: 183 return 0x7; 184 case 4: 185 return 0xf; 186 case 5: 187 return 0x1f; 188 case 6: 189 default: 190 return 0x3f; 191 } 192 } 193 EXPORT_IF_KUNIT(amdgpu_dm_get_encoder_crtc_mask); 194 195 int amdgpu_dm_encoder_init(struct drm_device *dev, 196 struct amdgpu_encoder *aencoder, 197 uint32_t link_index) 198 { 199 struct amdgpu_device *adev = drm_to_adev(dev); 200 201 int res = drm_encoder_init(dev, 202 &aencoder->base, 203 &amdgpu_dm_encoder_funcs, 204 DRM_MODE_ENCODER_TMDS, 205 NULL); 206 207 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 208 209 if (!res) 210 aencoder->encoder_id = link_index; 211 else 212 aencoder->encoder_id = -1; 213 214 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 215 216 return res; 217 } 218 219 STATIC_IFN_KUNIT enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 220 { 221 switch (link->dpcd_caps.dongle_type) { 222 case DISPLAY_DONGLE_NONE: 223 return DRM_MODE_SUBCONNECTOR_Native; 224 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 225 return DRM_MODE_SUBCONNECTOR_VGA; 226 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 227 case DISPLAY_DONGLE_DP_DVI_DONGLE: 228 return DRM_MODE_SUBCONNECTOR_DVID; 229 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 230 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 231 return DRM_MODE_SUBCONNECTOR_HDMIA; 232 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 233 default: 234 return DRM_MODE_SUBCONNECTOR_Unknown; 235 } 236 } 237 EXPORT_IF_KUNIT(get_subconnector_type); 238 239 STATIC_IFN_KUNIT void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 240 { 241 struct dc_link *link = aconnector->dc_link; 242 struct drm_connector *connector = &aconnector->base; 243 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 244 245 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 246 return; 247 248 if (aconnector->dc_sink) 249 subconnector = get_subconnector_type(link); 250 251 drm_object_property_set_value(&connector->base, 252 connector->dev->mode_config.dp_subconnector_property, 253 subconnector); 254 } 255 EXPORT_IF_KUNIT(update_subconnector_property); 256 257 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 258 259 STATIC_IFN_KUNIT void amdgpu_dm_fbc_init(struct drm_connector *connector) 260 { 261 struct amdgpu_device *adev = drm_to_adev(connector->dev); 262 struct dm_compressor_info *compressor = &adev->dm.compressor; 263 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 264 struct drm_display_mode *mode; 265 unsigned long max_size = 0; 266 267 if (adev->dm.dc->fbc_compressor == NULL) 268 return; 269 270 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 271 return; 272 273 if (compressor->bo_ptr) 274 return; 275 276 277 list_for_each_entry(mode, &connector->modes, head) { 278 if (max_size < (unsigned long) mode->htotal * mode->vtotal) 279 max_size = (unsigned long) mode->htotal * mode->vtotal; 280 } 281 282 if (max_size) { 283 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 284 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 285 &compressor->gpu_addr, &compressor->cpu_addr); 286 287 if (r) 288 drm_err(adev_to_drm(adev), "DM: Failed to initialize FBC\n"); 289 else { 290 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 291 drm_info(adev_to_drm(adev), "DM: FBC alloc %lu\n", max_size*4); 292 } 293 294 } 295 296 } 297 EXPORT_IF_KUNIT(amdgpu_dm_fbc_init); 298 299 300 int amdgpu_dm_detect_mst_link_for_all_connectors(struct drm_device *dev) 301 { 302 struct amdgpu_dm_connector *aconnector; 303 struct drm_connector *connector; 304 struct drm_connector_list_iter iter; 305 int ret = 0; 306 307 drm_connector_list_iter_begin(dev, &iter); 308 drm_for_each_connector_iter(connector, &iter) { 309 310 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 311 continue; 312 313 aconnector = to_amdgpu_dm_connector(connector); 314 if (aconnector->dc_link->type == dc_connection_mst_branch && 315 aconnector->mst_mgr.aux) { 316 drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n", 317 aconnector, 318 aconnector->base.base.id); 319 320 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 321 if (ret < 0) { 322 drm_err(dev, "DM_MST: Failed to start MST\n"); 323 aconnector->dc_link->type = 324 dc_connection_single; 325 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 326 aconnector->dc_link); 327 break; 328 } 329 } 330 } 331 drm_connector_list_iter_end(&iter); 332 333 return ret; 334 } 335 EXPORT_IF_KUNIT(amdgpu_dm_detect_mst_link_for_all_connectors); 336 337 STATIC_IFN_KUNIT void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector) 338 { 339 struct cec_notifier *n = aconnector->notifier; 340 341 if (!n) 342 return; 343 344 cec_notifier_phys_addr_invalidate(n); 345 } 346 EXPORT_IF_KUNIT(hdmi_cec_unset_edid); 347 348 void amdgpu_dm_hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector) 349 { 350 struct drm_connector *connector = &aconnector->base; 351 struct cec_notifier *n = aconnector->notifier; 352 353 if (!n) 354 return; 355 356 cec_notifier_set_phys_addr(n, 357 connector->display_info.source_physical_address); 358 } 359 EXPORT_IF_KUNIT(amdgpu_dm_hdmi_cec_set_edid); 360 361 void amdgpu_dm_s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend) 362 { 363 struct amdgpu_dm_connector *aconnector; 364 struct drm_connector *connector; 365 struct drm_connector_list_iter conn_iter; 366 367 drm_connector_list_iter_begin(ddev, &conn_iter); 368 drm_for_each_connector_iter(connector, &conn_iter) { 369 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 370 continue; 371 372 aconnector = to_amdgpu_dm_connector(connector); 373 if (suspend) 374 hdmi_cec_unset_edid(aconnector); 375 else 376 amdgpu_dm_hdmi_cec_set_edid(aconnector); 377 } 378 drm_connector_list_iter_end(&conn_iter); 379 } 380 EXPORT_IF_KUNIT(amdgpu_dm_s3_handle_hdmi_cec); 381 382 383 struct drm_connector * 384 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_commit *state, 385 struct drm_crtc *crtc) 386 { 387 u32 i; 388 struct drm_connector_state *new_con_state; 389 struct drm_connector *connector; 390 struct drm_crtc *crtc_from_state; 391 392 for_each_new_connector_in_state(state, connector, new_con_state, i) { 393 crtc_from_state = new_con_state->crtc; 394 395 if (crtc_from_state == crtc) 396 return connector; 397 } 398 399 return NULL; 400 } 401 EXPORT_IF_KUNIT(amdgpu_dm_find_first_crtc_matching_connector); 402 403 STATIC_IFN_KUNIT void amdgpu_dm_set_panel_type(struct amdgpu_dm_connector *aconnector) 404 { 405 struct drm_connector *connector = &aconnector->base; 406 struct drm_display_info *display_info = &connector->display_info; 407 struct dc_link *link = aconnector->dc_link; 408 struct amdgpu_device *adev; 409 enum dc_panel_type panel_type = PANEL_TYPE_NONE; 410 411 adev = drm_to_adev(connector->dev); 412 413 switch (display_info->amd_vsdb.panel_type) { 414 case AMD_VSDB_PANEL_TYPE_OLED: 415 panel_type = PANEL_TYPE_OLED; 416 break; 417 case AMD_VSDB_PANEL_TYPE_MINILED: 418 panel_type = PANEL_TYPE_MINILED; 419 break; 420 } 421 422 /* If VSDB didn't determine panel type, check DPCD ext caps */ 423 if (panel_type == PANEL_TYPE_NONE) { 424 if (link->dpcd_sink_ext_caps.bits.miniled == 1) 425 panel_type = PANEL_TYPE_MINILED; 426 if (link->dpcd_sink_ext_caps.bits.oled == 1) 427 panel_type = PANEL_TYPE_OLED; 428 } 429 430 /* If VSDB and DPCD didn't determine panel type, check DID */ 431 if (panel_type == PANEL_TYPE_NONE) { 432 if (display_info->panel_type == DRM_MODE_PANEL_TYPE_LCD) 433 panel_type = PANEL_TYPE_LCD; 434 else if (display_info->panel_type == DRM_MODE_PANEL_TYPE_OLED) 435 panel_type = PANEL_TYPE_OLED; 436 } 437 438 if (panel_type == PANEL_TYPE_NONE) { 439 struct drm_amd_vsdb_info *vsdb = &display_info->amd_vsdb; 440 u32 lum1_max = vsdb->luminance_range1.max_luminance; 441 u32 lum2_max = vsdb->luminance_range2.max_luminance; 442 443 if (vsdb->version && link->local_sink && 444 link->local_sink->edid_caps.manufacturer_id == 445 DDC_MANUFACTURERNAME_SAMSUNG && 446 lum1_max >= ((lum2_max * 3) / 2)) 447 panel_type = PANEL_TYPE_MINILED; 448 } 449 450 if (panel_type != PANEL_TYPE_NONE) 451 link->panel_type = panel_type; 452 else 453 link->panel_type = PANEL_TYPE_LCD; 454 455 if (link->panel_type == PANEL_TYPE_OLED) 456 drm_object_property_set_value(&connector->base, 457 adev_to_drm(adev)->mode_config.panel_type_property, 458 DRM_MODE_PANEL_TYPE_OLED); 459 else if (link->panel_type == PANEL_TYPE_LCD) 460 drm_object_property_set_value(&connector->base, 461 adev_to_drm(adev)->mode_config.panel_type_property, 462 DRM_MODE_PANEL_TYPE_LCD); 463 else 464 drm_object_property_set_value(&connector->base, 465 adev_to_drm(adev)->mode_config.panel_type_property, 466 DRM_MODE_PANEL_TYPE_UNKNOWN); 467 468 drm_dbg_kms(aconnector->base.dev, "Panel type: %d\n", link->panel_type); 469 } 470 EXPORT_IF_KUNIT(amdgpu_dm_set_panel_type); 471 472 STATIC_IFN_KUNIT void amdgpu_dm_update_cacp_caps(struct amdgpu_dm_connector *aconnector) 473 { 474 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 475 struct dc_link *link = aconnector->dc_link; 476 477 link->panel_config.cacp.cacp_supported = true; 478 479 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 1, 4) || 480 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 1, 6)) { 481 link->panel_config.cacp.cacp_supported = false; 482 return; 483 } 484 485 if (link->connector_signal != SIGNAL_TYPE_EDP && 486 link->connector_signal != SIGNAL_TYPE_LVDS) { 487 link->panel_config.cacp.cacp_supported = false; 488 return; 489 } 490 491 if (link->panel_type == PANEL_TYPE_LCD) 492 link->panel_config.cacp.cacp_supported = false; 493 494 drm_dbg_kms(aconnector->base.dev, "cacp_supported: %d\n", 495 link->panel_config.cacp.cacp_supported); 496 } 497 EXPORT_IF_KUNIT(amdgpu_dm_update_cacp_caps); 498 499 DEFINE_FREE(sink_release, struct dc_sink *, if (_T) dc_sink_release(_T)) 500 501 void amdgpu_dm_update_connector_after_detect( 502 struct amdgpu_dm_connector *aconnector) 503 { 504 struct drm_connector *connector = &aconnector->base; 505 struct dc_sink *sink __free(sink_release) = NULL; 506 struct drm_device *dev = connector->dev; 507 struct amdgpu_device *adev = drm_to_adev(dev); 508 int inst; 509 510 /* MST handled by drm_mst framework */ 511 if (aconnector->mst_mgr.mst_state) 512 return; 513 514 sink = aconnector->dc_link->local_sink; 515 if (sink) 516 dc_sink_retain(sink); 517 518 /* 519 * Edid mgmt connector gets first update only in mode_valid hook and then 520 * the connector sink is set to either fake or physical sink depends on link status. 521 * Skip if already done during boot. 522 */ 523 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 524 && aconnector->dc_em_sink) { 525 526 /* 527 * For S3 resume with headless use eml_sink to fake stream 528 * because on resume connector->sink is set to NULL 529 */ 530 guard(mutex)(&dev->mode_config.mutex); 531 532 if (sink) { 533 if (aconnector->dc_sink) { 534 amdgpu_dm_update_freesync_caps(connector, NULL, true); 535 /* 536 * retain and release below are used to 537 * bump up refcount for sink because the link doesn't point 538 * to it anymore after disconnect, so on next crtc to connector 539 * reshuffle by UMD we will get into unwanted dc_sink release 540 */ 541 dc_sink_release(aconnector->dc_sink); 542 } 543 aconnector->dc_sink = sink; 544 dc_sink_retain(aconnector->dc_sink); 545 amdgpu_dm_update_freesync_caps(connector, 546 aconnector->drm_edid, true); 547 } else { 548 amdgpu_dm_update_freesync_caps(connector, NULL, true); 549 if (!aconnector->dc_sink) { 550 aconnector->dc_sink = aconnector->dc_em_sink; 551 dc_sink_retain(aconnector->dc_sink); 552 } 553 } 554 555 return; 556 } 557 558 /* 559 * TODO: temporary guard to look for proper fix 560 * if this sink is MST sink, we should not do anything 561 */ 562 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 563 return; 564 565 if (aconnector->dc_sink == sink) { 566 /* 567 * We got a DP short pulse (Link Loss, DP CTS, etc...). 568 * Do nothing!! 569 */ 570 drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n", 571 aconnector->connector_id); 572 return; 573 } 574 575 drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 576 aconnector->connector_id, aconnector->dc_sink, sink); 577 578 /* When polling, DRM has already locked the mutex for us. */ 579 if (!drm_kms_helper_is_poll_worker()) 580 mutex_lock(&dev->mode_config.mutex); 581 582 /* 583 * 1. Update status of the drm connector 584 * 2. Send an event and let userspace tell us what to do 585 */ 586 if (sink) { 587 /* 588 * TODO: check if we still need the S3 mode update workaround. 589 * If yes, put it here. 590 */ 591 if (aconnector->dc_sink) { 592 amdgpu_dm_update_freesync_caps(connector, NULL, true); 593 dc_sink_release(aconnector->dc_sink); 594 } 595 596 aconnector->dc_sink = sink; 597 dc_sink_retain(aconnector->dc_sink); 598 drm_edid_free(aconnector->drm_edid); 599 aconnector->drm_edid = NULL; 600 if (sink->dc_edid.length == 0) { 601 hdmi_cec_unset_edid(aconnector); 602 if (aconnector->dc_link->aux_mode) 603 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 604 } else { 605 const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; 606 607 aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); 608 drm_edid_connector_update(connector, aconnector->drm_edid); 609 610 amdgpu_dm_hdmi_cec_set_edid(aconnector); 611 if (aconnector->dc_link->aux_mode) 612 drm_dp_cec_attach(&aconnector->dm_dp_aux.aux, 613 connector->display_info.source_physical_address); 614 } 615 616 if (!aconnector->timing_requested) { 617 aconnector->timing_requested = 618 kzalloc_obj(struct dc_crtc_timing); 619 if (!aconnector->timing_requested) 620 drm_err(dev, 621 "failed to create aconnector->requested_timing\n"); 622 } 623 624 amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid, true); 625 amdgpu_dm_update_connector_ext_caps(aconnector); 626 amdgpu_dm_set_panel_type(aconnector); 627 amdgpu_dm_update_cacp_caps(aconnector); 628 629 if (aconnector->hdmi_comp_auto) { 630 if (sink->sink_signal != SIGNAL_TYPE_HDMI_FRL) 631 sink->sink_signal = SIGNAL_TYPE_HDMI_FRL; 632 } 633 } else { 634 hdmi_cec_unset_edid(aconnector); 635 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 636 amdgpu_dm_update_freesync_caps(connector, NULL, true); 637 aconnector->num_modes = 0; 638 dc_sink_release(aconnector->dc_sink); 639 aconnector->dc_sink = NULL; 640 drm_edid_free(aconnector->drm_edid); 641 aconnector->drm_edid = NULL; 642 kfree(aconnector->timing_requested); 643 aconnector->timing_requested = NULL; 644 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 645 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 646 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 647 648 mutex_lock(&adev->dm.audio_lock); 649 inst = aconnector->audio_inst; 650 aconnector->audio_inst = -1; 651 mutex_unlock(&adev->dm.audio_lock); 652 if (inst != -1) 653 amdgpu_dm_audio_eld_notify(adev, inst); 654 } 655 656 update_subconnector_property(aconnector); 657 658 /* When polling, the mutex will be unlocked for us by DRM. */ 659 if (!drm_kms_helper_is_poll_worker()) 660 mutex_unlock(&dev->mode_config.mutex); 661 } 662 EXPORT_IF_KUNIT(amdgpu_dm_update_connector_after_detect); 663 664 enum dc_color_depth 665 amdgpu_dm_convert_color_depth_from_display_info(const struct drm_connector *connector, 666 bool is_y420, int requested_bpc) 667 { 668 u8 bpc; 669 670 if (is_y420) { 671 bpc = 8; 672 673 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 674 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 675 bpc = 16; 676 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 677 bpc = 12; 678 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 679 bpc = 10; 680 } else { 681 bpc = (uint8_t)connector->display_info.bpc; 682 /* Assume 8 bpc by default if no bpc is specified. */ 683 bpc = bpc ? bpc : 8; 684 } 685 686 if (requested_bpc > 0) { 687 /* 688 * Cap display bpc based on the user requested value. 689 * 690 * The value for state->max_bpc may not correctly updated 691 * depending on when the connector gets added to the state 692 * or if this was called outside of atomic check, so it 693 * can't be used directly. 694 */ 695 bpc = min_t(u8, bpc, requested_bpc); 696 697 /* Round down to the nearest even number. */ 698 bpc = bpc - (bpc & 1); 699 } 700 701 switch (bpc) { 702 case 0: 703 /* 704 * Temporary Work around, DRM doesn't parse color depth for 705 * EDID revision before 1.4 706 * TODO: Fix edid parsing 707 */ 708 return COLOR_DEPTH_888; 709 case 6: 710 return COLOR_DEPTH_666; 711 case 8: 712 return COLOR_DEPTH_888; 713 case 10: 714 return COLOR_DEPTH_101010; 715 case 12: 716 return COLOR_DEPTH_121212; 717 case 14: 718 return COLOR_DEPTH_141414; 719 case 16: 720 return COLOR_DEPTH_161616; 721 default: 722 return COLOR_DEPTH_UNDEFINED; 723 } 724 } 725 EXPORT_IF_KUNIT(amdgpu_dm_convert_color_depth_from_display_info); 726 727 STATIC_IFN_KUNIT enum dc_aspect_ratio 728 get_aspect_ratio(const struct drm_display_mode *mode_in) 729 { 730 /* 1-1 mapping, since both enums follow the HDMI spec. */ 731 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 732 } 733 EXPORT_IF_KUNIT(get_aspect_ratio); 734 735 /* 736 * CTA-861 5.1: RGB video formats default to limited range except 640x480 (VIC 1). 737 * With Broadcast RGB left at Automatic follow that default, as i915 does. 738 */ 739 static bool rgb_output_is_limited_range(const struct dc_crtc_timing *dc_crtc_timing, 740 const struct drm_connector_state *connector_state) 741 { 742 switch (connector_state->hdmi.broadcast_rgb) { 743 case DRM_HDMI_BROADCAST_RGB_FULL: 744 return false; 745 case DRM_HDMI_BROADCAST_RGB_LIMITED: 746 return true; 747 default: 748 return connector_state->connector->display_info.is_hdmi && 749 dc_crtc_timing->vic > 1; 750 } 751 } 752 753 enum dc_color_space 754 amdgpu_dm_get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 755 const struct drm_connector_state *connector_state) 756 { 757 enum dc_color_space color_space = COLOR_SPACE_SRGB; 758 759 switch (connector_state->colorspace) { 760 case DRM_MODE_COLORIMETRY_BT601_YCC: 761 if (dc_crtc_timing->flags.Y_ONLY) 762 color_space = COLOR_SPACE_YCBCR601_LIMITED; 763 else 764 color_space = COLOR_SPACE_YCBCR601; 765 break; 766 case DRM_MODE_COLORIMETRY_BT709_YCC: 767 if (dc_crtc_timing->flags.Y_ONLY) 768 color_space = COLOR_SPACE_YCBCR709_LIMITED; 769 else 770 color_space = COLOR_SPACE_YCBCR709; 771 break; 772 case DRM_MODE_COLORIMETRY_OPRGB: 773 color_space = COLOR_SPACE_ADOBERGB; 774 break; 775 case DRM_MODE_COLORIMETRY_BT2020_RGB: 776 case DRM_MODE_COLORIMETRY_BT2020_YCC: 777 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 778 if (rgb_output_is_limited_range(dc_crtc_timing, connector_state)) 779 color_space = COLOR_SPACE_2020_RGB_LIMITEDRANGE; 780 else 781 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 782 } else { 783 color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 784 } 785 break; 786 case DRM_MODE_COLORIMETRY_DEFAULT: /* ITU601 */ 787 default: 788 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 789 color_space = COLOR_SPACE_SRGB; 790 if (rgb_output_is_limited_range(dc_crtc_timing, connector_state)) 791 color_space = COLOR_SPACE_SRGB_LIMITED; 792 /* 793 * 27030khz is the separation point between HDTV and SDTV 794 * according to HDMI spec, we use YCbCr709 and YCbCr601 795 * respectively 796 */ 797 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 798 if (dc_crtc_timing->flags.Y_ONLY) 799 color_space = 800 COLOR_SPACE_YCBCR709_LIMITED; 801 else 802 color_space = COLOR_SPACE_YCBCR709; 803 } else { 804 if (dc_crtc_timing->flags.Y_ONLY) 805 color_space = 806 COLOR_SPACE_YCBCR601_LIMITED; 807 else 808 color_space = COLOR_SPACE_YCBCR601; 809 } 810 break; 811 } 812 813 return color_space; 814 } 815 EXPORT_IF_KUNIT(amdgpu_dm_get_output_color_space); 816 817 STATIC_IFN_KUNIT enum display_content_type 818 get_output_content_type(const struct drm_connector_state *connector_state) 819 { 820 switch (connector_state->content_type) { 821 default: 822 case DRM_MODE_CONTENT_TYPE_NO_DATA: 823 return DISPLAY_CONTENT_TYPE_NO_DATA; 824 case DRM_MODE_CONTENT_TYPE_GRAPHICS: 825 return DISPLAY_CONTENT_TYPE_GRAPHICS; 826 case DRM_MODE_CONTENT_TYPE_PHOTO: 827 return DISPLAY_CONTENT_TYPE_PHOTO; 828 case DRM_MODE_CONTENT_TYPE_CINEMA: 829 return DISPLAY_CONTENT_TYPE_CINEMA; 830 case DRM_MODE_CONTENT_TYPE_GAME: 831 return DISPLAY_CONTENT_TYPE_GAME; 832 } 833 } 834 EXPORT_IF_KUNIT(get_output_content_type); 835 836 STATIC_IFN_KUNIT bool adjust_colour_depth_from_display_info( 837 struct dc_crtc_timing *timing_out, 838 const struct drm_display_info *info) 839 { 840 enum dc_color_depth depth = timing_out->display_color_depth; 841 int normalized_clk; 842 843 do { 844 normalized_clk = timing_out->pix_clk_100hz / 10; 845 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 846 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 847 normalized_clk /= 2; 848 /* Adjusting pix clock following on HDMI spec based on colour depth */ 849 switch (depth) { 850 case COLOR_DEPTH_888: 851 break; 852 case COLOR_DEPTH_101010: 853 normalized_clk = (normalized_clk * 30) / 24; 854 break; 855 case COLOR_DEPTH_121212: 856 normalized_clk = (normalized_clk * 36) / 24; 857 break; 858 case COLOR_DEPTH_161616: 859 normalized_clk = (normalized_clk * 48) / 24; 860 break; 861 default: 862 /* The above depths are the only ones valid for HDMI. */ 863 return false; 864 } 865 if (normalized_clk <= info->max_tmds_clock) { 866 timing_out->display_color_depth = depth; 867 return true; 868 } 869 } while (--depth > COLOR_DEPTH_666); 870 return false; 871 } 872 EXPORT_IF_KUNIT(adjust_colour_depth_from_display_info); 873 874 STATIC_IFN_KUNIT void fill_stream_properties_from_drm_display_mode( 875 struct dc_stream_state *stream, 876 const struct drm_display_mode *mode_in, 877 const struct drm_connector *connector, 878 const struct drm_connector_state *connector_state, 879 const struct dc_stream_state *old_stream, 880 int requested_bpc, 881 enum dc_pixel_encoding requested_encoding, 882 bool is_hdmi_ep) 883 { 884 struct dc_crtc_timing *timing_out = &stream->timing; 885 const struct drm_display_info *info = &connector->display_info; 886 struct amdgpu_dm_connector *aconnector = NULL; 887 struct hdmi_vendor_infoframe hv_frame; 888 struct hdmi_avi_infoframe avi_frame; 889 ssize_t err; 890 891 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 892 aconnector = to_amdgpu_dm_connector(connector); 893 894 memset(&hv_frame, 0, sizeof(hv_frame)); 895 memset(&avi_frame, 0, sizeof(avi_frame)); 896 897 timing_out->h_border_left = 0; 898 timing_out->h_border_right = 0; 899 timing_out->v_border_top = 0; 900 timing_out->v_border_bottom = 0; 901 902 /* 903 * The pixel encoding to use is decided entirely by the caller (see 904 * amdgpu_dm_create_validate_stream_for_sink()), which enumerates only 905 * the encodings the sink actually advertises. This helper must not 906 * second-guess that choice; it simply applies it. 907 */ 908 timing_out->pixel_encoding = requested_encoding; 909 910 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 911 timing_out->display_color_depth = amdgpu_dm_convert_color_depth_from_display_info( 912 connector, 913 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 914 requested_bpc); 915 timing_out->scan_type = SCANNING_TYPE_NODATA; 916 timing_out->hdmi_vic = 0; 917 918 if (old_stream) { 919 timing_out->vic = old_stream->timing.vic; 920 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 921 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 922 } else { 923 timing_out->vic = drm_match_cea_mode(mode_in); 924 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 925 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 926 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 927 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 928 } 929 930 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 931 stream->signal == SIGNAL_TYPE_HDMI_FRL) { 932 err = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, 933 (struct drm_connector *)connector, 934 mode_in); 935 if (err < 0) 936 drm_warn_once(connector->dev, "Failed to setup avi infoframe on connector %s: %zd\n", 937 connector->name, err); 938 timing_out->vic = avi_frame.video_code; 939 err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, 940 (struct drm_connector *)connector, 941 mode_in); 942 if (err < 0) 943 drm_warn_once(connector->dev, "Failed to setup vendor infoframe on connector %s: %zd\n", 944 connector->name, err); 945 timing_out->hdmi_vic = hv_frame.vic; 946 } 947 948 if (aconnector && amdgpu_dm_is_freesync_video_mode(mode_in, aconnector)) { 949 timing_out->h_addressable = mode_in->hdisplay; 950 timing_out->h_total = mode_in->htotal; 951 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 952 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 953 timing_out->v_total = mode_in->vtotal; 954 timing_out->v_addressable = mode_in->vdisplay; 955 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 956 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 957 timing_out->pix_clk_100hz = mode_in->clock * 10; 958 } else { 959 timing_out->h_addressable = mode_in->crtc_hdisplay; 960 timing_out->h_total = mode_in->crtc_htotal; 961 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 962 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 963 timing_out->v_total = mode_in->crtc_vtotal; 964 timing_out->v_addressable = mode_in->crtc_vdisplay; 965 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 966 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 967 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 968 } 969 970 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 971 972 stream->out_transfer_func.type = TF_TYPE_PREDEFINED; 973 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; 974 975 /* Clamp the HDMI colour depth to what the sink's max TMDS clock 976 * allows. The pixel encoding is fixed by the caller and must not be 977 * changed here: the caller already enumerates YCbCr420 as its own 978 * candidate, so silently switching to it would hide an enumeration 979 * bug and produce a stream the caller never asked to validate. 980 */ 981 if (is_hdmi_ep) 982 adjust_colour_depth_from_display_info(timing_out, info); 983 984 stream->output_color_space = amdgpu_dm_get_output_color_space(timing_out, connector_state); 985 stream->content_type = get_output_content_type(connector_state); 986 } 987 EXPORT_IF_KUNIT(fill_stream_properties_from_drm_display_mode); 988 989 STATIC_IFN_KUNIT void 990 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 991 struct drm_display_mode *dst_mode) 992 { 993 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 994 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 995 dst_mode->crtc_clock = src_mode->crtc_clock; 996 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 997 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 998 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 999 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 1000 dst_mode->crtc_htotal = src_mode->crtc_htotal; 1001 dst_mode->crtc_hskew = src_mode->crtc_hskew; 1002 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 1003 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 1004 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 1005 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 1006 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 1007 } 1008 EXPORT_IF_KUNIT(copy_crtc_timing_for_drm_display_mode); 1009 1010 STATIC_IFN_KUNIT void 1011 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 1012 const struct drm_display_mode *native_mode, 1013 bool scale_enabled) 1014 { 1015 /* Inserted modes copy the native sync; a sink mode with equal totals may not */ 1016 if (scale_enabled || ( 1017 native_mode->clock == drm_mode->clock && 1018 native_mode->htotal == drm_mode->htotal && 1019 native_mode->vtotal == drm_mode->vtotal && 1020 native_mode->hsync_start == drm_mode->hsync_start && 1021 native_mode->hsync_end == drm_mode->hsync_end && 1022 native_mode->vsync_start == drm_mode->vsync_start && 1023 native_mode->vsync_end == drm_mode->vsync_end)) { 1024 if (native_mode->crtc_clock) 1025 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 1026 } else { 1027 /* no scaling nor amdgpu inserted, no need to patch */ 1028 } 1029 } 1030 EXPORT_IF_KUNIT(decide_crtc_timing_for_drm_display_mode); 1031 1032 static struct dc_sink * 1033 create_fake_sink(struct drm_device *dev, struct dc_link *link) 1034 { 1035 struct dc_sink_init_data sink_init_data = { 0 }; 1036 struct dc_sink *sink = NULL; 1037 1038 sink_init_data.link = link; 1039 sink_init_data.sink_signal = link->connector_signal; 1040 1041 sink = dc_sink_create(&sink_init_data); 1042 if (!sink) { 1043 drm_err(dev, "Failed to create sink!\n"); 1044 return NULL; 1045 } 1046 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 1047 1048 return sink; 1049 } 1050 1051 /** 1052 * DOC: FreeSync Video 1053 * 1054 * When a userspace application wants to play a video, the content follows a 1055 * standard format definition that usually specifies the FPS for that format. 1056 * The below list illustrates some video format and the expected FPS, 1057 * respectively: 1058 * 1059 * - TV/NTSC (23.976 FPS) 1060 * - Cinema (24 FPS) 1061 * - TV/PAL (25 FPS) 1062 * - TV/NTSC (29.97 FPS) 1063 * - TV/NTSC (30 FPS) 1064 * - Cinema HFR (48 FPS) 1065 * - TV/PAL (50 FPS) 1066 * - Commonly used (60 FPS) 1067 * - Multiples of 24 (48,72,96 FPS) 1068 * 1069 * The list of standards video format is not huge and can be added to the 1070 * connector modeset list beforehand. With that, userspace can leverage 1071 * FreeSync to extends the front porch in order to attain the target refresh 1072 * rate. Such a switch will happen seamlessly, without screen blanking or 1073 * reprogramming of the output in any other way. If the userspace requests a 1074 * modesetting change compatible with FreeSync modes that only differ in the 1075 * refresh rate, DC will skip the full update and avoid blink during the 1076 * transition. For example, the video player can change the modesetting from 1077 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 1078 * causing any display blink. This same concept can be applied to a mode 1079 * setting change. 1080 */ 1081 struct drm_display_mode * 1082 amdgpu_dm_get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 1083 bool use_probed_modes) 1084 { 1085 struct drm_display_mode *m, *m_pref = NULL; 1086 u16 current_refresh, highest_refresh; 1087 struct list_head *list_head = use_probed_modes ? 1088 &aconnector->base.probed_modes : 1089 &aconnector->base.modes; 1090 1091 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1092 return NULL; 1093 1094 if (aconnector->freesync_vid_base.clock != 0) 1095 return &aconnector->freesync_vid_base; 1096 1097 /* Find the preferred mode */ 1098 list_for_each_entry(m, list_head, head) { 1099 if (m->type & DRM_MODE_TYPE_PREFERRED) { 1100 m_pref = m; 1101 break; 1102 } 1103 } 1104 1105 if (!m_pref) { 1106 /* Probably an EDID with no preferred mode. Fallback to first entry */ 1107 m_pref = list_first_entry_or_null( 1108 &aconnector->base.modes, struct drm_display_mode, head); 1109 if (!m_pref) { 1110 drm_dbg_driver(aconnector->base.dev, "No preferred mode found in EDID\n"); 1111 return NULL; 1112 } 1113 } 1114 1115 highest_refresh = drm_mode_vrefresh(m_pref); 1116 1117 /* 1118 * Find the mode with highest refresh rate with same resolution. 1119 * For some monitors, preferred mode is not the mode with highest 1120 * supported refresh rate. 1121 */ 1122 list_for_each_entry(m, list_head, head) { 1123 current_refresh = drm_mode_vrefresh(m); 1124 1125 if (m->hdisplay == m_pref->hdisplay && 1126 m->vdisplay == m_pref->vdisplay && 1127 highest_refresh < current_refresh) { 1128 highest_refresh = current_refresh; 1129 m_pref = m; 1130 } 1131 } 1132 1133 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 1134 return m_pref; 1135 } 1136 EXPORT_IF_KUNIT(amdgpu_dm_get_highest_refresh_rate_mode); 1137 1138 bool amdgpu_dm_is_freesync_video_mode(const struct drm_display_mode *mode, 1139 struct amdgpu_dm_connector *aconnector) 1140 { 1141 struct drm_display_mode *high_mode; 1142 int timing_diff; 1143 1144 high_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 1145 if (!high_mode || !mode) 1146 return false; 1147 1148 timing_diff = high_mode->vtotal - mode->vtotal; 1149 1150 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 1151 high_mode->hdisplay != mode->hdisplay || 1152 high_mode->vdisplay != mode->vdisplay || 1153 high_mode->hsync_start != mode->hsync_start || 1154 high_mode->hsync_end != mode->hsync_end || 1155 high_mode->htotal != mode->htotal || 1156 high_mode->hskew != mode->hskew || 1157 high_mode->vscan != mode->vscan || 1158 high_mode->vsync_start - mode->vsync_start != timing_diff || 1159 high_mode->vsync_end - mode->vsync_end != timing_diff) 1160 return false; 1161 else 1162 return true; 1163 } 1164 EXPORT_IF_KUNIT(amdgpu_dm_is_freesync_video_mode); 1165 1166 #if defined(CONFIG_DRM_AMD_DC_FP) 1167 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 1168 struct dc_sink *sink, struct dc_stream_state *stream, 1169 struct dsc_dec_dpcd_caps *dsc_caps) 1170 { 1171 stream->timing.flags.DSC = 0; 1172 dsc_caps->is_dsc_supported = false; 1173 1174 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 1175 sink->sink_signal == SIGNAL_TYPE_EDP)) { 1176 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) 1177 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 1178 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 1179 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 1180 dsc_caps); 1181 else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 1182 if (aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT && 1183 !aconnector->dsc_settings.dsc_force_disable_passthrough && 1184 aconnector->dc_link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0 && 1185 sink->edid_caps.frl_dsc_support && 1186 sink->edid_caps.max_frl_rate > 0 && 1187 sink->edid_caps.frl_dsc_max_frl_rate > 0) 1188 dc_dsc_parse_dsc_edid(aconnector->dc_link->ctx->dc, &sink->edid_caps, dsc_caps); 1189 else 1190 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 1191 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 1192 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 1193 dsc_caps); 1194 } 1195 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_HDMI_FRL) { 1196 if (sink->edid_caps.frl_dsc_support && 1197 sink->edid_caps.max_frl_rate > 0 && 1198 sink->edid_caps.frl_dsc_max_frl_rate > 0) 1199 dc_dsc_parse_dsc_edid(aconnector->dc_link->ctx->dc, &sink->edid_caps, dsc_caps); 1200 } 1201 } 1202 1203 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 1204 struct dc_sink *sink, struct dc_stream_state *stream, 1205 struct dsc_dec_dpcd_caps *dsc_caps, 1206 uint32_t max_dsc_target_bpp_limit_override) 1207 { 1208 const struct dc_link_settings *verified_link_cap = NULL; 1209 u32 link_bw_in_kbps; 1210 u32 edp_min_bpp_x16, edp_max_bpp_x16; 1211 struct dc *dc = sink->ctx->dc; 1212 struct dc_dsc_bw_range bw_range = {0}; 1213 struct dc_dsc_config dsc_cfg = {0}; 1214 struct dc_dsc_config_options dsc_options = {0}; 1215 1216 dc_dsc_get_default_config_option(dc, &dsc_options); 1217 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 1218 1219 verified_link_cap = dc_link_get_link_cap(stream->link); 1220 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 1221 edp_min_bpp_x16 = 8 * 16; 1222 edp_max_bpp_x16 = 8 * 16; 1223 1224 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 1225 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 1226 1227 if (edp_max_bpp_x16 < edp_min_bpp_x16) 1228 edp_min_bpp_x16 = edp_max_bpp_x16; 1229 1230 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 1231 dc->debug.dsc_min_slice_height_override, 1232 edp_min_bpp_x16, edp_max_bpp_x16, 1233 dsc_caps, 1234 &stream->timing, 1235 dc_link_get_highest_encoding_format(aconnector->dc_link), 1236 &bw_range)) { 1237 1238 if (bw_range.max_kbps < link_bw_in_kbps) { 1239 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 1240 dsc_caps, 1241 &dsc_options, 1242 0, 1243 &stream->timing, 1244 dc_link_get_highest_encoding_format(aconnector->dc_link), 1245 &dsc_cfg)) { 1246 stream->timing.dsc_cfg = dsc_cfg; 1247 stream->timing.flags.DSC = 1; 1248 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 1249 } 1250 return; 1251 } 1252 } 1253 1254 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 1255 dsc_caps, 1256 &dsc_options, 1257 link_bw_in_kbps, 1258 &stream->timing, 1259 dc_link_get_highest_encoding_format(aconnector->dc_link), 1260 &dsc_cfg)) { 1261 stream->timing.dsc_cfg = dsc_cfg; 1262 stream->timing.flags.DSC = 1; 1263 } 1264 } 1265 1266 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 1267 struct dc_sink *sink, struct dc_stream_state *stream, 1268 struct dsc_dec_dpcd_caps *dsc_caps) 1269 { 1270 struct drm_connector *drm_connector = &aconnector->base; 1271 u32 link_bandwidth_kbps; 1272 struct dc *dc = sink->ctx->dc; 1273 const struct dc_hdmi_frl_link_settings *frl_verified_link_cap = NULL; 1274 u32 converter_bw_in_kbps; 1275 u32 sink_bw_in_kbps; 1276 u32 dsc_sink_bw_in_kbps; 1277 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 1278 u32 dsc_max_supported_bw_in_kbps; 1279 u32 max_dsc_target_bpp_limit_override = 1280 drm_connector->display_info.max_dsc_bpp; 1281 struct dc_dsc_config_options dsc_options = {0}; 1282 1283 if (!aconnector->dc_link) 1284 return; 1285 1286 dc_dsc_get_default_config_option(dc, &dsc_options); 1287 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 1288 1289 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 1290 dc_link_get_link_cap(aconnector->dc_link)); 1291 1292 /* Set DSC policy according to dsc_clock_en */ 1293 dc_dsc_policy_set_enable_dsc_when_not_needed( 1294 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 1295 1296 if (sink->sink_signal == SIGNAL_TYPE_EDP && 1297 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 1298 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 1299 1300 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 1301 1302 } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 1303 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 1304 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 1305 dsc_caps, 1306 &dsc_options, 1307 link_bandwidth_kbps, 1308 &stream->timing, 1309 dc_link_get_highest_encoding_format(aconnector->dc_link), 1310 &stream->timing.dsc_cfg)) { 1311 stream->timing.flags.DSC = 1; 1312 drm_dbg_driver(drm_connector->dev, "%s: SST_DSC [%s] DSC is selected from SST RX\n", 1313 __func__, drm_connector->name); 1314 } 1315 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 1316 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 1317 dc_link_get_highest_encoding_format(aconnector->dc_link)); 1318 converter_bw_in_kbps = aconnector->dc_link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps; 1319 sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(dc, sink->edid_caps.max_frl_rate); 1320 dsc_sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(dc, sink->edid_caps.frl_dsc_max_frl_rate); 1321 1322 if (dsc_caps->is_frl) { 1323 max_supported_bw_in_kbps = min(link_bandwidth_kbps, converter_bw_in_kbps); 1324 max_supported_bw_in_kbps = min(max_supported_bw_in_kbps, sink_bw_in_kbps); 1325 dsc_max_supported_bw_in_kbps = min(max_supported_bw_in_kbps, dsc_sink_bw_in_kbps); 1326 } else { 1327 max_supported_bw_in_kbps = link_bandwidth_kbps; 1328 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 1329 } 1330 1331 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 1332 max_supported_bw_in_kbps > 0 && 1333 dsc_max_supported_bw_in_kbps > 0) 1334 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 1335 dsc_caps, 1336 &dsc_options, 1337 dsc_max_supported_bw_in_kbps, 1338 &stream->timing, 1339 dc_link_get_highest_encoding_format(aconnector->dc_link), 1340 &stream->timing.dsc_cfg)) { 1341 stream->timing.flags.DSC = 1; 1342 drm_dbg_driver(drm_connector->dev, "%s: SST_DSC [%s] DSC is selected from %s\n", 1343 __func__, drm_connector->name, 1344 (dsc_caps->is_frl == 1) ? "HDMI FRL RX" : "DP-HDMI PCON"); 1345 } 1346 } 1347 } else if (sink->sink_signal == SIGNAL_TYPE_HDMI_FRL) { 1348 struct dc_dsc_policy dsc_policy = {0}; 1349 1350 frl_verified_link_cap = dc_link_get_frl_link_cap(stream->link); 1351 if (frl_verified_link_cap->frl_link_rate != HDMI_FRL_LINK_RATE_DISABLE && 1352 aconnector->dc_link->frl_flags.force_frl_dsc) { 1353 dc_dsc_policy_set_enable_dsc_when_not_needed(true); 1354 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link)); 1355 } 1356 1357 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, DC_LINK_ENCODING_HDMI_FRL); 1358 link_bandwidth_kbps = dc_link_frl_bandwidth_kbps(stream->link, frl_verified_link_cap->frl_link_rate); 1359 dsc_sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(dc, sink->edid_caps.frl_dsc_max_frl_rate); 1360 1361 if ((timing_bw_in_kbps > link_bandwidth_kbps && dsc_sink_bw_in_kbps > 0) || 1362 (dsc_policy.enable_dsc_when_not_needed || dsc_options.force_dsc_when_not_needed)) { 1363 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 1364 dsc_caps, 1365 &dsc_options, 1366 dsc_sink_bw_in_kbps, 1367 &stream->timing, 1368 dc_link_get_highest_encoding_format(aconnector->dc_link), 1369 &stream->timing.dsc_cfg)) { 1370 stream->timing.flags.DSC = 1; 1371 drm_dbg_driver(drm_connector->dev, "%s: HDMI_FRL_DSC [%s] DSC is selected from HDMI FRL RX\n", 1372 __func__, drm_connector->name); 1373 } 1374 } 1375 } 1376 1377 /* Overwrite the stream flag if DSC is enabled through debugfs */ 1378 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 1379 stream->timing.flags.DSC = 1; 1380 1381 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 1382 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 1383 1384 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 1385 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 1386 1387 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 1388 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 1389 } 1390 #endif 1391 1392 void amdgpu_dm_update_stream_scaling_settings(struct drm_device *dev, 1393 const struct drm_display_mode *mode, 1394 const struct dm_connector_state *dm_state, 1395 struct dc_stream_state *stream) 1396 { 1397 enum amdgpu_rmx_type rmx_type; 1398 1399 struct rect src = { 0 }; /* viewport in composition space*/ 1400 struct rect dst = { 0 }; /* stream addressable area */ 1401 1402 /* no mode. nothing to be done */ 1403 if (!mode) 1404 return; 1405 1406 /* Full screen scaling by default */ 1407 src.width = mode->hdisplay; 1408 src.height = mode->vdisplay; 1409 dst.width = stream->timing.h_addressable; 1410 dst.height = stream->timing.v_addressable; 1411 1412 if (dm_state) { 1413 rmx_type = dm_state->scaling; 1414 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 1415 if (src.width * dst.height < 1416 src.height * dst.width) { 1417 /* height needs less upscaling/more downscaling */ 1418 dst.width = src.width * 1419 dst.height / src.height; 1420 } else { 1421 /* width needs less upscaling/more downscaling */ 1422 dst.height = src.height * 1423 dst.width / src.width; 1424 } 1425 } else if (rmx_type == RMX_CENTER) { 1426 dst = src; 1427 } 1428 1429 dst.x = (stream->timing.h_addressable - dst.width) / 2; 1430 dst.y = (stream->timing.v_addressable - dst.height) / 2; 1431 1432 if (dm_state->underscan_enable) { 1433 dst.x += dm_state->underscan_hborder / 2; 1434 dst.y += dm_state->underscan_vborder / 2; 1435 dst.width -= dm_state->underscan_hborder; 1436 dst.height -= dm_state->underscan_vborder; 1437 } 1438 } 1439 1440 stream->src = src; 1441 stream->dst = dst; 1442 1443 drm_dbg_kms(dev, "Destination Rectangle x:%d y:%d width:%d height:%d\n", 1444 dst.x, dst.y, dst.width, dst.height); 1445 1446 } 1447 EXPORT_IF_KUNIT(amdgpu_dm_update_stream_scaling_settings); 1448 1449 STATIC_IFN_KUNIT struct dc_stream_state * 1450 create_stream_for_sink(struct drm_connector *connector, 1451 const struct drm_display_mode *drm_mode, 1452 const struct dm_connector_state *dm_state, 1453 const struct dc_stream_state *old_stream, 1454 int requested_bpc, 1455 enum dc_pixel_encoding requested_encoding, 1456 bool is_hdmi_ep) 1457 { 1458 struct drm_device *dev = connector->dev; 1459 struct amdgpu_dm_connector *aconnector = NULL; 1460 struct drm_display_mode *preferred_mode = NULL; 1461 const struct drm_connector_state *con_state = &dm_state->base; 1462 struct dc_stream_state *stream = NULL; 1463 struct drm_display_mode mode; 1464 struct drm_display_mode saved_mode; 1465 struct drm_display_mode *freesync_mode = NULL; 1466 bool native_mode_found = false; 1467 bool recalculate_timing = false; 1468 bool scale = dm_state->scaling != RMX_OFF; 1469 int mode_refresh; 1470 int preferred_refresh = 0; 1471 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 1472 #if defined(CONFIG_DRM_AMD_DC_FP) 1473 struct dsc_dec_dpcd_caps dsc_caps = {0}; 1474 #endif 1475 struct dc_link *link = NULL; 1476 struct dc_sink *sink = NULL; 1477 1478 drm_mode_init(&mode, drm_mode); 1479 memset(&saved_mode, 0, sizeof(saved_mode)); 1480 1481 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { 1482 aconnector = NULL; 1483 aconnector = to_amdgpu_dm_connector(connector); 1484 link = aconnector->dc_link; 1485 } else { 1486 struct drm_writeback_connector *wbcon = NULL; 1487 struct amdgpu_dm_wb_connector *dm_wbcon = NULL; 1488 1489 wbcon = drm_connector_to_writeback(connector); 1490 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon); 1491 link = dm_wbcon->link; 1492 } 1493 1494 if (!aconnector || !aconnector->dc_sink) { 1495 sink = create_fake_sink(dev, link); 1496 if (!sink) 1497 return stream; 1498 1499 } else { 1500 sink = aconnector->dc_sink; 1501 dc_sink_retain(sink); 1502 } 1503 1504 stream = dc_create_stream_for_sink(sink); 1505 1506 if (stream == NULL) { 1507 drm_err(dev, "Failed to create stream for sink!\n"); 1508 goto finish; 1509 } 1510 1511 /* We leave this NULL for writeback connectors */ 1512 stream->dm_stream_context = aconnector; 1513 1514 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 1515 connector->display_info.hdmi.scdc.scrambling.low_rates; 1516 1517 list_for_each_entry(preferred_mode, &connector->modes, head) { 1518 /* Search for preferred mode */ 1519 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 1520 native_mode_found = true; 1521 break; 1522 } 1523 } 1524 if (!native_mode_found) 1525 preferred_mode = list_first_entry_or_null( 1526 &connector->modes, 1527 struct drm_display_mode, 1528 head); 1529 1530 mode_refresh = drm_mode_vrefresh(&mode); 1531 1532 if (preferred_mode == NULL) { 1533 /* 1534 * This may not be an error, the use case is when we have no 1535 * usermode calls to reset and set mode upon hotplug. In this 1536 * case, we call set mode ourselves to restore the previous mode 1537 * and the modelist may not be filled in time. 1538 */ 1539 drm_dbg_driver(dev, "No preferred mode found\n"); 1540 } else if (aconnector) { 1541 recalculate_timing = amdgpu_freesync_vid_mode && 1542 amdgpu_dm_is_freesync_video_mode(&mode, aconnector); 1543 if (recalculate_timing) { 1544 freesync_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 1545 drm_mode_copy(&saved_mode, &mode); 1546 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; 1547 drm_mode_copy(&mode, freesync_mode); 1548 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; 1549 } else { 1550 decide_crtc_timing_for_drm_display_mode( 1551 &mode, preferred_mode, scale); 1552 1553 preferred_refresh = drm_mode_vrefresh(preferred_mode); 1554 } 1555 } 1556 1557 if (recalculate_timing) 1558 drm_mode_set_crtcinfo(&saved_mode, 0); 1559 1560 /* 1561 * If scaling is enabled and refresh rate didn't change 1562 * we copy the vic and polarities of the old timings 1563 */ 1564 if (!scale || mode_refresh != preferred_refresh) 1565 fill_stream_properties_from_drm_display_mode( 1566 stream, &mode, connector, con_state, NULL, 1567 requested_bpc, requested_encoding, is_hdmi_ep); 1568 else 1569 fill_stream_properties_from_drm_display_mode( 1570 stream, &mode, connector, con_state, old_stream, 1571 requested_bpc, requested_encoding, is_hdmi_ep); 1572 1573 /* The rest isn't needed for writeback connectors */ 1574 if (!aconnector) 1575 goto finish; 1576 1577 if (aconnector->timing_changed) { 1578 drm_dbg(aconnector->base.dev, 1579 "overriding timing for automated test, bpc %d, changing to %d\n", 1580 stream->timing.display_color_depth, 1581 aconnector->timing_requested->display_color_depth); 1582 stream->timing = *aconnector->timing_requested; 1583 } 1584 1585 #if defined(CONFIG_DRM_AMD_DC_FP) 1586 /* SST DSC determination policy */ 1587 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 1588 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 1589 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 1590 #endif 1591 1592 amdgpu_dm_update_stream_scaling_settings(dev, &mode, dm_state, stream); 1593 1594 amdgpu_dm_fill_audio_info( 1595 &stream->audio_info, 1596 connector, 1597 sink); 1598 1599 update_stream_signal(stream, sink); 1600 1601 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 1602 stream->signal == SIGNAL_TYPE_HDMI_FRL) 1603 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false); 1604 1605 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1606 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 1607 stream->signal == SIGNAL_TYPE_EDP) { 1608 const struct dc_edid_caps *edid_caps; 1609 unsigned int disable_colorimetry = 0; 1610 1611 if (aconnector->dc_sink) { 1612 edid_caps = &aconnector->dc_sink->edid_caps; 1613 disable_colorimetry = edid_caps->panel_patch.disable_colorimetry; 1614 } 1615 1616 /* 1617 * should decide stream support vsc sdp colorimetry capability 1618 * before building vsc info packet 1619 */ 1620 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && 1621 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED && 1622 !disable_colorimetry; 1623 1624 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) 1625 tf = TRANSFER_FUNC_GAMMA_22; 1626 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 1627 aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 1628 1629 } 1630 finish: 1631 dc_sink_release(sink); 1632 1633 return stream; 1634 } 1635 EXPORT_IF_KUNIT(create_stream_for_sink); 1636 1637 /** 1638 * amdgpu_dm_connector_poll - Poll a connector to see if it's connected to a display 1639 * @aconnector: DM connector to poll (owns @base drm_connector and @dc_link) 1640 * @force: if true, force polling even when DAC load detection was used 1641 * 1642 * Used for connectors that don't support HPD (hotplug detection) to 1643 * periodically check whether the connector is connected to a display. 1644 * 1645 * When connection was determined via DAC load detection, we avoid 1646 * re-running it on normal polls to prevent visible glitches, unless 1647 * @force is set. 1648 * 1649 * Return: The probed connector status (connected/disconnected/unknown). 1650 */ 1651 STATIC_IFN_KUNIT enum drm_connector_status 1652 amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force) 1653 { 1654 struct drm_connector *connector = &aconnector->base; 1655 struct drm_device *dev = connector->dev; 1656 struct amdgpu_device *adev = drm_to_adev(dev); 1657 struct dc_link *link = aconnector->dc_link; 1658 enum dc_connection_type conn_type = dc_connection_none; 1659 enum drm_connector_status status = connector_status_disconnected; 1660 1661 /* When we determined the connection using DAC load detection, 1662 * do NOT poll the connector do detect disconnect because 1663 * that would run DAC load detection again which can cause 1664 * visible visual glitches. 1665 * 1666 * Only allow to poll such a connector again when forcing. 1667 */ 1668 if (!force && link->local_sink && link->type == dc_connection_analog_load) 1669 return connector->status; 1670 1671 mutex_lock(&aconnector->hpd_lock); 1672 1673 if (dc_link_detect_connection_type(aconnector->dc_link, &conn_type) && 1674 conn_type != dc_connection_none) { 1675 mutex_lock(&adev->dm.dc_lock); 1676 1677 /* Only call full link detection when a sink isn't created yet, 1678 * ie. just when the display is plugged in, otherwise we risk flickering. 1679 */ 1680 if (link->local_sink || 1681 dc_link_detect(link, DETECT_REASON_HPD)) 1682 status = connector_status_connected; 1683 1684 mutex_unlock(&adev->dm.dc_lock); 1685 } 1686 1687 if (connector->status != status) { 1688 if (status == connector_status_disconnected) { 1689 if (link->local_sink) 1690 dc_sink_release(link->local_sink); 1691 1692 link->local_sink = NULL; 1693 link->dpcd_sink_count = 0; 1694 link->type = dc_connection_none; 1695 } 1696 1697 amdgpu_dm_update_connector_after_detect(aconnector); 1698 } 1699 1700 mutex_unlock(&aconnector->hpd_lock); 1701 return status; 1702 } 1703 EXPORT_IF_KUNIT(amdgpu_dm_connector_poll); 1704 1705 /* 1706 * Apple Studio Display exposes two SST DP links for a 2x1 tiled panel. 1707 * The primary tile advertises the full 5120x2880 mode (with DSC on the 1708 * bandwidth-sufficient link) while the secondary carries a per-tile 1709 * 2560x2880 timing on a insufficient bandwidth link. Hide the secondary 1710 * connector from userspace so compositors configure a single 5K stream 1711 * on the primary link only. 1712 */ 1713 static bool amdgpu_dm_hide_secondary_tile_from_userspace(struct drm_connector *connector) 1714 { 1715 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1716 1717 if (!aconnector->dc_sink) 1718 return false; 1719 1720 if (!aconnector->dc_sink->edid_caps.panel_patch.disable_second_tile) 1721 return false; 1722 1723 drm_edid_connector_update(connector, aconnector->drm_edid); 1724 1725 if (!connector->has_tile) 1726 return false; 1727 1728 if (!connector->tile_h_loc && !connector->tile_v_loc) 1729 return false; 1730 1731 drm_dbg_kms(connector->dev, 1732 "[CONNECTOR:%d:%s] hiding secondary Apple Studio Display tile from userspace\n", 1733 connector->base.id, connector->name); 1734 1735 return true; 1736 } 1737 1738 /** 1739 * amdgpu_dm_connector_detect() - Detect whether a DRM connector is connected to a display 1740 * 1741 * A connector is considered connected when it has a sink that is not NULL. 1742 * For connectors that support HPD (hotplug detection), the connection is 1743 * handled in the HPD interrupt. 1744 * For connectors that may not support HPD, such as analog connectors, 1745 * DRM will call this function repeatedly to poll them. 1746 * 1747 * Notes: 1748 * 1. This interface is NOT called in context of HPD irq. 1749 * 2. This interface *is called* in context of user-mode ioctl. Which 1750 * makes it a bad place for *any* MST-related activity. 1751 * 1752 * @connector: The DRM connector we are checking. We convert it to 1753 * amdgpu_dm_connector so we can read the DC link and state. 1754 * @force: If true, do a full detect again. This is used even when 1755 * a lighter check would normally be used to avoid flicker. 1756 * 1757 * Return: The connector status (connected, disconnected, or unknown). 1758 * 1759 */ 1760 STATIC_IFN_KUNIT enum drm_connector_status 1761 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 1762 { 1763 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1764 1765 update_subconnector_property(aconnector); 1766 1767 if (aconnector->base.force == DRM_FORCE_ON || 1768 aconnector->base.force == DRM_FORCE_ON_DIGITAL) 1769 return connector_status_connected; 1770 else if (aconnector->base.force == DRM_FORCE_OFF) 1771 return connector_status_disconnected; 1772 1773 /* Poll analog connectors and only when either 1774 * disconnected or connected to an analog display. 1775 */ 1776 if (drm_kms_helper_is_poll_worker() && 1777 dc_connector_supports_analog(aconnector->dc_link->link_id.id) && 1778 (!aconnector->dc_sink || aconnector->dc_sink->edid_caps.analog)) 1779 return amdgpu_dm_connector_poll(aconnector, force); 1780 1781 if (amdgpu_dm_hide_secondary_tile_from_userspace(connector)) 1782 return connector_status_disconnected; 1783 1784 return (aconnector->dc_sink ? connector_status_connected : 1785 connector_status_disconnected); 1786 } 1787 EXPORT_IF_KUNIT(amdgpu_dm_connector_detect); 1788 1789 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 1790 struct drm_connector_state *connector_state, 1791 struct drm_property *property, 1792 uint64_t val) 1793 { 1794 struct drm_device *dev = connector->dev; 1795 struct amdgpu_device *adev = drm_to_adev(dev); 1796 struct dm_connector_state *dm_old_state = 1797 to_dm_connector_state(connector->state); 1798 struct dm_connector_state *dm_new_state = 1799 to_dm_connector_state(connector_state); 1800 1801 int ret = -EINVAL; 1802 1803 if (property == dev->mode_config.scaling_mode_property) { 1804 enum amdgpu_rmx_type rmx_type; 1805 1806 switch (val) { 1807 case DRM_MODE_SCALE_CENTER: 1808 rmx_type = RMX_CENTER; 1809 break; 1810 case DRM_MODE_SCALE_ASPECT: 1811 rmx_type = RMX_ASPECT; 1812 break; 1813 case DRM_MODE_SCALE_FULLSCREEN: 1814 rmx_type = RMX_FULL; 1815 break; 1816 case DRM_MODE_SCALE_NONE: 1817 default: 1818 rmx_type = RMX_OFF; 1819 break; 1820 } 1821 1822 if (dm_old_state->scaling == rmx_type) 1823 return 0; 1824 1825 dm_new_state->scaling = rmx_type; 1826 ret = 0; 1827 } else if (property == adev->mode_info.underscan_hborder_property) { 1828 dm_new_state->underscan_hborder = val; 1829 ret = 0; 1830 } else if (property == adev->mode_info.underscan_vborder_property) { 1831 dm_new_state->underscan_vborder = val; 1832 ret = 0; 1833 } else if (property == adev->mode_info.underscan_property) { 1834 dm_new_state->underscan_enable = val; 1835 ret = 0; 1836 } else if (property == adev->mode_info.abm_level_property) { 1837 switch (val) { 1838 case ABM_SYSFS_CONTROL: 1839 dm_new_state->abm_sysfs_forbidden = false; 1840 break; 1841 case ABM_LEVEL_OFF: 1842 dm_new_state->abm_sysfs_forbidden = true; 1843 dm_new_state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 1844 break; 1845 default: 1846 dm_new_state->abm_sysfs_forbidden = true; 1847 dm_new_state->abm_level = val; 1848 } 1849 ret = 0; 1850 } 1851 1852 return ret; 1853 } 1854 EXPORT_IF_KUNIT(amdgpu_dm_connector_atomic_set_property); 1855 1856 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1857 const struct drm_connector_state *state, 1858 struct drm_property *property, 1859 uint64_t *val) 1860 { 1861 struct drm_device *dev = connector->dev; 1862 struct amdgpu_device *adev = drm_to_adev(dev); 1863 struct dm_connector_state *dm_state = 1864 to_dm_connector_state(state); 1865 int ret = -EINVAL; 1866 1867 if (property == dev->mode_config.scaling_mode_property) { 1868 switch (dm_state->scaling) { 1869 case RMX_CENTER: 1870 *val = DRM_MODE_SCALE_CENTER; 1871 break; 1872 case RMX_ASPECT: 1873 *val = DRM_MODE_SCALE_ASPECT; 1874 break; 1875 case RMX_FULL: 1876 *val = DRM_MODE_SCALE_FULLSCREEN; 1877 break; 1878 case RMX_OFF: 1879 default: 1880 *val = DRM_MODE_SCALE_NONE; 1881 break; 1882 } 1883 ret = 0; 1884 } else if (property == adev->mode_info.underscan_hborder_property) { 1885 *val = dm_state->underscan_hborder; 1886 ret = 0; 1887 } else if (property == adev->mode_info.underscan_vborder_property) { 1888 *val = dm_state->underscan_vborder; 1889 ret = 0; 1890 } else if (property == adev->mode_info.underscan_property) { 1891 *val = dm_state->underscan_enable; 1892 ret = 0; 1893 } else if (property == adev->mode_info.abm_level_property) { 1894 if (!dm_state->abm_sysfs_forbidden) 1895 *val = ABM_SYSFS_CONTROL; 1896 else 1897 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ? 1898 dm_state->abm_level : 0; 1899 ret = 0; 1900 } 1901 1902 return ret; 1903 } 1904 EXPORT_IF_KUNIT(amdgpu_dm_connector_atomic_get_property); 1905 1906 STATIC_IFN_KUNIT void amdgpu_dm_connector_unregister(struct drm_connector *connector) 1907 { 1908 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 1909 1910 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) 1911 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); 1912 1913 cec_notifier_conn_unregister(amdgpu_dm_connector->notifier); 1914 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 1915 } 1916 EXPORT_IF_KUNIT(amdgpu_dm_connector_unregister); 1917 1918 STATIC_IFN_KUNIT void amdgpu_dm_connector_destroy(struct drm_connector *connector) 1919 { 1920 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1921 struct amdgpu_device *adev = drm_to_adev(connector->dev); 1922 struct amdgpu_display_manager *dm = &adev->dm; 1923 1924 /* 1925 * Call only if mst_mgr was initialized before since it's not done 1926 * for all connector types. 1927 */ 1928 if (aconnector->mst_mgr.dev) 1929 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 1930 1931 /* Cancel and flush any pending HDMI HPD debounce work */ 1932 if (aconnector->hdmi_hpd_debounce_delay_ms) { 1933 cancel_delayed_work_sync(&aconnector->hdmi_hpd_debounce_work); 1934 if (aconnector->hdmi_prev_sink) { 1935 dc_sink_release(aconnector->hdmi_prev_sink); 1936 aconnector->hdmi_prev_sink = NULL; 1937 } 1938 } 1939 1940 if (aconnector->bl_idx != -1) { 1941 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 1942 dm->backlight_dev[aconnector->bl_idx] = NULL; 1943 } 1944 1945 if (aconnector->dc_em_sink) 1946 dc_sink_release(aconnector->dc_em_sink); 1947 aconnector->dc_em_sink = NULL; 1948 if (aconnector->dc_sink) 1949 dc_sink_release(aconnector->dc_sink); 1950 aconnector->dc_sink = NULL; 1951 1952 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 1953 drm_connector_unregister(connector); 1954 drm_connector_cleanup(connector); 1955 kfree(aconnector->dm_dp_aux.aux.name); 1956 1957 kfree(connector); 1958 } 1959 EXPORT_IF_KUNIT(amdgpu_dm_connector_destroy); 1960 1961 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 1962 { 1963 struct dm_connector_state *old_state = 1964 to_dm_connector_state(connector->state); 1965 struct dm_connector_state *state; 1966 1967 state = kzalloc_obj(*state); 1968 if (!state) 1969 return; 1970 1971 if (connector->state) 1972 __drm_atomic_helper_connector_destroy_state(connector->state); 1973 1974 kfree(old_state); 1975 1976 __drm_atomic_helper_connector_reset(connector, &state->base); 1977 1978 state->scaling = RMX_OFF; 1979 state->underscan_enable = false; 1980 state->underscan_hborder = 0; 1981 state->underscan_vborder = 0; 1982 state->base.max_requested_bpc = 8; 1983 state->vcpi_slots = 0; 1984 state->pbn = 0; 1985 1986 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1987 if (amdgpu_dm_abm_level <= 0) 1988 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 1989 else 1990 state->abm_level = amdgpu_dm_abm_level; 1991 } 1992 } 1993 EXPORT_IF_KUNIT(amdgpu_dm_connector_funcs_reset); 1994 1995 struct drm_connector_state * 1996 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 1997 { 1998 struct dm_connector_state *state = 1999 to_dm_connector_state(connector->state); 2000 2001 struct dm_connector_state *new_state = 2002 kmemdup(state, sizeof(*state), GFP_KERNEL); 2003 2004 if (!new_state) 2005 return NULL; 2006 2007 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 2008 2009 new_state->freesync_capable = state->freesync_capable; 2010 new_state->abm_level = state->abm_level; 2011 new_state->scaling = state->scaling; 2012 new_state->underscan_enable = state->underscan_enable; 2013 new_state->underscan_hborder = state->underscan_hborder; 2014 new_state->underscan_vborder = state->underscan_vborder; 2015 new_state->vcpi_slots = state->vcpi_slots; 2016 new_state->pbn = state->pbn; 2017 return &new_state->base; 2018 } 2019 EXPORT_IF_KUNIT(amdgpu_dm_connector_atomic_duplicate_state); 2020 2021 STATIC_IFN_KUNIT int 2022 amdgpu_dm_connector_late_register(struct drm_connector *connector) 2023 { 2024 struct amdgpu_dm_connector *amdgpu_dm_connector = 2025 to_amdgpu_dm_connector(connector); 2026 int r; 2027 2028 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) { 2029 r = sysfs_create_group(&connector->kdev->kobj, 2030 &amdgpu_group); 2031 if (r) 2032 return r; 2033 } 2034 2035 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 2036 2037 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 2038 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 2039 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 2040 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 2041 if (r) 2042 return r; 2043 } 2044 2045 #if defined(CONFIG_DEBUG_FS) 2046 connector_debugfs_init(amdgpu_dm_connector); 2047 #endif 2048 2049 return 0; 2050 } 2051 EXPORT_IF_KUNIT(amdgpu_dm_connector_late_register); 2052 2053 STATIC_IFN_KUNIT void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 2054 { 2055 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2056 struct dc_link *dc_link = aconnector->dc_link; 2057 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 2058 const struct drm_edid *drm_edid; 2059 struct i2c_adapter *ddc; 2060 struct drm_device *dev = connector->dev; 2061 2062 if (dc_link && dc_link->aux_mode) 2063 ddc = &aconnector->dm_dp_aux.aux.ddc; 2064 else 2065 ddc = &aconnector->i2c->base; 2066 2067 drm_edid = drm_edid_read_ddc(connector, ddc); 2068 drm_edid_connector_update(connector, drm_edid); 2069 if (!drm_edid) { 2070 drm_err(dev, "No EDID found on connector: %s.\n", connector->name); 2071 return; 2072 } 2073 2074 aconnector->drm_edid = drm_edid; 2075 /* Update emulated (virtual) sink's EDID */ 2076 if (dc_em_sink && dc_link) { 2077 /* FIXME: Get rid of drm_edid_raw() */ 2078 const struct edid *edid = drm_edid_raw(drm_edid); 2079 2080 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 2081 memmove(dc_em_sink->dc_edid.raw_edid, edid, 2082 (edid->extensions + 1) * EDID_LENGTH); 2083 dm_helpers_parse_edid_caps( 2084 dc_link, 2085 &dc_em_sink->dc_edid, 2086 &dc_em_sink->edid_caps); 2087 } 2088 } 2089 EXPORT_IF_KUNIT(amdgpu_dm_connector_funcs_force); 2090 2091 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 2092 .reset = amdgpu_dm_connector_funcs_reset, 2093 .detect = amdgpu_dm_connector_detect, 2094 .fill_modes = drm_helper_probe_single_connector_modes, 2095 .destroy = amdgpu_dm_connector_destroy, 2096 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 2097 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2098 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 2099 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 2100 .late_register = amdgpu_dm_connector_late_register, 2101 .early_unregister = amdgpu_dm_connector_unregister, 2102 .force = amdgpu_dm_connector_funcs_force 2103 }; 2104 2105 static int get_modes(struct drm_connector *connector) 2106 { 2107 return amdgpu_dm_connector_get_modes(connector); 2108 } 2109 2110 STATIC_IFN_KUNIT void create_eml_sink(struct amdgpu_dm_connector *aconnector) 2111 { 2112 struct drm_connector *connector = &aconnector->base; 2113 struct dc_link *dc_link = aconnector->dc_link; 2114 struct dc_sink_init_data init_params = { 2115 .link = aconnector->dc_link, 2116 .sink_signal = SIGNAL_TYPE_VIRTUAL 2117 }; 2118 const struct drm_edid *drm_edid; 2119 const struct edid *edid; 2120 struct i2c_adapter *ddc; 2121 2122 if (dc_link && dc_link->aux_mode) 2123 ddc = &aconnector->dm_dp_aux.aux.ddc; 2124 else 2125 ddc = &aconnector->i2c->base; 2126 2127 drm_edid = drm_edid_read_ddc(connector, ddc); 2128 drm_edid_connector_update(connector, drm_edid); 2129 if (!drm_edid) { 2130 drm_err(connector->dev, "No EDID found on connector: %s.\n", connector->name); 2131 return; 2132 } 2133 2134 if (connector->display_info.is_hdmi) 2135 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 2136 2137 aconnector->drm_edid = drm_edid; 2138 2139 /* FIXME: Get rid of drm_edid_raw() */ 2140 edid = drm_edid_raw(drm_edid); 2141 aconnector->dc_em_sink = dc_link_add_remote_sink( 2142 aconnector->dc_link, 2143 (uint8_t *)edid, 2144 (edid->extensions + 1) * EDID_LENGTH, 2145 &init_params); 2146 2147 if (aconnector->base.force == DRM_FORCE_ON) { 2148 aconnector->dc_sink = aconnector->dc_link->local_sink ? 2149 aconnector->dc_link->local_sink : 2150 aconnector->dc_em_sink; 2151 if (aconnector->dc_sink) 2152 dc_sink_retain(aconnector->dc_sink); 2153 } 2154 } 2155 EXPORT_IF_KUNIT(create_eml_sink); 2156 2157 STATIC_IFN_KUNIT void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 2158 { 2159 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 2160 2161 /* 2162 * In case of headless boot with force on for DP managed connector 2163 * Those settings have to be != 0 to get initial modeset 2164 */ 2165 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 2166 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 2167 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 2168 } 2169 2170 create_eml_sink(aconnector); 2171 } 2172 EXPORT_IF_KUNIT(handle_edid_mgmt); 2173 2174 STATIC_IFN_KUNIT enum dc_status dm_validate_stream_and_context(struct dc *dc, 2175 struct dc_stream_state *stream) 2176 { 2177 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 2178 struct dc_plane_state *dc_plane_state = NULL; 2179 struct dc_state *dc_state = NULL; 2180 2181 if (!stream) 2182 goto cleanup; 2183 2184 dc_plane_state = dc_create_plane_state(dc); 2185 if (!dc_plane_state) 2186 goto cleanup; 2187 2188 dc_state = dc_state_create(dc, NULL); 2189 if (!dc_state) 2190 goto cleanup; 2191 2192 /* populate stream to plane */ 2193 dc_plane_state->src_rect.height = stream->src.height; 2194 dc_plane_state->src_rect.width = stream->src.width; 2195 dc_plane_state->dst_rect.height = stream->src.height; 2196 dc_plane_state->dst_rect.width = stream->src.width; 2197 dc_plane_state->clip_rect.height = stream->src.height; 2198 dc_plane_state->clip_rect.width = stream->src.width; 2199 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 2200 dc_plane_state->plane_size.surface_size.height = stream->src.height; 2201 dc_plane_state->plane_size.surface_size.width = stream->src.width; 2202 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 2203 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 2204 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2205 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 2206 dc_plane_state->rotation = ROTATION_ANGLE_0; 2207 dc_plane_state->is_tiling_rotated = false; 2208 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 2209 2210 dc_result = dc_validate_stream(dc, stream); 2211 if (dc_result == DC_OK) 2212 dc_result = dc_validate_plane(dc, dc_plane_state); 2213 2214 if (dc_result == DC_OK) 2215 dc_result = dc_state_add_stream(dc, dc_state, stream); 2216 2217 if (dc_result == DC_OK && !dc_state_add_plane( 2218 dc, 2219 stream, 2220 dc_plane_state, 2221 dc_state)) 2222 dc_result = DC_FAIL_ATTACH_SURFACES; 2223 2224 if (dc_result == DC_OK) 2225 dc_result = dc_validate_global_state(dc, dc_state, DC_VALIDATE_MODE_ONLY); 2226 2227 cleanup: 2228 if (dc_state) 2229 dc_state_release(dc_state); 2230 2231 if (dc_plane_state) 2232 dc_plane_state_release(dc_plane_state); 2233 2234 return dc_result; 2235 } 2236 EXPORT_IF_KUNIT(dm_validate_stream_and_context); 2237 2238 static enum dc_status 2239 dm_validate_stream_color_format(const struct drm_connector_state *drm_state, 2240 const struct dc_stream_state *stream) 2241 { 2242 enum dc_pixel_encoding encoding; 2243 2244 if (!drm_state->color_format) 2245 return DC_OK; 2246 2247 switch (drm_state->color_format) { 2248 case DRM_CONNECTOR_COLOR_FORMAT_AUTO: 2249 case DRM_CONNECTOR_COLOR_FORMAT_RGB444: 2250 encoding = PIXEL_ENCODING_RGB; 2251 break; 2252 case DRM_CONNECTOR_COLOR_FORMAT_YCBCR444: 2253 encoding = PIXEL_ENCODING_YCBCR444; 2254 break; 2255 case DRM_CONNECTOR_COLOR_FORMAT_YCBCR422: 2256 encoding = PIXEL_ENCODING_YCBCR422; 2257 break; 2258 case DRM_CONNECTOR_COLOR_FORMAT_YCBCR420: 2259 encoding = PIXEL_ENCODING_YCBCR420; 2260 break; 2261 default: 2262 encoding = PIXEL_ENCODING_UNDEFINED; 2263 break; 2264 } 2265 2266 return encoding == stream->timing.pixel_encoding ? 2267 DC_OK : DC_UNSUPPORTED_VALUE; 2268 } 2269 2270 struct dc_stream_state * 2271 amdgpu_dm_create_validate_stream_for_sink(struct drm_connector *connector, 2272 const struct drm_display_mode *drm_mode, 2273 const struct dm_connector_state *dm_state, 2274 const struct dc_stream_state *old_stream) 2275 { 2276 /* 2277 * Ordered lists of the encodings and bit depths we are willing to 2278 * validate, best quality/bandwidth first. The per-sink masks built 2279 * below gate which of these entries are actually attempted. 2280 */ 2281 static const enum dc_pixel_encoding encoding_order[] = { 2282 PIXEL_ENCODING_RGB, 2283 PIXEL_ENCODING_YCBCR444, 2284 PIXEL_ENCODING_YCBCR422, 2285 PIXEL_ENCODING_YCBCR420, 2286 }; 2287 static const u8 bpc_order[] = { 16, 12, 10, 8, 6 }; 2288 2289 struct amdgpu_dm_connector *aconnector = NULL; 2290 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2291 const struct drm_display_info *info = &connector->display_info; 2292 struct dc_stream_state *stream = NULL; 2293 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 2294 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 2295 enum dc_status dc_result = DC_OK; 2296 enum signal_type signal = SIGNAL_TYPE_NONE; 2297 bool want_420, want_422, is_dp_or_hdmi; 2298 u32 encoding_mask = 0; 2299 u32 bpc_mask = 0; 2300 bool is_hdmi_ep = false; 2301 unsigned int i, j; 2302 2303 if (!dm_state) 2304 return NULL; 2305 2306 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 2307 aconnector = to_amdgpu_dm_connector(connector); 2308 2309 /* 2310 * Writeback connectors have no sink EDID to enumerate against. They 2311 * only ever use RGB at the requested depth, so build and validate a 2312 * single stream directly and return it (dc_validate_stream() is not 2313 * meaningful for the writeback path). 2314 */ 2315 if (!aconnector) { 2316 stream = create_stream_for_sink(connector, drm_mode, dm_state, 2317 old_stream, requested_bpc, 2318 PIXEL_ENCODING_RGB, is_hdmi_ep); 2319 if (!stream) 2320 drm_err(adev_to_drm(adev), "Failed to create stream for sink!\n"); 2321 return stream; 2322 } 2323 2324 signal = aconnector->dc_link->connector_signal; 2325 2326 /* 2327 * Determine whether this is a native HDMI sink or a DP->HDMI dongle. 2328 * Since we check for it a few times below, cache the result. 2329 */ 2330 is_hdmi_ep = (signal == SIGNAL_TYPE_HDMI_TYPE_A || 2331 signal == SIGNAL_TYPE_HDMI_FRL || 2332 aconnector->dc_link->dpcd_caps.dongle_type == 2333 DISPLAY_DONGLE_DP_HDMI_CONVERTER); 2334 is_dp_or_hdmi = dc_is_hdmi_signal(signal) || dc_is_dp_signal(signal); 2335 2336 /* 2337 * Build the set of pixel encodings this sink advertises, so we only 2338 * ever validate combinations the display can actually accept. Ordered 2339 * best-first: RGB / YCbCr444 (full bandwidth) -> YCbCr422 -> YCbCr420. 2340 * 2341 * - RGB is the mandatory baseline and always available. 2342 * - YCbCr444 is only meaningful for native HDMI sinks. 2343 * - A 420-only mode collapses the mask to YCbCr420 alone. 2344 * - The debugfs force_yuv_pixel_format override pins the encoding to a 2345 * single dc_pixel_encoding when set (PIXEL_ENCODING_UNDEFINED means 2346 * "no override"). An explicit YCbCr420 force is honoured even on 2347 * modes the sink only lists as RGB/4:4:4 capable 2348 * (drm_mode_is_420_also() clear), as required for HDMI compliance 2349 * testing; dc_validate_stream() still rejects anything the link 2350 * genuinely cannot carry. The YCbCr422/YCbCr444 forces stay gated on 2351 * the sink's advertised caps. 2352 */ 2353 want_420 = (aconnector->force_yuv_pixel_format == PIXEL_ENCODING_YCBCR420) || 2354 (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_YCBCR420); 2355 want_422 = (aconnector->force_yuv_pixel_format == PIXEL_ENCODING_YCBCR422) || 2356 (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_YCBCR422); 2357 2358 if (drm_mode_is_420_only(info, drm_mode) && 2359 (want_420 || (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_AUTO))) { 2360 encoding_mask = BIT(PIXEL_ENCODING_YCBCR420); 2361 } else if (drm_mode_is_420_also(info, drm_mode) && want_420) { 2362 encoding_mask = BIT(PIXEL_ENCODING_YCBCR420); 2363 } else if ((info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422)) && 2364 want_422 && is_dp_or_hdmi) { 2365 encoding_mask = BIT(PIXEL_ENCODING_YCBCR422); 2366 } else if (((aconnector->force_yuv_pixel_format == PIXEL_ENCODING_YCBCR444) || 2367 (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_YCBCR444)) && 2368 (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444)) && 2369 is_dp_or_hdmi) { 2370 encoding_mask = BIT(PIXEL_ENCODING_YCBCR444); 2371 } else if (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_RGB444) { 2372 encoding_mask = BIT(PIXEL_ENCODING_RGB); 2373 } else { 2374 encoding_mask = BIT(PIXEL_ENCODING_RGB); 2375 2376 if ((info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444)) && 2377 is_hdmi_ep) 2378 encoding_mask |= BIT(PIXEL_ENCODING_YCBCR444); 2379 2380 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422)) 2381 encoding_mask |= BIT(PIXEL_ENCODING_YCBCR422); 2382 2383 if (drm_mode_is_420_also(info, drm_mode)) 2384 encoding_mask |= BIT(PIXEL_ENCODING_YCBCR420); 2385 } 2386 2387 /* 2388 * Build the set of bit depths to try, high-to-low. Start from the 2389 * atomic-requested cap and clear anything the sink cannot do: 2390 * 2391 * - Never exceed the requested bpc. 2392 * - HDMI/FRL and DP->HDMI dongles have no defined 6 bpc mode. 2393 * - Any depth above the EDID-reported bpc is dropped. 2394 * 2395 * amdgpu_dm_convert_color_depth_from_display_info() applies the final 2396 * per-encoding cap (e.g. YCbCr420 deep-colour limits) when the stream 2397 * is built, so this mask only needs the coarse sink limits. 2398 */ 2399 for (j = 0; j < ARRAY_SIZE(bpc_order); j++) { 2400 u8 bpc = bpc_order[j]; 2401 2402 if (requested_bpc > 0 && bpc > requested_bpc) 2403 continue; 2404 2405 if (bpc == 6 && is_hdmi_ep) 2406 continue; 2407 2408 if (info->bpc && bpc > info->bpc) 2409 continue; 2410 2411 bpc_mask |= BIT(bpc); 2412 } 2413 2414 /* 2415 * Enumerate the supported (encoding, bpc) combinations in priority 2416 * order and return the first that validates. Because the masks only 2417 * contain sink-supported entries, this is generic across connector 2418 * types and needs no encoding-specific fallback afterwards. 2419 * 2420 * The selection lives entirely on the stack and is passed by value to 2421 * create_stream_for_sink(); no shared connector state is mutated. This 2422 * matters because this helper runs concurrently from the connector 2423 * probe worker (->mode_valid) and from a compositor's atomic check on 2424 * the same connector. 2425 */ 2426 for (i = 0; i < ARRAY_SIZE(encoding_order); i++) { 2427 enum dc_pixel_encoding enc = encoding_order[i]; 2428 2429 if (!(encoding_mask & BIT(enc))) 2430 continue; 2431 2432 for (j = 0; j < ARRAY_SIZE(bpc_order); j++) { 2433 u8 bpc = bpc_order[j]; 2434 2435 if (!(bpc_mask & BIT(bpc))) 2436 continue; 2437 2438 drm_dbg_kms(connector->dev, 2439 "Trying %s with %d bpc (encoding_mask=0x%x bpc_mask=0x%x requested_bpc=%d drm max_bpc)\n", 2440 dc_pixel_encoding_to_str(enc), bpc, 2441 encoding_mask, bpc_mask, requested_bpc); 2442 2443 stream = create_stream_for_sink(connector, drm_mode, 2444 dm_state, old_stream, 2445 bpc, enc, is_hdmi_ep); 2446 if (stream == NULL) { 2447 drm_err(adev_to_drm(adev), "Failed to create stream for sink!\n"); 2448 return NULL; 2449 } 2450 2451 dc_result = dc_validate_stream(adev->dm.dc, stream); 2452 2453 if (dc_result == DC_OK && 2454 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2455 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 2456 2457 if (dc_result == DC_OK) 2458 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 2459 2460 if (dc_result == DC_OK) 2461 dc_result = dm_validate_stream_color_format(drm_state, stream); 2462 2463 if (dc_result == DC_OK) 2464 return stream; 2465 2466 drm_dbg_kms(connector->dev, "Pruned mode %d x %d (refresh rate %d) %s %s -- %s\n", 2467 drm_mode->hdisplay, 2468 drm_mode->vdisplay, 2469 drm_mode_vrefresh(drm_mode), 2470 dc_pixel_encoding_to_str(stream->timing.pixel_encoding), 2471 dc_color_depth_to_str(stream->timing.display_color_depth), 2472 dc_status_to_str(dc_result)); 2473 2474 dc_stream_release(stream); 2475 stream = NULL; 2476 } 2477 } 2478 2479 /* 2480 * Every sink-supported combination was exhausted without validating; 2481 * the mode is genuinely unsupported on this link. 2482 */ 2483 return NULL; 2484 } 2485 EXPORT_IF_KUNIT(amdgpu_dm_create_validate_stream_for_sink); 2486 2487 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 2488 const struct drm_display_mode *mode) 2489 { 2490 int result = MODE_ERROR; 2491 struct dc_sink *dc_sink; 2492 struct drm_display_mode *test_mode; 2493 /* TODO: Unhardcode stream count */ 2494 struct dc_stream_state *stream; 2495 /* we always have an amdgpu_dm_connector here since we got 2496 * here via the amdgpu_dm_connector_helper_funcs 2497 */ 2498 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2499 2500 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 2501 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 2502 return result; 2503 2504 /* 2505 * Only run this the first time mode_valid is called to initilialize 2506 * EDID mgmt 2507 */ 2508 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 2509 !aconnector->dc_em_sink) 2510 handle_edid_mgmt(aconnector); 2511 2512 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 2513 2514 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 2515 aconnector->base.force != DRM_FORCE_ON) { 2516 drm_err(connector->dev, "dc_sink is NULL!\n"); 2517 goto fail; 2518 } 2519 2520 test_mode = drm_mode_duplicate(connector->dev, mode); 2521 if (!test_mode) 2522 goto fail; 2523 2524 drm_mode_set_crtcinfo(test_mode, 0); 2525 2526 stream = amdgpu_dm_create_validate_stream_for_sink(connector, test_mode, 2527 to_dm_connector_state(connector->state), 2528 NULL); 2529 drm_mode_destroy(connector->dev, test_mode); 2530 if (stream) { 2531 dc_stream_release(stream); 2532 result = MODE_OK; 2533 } 2534 2535 fail: 2536 /* TODO: error handling*/ 2537 return result; 2538 } 2539 EXPORT_IF_KUNIT(amdgpu_dm_connector_mode_valid); 2540 2541 int amdgpu_dm_fill_hdr_info_packet(const struct drm_connector_state *state, 2542 struct dc_info_packet *out) 2543 { 2544 struct hdmi_drm_infoframe frame; 2545 unsigned char buf[30]; /* 26 + 4 */ 2546 ssize_t len; 2547 int ret, i; 2548 2549 memset(out, 0, sizeof(*out)); 2550 2551 if (!state->hdr_output_metadata) 2552 return 0; 2553 2554 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 2555 if (ret) 2556 return ret; 2557 2558 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 2559 if (len < 0) 2560 return (int)len; 2561 2562 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 2563 if (len != 30) 2564 return -EINVAL; 2565 2566 /* Prepare the infopacket for DC. */ 2567 switch (state->connector->connector_type) { 2568 case DRM_MODE_CONNECTOR_HDMIA: 2569 out->hb0 = 0x87; /* type */ 2570 out->hb1 = 0x01; /* version */ 2571 out->hb2 = 0x1A; /* length */ 2572 out->sb[0] = buf[3]; /* checksum */ 2573 i = 1; 2574 break; 2575 2576 case DRM_MODE_CONNECTOR_DisplayPort: 2577 case DRM_MODE_CONNECTOR_eDP: 2578 out->hb0 = 0x00; /* sdp id, zero */ 2579 out->hb1 = 0x87; /* type */ 2580 out->hb2 = 0x1D; /* payload len - 1 */ 2581 out->hb3 = (0x13 << 2); /* sdp version */ 2582 out->sb[0] = 0x01; /* version */ 2583 out->sb[1] = 0x1A; /* length */ 2584 i = 2; 2585 break; 2586 2587 default: 2588 return -EINVAL; 2589 } 2590 2591 memcpy(&out->sb[i], &buf[4], 26); 2592 out->valid = true; 2593 2594 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 2595 sizeof(out->sb), false); 2596 2597 return 0; 2598 } 2599 EXPORT_IF_KUNIT(amdgpu_dm_fill_hdr_info_packet); 2600 2601 static int 2602 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 2603 struct drm_atomic_commit *state) 2604 { 2605 struct drm_connector_state *new_con_state = 2606 drm_atomic_get_new_connector_state(state, conn); 2607 struct drm_connector_state *old_con_state = 2608 drm_atomic_get_old_connector_state(state, conn); 2609 struct drm_crtc *crtc; 2610 struct drm_crtc_state *new_crtc_state; 2611 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 2612 int ret; 2613 2614 if (WARN_ON(unlikely(!old_con_state || !new_con_state))) 2615 return -EINVAL; 2616 2617 trace_amdgpu_dm_connector_atomic_check(new_con_state); 2618 2619 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 2620 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 2621 if (ret < 0) 2622 return ret; 2623 } 2624 2625 crtc = new_con_state->crtc; 2626 if (!crtc) 2627 return 0; 2628 2629 if (new_con_state->privacy_screen_sw_state != old_con_state->privacy_screen_sw_state) { 2630 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 2631 if (IS_ERR(new_crtc_state)) 2632 return PTR_ERR(new_crtc_state); 2633 2634 new_crtc_state->mode_changed = true; 2635 } 2636 2637 if (new_con_state->colorspace != old_con_state->colorspace) { 2638 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 2639 if (IS_ERR(new_crtc_state)) 2640 return PTR_ERR(new_crtc_state); 2641 2642 new_crtc_state->mode_changed = true; 2643 } 2644 2645 if (new_con_state->content_type != old_con_state->content_type) { 2646 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 2647 if (IS_ERR(new_crtc_state)) 2648 return PTR_ERR(new_crtc_state); 2649 2650 new_crtc_state->mode_changed = true; 2651 } 2652 2653 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 2654 struct dc_info_packet hdr_infopacket; 2655 2656 ret = amdgpu_dm_fill_hdr_info_packet(new_con_state, &hdr_infopacket); 2657 if (ret) 2658 return ret; 2659 2660 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 2661 if (IS_ERR(new_crtc_state)) 2662 return PTR_ERR(new_crtc_state); 2663 2664 /* 2665 * DC considers the stream backends changed if the 2666 * static metadata changes. Forcing the modeset also 2667 * gives a simple way for userspace to switch from 2668 * 8bpc to 10bpc when setting the metadata to enter 2669 * or exit HDR. 2670 * 2671 * Changing the static metadata after it's been 2672 * set is permissible, however. So only force a 2673 * modeset if we're entering or exiting HDR. 2674 */ 2675 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 2676 !old_con_state->hdr_output_metadata || 2677 !new_con_state->hdr_output_metadata; 2678 } 2679 2680 return 0; 2681 } 2682 2683 static const struct drm_connector_helper_funcs 2684 amdgpu_dm_connector_helper_funcs = { 2685 /* 2686 * If hotplugging a second bigger display in FB Con mode, bigger resolution 2687 * modes will be filtered by drm_mode_validate_size(), and those modes 2688 * are missing after user start lightdm. So we need to renew modes list. 2689 * in get_modes call back, not just return the modes count 2690 */ 2691 .get_modes = get_modes, 2692 .mode_valid = amdgpu_dm_connector_mode_valid, 2693 .atomic_check = amdgpu_dm_connector_atomic_check, 2694 }; 2695 2696 int amdgpu_dm_convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 2697 { 2698 switch (display_color_depth) { 2699 case COLOR_DEPTH_666: 2700 return 6; 2701 case COLOR_DEPTH_888: 2702 return 8; 2703 case COLOR_DEPTH_101010: 2704 return 10; 2705 case COLOR_DEPTH_121212: 2706 return 12; 2707 case COLOR_DEPTH_141414: 2708 return 14; 2709 case COLOR_DEPTH_161616: 2710 return 16; 2711 default: 2712 break; 2713 } 2714 return 0; 2715 } 2716 EXPORT_IF_KUNIT(amdgpu_dm_convert_dc_color_depth_into_bpc); 2717 2718 STATIC_IFN_KUNIT int to_drm_connector_type(enum signal_type st, uint32_t connector_id) 2719 { 2720 switch (st) { 2721 case SIGNAL_TYPE_HDMI_TYPE_A: 2722 return DRM_MODE_CONNECTOR_HDMIA; 2723 case SIGNAL_TYPE_EDP: 2724 return DRM_MODE_CONNECTOR_eDP; 2725 case SIGNAL_TYPE_LVDS: 2726 return DRM_MODE_CONNECTOR_LVDS; 2727 case SIGNAL_TYPE_RGB: 2728 return DRM_MODE_CONNECTOR_VGA; 2729 case SIGNAL_TYPE_DISPLAY_PORT: 2730 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2731 /* External DP bridges have a different connector type. */ 2732 if (connector_id == CONNECTOR_ID_VGA) 2733 return DRM_MODE_CONNECTOR_VGA; 2734 else if (connector_id == CONNECTOR_ID_LVDS) 2735 return DRM_MODE_CONNECTOR_LVDS; 2736 2737 return DRM_MODE_CONNECTOR_DisplayPort; 2738 case SIGNAL_TYPE_DVI_DUAL_LINK: 2739 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2740 if (connector_id == CONNECTOR_ID_SINGLE_LINK_DVII || 2741 connector_id == CONNECTOR_ID_DUAL_LINK_DVII) 2742 return DRM_MODE_CONNECTOR_DVII; 2743 2744 return DRM_MODE_CONNECTOR_DVID; 2745 case SIGNAL_TYPE_VIRTUAL: 2746 return DRM_MODE_CONNECTOR_VIRTUAL; 2747 2748 default: 2749 return DRM_MODE_CONNECTOR_Unknown; 2750 } 2751 } 2752 EXPORT_IF_KUNIT(to_drm_connector_type); 2753 2754 STATIC_IFN_KUNIT struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 2755 { 2756 struct drm_encoder *encoder; 2757 2758 /* There is only one encoder per connector */ 2759 drm_connector_for_each_possible_encoder(connector, encoder) 2760 return encoder; 2761 2762 return NULL; 2763 } 2764 EXPORT_IF_KUNIT(amdgpu_dm_connector_to_encoder); 2765 2766 STATIC_IFN_KUNIT void amdgpu_dm_get_native_mode(struct drm_connector *connector) 2767 { 2768 struct drm_encoder *encoder; 2769 struct amdgpu_encoder *amdgpu_encoder; 2770 2771 encoder = amdgpu_dm_connector_to_encoder(connector); 2772 2773 if (encoder == NULL) 2774 return; 2775 2776 amdgpu_encoder = to_amdgpu_encoder(encoder); 2777 2778 amdgpu_encoder->native_mode.clock = 0; 2779 2780 if (!list_empty(&connector->probed_modes)) { 2781 struct drm_display_mode *preferred_mode = NULL; 2782 2783 list_for_each_entry(preferred_mode, 2784 &connector->probed_modes, 2785 head) { 2786 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 2787 amdgpu_encoder->native_mode = *preferred_mode; 2788 2789 break; 2790 } 2791 2792 } 2793 } 2794 EXPORT_IF_KUNIT(amdgpu_dm_get_native_mode); 2795 2796 STATIC_IFN_KUNIT struct drm_display_mode * 2797 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 2798 const char *name, 2799 int hdisplay, int vdisplay) 2800 { 2801 struct drm_device *dev = encoder->dev; 2802 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2803 struct drm_display_mode *mode = NULL; 2804 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 2805 2806 mode = drm_mode_duplicate(dev, native_mode); 2807 2808 if (mode == NULL) 2809 return NULL; 2810 2811 mode->hdisplay = hdisplay; 2812 mode->vdisplay = vdisplay; 2813 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2814 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 2815 2816 return mode; 2817 2818 } 2819 EXPORT_IF_KUNIT(amdgpu_dm_create_common_mode); 2820 2821 static const struct amdgpu_dm_mode_size { 2822 char name[DRM_DISPLAY_MODE_LEN]; 2823 int w; 2824 int h; 2825 } common_modes[] = { 2826 { "640x480", 640, 480}, 2827 { "800x600", 800, 600}, 2828 { "1024x768", 1024, 768}, 2829 { "1280x720", 1280, 720}, 2830 { "1280x800", 1280, 800}, 2831 {"1280x1024", 1280, 1024}, 2832 { "1440x900", 1440, 900}, 2833 {"1680x1050", 1680, 1050}, 2834 {"1600x1200", 1600, 1200}, 2835 {"1920x1080", 1920, 1080}, 2836 {"1920x1200", 1920, 1200} 2837 }; 2838 2839 STATIC_IFN_KUNIT void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 2840 struct drm_connector *connector) 2841 { 2842 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2843 struct drm_display_mode *mode = NULL; 2844 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 2845 struct amdgpu_dm_connector *amdgpu_dm_connector = 2846 to_amdgpu_dm_connector(connector); 2847 int i; 2848 int n; 2849 2850 if ((connector->connector_type != DRM_MODE_CONNECTOR_eDP) && 2851 (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) 2852 return; 2853 2854 n = ARRAY_SIZE(common_modes); 2855 2856 for (i = 0; i < n; i++) { 2857 struct drm_display_mode *curmode = NULL; 2858 bool mode_existed = false; 2859 2860 if (common_modes[i].w > native_mode->hdisplay || 2861 common_modes[i].h > native_mode->vdisplay || 2862 (common_modes[i].w == native_mode->hdisplay && 2863 common_modes[i].h == native_mode->vdisplay)) 2864 continue; 2865 2866 list_for_each_entry(curmode, &connector->probed_modes, head) { 2867 if (common_modes[i].w == curmode->hdisplay && 2868 common_modes[i].h == curmode->vdisplay) { 2869 mode_existed = true; 2870 break; 2871 } 2872 } 2873 2874 if (mode_existed) 2875 continue; 2876 2877 mode = amdgpu_dm_create_common_mode(encoder, 2878 common_modes[i].name, common_modes[i].w, 2879 common_modes[i].h); 2880 if (!mode) 2881 continue; 2882 2883 drm_mode_probed_add(connector, mode); 2884 amdgpu_dm_connector->num_modes++; 2885 } 2886 } 2887 EXPORT_IF_KUNIT(amdgpu_dm_connector_add_common_modes); 2888 2889 void amdgpu_set_panel_orientation(struct drm_connector *connector) 2890 { 2891 struct drm_encoder *encoder; 2892 struct amdgpu_encoder *amdgpu_encoder; 2893 const struct drm_display_mode *native_mode; 2894 2895 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 2896 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 2897 return; 2898 2899 mutex_lock(&connector->dev->mode_config.mutex); 2900 amdgpu_dm_connector_get_modes(connector); 2901 mutex_unlock(&connector->dev->mode_config.mutex); 2902 2903 encoder = amdgpu_dm_connector_to_encoder(connector); 2904 if (!encoder) 2905 return; 2906 2907 amdgpu_encoder = to_amdgpu_encoder(encoder); 2908 2909 native_mode = &amdgpu_encoder->native_mode; 2910 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 2911 return; 2912 2913 drm_connector_set_panel_orientation_with_quirk(connector, 2914 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 2915 native_mode->hdisplay, 2916 native_mode->vdisplay); 2917 } 2918 2919 /* 2920 * The Apple Studio Display primary tile advertises both the full 5120x2880 2921 * mode and the per-tile 2560x2880 timing. As the secondary tile is hidden from 2922 * userspace (see amdgpu_dm_hide_secondary_tile_from_userspace()), drop the 2923 * per-tile timing from the primary connector so compositors only pick the full 2924 * 5K mode. 2925 */ 2926 static void amdgpu_dm_prune_primary_tile_modes(struct drm_connector *connector) 2927 { 2928 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2929 struct drm_display_mode *mode, *t; 2930 2931 if (!aconnector->dc_sink) 2932 return; 2933 2934 if (!aconnector->dc_sink->edid_caps.panel_patch.disable_second_tile) 2935 return; 2936 2937 if (!connector->has_tile) 2938 return; 2939 2940 /* Only prune the per-tile timing from the primary tile. */ 2941 if (connector->tile_h_loc || connector->tile_v_loc) 2942 return; 2943 2944 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 2945 if (mode->hdisplay != connector->tile_h_size || 2946 mode->vdisplay != connector->tile_v_size) 2947 continue; 2948 2949 drm_dbg_kms(connector->dev, 2950 "[CONNECTOR:%d:%s] pruning per-tile %dx%d timing from primary Apple Studio Display tile\n", 2951 connector->base.id, connector->name, 2952 mode->hdisplay, mode->vdisplay); 2953 2954 list_del(&mode->head); 2955 drm_mode_destroy(connector->dev, mode); 2956 aconnector->num_modes--; 2957 } 2958 } 2959 2960 STATIC_IFN_KUNIT void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 2961 const struct drm_edid *drm_edid) 2962 { 2963 struct amdgpu_dm_connector *amdgpu_dm_connector = 2964 to_amdgpu_dm_connector(connector); 2965 2966 if (drm_edid) { 2967 /* empty probed_modes */ 2968 INIT_LIST_HEAD(&connector->probed_modes); 2969 amdgpu_dm_connector->num_modes = 2970 drm_edid_connector_add_modes(connector); 2971 2972 amdgpu_dm_prune_primary_tile_modes(connector); 2973 2974 /* sorting the probed modes before calling function 2975 * amdgpu_dm_get_native_mode() since EDID can have 2976 * more than one preferred mode. The modes that are 2977 * later in the probed mode list could be of higher 2978 * and preferred resolution. For example, 3840x2160 2979 * resolution in base EDID preferred timing and 4096x2160 2980 * preferred resolution in DID extension block later. 2981 */ 2982 drm_mode_sort(&connector->probed_modes); 2983 amdgpu_dm_get_native_mode(connector); 2984 2985 /* Freesync capabilities are reset by calling 2986 * drm_edid_connector_add_modes() and need to be 2987 * restored here. 2988 */ 2989 amdgpu_dm_update_freesync_caps(connector, drm_edid, false); 2990 } else { 2991 amdgpu_dm_connector->num_modes = 0; 2992 } 2993 } 2994 EXPORT_IF_KUNIT(amdgpu_dm_connector_ddc_get_modes); 2995 2996 STATIC_IFN_KUNIT bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 2997 struct drm_display_mode *mode) 2998 { 2999 struct drm_display_mode *m; 3000 3001 list_for_each_entry(m, &aconnector->base.probed_modes, head) { 3002 if (drm_mode_equal(m, mode)) 3003 return true; 3004 } 3005 3006 return false; 3007 } 3008 EXPORT_IF_KUNIT(is_duplicate_mode); 3009 3010 STATIC_IFN_KUNIT uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 3011 { 3012 const struct drm_display_mode *m; 3013 struct drm_display_mode *new_mode; 3014 uint i; 3015 u32 new_modes_count = 0; 3016 3017 /* Standard FPS values 3018 * 3019 * 23.976 - TV/NTSC 3020 * 24 - Cinema 3021 * 25 - TV/PAL 3022 * 29.97 - TV/NTSC 3023 * 30 - TV/NTSC 3024 * 48 - Cinema HFR 3025 * 50 - TV/PAL 3026 * 60 - Commonly used 3027 * 48,72,96,120 - Multiples of 24 3028 */ 3029 static const u32 common_rates[] = { 3030 23976, 24000, 25000, 29970, 30000, 3031 48000, 50000, 60000, 72000, 96000, 120000 3032 }; 3033 3034 /* 3035 * Find mode with highest refresh rate with the same resolution 3036 * as the preferred mode. Some monitors report a preferred mode 3037 * with lower resolution than the highest refresh rate supported. 3038 */ 3039 3040 m = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, true); 3041 if (!m) 3042 return 0; 3043 3044 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 3045 u64 target_vtotal, target_vtotal_diff; 3046 u64 num, den; 3047 3048 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 3049 continue; 3050 3051 if (common_rates[i] < aconnector->min_vfreq * 1000 || 3052 common_rates[i] > aconnector->max_vfreq * 1000) 3053 continue; 3054 3055 num = (unsigned long long)m->clock * 1000 * 1000; 3056 den = common_rates[i] * (unsigned long long)m->htotal; 3057 target_vtotal = div_u64(num, den); 3058 target_vtotal_diff = target_vtotal - m->vtotal; 3059 3060 /* Check for illegal modes */ 3061 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 3062 m->vsync_end + target_vtotal_diff < m->vsync_start || 3063 m->vtotal + target_vtotal_diff < m->vsync_end) 3064 continue; 3065 3066 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 3067 if (!new_mode) 3068 goto out; 3069 3070 new_mode->vtotal += (u16)target_vtotal_diff; 3071 new_mode->vsync_start += (u16)target_vtotal_diff; 3072 new_mode->vsync_end += (u16)target_vtotal_diff; 3073 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3074 new_mode->type |= DRM_MODE_TYPE_DRIVER; 3075 3076 if (!is_duplicate_mode(aconnector, new_mode)) { 3077 drm_mode_probed_add(&aconnector->base, new_mode); 3078 new_modes_count += 1; 3079 } else 3080 drm_mode_destroy(aconnector->base.dev, new_mode); 3081 } 3082 out: 3083 return new_modes_count; 3084 } 3085 EXPORT_IF_KUNIT(add_fs_modes); 3086 3087 STATIC_IFN_KUNIT void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 3088 const struct drm_edid *drm_edid) 3089 { 3090 struct amdgpu_dm_connector *amdgpu_dm_connector = 3091 to_amdgpu_dm_connector(connector); 3092 3093 if (!(amdgpu_freesync_vid_mode && drm_edid)) 3094 return; 3095 3096 if (!amdgpu_dm_connector->dc_sink || !amdgpu_dm_connector->dc_link) 3097 return; 3098 3099 if (!dc_supports_vrr(amdgpu_dm_connector->dc_sink->ctx->dce_version)) 3100 return; 3101 3102 if (dc_connector_supports_analog(amdgpu_dm_connector->dc_link->link_id.id) && 3103 amdgpu_dm_connector->dc_sink->edid_caps.analog) 3104 return; 3105 3106 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 3107 amdgpu_dm_connector->num_modes += 3108 add_fs_modes(amdgpu_dm_connector); 3109 } 3110 EXPORT_IF_KUNIT(amdgpu_dm_connector_add_freesync_modes); 3111 3112 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 3113 { 3114 struct amdgpu_dm_connector *amdgpu_dm_connector = 3115 to_amdgpu_dm_connector(connector); 3116 struct dc_link *dc_link = amdgpu_dm_connector->dc_link; 3117 struct drm_encoder *encoder; 3118 const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid; 3119 struct dc_link_settings *verified_link_cap = &dc_link->verified_link_cap; 3120 const struct dc *dc = dc_link->dc; 3121 3122 encoder = amdgpu_dm_connector_to_encoder(connector); 3123 3124 if (!drm_edid) { 3125 amdgpu_dm_connector->num_modes = 3126 drm_add_modes_noedid(connector, 640, 480); 3127 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 3128 amdgpu_dm_connector->num_modes += 3129 drm_add_modes_noedid(connector, 1920, 1080); 3130 3131 if (amdgpu_dm_connector->dc_sink && 3132 amdgpu_dm_connector->dc_sink->edid_caps.analog && 3133 dc_connector_supports_analog(dc_link->link_id.id)) { 3134 /* Analog monitor connected by DAC load detection. 3135 * Add common modes. It will be up to the user to select one that works. 3136 */ 3137 for (int i = 0; i < ARRAY_SIZE(common_modes); i++) 3138 amdgpu_dm_connector->num_modes += drm_add_modes_noedid( 3139 connector, common_modes[i].w, common_modes[i].h); 3140 } 3141 } else { 3142 amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); 3143 if (encoder) 3144 amdgpu_dm_connector_add_common_modes(encoder, connector); 3145 amdgpu_dm_connector_add_freesync_modes(connector, drm_edid); 3146 } 3147 amdgpu_dm_fbc_init(connector); 3148 3149 return amdgpu_dm_connector->num_modes; 3150 } 3151 3152 static const u32 supported_colorspaces = 3153 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 3154 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 3155 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 3156 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 3157 3158 static const u32 supported_colorformats = 3159 BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444) | 3160 BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444) | 3161 BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422) | 3162 BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420); 3163 3164 static void hdmi_frl_status_polling_work(struct work_struct *work) 3165 { 3166 struct amdgpu_display_manager *dm = 3167 container_of(to_delayed_work(work), struct amdgpu_display_manager, 3168 hdmi_frl_status_polling_work); 3169 struct dc *dc = dm->dc; 3170 struct dc_link *dc_link; 3171 bool link_update = false; 3172 3173 for (int i = 0; i < MAX_LINKS; i++) { 3174 dc_link = dc->links[i]; 3175 3176 3177 if (!dc_link || !dc_link->local_sink) 3178 continue; 3179 3180 if (!dc_is_hdmi_signal(dc_link->connector_signal)) 3181 continue; 3182 3183 if (dc_link->frl_link_settings.frl_link_rate == 0) 3184 continue; 3185 3186 link_update = dc_link_frl_poll_status_flag(dc_link); 3187 if (link_update) { 3188 mutex_lock(&dm->dc_lock); 3189 dc_link_detect(dc_link, DETECT_REASON_RETRAIN); 3190 mutex_unlock(&dm->dc_lock); 3191 } 3192 } 3193 3194 queue_delayed_work(dm->hdmi_frl_status_polling_wq, 3195 &dm->hdmi_frl_status_polling_work, 3196 msecs_to_jiffies(dm->hdmi_frl_status_polling_delay_ms)); 3197 } 3198 3199 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 3200 struct amdgpu_dm_connector *aconnector, 3201 int connector_type, 3202 struct dc_link *link, 3203 int link_index) 3204 { 3205 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 3206 3207 /* 3208 * Some of the properties below require access to state, like bpc. 3209 * Allocate some default initial connector state with our reset helper. 3210 */ 3211 if (aconnector->base.funcs->reset) 3212 aconnector->base.funcs->reset(&aconnector->base); 3213 3214 aconnector->connector_id = link_index; 3215 aconnector->bl_idx = -1; 3216 aconnector->dc_link = link; 3217 aconnector->base.interlace_allowed = false; 3218 aconnector->base.doublescan_allowed = false; 3219 aconnector->base.stereo_allowed = false; 3220 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 3221 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 3222 aconnector->audio_inst = -1; 3223 aconnector->pack_sdp_v1_3 = false; 3224 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 3225 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 3226 mutex_init(&aconnector->hpd_lock); 3227 mutex_init(&aconnector->handle_mst_msg_ready); 3228 3229 /* 3230 * If HDMI HPD debounce delay is set, use the minimum between selected 3231 * value and AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 3232 */ 3233 if (amdgpu_hdmi_hpd_debounce_delay_ms) { 3234 aconnector->hdmi_hpd_debounce_delay_ms = min(amdgpu_hdmi_hpd_debounce_delay_ms, 3235 AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS); 3236 INIT_DELAYED_WORK(&aconnector->hdmi_hpd_debounce_work, amdgpu_dm_hdmi_hpd_debounce_work); 3237 aconnector->hdmi_prev_sink = NULL; 3238 } else { 3239 aconnector->hdmi_hpd_debounce_delay_ms = 0; 3240 } 3241 3242 dm->hdmi_frl_status_polling_delay_ms = 200; 3243 INIT_DELAYED_WORK(&dm->hdmi_frl_status_polling_work, hdmi_frl_status_polling_work); 3244 /* 3245 * configure support HPD hot plug connector_>polled default value is 0 3246 * which means HPD hot plug not supported 3247 */ 3248 switch (connector_type) { 3249 case DRM_MODE_CONNECTOR_HDMIA: 3250 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3251 aconnector->base.ycbcr_420_allowed = 3252 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 3253 break; 3254 case DRM_MODE_CONNECTOR_DisplayPort: 3255 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3256 link->link_enc = link_enc_cfg_get_link_enc(link); 3257 ASSERT(link->link_enc); 3258 if (link->link_enc) 3259 aconnector->base.ycbcr_420_allowed = 3260 link->link_enc->features.dp_ycbcr420_supported ? true : false; 3261 break; 3262 case DRM_MODE_CONNECTOR_DVID: 3263 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3264 break; 3265 case DRM_MODE_CONNECTOR_DVII: 3266 case DRM_MODE_CONNECTOR_VGA: 3267 aconnector->base.polled = 3268 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 3269 break; 3270 default: 3271 break; 3272 } 3273 3274 drm_object_attach_property(&aconnector->base.base, 3275 dm->ddev->mode_config.scaling_mode_property, 3276 DRM_MODE_SCALE_NONE); 3277 3278 if (connector_type == DRM_MODE_CONNECTOR_HDMIA 3279 || (connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root)) 3280 drm_connector_attach_broadcast_rgb_property(&aconnector->base); 3281 3282 drm_object_attach_property(&aconnector->base.base, 3283 adev->mode_info.underscan_property, 3284 UNDERSCAN_OFF); 3285 drm_object_attach_property(&aconnector->base.base, 3286 adev->mode_info.underscan_hborder_property, 3287 0); 3288 drm_object_attach_property(&aconnector->base.base, 3289 adev->mode_info.underscan_vborder_property, 3290 0); 3291 3292 if (!aconnector->mst_root) 3293 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 3294 3295 aconnector->base.state->max_bpc = 16; 3296 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 3297 3298 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3299 /* Content Type is currently only implemented for HDMI. */ 3300 drm_connector_attach_content_type_property(&aconnector->base); 3301 } 3302 3303 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3304 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 3305 drm_connector_attach_colorspace_property(&aconnector->base); 3306 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || 3307 connector_type == DRM_MODE_CONNECTOR_eDP) { 3308 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 3309 drm_connector_attach_colorspace_property(&aconnector->base); 3310 } 3311 3312 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 3313 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3314 connector_type == DRM_MODE_CONNECTOR_eDP) { 3315 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 3316 3317 if (!aconnector->mst_root) { 3318 drm_connector_attach_vrr_capable_property(&aconnector->base); 3319 drm_connector_attach_color_format_property(&aconnector->base, 3320 supported_colorformats); 3321 } 3322 3323 3324 if (adev->dm.hdcp_workqueue) 3325 drm_connector_attach_content_protection_property(&aconnector->base, true); 3326 } 3327 3328 if (connector_type == DRM_MODE_CONNECTOR_eDP) { 3329 struct drm_privacy_screen *privacy_screen; 3330 3331 drm_connector_attach_panel_type_property(&aconnector->base); 3332 3333 privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); 3334 if (!IS_ERR(privacy_screen)) { 3335 drm_connector_attach_privacy_screen_provider(&aconnector->base, 3336 privacy_screen); 3337 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3338 drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n"); 3339 } 3340 } 3341 } 3342 3343 STATIC_IFN_KUNIT int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 3344 struct i2c_msg *msgs, int num) 3345 { 3346 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 3347 struct ddc_service *ddc_service = i2c->ddc_service; 3348 struct i2c_command cmd; 3349 int i; 3350 int result = -EIO; 3351 3352 if (!ddc_service->ddc_pin) 3353 return result; 3354 3355 cmd.payloads = kzalloc_objs(struct i2c_payload, num); 3356 3357 if (!cmd.payloads) 3358 return result; 3359 3360 cmd.number_of_payloads = num; 3361 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 3362 cmd.speed = 100; 3363 3364 for (i = 0; i < num; i++) { 3365 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 3366 cmd.payloads[i].address = msgs[i].addr; 3367 cmd.payloads[i].length = msgs[i].len; 3368 cmd.payloads[i].data = msgs[i].buf; 3369 } 3370 3371 if (i2c->oem) { 3372 if (dc_submit_i2c_oem( 3373 ddc_service->ctx->dc, 3374 &cmd)) 3375 result = num; 3376 } else { 3377 if (dc_submit_i2c( 3378 ddc_service->ctx->dc, 3379 ddc_service->link->link_index, 3380 &cmd)) 3381 result = num; 3382 } 3383 3384 kfree(cmd.payloads); 3385 return result; 3386 } 3387 EXPORT_IF_KUNIT(amdgpu_dm_i2c_xfer); 3388 3389 STATIC_IFN_KUNIT u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 3390 { 3391 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3392 } 3393 EXPORT_IF_KUNIT(amdgpu_dm_i2c_func); 3394 3395 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 3396 .master_xfer = amdgpu_dm_i2c_xfer, 3397 .functionality = amdgpu_dm_i2c_func, 3398 }; 3399 3400 struct amdgpu_i2c_adapter * 3401 amdgpu_dm_create_i2c(struct ddc_service *ddc_service, bool oem) 3402 { 3403 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 3404 struct amdgpu_i2c_adapter *i2c; 3405 3406 i2c = kzalloc_obj(struct amdgpu_i2c_adapter); 3407 if (!i2c) 3408 return NULL; 3409 i2c->base.owner = THIS_MODULE; 3410 i2c->base.dev.parent = &adev->pdev->dev; 3411 i2c->base.algo = &amdgpu_dm_i2c_algo; 3412 if (oem) 3413 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c OEM bus"); 3414 else 3415 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", 3416 ddc_service->link->link_index); 3417 i2c_set_adapdata(&i2c->base, i2c); 3418 i2c->ddc_service = ddc_service; 3419 i2c->oem = oem; 3420 3421 return i2c; 3422 } 3423 3424 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector) 3425 { 3426 struct cec_connector_info conn_info; 3427 struct drm_device *ddev = aconnector->base.dev; 3428 struct device *hdmi_dev = ddev->dev; 3429 3430 if (amdgpu_dc_debug_mask & DC_DISABLE_HDMI_CEC) { 3431 drm_info(ddev, "HDMI-CEC feature masked\n"); 3432 return -EINVAL; 3433 } 3434 3435 cec_fill_conn_info_from_drm(&conn_info, &aconnector->base); 3436 aconnector->notifier = 3437 cec_notifier_conn_register(hdmi_dev, NULL, &conn_info); 3438 if (!aconnector->notifier) { 3439 drm_err(ddev, "Failed to create cec notifier\n"); 3440 return -ENOMEM; 3441 } 3442 3443 return 0; 3444 } 3445 3446 /* 3447 * Note: this function assumes that dc_link_detect() was called for the 3448 * dc_link which will be represented by this aconnector. 3449 */ 3450 int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 3451 struct amdgpu_dm_connector *aconnector, 3452 u32 link_index, 3453 struct amdgpu_encoder *aencoder) 3454 { 3455 int res = 0; 3456 int connector_type; 3457 struct dc *dc = dm->dc; 3458 struct dc_link *link = dc_get_link_at_index(dc, link_index); 3459 struct amdgpu_i2c_adapter *i2c; 3460 3461 /* Not needed for writeback connector */ 3462 link->priv = aconnector; 3463 3464 3465 i2c = amdgpu_dm_create_i2c(link->ddc, false); 3466 if (!i2c) { 3467 drm_err(adev_to_drm(dm->adev), "Failed to create i2c adapter data\n"); 3468 return -ENOMEM; 3469 } 3470 3471 aconnector->i2c = i2c; 3472 res = devm_i2c_add_adapter(dm->adev->dev, &i2c->base); 3473 3474 if (res) { 3475 drm_err(adev_to_drm(dm->adev), "Failed to register hw i2c %d\n", link->link_index); 3476 goto out_free; 3477 } 3478 3479 connector_type = to_drm_connector_type(link->connector_signal, link->link_id.id); 3480 3481 res = drm_connector_init_with_ddc( 3482 dm->ddev, 3483 &aconnector->base, 3484 &amdgpu_dm_connector_funcs, 3485 connector_type, 3486 &i2c->base); 3487 3488 if (res) { 3489 drm_err(adev_to_drm(dm->adev), "connector_init failed\n"); 3490 aconnector->connector_id = -1; 3491 goto out_free; 3492 } 3493 3494 drm_connector_helper_add( 3495 &aconnector->base, 3496 &amdgpu_dm_connector_helper_funcs); 3497 3498 amdgpu_dm_connector_init_helper( 3499 dm, 3500 aconnector, 3501 connector_type, 3502 link, 3503 link_index); 3504 3505 drm_connector_attach_encoder( 3506 &aconnector->base, &aencoder->base); 3507 3508 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 3509 connector_type == DRM_MODE_CONNECTOR_HDMIB) 3510 amdgpu_dm_initialize_hdmi_connector(aconnector); 3511 3512 if (dc_is_dp_signal(link->connector_signal)) 3513 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 3514 3515 out_free: 3516 if (res) { 3517 kfree(i2c); 3518 aconnector->i2c = NULL; 3519 } 3520 return res; 3521 } 3522 3523 static int dm_force_atomic_commit(struct drm_connector *connector) 3524 { 3525 int ret = 0; 3526 struct drm_device *ddev = connector->dev; 3527 struct drm_atomic_commit *state = drm_atomic_commit_alloc(ddev); 3528 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 3529 struct drm_plane *plane = disconnected_acrtc->base.primary; 3530 struct drm_connector_state *conn_state; 3531 struct drm_crtc_state *crtc_state; 3532 struct drm_plane_state *plane_state; 3533 3534 if (!state) 3535 return -ENOMEM; 3536 3537 state->acquire_ctx = ddev->mode_config.acquire_ctx; 3538 3539 /* Construct an atomic state to restore previous display setting */ 3540 3541 /* 3542 * Attach connectors to drm_atomic_commit 3543 */ 3544 conn_state = drm_atomic_get_connector_state(state, connector); 3545 3546 /* Check for error in getting connector state */ 3547 if (IS_ERR(conn_state)) { 3548 ret = PTR_ERR(conn_state); 3549 goto out; 3550 } 3551 3552 /* Attach crtc to drm_atomic_commit*/ 3553 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 3554 3555 /* Check for error in getting crtc state */ 3556 if (IS_ERR(crtc_state)) { 3557 ret = PTR_ERR(crtc_state); 3558 goto out; 3559 } 3560 3561 /* force a restore */ 3562 crtc_state->mode_changed = true; 3563 3564 /* Attach plane to drm_atomic_commit */ 3565 plane_state = drm_atomic_get_plane_state(state, plane); 3566 3567 /* Check for error in getting plane state */ 3568 if (IS_ERR(plane_state)) { 3569 ret = PTR_ERR(plane_state); 3570 goto out; 3571 } 3572 3573 /* Call commit internally with the state we just constructed */ 3574 ret = drm_atomic_commit(state); 3575 3576 out: 3577 drm_atomic_commit_put(state); 3578 if (ret) 3579 drm_err(ddev, "Restoring old state failed with %i\n", ret); 3580 3581 return ret; 3582 } 3583 3584 /* 3585 * This function handles all cases when set mode does not come upon hotplug. 3586 * This includes when a display is unplugged then plugged back into the 3587 * same port and when running without usermode desktop manager support 3588 */ 3589 void dm_restore_drm_connector_state(struct drm_device *dev, 3590 struct drm_connector *connector) 3591 { 3592 struct amdgpu_dm_connector *aconnector; 3593 struct amdgpu_crtc *disconnected_acrtc; 3594 struct dm_crtc_state *acrtc_state; 3595 3596 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3597 return; 3598 3599 aconnector = to_amdgpu_dm_connector(connector); 3600 3601 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 3602 return; 3603 3604 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 3605 if (!disconnected_acrtc) 3606 return; 3607 3608 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 3609 if (!acrtc_state->stream) 3610 return; 3611 3612 /* 3613 * If the previous sink is not released and different from the current, 3614 * we deduce we are in a state where we can not rely on usermode call 3615 * to turn on the display, so we do it here 3616 */ 3617 if (acrtc_state->stream->sink != aconnector->dc_sink) 3618 dm_force_atomic_commit(&aconnector->base); 3619 } 3620 3621 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 3622 unsigned int offset, 3623 unsigned int total_length, 3624 u8 *data, 3625 unsigned int length, 3626 struct amdgpu_hdmi_vsdb_info *vsdb) 3627 { 3628 bool res; 3629 union dmub_rb_cmd cmd; 3630 struct dmub_cmd_send_edid_cea *input; 3631 struct dmub_cmd_edid_cea_output *output; 3632 3633 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 3634 return false; 3635 3636 memset(&cmd, 0, sizeof(cmd)); 3637 3638 input = &cmd.edid_cea.data.input; 3639 3640 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 3641 cmd.edid_cea.header.sub_type = 0; 3642 cmd.edid_cea.header.payload_bytes = 3643 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 3644 input->offset = offset; 3645 input->length = length; 3646 input->cea_total_length = total_length; 3647 memcpy(input->payload, data, length); 3648 3649 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 3650 if (!res) { 3651 drm_err(adev_to_drm(dm->adev), "EDID CEA parser failed\n"); 3652 return false; 3653 } 3654 3655 output = &cmd.edid_cea.data.output; 3656 3657 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 3658 if (!output->ack.success) { 3659 drm_err(adev_to_drm(dm->adev), "EDID CEA ack failed at offset %d\n", 3660 output->ack.offset); 3661 } 3662 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 3663 if (!output->amd_vsdb.vsdb_found) 3664 return false; 3665 3666 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 3667 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 3668 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 3669 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 3670 vsdb->freesync_mccs_vcp_code = output->amd_vsdb.freesync_mccs_vcp_code; 3671 } else { 3672 drm_warn(adev_to_drm(dm->adev), "Unknown EDID CEA parser results\n"); 3673 return false; 3674 } 3675 3676 return true; 3677 } 3678 3679 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 3680 u8 *edid_ext, int len, 3681 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3682 { 3683 int i; 3684 3685 /* send extension block to DMCU for parsing */ 3686 for (i = 0; i < len; i += 8) { 3687 bool res; 3688 int offset; 3689 3690 /* send 8 bytes a time */ 3691 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 3692 return false; 3693 3694 if (i+8 == len) { 3695 /* EDID block sent completed, expect result */ 3696 int version, min_rate, max_rate; 3697 3698 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 3699 if (res) { 3700 /* amd vsdb found */ 3701 vsdb_info->freesync_supported = 1; 3702 vsdb_info->amd_vsdb_version = version; 3703 vsdb_info->min_refresh_rate_hz = min_rate; 3704 vsdb_info->max_refresh_rate_hz = max_rate; 3705 /* Not enabled on DMCU*/ 3706 vsdb_info->freesync_mccs_vcp_code = 0; 3707 return true; 3708 } 3709 /* not amd vsdb */ 3710 return false; 3711 } 3712 3713 /* check for ack*/ 3714 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 3715 if (!res) 3716 return false; 3717 } 3718 3719 return false; 3720 } 3721 3722 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 3723 u8 *edid_ext, int len, 3724 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3725 { 3726 int i; 3727 3728 /* send extension block to DMCU for parsing */ 3729 for (i = 0; i < len; i += 8) { 3730 /* send 8 bytes a time */ 3731 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 3732 return false; 3733 } 3734 3735 return vsdb_info->freesync_supported; 3736 } 3737 3738 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 3739 u8 *edid_ext, int len, 3740 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3741 { 3742 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 3743 bool ret; 3744 3745 mutex_lock(&adev->dm.dc_lock); 3746 if (adev->dm.dmub_srv) 3747 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 3748 else 3749 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 3750 mutex_unlock(&adev->dm.dc_lock); 3751 return ret; 3752 } 3753 3754 STATIC_IFN_KUNIT void parse_edid_displayid_vrr(struct drm_connector *connector, 3755 const struct edid *edid) 3756 { 3757 u8 *edid_ext = NULL; 3758 int i; 3759 int j = 0; 3760 u16 min_vfreq; 3761 u16 max_vfreq; 3762 3763 if (!edid || !edid->extensions) 3764 return; 3765 3766 /* Find DisplayID extension */ 3767 for (i = 0; i < edid->extensions; i++) { 3768 edid_ext = (void *)(edid + (i + 1)); 3769 if (edid_ext[0] == DISPLAYID_EXT) 3770 break; 3771 } 3772 3773 if (i == edid->extensions) 3774 return; 3775 3776 while (j < EDID_LENGTH) { 3777 /* Get dynamic video timing range from DisplayID if available */ 3778 if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25 && 3779 (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) { 3780 min_vfreq = edid_ext[j+9]; 3781 if (edid_ext[j+1] & 7) 3782 max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8); 3783 else 3784 max_vfreq = edid_ext[j+10]; 3785 3786 if (max_vfreq && min_vfreq) { 3787 connector->display_info.monitor_range.max_vfreq = max_vfreq; 3788 connector->display_info.monitor_range.min_vfreq = min_vfreq; 3789 3790 return; 3791 } 3792 } 3793 j++; 3794 } 3795 } 3796 EXPORT_IF_KUNIT(parse_edid_displayid_vrr); 3797 3798 STATIC_IFN_KUNIT int get_amd_vsdb(struct amdgpu_dm_connector *aconnector, 3799 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3800 { 3801 struct drm_connector *connector = &aconnector->base; 3802 3803 vsdb_info->replay_mode = connector->display_info.amd_vsdb.replay_mode; 3804 vsdb_info->amd_vsdb_version = connector->display_info.amd_vsdb.version; 3805 3806 return connector->display_info.amd_vsdb.version != 0; 3807 } 3808 EXPORT_IF_KUNIT(get_amd_vsdb); 3809 3810 STATIC_IFN_KUNIT int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 3811 const struct edid *edid, 3812 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3813 { 3814 u8 *edid_ext = NULL; 3815 int i; 3816 bool valid_vsdb_found = false; 3817 3818 /*----- drm_find_cea_extension() -----*/ 3819 /* No EDID or EDID extensions */ 3820 if (edid == NULL || edid->extensions == 0) 3821 return -ENODEV; 3822 3823 /* Find CEA extension */ 3824 for (i = 0; i < edid->extensions; i++) { 3825 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 3826 if (edid_ext[0] == CEA_EXT) 3827 break; 3828 } 3829 3830 if (i == edid->extensions) 3831 return -ENODEV; 3832 3833 /*----- cea_db_offsets() -----*/ 3834 if (edid_ext[0] != CEA_EXT) 3835 return -ENODEV; 3836 3837 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 3838 3839 return valid_vsdb_found ? i : -ENODEV; 3840 } 3841 EXPORT_IF_KUNIT(parse_hdmi_amd_vsdb); 3842 3843 /** 3844 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 3845 * 3846 * @connector: Connector to query. 3847 * @drm_edid: DRM EDID from monitor 3848 * @do_mccs: Controls whether MCCS (Monitor Control Command Set) over 3849 * DDC (Display Data Channel) transactions are performed. When true, 3850 * the driver queries the monitor to get or update additional FreeSync 3851 * capability information. When false, these transactions are skipped. 3852 * 3853 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 3854 * track of some of the display information in the internal data struct used by 3855 * amdgpu_dm. This function checks which type of connector we need to set the 3856 * FreeSync parameters. 3857 */ 3858 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 3859 const struct drm_edid *drm_edid, bool do_mccs) 3860 { 3861 int i = 0; 3862 struct amdgpu_dm_connector *amdgpu_dm_connector = 3863 to_amdgpu_dm_connector(connector); 3864 struct dm_connector_state *dm_con_state = NULL; 3865 struct dc_sink *sink; 3866 struct amdgpu_device *adev = drm_to_adev(connector->dev); 3867 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 3868 const struct edid *edid; 3869 bool freesync_capable = false; 3870 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 3871 3872 if (!connector->state) { 3873 drm_err(adev_to_drm(adev), "%s - Connector has no state", __func__); 3874 goto update; 3875 } 3876 3877 sink = amdgpu_dm_connector->dc_sink ? 3878 amdgpu_dm_connector->dc_sink : 3879 amdgpu_dm_connector->dc_em_sink; 3880 3881 drm_edid_connector_update(connector, drm_edid); 3882 3883 if (!drm_edid || !sink) { 3884 dm_con_state = to_dm_connector_state(connector->state); 3885 3886 amdgpu_dm_connector->min_vfreq = 0; 3887 amdgpu_dm_connector->max_vfreq = 0; 3888 freesync_capable = false; 3889 3890 goto update; 3891 } 3892 3893 dm_con_state = to_dm_connector_state(connector->state); 3894 3895 if (!adev->dm.freesync_module || !dc_supports_vrr(sink->ctx->dce_version)) 3896 goto update; 3897 3898 /* FIXME: Get rid of drm_edid_raw() */ 3899 edid = drm_edid_raw(drm_edid); 3900 3901 /* Some eDP panels only have the refresh rate range info in DisplayID */ 3902 if ((connector->display_info.monitor_range.min_vfreq == 0 || 3903 connector->display_info.monitor_range.max_vfreq == 0)) 3904 parse_edid_displayid_vrr(connector, edid); 3905 3906 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 3907 sink->sink_signal == SIGNAL_TYPE_EDP)) { 3908 if (amdgpu_dm_connector->dc_link && 3909 amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { 3910 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; 3911 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; 3912 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 3913 freesync_capable = true; 3914 } 3915 3916 get_amd_vsdb(amdgpu_dm_connector, &vsdb_info); 3917 3918 if (vsdb_info.replay_mode) { 3919 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; 3920 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; 3921 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; 3922 } 3923 3924 } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 3925 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 3926 if (i >= 0) { 3927 amdgpu_dm_connector->vsdb_info = vsdb_info; 3928 sink->edid_caps.freesync_vcp_code = vsdb_info.freesync_mccs_vcp_code; 3929 3930 if (vsdb_info.freesync_supported) { 3931 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 3932 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 3933 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 3934 freesync_capable = true; 3935 3936 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 3937 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 3938 } 3939 } 3940 } 3941 3942 if (amdgpu_dm_connector->dc_link) 3943 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 3944 3945 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 3946 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 3947 if (i >= 0) { 3948 amdgpu_dm_connector->vsdb_info = vsdb_info; 3949 sink->edid_caps.freesync_vcp_code = vsdb_info.freesync_mccs_vcp_code; 3950 3951 if (vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 3952 amdgpu_dm_connector->pack_sdp_v1_3 = true; 3953 amdgpu_dm_connector->as_type = as_type; 3954 3955 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 3956 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 3957 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 3958 freesync_capable = true; 3959 3960 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 3961 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 3962 } 3963 } 3964 } 3965 3966 /* Handle MCCS */ 3967 if (do_mccs) { 3968 dm_helpers_read_mccs_caps(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink); 3969 3970 if (sink->edid_caps.freesync_vcp_code && !sink->mccs_caps.freesync_supported) 3971 freesync_capable = false; 3972 3973 if (sink->mccs_caps.freesync_supported && freesync_capable) 3974 dm_helpers_mccs_vcp_set(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink); 3975 } 3976 3977 update: 3978 if (dm_con_state) 3979 dm_con_state->freesync_capable = freesync_capable; 3980 3981 if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable && 3982 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) { 3983 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false; 3984 amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false; 3985 } 3986 3987 if (connector->vrr_capable_property) 3988 drm_connector_set_vrr_capable_property(connector, 3989 freesync_capable); 3990 } 3991