1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_11_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v11_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_11_0_2_offset.h"
43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_11_0_offset.h"
45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
66 MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
67
68 #define SMU11_VOLTAGE_SCALE 4
69
70 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
71
72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
73 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
75 #define smnPCIE_LC_SPEED_CNTL 0x11140290
76 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
78
79 #define mmTHM_BACO_CNTL_ARCT 0xA7
80 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
81
smu_v11_0_poll_baco_exit(struct smu_context * smu)82 static void smu_v11_0_poll_baco_exit(struct smu_context *smu)
83 {
84 struct amdgpu_device *adev = smu->adev;
85 uint32_t data, loop = 0;
86
87 do {
88 usleep_range(1000, 1100);
89 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
90 } while ((data & 0x100) && (++loop < 100));
91 }
92
smu_v11_0_init_microcode(struct smu_context * smu)93 int smu_v11_0_init_microcode(struct smu_context *smu)
94 {
95 struct amdgpu_device *adev = smu->adev;
96 char ucode_prefix[25];
97 int err = 0;
98 const struct smc_firmware_header_v1_0 *hdr;
99 const struct common_firmware_header *header;
100 struct amdgpu_firmware_info *ucode = NULL;
101
102 if (amdgpu_sriov_vf(adev) &&
103 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) ||
104 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7))))
105 return 0;
106
107 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
108 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
109 "amdgpu/%s.bin", ucode_prefix);
110 if (err)
111 goto out;
112
113 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
114 amdgpu_ucode_print_smc_hdr(&hdr->header);
115 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
116
117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
118 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
119 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
120 ucode->fw = adev->pm.fw;
121 header = (const struct common_firmware_header *)ucode->fw->data;
122 adev->firmware.fw_size +=
123 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
124 }
125
126 out:
127 if (err)
128 amdgpu_ucode_release(&adev->pm.fw);
129 return err;
130 }
131
smu_v11_0_fini_microcode(struct smu_context * smu)132 void smu_v11_0_fini_microcode(struct smu_context *smu)
133 {
134 struct amdgpu_device *adev = smu->adev;
135
136 amdgpu_ucode_release(&adev->pm.fw);
137 adev->pm.fw_version = 0;
138 }
139
smu_v11_0_load_microcode(struct smu_context * smu)140 int smu_v11_0_load_microcode(struct smu_context *smu)
141 {
142 struct amdgpu_device *adev = smu->adev;
143 const uint32_t *src;
144 const struct smc_firmware_header_v1_0 *hdr;
145 uint32_t addr_start = MP1_SRAM;
146 uint32_t i;
147 uint32_t smc_fw_size;
148 uint32_t mp1_fw_flags;
149
150 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
151 src = (const uint32_t *)(adev->pm.fw->data +
152 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
153 smc_fw_size = hdr->header.ucode_size_bytes;
154
155 for (i = 1; i < smc_fw_size/4 - 1; i++) {
156 WREG32_PCIE(addr_start, src[i]);
157 addr_start += 4;
158 }
159
160 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
161 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
162 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
163 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
164
165 for (i = 0; i < adev->usec_timeout; i++) {
166 mp1_fw_flags = RREG32_PCIE(MP1_Public |
167 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
168 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
169 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
170 break;
171 udelay(1);
172 }
173
174 if (i == adev->usec_timeout)
175 return -ETIME;
176
177 return 0;
178 }
179
smu_v11_0_check_fw_status(struct smu_context * smu)180 int smu_v11_0_check_fw_status(struct smu_context *smu)
181 {
182 struct amdgpu_device *adev = smu->adev;
183 uint32_t mp1_fw_flags;
184
185 mp1_fw_flags = RREG32_PCIE(MP1_Public |
186 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
187
188 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
189 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
190 return 0;
191
192 return -EIO;
193 }
194
smu_v11_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)195 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
196 {
197 struct amdgpu_device *adev = smu->adev;
198 uint32_t ppt_offset_bytes;
199 const struct smc_firmware_header_v2_0 *v2;
200
201 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
202
203 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
204 *size = le32_to_cpu(v2->ppt_size_bytes);
205 *table = (uint8_t *)v2 + ppt_offset_bytes;
206
207 return 0;
208 }
209
smu_v11_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)210 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
211 uint32_t *size, uint32_t pptable_id)
212 {
213 struct amdgpu_device *adev = smu->adev;
214 const struct smc_firmware_header_v2_1 *v2_1;
215 struct smc_soft_pptable_entry *entries;
216 uint32_t pptable_count = 0;
217 int i = 0;
218
219 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
220 entries = (struct smc_soft_pptable_entry *)
221 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
222 pptable_count = le32_to_cpu(v2_1->pptable_count);
223 for (i = 0; i < pptable_count; i++) {
224 if (le32_to_cpu(entries[i].id) == pptable_id) {
225 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
226 *size = le32_to_cpu(entries[i].ppt_size_bytes);
227 break;
228 }
229 }
230
231 if (i == pptable_count)
232 return -EINVAL;
233
234 return 0;
235 }
236
smu_v11_0_setup_pptable(struct smu_context * smu)237 int smu_v11_0_setup_pptable(struct smu_context *smu)
238 {
239 struct amdgpu_device *adev = smu->adev;
240 const struct smc_firmware_header_v1_0 *hdr;
241 int ret, index;
242 uint32_t size = 0;
243 uint16_t atom_table_size;
244 uint8_t frev, crev;
245 void *table;
246 uint16_t version_major, version_minor;
247
248 if (!amdgpu_sriov_vf(adev)) {
249 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
250 version_major = le16_to_cpu(hdr->header.header_version_major);
251 version_minor = le16_to_cpu(hdr->header.header_version_minor);
252 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
253 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
254 switch (version_minor) {
255 case 0:
256 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
257 break;
258 case 1:
259 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
260 smu->smu_table.boot_values.pp_table_id);
261 break;
262 default:
263 ret = -EINVAL;
264 break;
265 }
266 if (ret)
267 return ret;
268 goto out;
269 }
270 }
271
272 dev_info(adev->dev, "use vbios provided pptable\n");
273 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
274 powerplayinfo);
275
276 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
277 (uint8_t **)&table);
278 if (ret)
279 return ret;
280 size = atom_table_size;
281
282 out:
283 if (!smu->smu_table.power_play_table)
284 smu->smu_table.power_play_table = table;
285 if (!smu->smu_table.power_play_table_size)
286 smu->smu_table.power_play_table_size = size;
287
288 return 0;
289 }
290
smu_v11_0_init_smc_tables(struct smu_context * smu)291 int smu_v11_0_init_smc_tables(struct smu_context *smu)
292 {
293 struct smu_table_context *smu_table = &smu->smu_table;
294 struct smu_table *tables = smu_table->tables;
295 int ret = 0;
296
297 smu_table->driver_pptable =
298 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
299 if (!smu_table->driver_pptable) {
300 ret = -ENOMEM;
301 goto err0_out;
302 }
303
304 smu_table->max_sustainable_clocks =
305 kzalloc_obj(struct smu_11_0_max_sustainable_clocks);
306 if (!smu_table->max_sustainable_clocks) {
307 ret = -ENOMEM;
308 goto err1_out;
309 }
310
311 /* Arcturus does not support OVERDRIVE */
312 if (tables[SMU_TABLE_OVERDRIVE].size) {
313 smu_table->overdrive_table =
314 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
315 if (!smu_table->overdrive_table) {
316 ret = -ENOMEM;
317 goto err2_out;
318 }
319
320 smu_table->boot_overdrive_table =
321 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
322 if (!smu_table->boot_overdrive_table) {
323 ret = -ENOMEM;
324 goto err3_out;
325 }
326
327 smu_table->user_overdrive_table =
328 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
329 if (!smu_table->user_overdrive_table) {
330 ret = -ENOMEM;
331 goto err4_out;
332 }
333
334 }
335
336 return 0;
337
338 err4_out:
339 kfree(smu_table->boot_overdrive_table);
340 err3_out:
341 kfree(smu_table->overdrive_table);
342 err2_out:
343 kfree(smu_table->max_sustainable_clocks);
344 err1_out:
345 kfree(smu_table->driver_pptable);
346 err0_out:
347 return ret;
348 }
349
smu_v11_0_fini_smc_tables(struct smu_context * smu)350 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
351 {
352 struct smu_table_context *smu_table = &smu->smu_table;
353 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
354
355 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
356 kfree(smu_table->user_overdrive_table);
357 kfree(smu_table->boot_overdrive_table);
358 kfree(smu_table->overdrive_table);
359 kfree(smu_table->max_sustainable_clocks);
360 kfree(smu_table->driver_pptable);
361 kfree(smu_table->clocks_table);
362 smu_table->user_overdrive_table = NULL;
363 smu_table->boot_overdrive_table = NULL;
364 smu_table->overdrive_table = NULL;
365 smu_table->max_sustainable_clocks = NULL;
366 smu_table->driver_pptable = NULL;
367 smu_table->clocks_table = NULL;
368 kfree(smu_table->hardcode_pptable);
369 smu_table->hardcode_pptable = NULL;
370
371 kfree(smu_table->driver_smu_config_table);
372 kfree(smu_table->ecc_table);
373 kfree(smu_table->metrics_table);
374 kfree(smu_table->watermarks_table);
375 smu_table->driver_smu_config_table = NULL;
376 smu_table->ecc_table = NULL;
377 smu_table->metrics_table = NULL;
378 smu_table->watermarks_table = NULL;
379 smu_table->metrics_time = 0;
380
381 kfree(smu_dpm->dpm_context);
382 kfree(smu_dpm->golden_dpm_context);
383 kfree(smu_dpm->dpm_current_power_state);
384 kfree(smu_dpm->dpm_request_power_state);
385 smu_dpm->dpm_context = NULL;
386 smu_dpm->golden_dpm_context = NULL;
387 smu_dpm->dpm_context_size = 0;
388 smu_dpm->dpm_current_power_state = NULL;
389 smu_dpm->dpm_request_power_state = NULL;
390
391 return 0;
392 }
393
smu_v11_0_init_power(struct smu_context * smu)394 int smu_v11_0_init_power(struct smu_context *smu)
395 {
396 struct amdgpu_device *adev = smu->adev;
397 struct smu_power_context *smu_power = &smu->smu_power;
398 u32 ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0);
399 size_t size = ((ip_version == IP_VERSION(11, 5, 0)) ||
400 (ip_version == IP_VERSION(11, 5, 2))) ?
401 sizeof(struct smu_11_5_power_context) :
402 sizeof(struct smu_11_0_power_context);
403
404 smu_power->power_context = kzalloc(size, GFP_KERNEL);
405 if (!smu_power->power_context)
406 return -ENOMEM;
407 smu_power->power_context_size = size;
408
409 return 0;
410 }
411
smu_v11_0_fini_power(struct smu_context * smu)412 int smu_v11_0_fini_power(struct smu_context *smu)
413 {
414 struct smu_power_context *smu_power = &smu->smu_power;
415
416 kfree(smu_power->power_context);
417 smu_power->power_context = NULL;
418 smu_power->power_context_size = 0;
419
420 return 0;
421 }
422
smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device * adev,uint8_t clk_id,uint8_t syspll_id,uint32_t * clk_freq)423 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
424 uint8_t clk_id,
425 uint8_t syspll_id,
426 uint32_t *clk_freq)
427 {
428 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
429 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
430 int ret, index;
431
432 input.clk_id = clk_id;
433 input.syspll_id = syspll_id;
434 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
435 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
436 getsmuclockinfo);
437
438 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
439 (uint32_t *)&input, sizeof(input));
440 if (ret)
441 return -EINVAL;
442
443 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
444 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
445
446 return 0;
447 }
448
smu_v11_0_get_vbios_bootup_values(struct smu_context * smu)449 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
450 {
451 int ret, index;
452 uint16_t size;
453 uint8_t frev, crev;
454 struct atom_common_table_header *header;
455 struct atom_firmware_info_v3_3 *v_3_3;
456 struct atom_firmware_info_v3_1 *v_3_1;
457
458 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
459 firmwareinfo);
460
461 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
462 (uint8_t **)&header);
463 if (ret)
464 return ret;
465
466 if (header->format_revision != 3) {
467 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
468 return -EINVAL;
469 }
470
471 switch (header->content_revision) {
472 case 0:
473 case 1:
474 case 2:
475 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
476 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
477 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
478 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
479 smu->smu_table.boot_values.socclk = 0;
480 smu->smu_table.boot_values.dcefclk = 0;
481 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
482 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
483 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
484 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
485 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
486 smu->smu_table.boot_values.pp_table_id = 0;
487 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
488 break;
489 case 3:
490 case 4:
491 default:
492 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
493 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
494 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
495 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
496 smu->smu_table.boot_values.socclk = 0;
497 smu->smu_table.boot_values.dcefclk = 0;
498 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
499 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
500 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
501 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
502 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
503 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
504 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
505 }
506
507 smu->smu_table.boot_values.format_revision = header->format_revision;
508 smu->smu_table.boot_values.content_revision = header->content_revision;
509
510 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
511 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
512 (uint8_t)0,
513 &smu->smu_table.boot_values.socclk);
514
515 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
516 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
517 (uint8_t)0,
518 &smu->smu_table.boot_values.dcefclk);
519
520 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
521 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
522 (uint8_t)0,
523 &smu->smu_table.boot_values.eclk);
524
525 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
526 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
527 (uint8_t)0,
528 &smu->smu_table.boot_values.vclk);
529
530 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
531 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
532 (uint8_t)0,
533 &smu->smu_table.boot_values.dclk);
534
535 if ((smu->smu_table.boot_values.format_revision == 3) &&
536 (smu->smu_table.boot_values.content_revision >= 2))
537 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
538 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
539 (uint8_t)SMU11_SYSPLL1_2_ID,
540 &smu->smu_table.boot_values.fclk);
541
542 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
543 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
544 (uint8_t)SMU11_SYSPLL3_1_ID,
545 &smu->smu_table.boot_values.lclk);
546
547 return 0;
548 }
549
smu_v11_0_notify_memory_pool_location(struct smu_context * smu)550 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
551 {
552 struct smu_table_context *smu_table = &smu->smu_table;
553 struct smu_table *memory_pool = &smu_table->memory_pool;
554 int ret = 0;
555 uint64_t address;
556 uint32_t address_low, address_high;
557
558 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
559 return ret;
560
561 address = (uintptr_t)memory_pool->cpu_addr;
562 address_high = (uint32_t)upper_32_bits(address);
563 address_low = (uint32_t)lower_32_bits(address);
564
565 ret = smu_cmn_send_smc_msg_with_param(smu,
566 SMU_MSG_SetSystemVirtualDramAddrHigh,
567 address_high,
568 NULL);
569 if (ret)
570 return ret;
571 ret = smu_cmn_send_smc_msg_with_param(smu,
572 SMU_MSG_SetSystemVirtualDramAddrLow,
573 address_low,
574 NULL);
575 if (ret)
576 return ret;
577
578 address = memory_pool->mc_address;
579 address_high = (uint32_t)upper_32_bits(address);
580 address_low = (uint32_t)lower_32_bits(address);
581
582 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
583 address_high, NULL);
584 if (ret)
585 return ret;
586 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
587 address_low, NULL);
588 if (ret)
589 return ret;
590 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
591 (uint32_t)memory_pool->size, NULL);
592 if (ret)
593 return ret;
594
595 return ret;
596 }
597
smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)598 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
599 {
600 int ret;
601
602 ret = smu_cmn_send_smc_msg_with_param(smu,
603 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
604 if (ret)
605 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
606
607 return ret;
608 }
609
smu_v11_0_set_driver_table_location(struct smu_context * smu)610 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
611 {
612 struct smu_table *driver_table = &smu->smu_table.driver_table;
613 int ret = 0;
614
615 if (driver_table->mc_address) {
616 ret = smu_cmn_send_smc_msg_with_param(smu,
617 SMU_MSG_SetDriverDramAddrHigh,
618 upper_32_bits(driver_table->mc_address),
619 NULL);
620 if (!ret)
621 ret = smu_cmn_send_smc_msg_with_param(smu,
622 SMU_MSG_SetDriverDramAddrLow,
623 lower_32_bits(driver_table->mc_address),
624 NULL);
625 }
626
627 return ret;
628 }
629
smu_v11_0_set_tool_table_location(struct smu_context * smu)630 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
631 {
632 int ret = 0;
633 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
634
635 if (tool_table->mc_address) {
636 ret = smu_cmn_send_smc_msg_with_param(smu,
637 SMU_MSG_SetToolsDramAddrHigh,
638 upper_32_bits(tool_table->mc_address),
639 NULL);
640 if (!ret)
641 ret = smu_cmn_send_smc_msg_with_param(smu,
642 SMU_MSG_SetToolsDramAddrLow,
643 lower_32_bits(tool_table->mc_address),
644 NULL);
645 }
646
647 return ret;
648 }
649
smu_v11_0_init_display_count(struct smu_context * smu,uint32_t count)650 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
651 {
652 struct amdgpu_device *adev = smu->adev;
653
654 /* Navy_Flounder/Dimgrey_Cavefish do not support to change
655 * display num currently
656 */
657 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11) ||
658 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
659 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2) ||
660 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 12) ||
661 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
662 return 0;
663
664 return smu_cmn_send_smc_msg_with_param(smu,
665 SMU_MSG_NumOfDisplays,
666 count,
667 NULL);
668 }
669
670
smu_v11_0_set_allowed_mask(struct smu_context * smu)671 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
672 {
673 struct smu_feature *feature = &smu->smu_feature;
674 int ret = 0;
675 uint32_t feature_mask[2];
676
677 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
678 feature->feature_num < SMU_FEATURE_NUM_DEFAULT) {
679 ret = -EINVAL;
680 goto failed;
681 }
682
683 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
684
685 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
686 feature_mask[1], NULL);
687 if (ret)
688 goto failed;
689
690 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
691 feature_mask[0], NULL);
692 if (ret)
693 goto failed;
694
695 failed:
696 return ret;
697 }
698
smu_v11_0_system_features_control(struct smu_context * smu,bool en)699 int smu_v11_0_system_features_control(struct smu_context *smu,
700 bool en)
701 {
702 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
703 SMU_MSG_DisableAllSmuFeatures), NULL);
704 }
705
smu_v11_0_notify_display_change(struct smu_context * smu)706 int smu_v11_0_notify_display_change(struct smu_context *smu)
707 {
708 int ret = 0;
709
710 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
711 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
712 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
713
714 return ret;
715 }
716
717 static int
smu_v11_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)718 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
719 enum smu_clk_type clock_select)
720 {
721 int ret = 0;
722 int clk_id;
723
724 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
725 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
726 return 0;
727
728 clk_id = smu_cmn_to_asic_specific_index(smu,
729 CMN2ASIC_MAPPING_CLK,
730 clock_select);
731 if (clk_id < 0)
732 return -EINVAL;
733
734 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
735 clk_id << 16, clock);
736 if (ret) {
737 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
738 return ret;
739 }
740
741 if (*clock != 0)
742 return 0;
743
744 /* if DC limit is zero, return AC limit */
745 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
746 clk_id << 16, clock);
747 if (ret) {
748 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
749 return ret;
750 }
751
752 return 0;
753 }
754
smu_v11_0_init_max_sustainable_clocks(struct smu_context * smu)755 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
756 {
757 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
758 smu->smu_table.max_sustainable_clocks;
759 int ret = 0;
760
761 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
762 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
763 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
764 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
765 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
766 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
767
768 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
769 ret = smu_v11_0_get_max_sustainable_clock(smu,
770 &(max_sustainable_clocks->uclock),
771 SMU_UCLK);
772 if (ret) {
773 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
774 __func__);
775 return ret;
776 }
777 }
778
779 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
780 ret = smu_v11_0_get_max_sustainable_clock(smu,
781 &(max_sustainable_clocks->soc_clock),
782 SMU_SOCCLK);
783 if (ret) {
784 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
785 __func__);
786 return ret;
787 }
788 }
789
790 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
791 ret = smu_v11_0_get_max_sustainable_clock(smu,
792 &(max_sustainable_clocks->dcef_clock),
793 SMU_DCEFCLK);
794 if (ret) {
795 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
796 __func__);
797 return ret;
798 }
799
800 ret = smu_v11_0_get_max_sustainable_clock(smu,
801 &(max_sustainable_clocks->display_clock),
802 SMU_DISPCLK);
803 if (ret) {
804 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
805 __func__);
806 return ret;
807 }
808 ret = smu_v11_0_get_max_sustainable_clock(smu,
809 &(max_sustainable_clocks->phy_clock),
810 SMU_PHYCLK);
811 if (ret) {
812 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
813 __func__);
814 return ret;
815 }
816 ret = smu_v11_0_get_max_sustainable_clock(smu,
817 &(max_sustainable_clocks->pixel_clock),
818 SMU_PIXCLK);
819 if (ret) {
820 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
821 __func__);
822 return ret;
823 }
824 }
825
826 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
827 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
828
829 return 0;
830 }
831
smu_v11_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)832 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
833 uint32_t *power_limit)
834 {
835 int power_src;
836 int ret = 0;
837
838 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
839 return -EINVAL;
840
841 power_src = smu_cmn_to_asic_specific_index(smu,
842 CMN2ASIC_MAPPING_PWR,
843 smu->adev->pm.ac_power ?
844 SMU_POWER_SOURCE_AC :
845 SMU_POWER_SOURCE_DC);
846 if (power_src < 0)
847 return -EINVAL;
848
849 /*
850 * BIT 24-31: ControllerId (only PPT0 is supported for now)
851 * BIT 16-23: PowerSource
852 */
853 ret = smu_cmn_send_smc_msg_with_param(smu,
854 SMU_MSG_GetPptLimit,
855 (0 << 24) | (power_src << 16),
856 power_limit);
857 if (ret)
858 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
859
860 return ret;
861 }
862
smu_v11_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)863 int smu_v11_0_set_power_limit(struct smu_context *smu,
864 enum smu_ppt_limit_type limit_type,
865 uint32_t limit)
866 {
867 int power_src;
868 int ret = 0;
869 uint32_t limit_param;
870
871 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
872 return -EINVAL;
873
874 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
875 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
876 return -EOPNOTSUPP;
877 }
878
879 power_src = smu_cmn_to_asic_specific_index(smu,
880 CMN2ASIC_MAPPING_PWR,
881 smu->adev->pm.ac_power ?
882 SMU_POWER_SOURCE_AC :
883 SMU_POWER_SOURCE_DC);
884 if (power_src < 0)
885 return -EINVAL;
886
887 /*
888 * BIT 24-31: ControllerId (only PPT0 is supported for now)
889 * BIT 16-23: PowerSource
890 * BIT 0-15: PowerLimit
891 */
892 limit_param = (limit & 0xFFFF);
893 limit_param |= 0 << 24;
894 limit_param |= (power_src) << 16;
895 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL);
896 if (ret) {
897 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
898 return ret;
899 }
900
901 smu->current_power_limit = limit;
902
903 return 0;
904 }
905
smu_v11_0_ack_ac_dc_interrupt(struct smu_context * smu)906 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
907 {
908 return smu_cmn_send_smc_msg(smu,
909 SMU_MSG_ReenableAcDcInterrupt,
910 NULL);
911 }
912
smu_v11_0_process_pending_interrupt(struct smu_context * smu)913 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
914 {
915 int ret = 0;
916
917 if (smu->dc_controlled_by_gpio &&
918 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
919 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
920
921 return ret;
922 }
923
smu_v11_0_interrupt_work(struct smu_context * smu)924 void smu_v11_0_interrupt_work(struct smu_context *smu)
925 {
926 if (smu_v11_0_ack_ac_dc_interrupt(smu))
927 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
928 }
929
smu_v11_0_enable_thermal_alert(struct smu_context * smu)930 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
931 {
932 int ret = 0;
933
934 if (smu->smu_table.thermal_controller_type) {
935 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
936 if (ret)
937 return ret;
938 }
939
940 /*
941 * After init there might have been missed interrupts triggered
942 * before driver registers for interrupt (Ex. AC/DC).
943 */
944 return smu_v11_0_process_pending_interrupt(smu);
945 }
946
smu_v11_0_disable_thermal_alert(struct smu_context * smu)947 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
948 {
949 int ret = 0;
950
951 if (smu->smu_table.thermal_controller_type)
952 ret = amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
953
954 return ret;
955 }
956
convert_to_vddc(uint8_t vid)957 static uint16_t convert_to_vddc(uint8_t vid)
958 {
959 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
960 }
961
smu_v11_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)962 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
963 {
964 struct amdgpu_device *adev = smu->adev;
965 uint32_t vdd = 0, val_vid = 0;
966
967 if (!value)
968 return -EINVAL;
969 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
970 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
971 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
972
973 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
974
975 *value = vdd;
976
977 return 0;
978
979 }
980
981 int
smu_v11_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)982 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
983 struct pp_display_clock_request
984 *clock_req)
985 {
986 enum amd_pp_clock_type clk_type = clock_req->clock_type;
987 int ret = 0;
988 enum smu_clk_type clk_select = 0;
989 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
990
991 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
992 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
993 switch (clk_type) {
994 case amd_pp_dcef_clock:
995 clk_select = SMU_DCEFCLK;
996 break;
997 case amd_pp_disp_clock:
998 clk_select = SMU_DISPCLK;
999 break;
1000 case amd_pp_pixel_clock:
1001 clk_select = SMU_PIXCLK;
1002 break;
1003 case amd_pp_phy_clock:
1004 clk_select = SMU_PHYCLK;
1005 break;
1006 case amd_pp_mem_clock:
1007 clk_select = SMU_UCLK;
1008 break;
1009 default:
1010 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1011 ret = -EINVAL;
1012 break;
1013 }
1014
1015 if (ret)
1016 goto failed;
1017
1018 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1019 return 0;
1020
1021 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1022
1023 if(clk_select == SMU_UCLK)
1024 smu->hard_min_uclk_req_from_dal = clk_freq;
1025 }
1026
1027 failed:
1028 return ret;
1029 }
1030
smu_v11_0_gfx_off_control(struct smu_context * smu,bool enable)1031 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1032 {
1033 int ret = 0;
1034 struct amdgpu_device *adev = smu->adev;
1035
1036 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1037 case IP_VERSION(11, 0, 0):
1038 case IP_VERSION(11, 0, 5):
1039 case IP_VERSION(11, 0, 9):
1040 case IP_VERSION(11, 0, 7):
1041 case IP_VERSION(11, 0, 11):
1042 case IP_VERSION(11, 0, 12):
1043 case IP_VERSION(11, 0, 13):
1044 case IP_VERSION(11, 5, 0):
1045 case IP_VERSION(11, 5, 2):
1046 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1047 return 0;
1048 if (enable)
1049 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1050 else
1051 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1052 break;
1053 default:
1054 break;
1055 }
1056
1057 return ret;
1058 }
1059
1060 uint32_t
smu_v11_0_get_fan_control_mode(struct smu_context * smu)1061 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1062 {
1063 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1064 return AMD_FAN_CTRL_AUTO;
1065 else
1066 return smu->user_dpm_profile.fan_mode;
1067 }
1068
1069 static int
smu_v11_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1070 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1071 {
1072 int ret = 0;
1073
1074 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1075 return 0;
1076
1077 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1078 if (ret)
1079 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1080 __func__, (auto_fan_control ? "Start" : "Stop"));
1081
1082 return ret;
1083 }
1084
1085 static int
smu_v11_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1086 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1087 {
1088 struct amdgpu_device *adev = smu->adev;
1089
1090 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1091 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1092 CG_FDO_CTRL2, TMIN, 0));
1093 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1094 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1095 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1096
1097 return 0;
1098 }
1099
1100 int
smu_v11_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1101 smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed)
1102 {
1103 struct amdgpu_device *adev = smu->adev;
1104 uint32_t duty100, duty;
1105 uint64_t tmp64;
1106
1107 speed = min_t(uint32_t, speed, 255);
1108
1109 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1110 CG_FDO_CTRL1, FMAX_DUTY100);
1111 if (!duty100)
1112 return -EINVAL;
1113
1114 tmp64 = (uint64_t)speed * duty100;
1115 do_div(tmp64, 255);
1116 duty = (uint32_t)tmp64;
1117
1118 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1119 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1120 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1121
1122 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1123 }
1124
smu_v11_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1125 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1126 uint32_t speed)
1127 {
1128 struct amdgpu_device *adev = smu->adev;
1129 /*
1130 * crystal_clock_freq used for fan speed rpm calculation is
1131 * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1132 */
1133 uint32_t crystal_clock_freq = 2500;
1134 uint32_t tach_period;
1135
1136 if (!speed || speed > UINT_MAX/8)
1137 return -EINVAL;
1138 /*
1139 * To prevent from possible overheat, some ASICs may have requirement
1140 * for minimum fan speed:
1141 * - For some NV10 SKU, the fan speed cannot be set lower than
1142 * 700 RPM.
1143 * - For some Sienna Cichlid SKU, the fan speed cannot be set
1144 * lower than 500 RPM.
1145 */
1146 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1147 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1148 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1149 CG_TACH_CTRL, TARGET_PERIOD,
1150 tach_period));
1151
1152 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1153 }
1154
smu_v11_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1155 int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
1156 uint32_t *speed)
1157 {
1158 struct amdgpu_device *adev = smu->adev;
1159 uint32_t duty100, duty;
1160 uint64_t tmp64;
1161
1162 /*
1163 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1164 * detected via register retrieving. To workaround this, we will
1165 * report the fan speed as 0 PWM if user just requested such.
1166 */
1167 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1168 && !smu->user_dpm_profile.fan_speed_pwm) {
1169 *speed = 0;
1170 return 0;
1171 }
1172
1173 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1174 CG_FDO_CTRL1, FMAX_DUTY100);
1175 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
1176 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1177 if (!duty100)
1178 return -EINVAL;
1179
1180 tmp64 = (uint64_t)duty * 255;
1181 do_div(tmp64, duty100);
1182 *speed = min_t(uint32_t, tmp64, 255);
1183
1184 return 0;
1185 }
1186
smu_v11_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1187 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1188 uint32_t *speed)
1189 {
1190 struct amdgpu_device *adev = smu->adev;
1191 uint32_t crystal_clock_freq = 2500;
1192 uint32_t tach_status;
1193 uint64_t tmp64;
1194
1195 /*
1196 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1197 * detected via register retrieving. To workaround this, we will
1198 * report the fan speed as 0 RPM if user just requested such.
1199 */
1200 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1201 && !smu->user_dpm_profile.fan_speed_rpm) {
1202 *speed = 0;
1203 return 0;
1204 }
1205
1206 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1207
1208 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
1209 if (tach_status) {
1210 do_div(tmp64, tach_status);
1211 *speed = (uint32_t)tmp64;
1212 } else {
1213 dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n");
1214 *speed = 0;
1215 }
1216
1217 return 0;
1218 }
1219
1220 int
smu_v11_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1221 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1222 uint32_t mode)
1223 {
1224 int ret = 0;
1225
1226 switch (mode) {
1227 case AMD_FAN_CTRL_NONE:
1228 ret = smu_v11_0_auto_fan_control(smu, 0);
1229 if (!ret)
1230 ret = smu_v11_0_set_fan_speed_pwm(smu, 255);
1231 break;
1232 case AMD_FAN_CTRL_MANUAL:
1233 ret = smu_v11_0_auto_fan_control(smu, 0);
1234 break;
1235 case AMD_FAN_CTRL_AUTO:
1236 ret = smu_v11_0_auto_fan_control(smu, 1);
1237 break;
1238 default:
1239 break;
1240 }
1241
1242 if (ret) {
1243 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1244 return -EINVAL;
1245 }
1246
1247 return ret;
1248 }
1249
smu_v11_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1250 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1251 uint32_t pstate)
1252 {
1253 return smu_cmn_send_smc_msg_with_param(smu,
1254 SMU_MSG_SetXgmiMode,
1255 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1256 NULL);
1257 }
1258
smu_v11_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1259 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1260 struct amdgpu_irq_src *source,
1261 unsigned tyep,
1262 enum amdgpu_interrupt_state state)
1263 {
1264 struct smu_context *smu = adev->powerplay.pp_handle;
1265 uint32_t low, high;
1266 uint32_t val = 0;
1267
1268 switch (state) {
1269 case AMDGPU_IRQ_STATE_DISABLE:
1270 /* For THM irqs */
1271 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1272 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1273 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1274 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1275
1276 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1277
1278 /* For MP1 SW irqs */
1279 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1280 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1281 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1282
1283 break;
1284 case AMDGPU_IRQ_STATE_ENABLE:
1285 /* For THM irqs */
1286 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1287 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1288 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1289 smu->thermal_range.software_shutdown_temp);
1290
1291 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1292 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1293 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1294 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1295 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1296 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1297 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1298 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1299 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1300
1301 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1302 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1303 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1304 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1305
1306 /* For MP1 SW irqs */
1307 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1308 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1309 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1310 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1311
1312 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1313 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1314 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1315
1316 break;
1317 default:
1318 break;
1319 }
1320
1321 return 0;
1322 }
1323
1324 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1325 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1326
1327 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1328
smu_v11_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1329 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1330 struct amdgpu_irq_src *source,
1331 struct amdgpu_iv_entry *entry)
1332 {
1333 struct smu_context *smu = adev->powerplay.pp_handle;
1334 uint32_t client_id = entry->client_id;
1335 uint32_t src_id = entry->src_id;
1336 /*
1337 * ctxid is used to distinguish different
1338 * events for SMCToHost interrupt.
1339 */
1340 uint32_t ctxid = entry->src_data[0];
1341 uint32_t data;
1342
1343 if (client_id == SOC15_IH_CLIENTID_THM) {
1344 switch (src_id) {
1345 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1346 schedule_delayed_work(&smu->swctf_delayed_work,
1347 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1348 break;
1349 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1350 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1351 break;
1352 default:
1353 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1354 src_id);
1355 break;
1356 }
1357 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1358 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1359 /*
1360 * HW CTF just occurred. Shutdown to prevent further damage.
1361 */
1362 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1363 orderly_poweroff(true);
1364 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1365 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
1366 /* ACK SMUToHost interrupt */
1367 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1368 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1369 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1370
1371 switch (ctxid) {
1372 case SMU_IH_INTERRUPT_CONTEXT_ID_AC:
1373 dev_dbg(adev->dev, "Switched to AC mode!\n");
1374 schedule_work(&smu->interrupt_work);
1375 adev->pm.ac_power = true;
1376 break;
1377 case SMU_IH_INTERRUPT_CONTEXT_ID_DC:
1378 dev_dbg(adev->dev, "Switched to DC mode!\n");
1379 schedule_work(&smu->interrupt_work);
1380 adev->pm.ac_power = false;
1381 break;
1382 case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1383 /*
1384 * Increment the throttle interrupt counter
1385 */
1386 atomic64_inc(&smu->throttle_int_counter);
1387
1388 if (!atomic_read(&adev->throttling_logging_enabled))
1389 return 0;
1390
1391 if (__ratelimit(&adev->throttling_logging_rs))
1392 schedule_work(&smu->throttling_logging_work);
1393
1394 break;
1395 default:
1396 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1397 ctxid, client_id);
1398 break;
1399 }
1400 }
1401 }
1402
1403 return 0;
1404 }
1405
1406 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1407 {
1408 .set = smu_v11_0_set_irq_state,
1409 .process = smu_v11_0_irq_process,
1410 };
1411
smu_v11_0_register_irq_handler(struct smu_context * smu)1412 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1413 {
1414 struct amdgpu_device *adev = smu->adev;
1415 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1416 int ret = 0;
1417
1418 irq_src->num_types = 1;
1419 irq_src->funcs = &smu_v11_0_irq_funcs;
1420
1421 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1422 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1423 irq_src);
1424 if (ret)
1425 return ret;
1426
1427 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1428 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1429 irq_src);
1430 if (ret)
1431 return ret;
1432
1433 /* Register CTF(GPIO_19) interrupt */
1434 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1435 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1436 irq_src);
1437 if (ret)
1438 return ret;
1439
1440 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1441 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1442 irq_src);
1443 if (ret)
1444 return ret;
1445
1446 return ret;
1447 }
1448
smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1449 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1450 struct pp_smu_nv_clock_table *max_clocks)
1451 {
1452 struct smu_table_context *table_context = &smu->smu_table;
1453 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1454
1455 if (!max_clocks || !table_context->max_sustainable_clocks)
1456 return -EINVAL;
1457
1458 sustainable_clocks = table_context->max_sustainable_clocks;
1459
1460 max_clocks->dcfClockInKhz =
1461 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1462 max_clocks->displayClockInKhz =
1463 (unsigned int) sustainable_clocks->display_clock * 1000;
1464 max_clocks->phyClockInKhz =
1465 (unsigned int) sustainable_clocks->phy_clock * 1000;
1466 max_clocks->pixelClockInKhz =
1467 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1468 max_clocks->uClockInKhz =
1469 (unsigned int) sustainable_clocks->uclock * 1000;
1470 max_clocks->socClockInKhz =
1471 (unsigned int) sustainable_clocks->soc_clock * 1000;
1472 max_clocks->dscClockInKhz = 0;
1473 max_clocks->dppClockInKhz = 0;
1474 max_clocks->fabricClockInKhz = 0;
1475
1476 return 0;
1477 }
1478
smu_v11_0_set_azalia_d3_pme(struct smu_context * smu)1479 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1480 {
1481 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1482 }
1483
smu_v11_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)1484 int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
1485 enum smu_baco_seq baco_seq)
1486 {
1487 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1488 }
1489
smu_v11_0_get_bamaco_support(struct smu_context * smu)1490 int smu_v11_0_get_bamaco_support(struct smu_context *smu)
1491 {
1492 struct smu_baco_context *smu_baco = &smu->smu_baco;
1493 int bamaco_support = 0;
1494
1495 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
1496 return 0;
1497
1498 if (smu_baco->maco_support)
1499 bamaco_support |= MACO_SUPPORT;
1500
1501 /* return true if ASIC is in BACO state already */
1502 if (smu_v11_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1503 return bamaco_support |= BACO_SUPPORT;
1504
1505 /* Arcturus does not support this bit mask */
1506 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1507 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1508 return 0;
1509
1510 return (bamaco_support |= BACO_SUPPORT);
1511 }
1512
smu_v11_0_baco_get_state(struct smu_context * smu)1513 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1514 {
1515 struct smu_baco_context *smu_baco = &smu->smu_baco;
1516
1517 return smu_baco->state;
1518 }
1519
1520 #define D3HOT_BACO_SEQUENCE 0
1521 #define D3HOT_BAMACO_SEQUENCE 2
1522
smu_v11_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)1523 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1524 {
1525 struct smu_baco_context *smu_baco = &smu->smu_baco;
1526 struct amdgpu_device *adev = smu->adev;
1527 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1528 uint32_t data;
1529 int ret = 0;
1530
1531 if (smu_v11_0_baco_get_state(smu) == state)
1532 return 0;
1533
1534 if (state == SMU_BACO_STATE_ENTER) {
1535 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1536 case IP_VERSION(11, 0, 7):
1537 case IP_VERSION(11, 0, 11):
1538 case IP_VERSION(11, 0, 12):
1539 case IP_VERSION(11, 0, 13):
1540 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)
1541 ret = smu_cmn_send_smc_msg_with_param(smu,
1542 SMU_MSG_EnterBaco,
1543 D3HOT_BAMACO_SEQUENCE,
1544 NULL);
1545 else
1546 ret = smu_cmn_send_smc_msg_with_param(smu,
1547 SMU_MSG_EnterBaco,
1548 D3HOT_BACO_SEQUENCE,
1549 NULL);
1550 break;
1551 default:
1552 if (!ras || !adev->ras_enabled ||
1553 (adev->init_lvl->level ==
1554 AMDGPU_INIT_LEVEL_MINIMAL_XGMI)) {
1555 if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1556 IP_VERSION(11, 0, 2)) {
1557 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1558 data |= 0x80000000;
1559 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1560 } else {
1561 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1562 data |= 0x80000000;
1563 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1564 }
1565
1566 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1567 } else {
1568 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1569 }
1570 break;
1571 }
1572
1573 } else {
1574 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1575 if (ret)
1576 return ret;
1577
1578 /* clear vbios scratch 6 and 7 for coming asic reinit */
1579 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1580 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1581 }
1582
1583 if (!ret)
1584 smu_baco->state = state;
1585
1586 return ret;
1587 }
1588
smu_v11_0_baco_enter(struct smu_context * smu)1589 int smu_v11_0_baco_enter(struct smu_context *smu)
1590 {
1591 int ret = 0;
1592
1593 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1594 if (ret)
1595 return ret;
1596
1597 msleep(10);
1598
1599 return ret;
1600 }
1601
smu_v11_0_baco_exit(struct smu_context * smu)1602 int smu_v11_0_baco_exit(struct smu_context *smu)
1603 {
1604 int ret;
1605
1606 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1607 if (!ret) {
1608 /*
1609 * Poll BACO exit status to ensure FW has completed
1610 * BACO exit process to avoid timing issues.
1611 */
1612 smu_v11_0_poll_baco_exit(smu);
1613 }
1614
1615 return ret;
1616 }
1617
smu_v11_0_mode1_reset(struct smu_context * smu)1618 int smu_v11_0_mode1_reset(struct smu_context *smu)
1619 {
1620 int ret = 0;
1621
1622 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1623 if (!ret)
1624 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1625
1626 return ret;
1627 }
1628
smu_v11_0_handle_passthrough_sbr(struct smu_context * smu,bool enable)1629 int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1630 {
1631 int ret = 0;
1632
1633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
1634
1635 return ret;
1636 }
1637
1638
smu_v11_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1639 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1640 uint32_t *min, uint32_t *max)
1641 {
1642 int ret = 0, clk_id = 0;
1643 uint32_t param = 0;
1644 uint32_t clock_limit;
1645
1646 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1647 switch (clk_type) {
1648 case SMU_MCLK:
1649 case SMU_UCLK:
1650 clock_limit = smu->smu_table.boot_values.uclk;
1651 break;
1652 case SMU_GFXCLK:
1653 case SMU_SCLK:
1654 clock_limit = smu->smu_table.boot_values.gfxclk;
1655 break;
1656 case SMU_SOCCLK:
1657 clock_limit = smu->smu_table.boot_values.socclk;
1658 break;
1659 default:
1660 clock_limit = 0;
1661 break;
1662 }
1663
1664 /* clock in Mhz unit */
1665 if (min)
1666 *min = clock_limit / 100;
1667 if (max)
1668 *max = clock_limit / 100;
1669
1670 return 0;
1671 }
1672
1673 clk_id = smu_cmn_to_asic_specific_index(smu,
1674 CMN2ASIC_MAPPING_CLK,
1675 clk_type);
1676 if (clk_id < 0) {
1677 ret = -EINVAL;
1678 goto failed;
1679 }
1680 param = (clk_id & 0xffff) << 16;
1681
1682 if (max) {
1683 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1684 if (ret)
1685 goto failed;
1686 }
1687
1688 if (min) {
1689 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1690 if (ret)
1691 goto failed;
1692 }
1693
1694 failed:
1695 return ret;
1696 }
1697
smu_v11_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1698 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1699 enum smu_clk_type clk_type,
1700 uint32_t min,
1701 uint32_t max,
1702 bool automatic)
1703 {
1704 int ret = 0, clk_id = 0;
1705 uint32_t param;
1706
1707 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1708 return 0;
1709
1710 clk_id = smu_cmn_to_asic_specific_index(smu,
1711 CMN2ASIC_MAPPING_CLK,
1712 clk_type);
1713 if (clk_id < 0)
1714 return clk_id;
1715
1716 if (max > 0) {
1717 if (automatic)
1718 param = (uint32_t)((clk_id << 16) | 0xffff);
1719 else
1720 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1721 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1722 param, NULL);
1723 if (ret)
1724 goto out;
1725 }
1726
1727 if (min > 0) {
1728 if (automatic)
1729 param = (uint32_t)((clk_id << 16) | 0);
1730 else
1731 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1732 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1733 param, NULL);
1734 if (ret)
1735 goto out;
1736 }
1737
1738 out:
1739 return ret;
1740 }
1741
smu_v11_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1742 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1743 enum smu_clk_type clk_type,
1744 uint32_t min,
1745 uint32_t max)
1746 {
1747 int ret = 0, clk_id = 0;
1748 uint32_t param;
1749
1750 if (min <= 0 && max <= 0)
1751 return -EINVAL;
1752
1753 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1754 return 0;
1755
1756 clk_id = smu_cmn_to_asic_specific_index(smu,
1757 CMN2ASIC_MAPPING_CLK,
1758 clk_type);
1759 if (clk_id < 0)
1760 return clk_id;
1761
1762 if (max > 0) {
1763 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1764 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1765 param, NULL);
1766 if (ret)
1767 return ret;
1768 }
1769
1770 if (min > 0) {
1771 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1772 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1773 param, NULL);
1774 if (ret)
1775 return ret;
1776 }
1777
1778 return ret;
1779 }
1780
smu_v11_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1781 int smu_v11_0_set_performance_level(struct smu_context *smu,
1782 enum amd_dpm_forced_level level)
1783 {
1784 struct smu_11_0_dpm_context *dpm_context =
1785 smu->smu_dpm.dpm_context;
1786 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
1787 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
1788 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
1789 struct smu_umd_pstate_table *pstate_table =
1790 &smu->pstate_table;
1791 struct amdgpu_device *adev = smu->adev;
1792 uint32_t sclk_min = 0, sclk_max = 0;
1793 uint32_t mclk_min = 0, mclk_max = 0;
1794 uint32_t socclk_min = 0, socclk_max = 0;
1795 int ret = 0;
1796 bool auto_level = false;
1797
1798 switch (level) {
1799 case AMD_DPM_FORCED_LEVEL_HIGH:
1800 sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
1801 mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table);
1802 socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table);
1803 break;
1804 case AMD_DPM_FORCED_LEVEL_LOW:
1805 sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table);
1806 mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table);
1807 socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table);
1808 break;
1809 case AMD_DPM_FORCED_LEVEL_AUTO:
1810 sclk_min = SMU_DPM_TABLE_MIN(gfx_table);
1811 sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
1812 mclk_min = SMU_DPM_TABLE_MIN(mem_table);
1813 mclk_max = SMU_DPM_TABLE_MAX(mem_table);
1814 socclk_min = SMU_DPM_TABLE_MIN(soc_table);
1815 socclk_max = SMU_DPM_TABLE_MAX(soc_table);
1816 auto_level = true;
1817 break;
1818 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1819 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1820 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1821 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1822 break;
1823 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1824 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1825 break;
1826 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1827 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1828 break;
1829 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1830 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1831 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1832 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1833 break;
1834 case AMD_DPM_FORCED_LEVEL_MANUAL:
1835 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1836 return 0;
1837 default:
1838 dev_err(adev->dev, "Invalid performance level %d\n", level);
1839 return -EINVAL;
1840 }
1841
1842 /*
1843 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1844 * on Arcturus.
1845 */
1846 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) {
1847 mclk_min = mclk_max = 0;
1848 socclk_min = socclk_max = 0;
1849 auto_level = false;
1850 }
1851
1852 if (sclk_min && sclk_max) {
1853 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1854 SMU_GFXCLK,
1855 sclk_min,
1856 sclk_max,
1857 auto_level);
1858 if (ret)
1859 return ret;
1860 }
1861
1862 if (mclk_min && mclk_max) {
1863 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1864 SMU_MCLK,
1865 mclk_min,
1866 mclk_max,
1867 auto_level);
1868 if (ret)
1869 return ret;
1870 }
1871
1872 if (socclk_min && socclk_max) {
1873 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1874 SMU_SOCCLK,
1875 socclk_min,
1876 socclk_max,
1877 auto_level);
1878 if (ret)
1879 return ret;
1880 }
1881
1882 return ret;
1883 }
1884
smu_v11_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1885 int smu_v11_0_set_power_source(struct smu_context *smu,
1886 enum smu_power_src_type power_src)
1887 {
1888 int pwr_source;
1889
1890 pwr_source = smu_cmn_to_asic_specific_index(smu,
1891 CMN2ASIC_MAPPING_PWR,
1892 (uint32_t)power_src);
1893 if (pwr_source < 0)
1894 return -EINVAL;
1895
1896 return smu_cmn_send_smc_msg_with_param(smu,
1897 SMU_MSG_NotifyPowerSource,
1898 pwr_source,
1899 NULL);
1900 }
1901
smu_v11_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1902 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1903 enum smu_clk_type clk_type,
1904 uint16_t level,
1905 uint32_t *value)
1906 {
1907 int ret = 0, clk_id = 0;
1908 uint32_t param;
1909
1910 if (!value)
1911 return -EINVAL;
1912
1913 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1914 return 0;
1915
1916 clk_id = smu_cmn_to_asic_specific_index(smu,
1917 CMN2ASIC_MAPPING_CLK,
1918 clk_type);
1919 if (clk_id < 0)
1920 return clk_id;
1921
1922 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1923
1924 ret = smu_cmn_send_smc_msg_with_param(smu,
1925 SMU_MSG_GetDpmFreqByIndex,
1926 param,
1927 value);
1928 if (ret)
1929 return ret;
1930
1931 /*
1932 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1933 * now, we un-support it
1934 */
1935 *value = *value & 0x7fffffff;
1936
1937 return ret;
1938 }
1939
smu_v11_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1940 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1941 enum smu_clk_type clk_type,
1942 uint32_t *value)
1943 {
1944 return smu_v11_0_get_dpm_freq_by_index(smu,
1945 clk_type,
1946 0xff,
1947 value);
1948 }
1949
smu_v11_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_dpm_table * single_dpm_table)1950 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1951 enum smu_clk_type clk_type,
1952 struct smu_dpm_table *single_dpm_table)
1953 {
1954 int ret = 0;
1955 uint32_t clk;
1956 int i;
1957
1958 ret = smu_v11_0_get_dpm_level_count(smu,
1959 clk_type,
1960 &single_dpm_table->count);
1961 if (ret) {
1962 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1963 return ret;
1964 }
1965
1966 for (i = 0; i < single_dpm_table->count; i++) {
1967 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1968 clk_type,
1969 i,
1970 &clk);
1971 if (ret) {
1972 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1973 return ret;
1974 }
1975
1976 single_dpm_table->dpm_levels[i].value = clk;
1977 single_dpm_table->dpm_levels[i].enabled = true;
1978 }
1979
1980 return 0;
1981 }
1982
smu_v11_0_get_current_pcie_link_width_level(struct smu_context * smu)1983 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
1984 {
1985 struct amdgpu_device *adev = smu->adev;
1986
1987 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1988 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1989 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1990 }
1991
smu_v11_0_get_current_pcie_link_width(struct smu_context * smu)1992 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
1993 {
1994 uint32_t width_level;
1995
1996 width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
1997 if (width_level > LINK_WIDTH_MAX)
1998 width_level = 0;
1999
2000 return link_width[width_level];
2001 }
2002
smu_v11_0_get_current_pcie_link_speed_level(struct smu_context * smu)2003 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2004 {
2005 struct amdgpu_device *adev = smu->adev;
2006
2007 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2008 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2009 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2010 }
2011
smu_v11_0_get_current_pcie_link_speed(struct smu_context * smu)2012 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2013 {
2014 uint32_t speed_level;
2015
2016 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2017 if (speed_level > LINK_SPEED_MAX)
2018 speed_level = 0;
2019
2020 return link_speed[speed_level];
2021 }
2022
smu_v11_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2023 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2024 bool enablement)
2025 {
2026 int ret = 0;
2027
2028 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2029 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2030
2031 return ret;
2032 }
2033
smu_v11_0_deep_sleep_control(struct smu_context * smu,bool enablement)2034 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2035 bool enablement)
2036 {
2037 struct amdgpu_device *adev = smu->adev;
2038 int ret = 0;
2039
2040 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2041 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2042 if (ret) {
2043 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2044 return ret;
2045 }
2046 }
2047
2048 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2049 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2050 if (ret) {
2051 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2052 return ret;
2053 }
2054 }
2055
2056 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2057 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2058 if (ret) {
2059 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2060 return ret;
2061 }
2062 }
2063
2064 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2065 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2066 if (ret) {
2067 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2068 return ret;
2069 }
2070 }
2071
2072 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2073 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2074 if (ret) {
2075 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2076 return ret;
2077 }
2078 }
2079
2080 return ret;
2081 }
2082
smu_v11_0_restore_user_od_settings(struct smu_context * smu)2083 int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
2084 {
2085 struct smu_table_context *table_context = &smu->smu_table;
2086 void *user_od_table = table_context->user_overdrive_table;
2087 int ret = 0;
2088
2089 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true);
2090 if (ret)
2091 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2092
2093 return ret;
2094 }
2095
smu_v11_0_init_msg_ctl(struct smu_context * smu,const struct cmn2asic_msg_mapping * message_map)2096 void smu_v11_0_init_msg_ctl(struct smu_context *smu,
2097 const struct cmn2asic_msg_mapping *message_map)
2098 {
2099 struct amdgpu_device *adev = smu->adev;
2100 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2101
2102 ctl->smu = smu;
2103 mutex_init(&ctl->lock);
2104 ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2105 ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2106 ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2107 ctl->config.num_arg_regs = 1;
2108 ctl->ops = &smu_msg_v1_ops;
2109 ctl->default_timeout = adev->usec_timeout * 20;
2110 ctl->message_map = message_map;
2111 }
2112