xref: /linux/drivers/clk/sunxi/clk-sunxi.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2013 Emilio López
4  *
5  * Emilio López <emilio@elopez.com.ar>
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/clkdev.h>
11 #include <linux/io.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/reset-controller.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/log2.h>
18 
19 #include "clk-factors.h"
20 
21 static DEFINE_SPINLOCK(clk_lock);
22 
23 /* Maximum number of parents our clocks have */
24 #define SUNXI_MAX_PARENTS	5
25 
26 /*
27  * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28  * PLL1 rate is calculated as follows
29  * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
30  * parent_rate is always 24Mhz
31  */
32 
sun4i_get_pll1_factors(struct factors_request * req)33 static void sun4i_get_pll1_factors(struct factors_request *req)
34 {
35 	u8 div;
36 
37 	/* Normalize value to a 6M multiple */
38 	div = req->rate / 6000000;
39 	req->rate = 6000000 * div;
40 
41 	/* m is always zero for pll1 */
42 	req->m = 0;
43 
44 	/* k is 1 only on these cases */
45 	if (req->rate >= 768000000 || req->rate == 42000000 ||
46 			req->rate == 54000000)
47 		req->k = 1;
48 	else
49 		req->k = 0;
50 
51 	/* p will be 3 for divs under 10 */
52 	if (div < 10)
53 		req->p = 3;
54 
55 	/* p will be 2 for divs between 10 - 20 and odd divs under 32 */
56 	else if (div < 20 || (div < 32 && (div & 1)))
57 		req->p = 2;
58 
59 	/* p will be 1 for even divs under 32, divs under 40 and odd pairs
60 	 * of divs between 40-62 */
61 	else if (div < 40 || (div < 64 && (div & 2)))
62 		req->p = 1;
63 
64 	/* any other entries have p = 0 */
65 	else
66 		req->p = 0;
67 
68 	/* calculate a suitable n based on k and p */
69 	div <<= req->p;
70 	div /= (req->k + 1);
71 	req->n = div / 4;
72 }
73 
74 /*
75  * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
76  * PLL1 rate is calculated as follows
77  * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
78  * parent_rate should always be 24MHz
79  */
sun6i_a31_get_pll1_factors(struct factors_request * req)80 static void sun6i_a31_get_pll1_factors(struct factors_request *req)
81 {
82 	/*
83 	 * We can operate only on MHz, this will make our life easier
84 	 * later.
85 	 */
86 	u32 freq_mhz = req->rate / 1000000;
87 	u32 parent_freq_mhz = req->parent_rate / 1000000;
88 
89 	/*
90 	 * Round down the frequency to the closest multiple of either
91 	 * 6 or 16
92 	 */
93 	u32 round_freq_6 = rounddown(freq_mhz, 6);
94 	u32 round_freq_16 = round_down(freq_mhz, 16);
95 
96 	if (round_freq_6 > round_freq_16)
97 		freq_mhz = round_freq_6;
98 	else
99 		freq_mhz = round_freq_16;
100 
101 	req->rate = freq_mhz * 1000000;
102 
103 	/* If the frequency is a multiple of 32 MHz, k is always 3 */
104 	if (!(freq_mhz % 32))
105 		req->k = 3;
106 	/* If the frequency is a multiple of 9 MHz, k is always 2 */
107 	else if (!(freq_mhz % 9))
108 		req->k = 2;
109 	/* If the frequency is a multiple of 8 MHz, k is always 1 */
110 	else if (!(freq_mhz % 8))
111 		req->k = 1;
112 	/* Otherwise, we don't use the k factor */
113 	else
114 		req->k = 0;
115 
116 	/*
117 	 * If the frequency is a multiple of 2 but not a multiple of
118 	 * 3, m is 3. This is the first time we use 6 here, yet we
119 	 * will use it on several other places.
120 	 * We use this number because it's the lowest frequency we can
121 	 * generate (with n = 0, k = 0, m = 3), so every other frequency
122 	 * somehow relates to this frequency.
123 	 */
124 	if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
125 		req->m = 2;
126 	/*
127 	 * If the frequency is a multiple of 6MHz, but the factor is
128 	 * odd, m will be 3
129 	 */
130 	else if ((freq_mhz / 6) & 1)
131 		req->m = 3;
132 	/* Otherwise, we end up with m = 1 */
133 	else
134 		req->m = 1;
135 
136 	/* Calculate n thanks to the above factors we already got */
137 	req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz)
138 		 - 1;
139 
140 	/*
141 	 * If n end up being outbound, and that we can still decrease
142 	 * m, do it.
143 	 */
144 	if ((req->n + 1) > 31 && (req->m + 1) > 1) {
145 		req->n = (req->n + 1) / 2 - 1;
146 		req->m = (req->m + 1) / 2 - 1;
147 	}
148 }
149 
150 /*
151  * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
152  * PLL1 rate is calculated as follows
153  * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
154  * parent_rate is always 24Mhz
155  */
156 
sun8i_a23_get_pll1_factors(struct factors_request * req)157 static void sun8i_a23_get_pll1_factors(struct factors_request *req)
158 {
159 	u8 div;
160 
161 	/* Normalize value to a 6M multiple */
162 	div = req->rate / 6000000;
163 	req->rate = 6000000 * div;
164 
165 	/* m is always zero for pll1 */
166 	req->m = 0;
167 
168 	/* k is 1 only on these cases */
169 	if (req->rate >= 768000000 || req->rate == 42000000 ||
170 			req->rate == 54000000)
171 		req->k = 1;
172 	else
173 		req->k = 0;
174 
175 	/* p will be 2 for divs under 20 and odd divs under 32 */
176 	if (div < 20 || (div < 32 && (div & 1)))
177 		req->p = 2;
178 
179 	/* p will be 1 for even divs under 32, divs under 40 and odd pairs
180 	 * of divs between 40-62 */
181 	else if (div < 40 || (div < 64 && (div & 2)))
182 		req->p = 1;
183 
184 	/* any other entries have p = 0 */
185 	else
186 		req->p = 0;
187 
188 	/* calculate a suitable n based on k and p */
189 	div <<= req->p;
190 	div /= (req->k + 1);
191 	req->n = div / 4 - 1;
192 }
193 
194 /*
195  * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
196  * PLL5 rate is calculated as follows
197  * rate = parent_rate * n * (k + 1)
198  * parent_rate is always 24Mhz
199  */
200 
sun4i_get_pll5_factors(struct factors_request * req)201 static void sun4i_get_pll5_factors(struct factors_request *req)
202 {
203 	u8 div;
204 
205 	/* Normalize value to a parent_rate multiple (24M) */
206 	div = req->rate / req->parent_rate;
207 	req->rate = req->parent_rate * div;
208 
209 	if (div < 31)
210 		req->k = 0;
211 	else if (div / 2 < 31)
212 		req->k = 1;
213 	else if (div / 3 < 31)
214 		req->k = 2;
215 	else
216 		req->k = 3;
217 
218 	req->n = DIV_ROUND_UP(div, (req->k + 1));
219 }
220 
221 /*
222  * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
223  * PLL6x2 rate is calculated as follows
224  * rate = parent_rate * (n + 1) * (k + 1)
225  * parent_rate is always 24Mhz
226  */
227 
sun6i_a31_get_pll6_factors(struct factors_request * req)228 static void sun6i_a31_get_pll6_factors(struct factors_request *req)
229 {
230 	u8 div;
231 
232 	/* Normalize value to a parent_rate multiple (24M) */
233 	div = req->rate / req->parent_rate;
234 	req->rate = req->parent_rate * div;
235 
236 	req->k = div / 32;
237 	if (req->k > 3)
238 		req->k = 3;
239 
240 	req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
241 }
242 
243 /*
244  * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
245  * AHB rate is calculated as follows
246  * rate = parent_rate >> p
247  */
248 
sun5i_a13_get_ahb_factors(struct factors_request * req)249 static void sun5i_a13_get_ahb_factors(struct factors_request *req)
250 {
251 	u32 div;
252 
253 	/* divide only */
254 	if (req->parent_rate < req->rate)
255 		req->rate = req->parent_rate;
256 
257 	/*
258 	 * user manual says valid speed is 8k ~ 276M, but tests show it
259 	 * can work at speeds up to 300M, just after reparenting to pll6
260 	 */
261 	if (req->rate < 8000)
262 		req->rate = 8000;
263 	if (req->rate > 300000000)
264 		req->rate = 300000000;
265 
266 	div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
267 
268 	/* p = 0 ~ 3 */
269 	if (div > 3)
270 		div = 3;
271 
272 	req->rate = req->parent_rate >> div;
273 
274 	req->p = div;
275 }
276 
277 #define SUN6I_AHB1_PARENT_PLL6	3
278 
279 /*
280  * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
281  * AHB rate is calculated as follows
282  * rate = parent_rate >> p
283  *
284  * if parent is pll6, then
285  * parent_rate = pll6 rate / (m + 1)
286  */
287 
sun6i_get_ahb1_factors(struct factors_request * req)288 static void sun6i_get_ahb1_factors(struct factors_request *req)
289 {
290 	u8 div, calcp, calcm = 1;
291 
292 	/*
293 	 * clock can only divide, so we will never be able to achieve
294 	 * frequencies higher than the parent frequency
295 	 */
296 	if (req->parent_rate && req->rate > req->parent_rate)
297 		req->rate = req->parent_rate;
298 
299 	div = DIV_ROUND_UP(req->parent_rate, req->rate);
300 
301 	/* calculate pre-divider if parent is pll6 */
302 	if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
303 		if (div < 4)
304 			calcp = 0;
305 		else if (div / 2 < 4)
306 			calcp = 1;
307 		else if (div / 4 < 4)
308 			calcp = 2;
309 		else
310 			calcp = 3;
311 
312 		calcm = DIV_ROUND_UP(div, 1 << calcp);
313 	} else {
314 		calcp = __roundup_pow_of_two(div);
315 		calcp = calcp > 3 ? 3 : calcp;
316 	}
317 
318 	req->rate = (req->parent_rate / calcm) >> calcp;
319 	req->p = calcp;
320 	req->m = calcm - 1;
321 }
322 
323 /*
324  * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
325  *			 parent index
326  */
sun6i_ahb1_recalc(struct factors_request * req)327 static void sun6i_ahb1_recalc(struct factors_request *req)
328 {
329 	req->rate = req->parent_rate;
330 
331 	/* apply pre-divider first if parent is pll6 */
332 	if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
333 		req->rate /= req->m + 1;
334 
335 	/* clk divider */
336 	req->rate >>= req->p;
337 }
338 
339 /*
340  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
341  * APB1 rate is calculated as follows
342  * rate = (parent_rate >> p) / (m + 1);
343  */
344 
sun4i_get_apb1_factors(struct factors_request * req)345 static void sun4i_get_apb1_factors(struct factors_request *req)
346 {
347 	u8 calcm, calcp;
348 	int div;
349 
350 	if (req->parent_rate < req->rate)
351 		req->rate = req->parent_rate;
352 
353 	div = DIV_ROUND_UP(req->parent_rate, req->rate);
354 
355 	/* Invalid rate! */
356 	if (div > 32)
357 		return;
358 
359 	if (div <= 4)
360 		calcp = 0;
361 	else if (div <= 8)
362 		calcp = 1;
363 	else if (div <= 16)
364 		calcp = 2;
365 	else
366 		calcp = 3;
367 
368 	calcm = (div >> calcp) - 1;
369 
370 	req->rate = (req->parent_rate >> calcp) / (calcm + 1);
371 	req->m = calcm;
372 	req->p = calcp;
373 }
374 
375 
376 
377 
378 /*
379  * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
380  * CLK_OUT rate is calculated as follows
381  * rate = (parent_rate >> p) / (m + 1);
382  */
383 
sun7i_a20_get_out_factors(struct factors_request * req)384 static void sun7i_a20_get_out_factors(struct factors_request *req)
385 {
386 	u8 div, calcm, calcp;
387 
388 	/* These clocks can only divide, so we will never be able to achieve
389 	 * frequencies higher than the parent frequency */
390 	if (req->rate > req->parent_rate)
391 		req->rate = req->parent_rate;
392 
393 	div = DIV_ROUND_UP(req->parent_rate, req->rate);
394 
395 	if (div < 32)
396 		calcp = 0;
397 	else if (div / 2 < 32)
398 		calcp = 1;
399 	else if (div / 4 < 32)
400 		calcp = 2;
401 	else
402 		calcp = 3;
403 
404 	calcm = DIV_ROUND_UP(div, 1 << calcp);
405 
406 	req->rate = (req->parent_rate >> calcp) / calcm;
407 	req->m = calcm - 1;
408 	req->p = calcp;
409 }
410 
411 /*
412  * sunxi_factors_clk_setup() - Setup function for factor clocks
413  */
414 
415 static const struct clk_factors_config sun4i_pll1_config = {
416 	.nshift = 8,
417 	.nwidth = 5,
418 	.kshift = 4,
419 	.kwidth = 2,
420 	.mshift = 0,
421 	.mwidth = 2,
422 	.pshift = 16,
423 	.pwidth = 2,
424 };
425 
426 static const struct clk_factors_config sun6i_a31_pll1_config = {
427 	.nshift	= 8,
428 	.nwidth = 5,
429 	.kshift = 4,
430 	.kwidth = 2,
431 	.mshift = 0,
432 	.mwidth = 2,
433 	.n_start = 1,
434 };
435 
436 static const struct clk_factors_config sun8i_a23_pll1_config = {
437 	.nshift = 8,
438 	.nwidth = 5,
439 	.kshift = 4,
440 	.kwidth = 2,
441 	.mshift = 0,
442 	.mwidth = 2,
443 	.pshift = 16,
444 	.pwidth = 2,
445 	.n_start = 1,
446 };
447 
448 static const struct clk_factors_config sun4i_pll5_config = {
449 	.nshift = 8,
450 	.nwidth = 5,
451 	.kshift = 4,
452 	.kwidth = 2,
453 };
454 
455 static const struct clk_factors_config sun6i_a31_pll6_config = {
456 	.nshift	= 8,
457 	.nwidth = 5,
458 	.kshift = 4,
459 	.kwidth = 2,
460 	.n_start = 1,
461 };
462 
463 static const struct clk_factors_config sun5i_a13_ahb_config = {
464 	.pshift = 4,
465 	.pwidth = 2,
466 };
467 
468 static const struct clk_factors_config sun6i_ahb1_config = {
469 	.mshift = 6,
470 	.mwidth = 2,
471 	.pshift = 4,
472 	.pwidth = 2,
473 };
474 
475 static const struct clk_factors_config sun4i_apb1_config = {
476 	.mshift = 0,
477 	.mwidth = 5,
478 	.pshift = 16,
479 	.pwidth = 2,
480 };
481 
482 /* user manual says "n" but it's really "p" */
483 static const struct clk_factors_config sun7i_a20_out_config = {
484 	.mshift = 8,
485 	.mwidth = 5,
486 	.pshift = 20,
487 	.pwidth = 2,
488 };
489 
490 static const struct factors_data sun4i_pll1_data __initconst = {
491 	.enable = 31,
492 	.table = &sun4i_pll1_config,
493 	.getter = sun4i_get_pll1_factors,
494 };
495 
496 static const struct factors_data sun6i_a31_pll1_data __initconst = {
497 	.enable = 31,
498 	.table = &sun6i_a31_pll1_config,
499 	.getter = sun6i_a31_get_pll1_factors,
500 };
501 
502 static const struct factors_data sun8i_a23_pll1_data __initconst = {
503 	.enable = 31,
504 	.table = &sun8i_a23_pll1_config,
505 	.getter = sun8i_a23_get_pll1_factors,
506 };
507 
508 static const struct factors_data sun7i_a20_pll4_data __initconst = {
509 	.enable = 31,
510 	.table = &sun4i_pll5_config,
511 	.getter = sun4i_get_pll5_factors,
512 };
513 
514 static const struct factors_data sun4i_pll5_data __initconst = {
515 	.enable = 31,
516 	.table = &sun4i_pll5_config,
517 	.getter = sun4i_get_pll5_factors,
518 };
519 
520 static const struct factors_data sun6i_a31_pll6_data __initconst = {
521 	.enable = 31,
522 	.table = &sun6i_a31_pll6_config,
523 	.getter = sun6i_a31_get_pll6_factors,
524 };
525 
526 static const struct factors_data sun5i_a13_ahb_data __initconst = {
527 	.mux = 6,
528 	.muxmask = BIT(1) | BIT(0),
529 	.table = &sun5i_a13_ahb_config,
530 	.getter = sun5i_a13_get_ahb_factors,
531 };
532 
533 static const struct factors_data sun6i_ahb1_data __initconst = {
534 	.mux = 12,
535 	.muxmask = BIT(1) | BIT(0),
536 	.table = &sun6i_ahb1_config,
537 	.getter = sun6i_get_ahb1_factors,
538 	.recalc = sun6i_ahb1_recalc,
539 };
540 
541 static const struct factors_data sun4i_apb1_data __initconst = {
542 	.mux = 24,
543 	.muxmask = BIT(1) | BIT(0),
544 	.table = &sun4i_apb1_config,
545 	.getter = sun4i_get_apb1_factors,
546 };
547 
548 static const struct factors_data sun7i_a20_out_data __initconst = {
549 	.enable = 31,
550 	.mux = 24,
551 	.muxmask = BIT(1) | BIT(0),
552 	.table = &sun7i_a20_out_config,
553 	.getter = sun7i_a20_get_out_factors,
554 };
555 
sunxi_factors_clk_setup(struct device_node * node,const struct factors_data * data)556 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
557 						   const struct factors_data *data)
558 {
559 	void __iomem *reg;
560 
561 	reg = of_iomap(node, 0);
562 	if (!reg) {
563 		pr_err("Could not get registers for factors-clk: %pOFn\n",
564 		       node);
565 		return NULL;
566 	}
567 
568 	return sunxi_factors_register(node, data, &clk_lock, reg);
569 }
570 
sun4i_pll1_clk_setup(struct device_node * node)571 static void __init sun4i_pll1_clk_setup(struct device_node *node)
572 {
573 	sunxi_factors_clk_setup(node, &sun4i_pll1_data);
574 }
575 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
576 	       sun4i_pll1_clk_setup);
577 
sun6i_pll1_clk_setup(struct device_node * node)578 static void __init sun6i_pll1_clk_setup(struct device_node *node)
579 {
580 	sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data);
581 }
582 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
583 	       sun6i_pll1_clk_setup);
584 
sun8i_pll1_clk_setup(struct device_node * node)585 static void __init sun8i_pll1_clk_setup(struct device_node *node)
586 {
587 	sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data);
588 }
589 CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
590 	       sun8i_pll1_clk_setup);
591 
sun7i_pll4_clk_setup(struct device_node * node)592 static void __init sun7i_pll4_clk_setup(struct device_node *node)
593 {
594 	sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data);
595 }
596 CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
597 	       sun7i_pll4_clk_setup);
598 
sun5i_ahb_clk_setup(struct device_node * node)599 static void __init sun5i_ahb_clk_setup(struct device_node *node)
600 {
601 	sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data);
602 }
603 CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
604 	       sun5i_ahb_clk_setup);
605 
sun6i_ahb1_clk_setup(struct device_node * node)606 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
607 {
608 	sunxi_factors_clk_setup(node, &sun6i_ahb1_data);
609 }
610 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
611 	       sun6i_ahb1_clk_setup);
612 
sun4i_apb1_clk_setup(struct device_node * node)613 static void __init sun4i_apb1_clk_setup(struct device_node *node)
614 {
615 	sunxi_factors_clk_setup(node, &sun4i_apb1_data);
616 }
617 CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
618 	       sun4i_apb1_clk_setup);
619 
sun7i_out_clk_setup(struct device_node * node)620 static void __init sun7i_out_clk_setup(struct device_node *node)
621 {
622 	sunxi_factors_clk_setup(node, &sun7i_a20_out_data);
623 }
624 CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
625 	       sun7i_out_clk_setup);
626 
627 
628 /*
629  * sunxi_mux_clk_setup() - Setup function for muxes
630  */
631 
632 #define SUNXI_MUX_GATE_WIDTH	2
633 
634 struct mux_data {
635 	u8 shift;
636 };
637 
638 static const struct mux_data sun4i_cpu_mux_data __initconst = {
639 	.shift = 16,
640 };
641 
642 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
643 	.shift = 12,
644 };
645 
646 static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
647 	.shift = 0,
648 };
649 
sunxi_mux_clk_setup(struct device_node * node,const struct mux_data * data,unsigned long flags)650 static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
651 					       const struct mux_data *data,
652 					       unsigned long flags)
653 {
654 	struct clk *clk;
655 	const char *clk_name = node->name;
656 	const char *parents[SUNXI_MAX_PARENTS];
657 	void __iomem *reg;
658 	int i;
659 
660 	reg = of_iomap(node, 0);
661 	if (!reg) {
662 		pr_err("Could not map registers for mux-clk: %pOF\n", node);
663 		return NULL;
664 	}
665 
666 	i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
667 	if (of_property_read_string(node, "clock-output-names", &clk_name)) {
668 		pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
669 		       __func__, node);
670 		goto out_unmap;
671 	}
672 
673 	clk = clk_register_mux(NULL, clk_name, parents, i,
674 			       CLK_SET_RATE_PARENT | flags, reg,
675 			       data->shift, SUNXI_MUX_GATE_WIDTH,
676 			       0, &clk_lock);
677 
678 	if (IS_ERR(clk)) {
679 		pr_err("%s: failed to register mux clock %s: %ld\n", __func__,
680 		       clk_name, PTR_ERR(clk));
681 		goto out_unmap;
682 	}
683 
684 	if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
685 		pr_err("%s: failed to add clock provider for %s\n",
686 		       __func__, clk_name);
687 		clk_unregister_divider(clk);
688 		goto out_unmap;
689 	}
690 
691 	return clk;
692 out_unmap:
693 	iounmap(reg);
694 	return NULL;
695 }
696 
sun4i_cpu_clk_setup(struct device_node * node)697 static void __init sun4i_cpu_clk_setup(struct device_node *node)
698 {
699 	/* Protect CPU clock */
700 	sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data, CLK_IS_CRITICAL);
701 }
702 CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
703 	       sun4i_cpu_clk_setup);
704 
sun6i_ahb1_mux_clk_setup(struct device_node * node)705 static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
706 {
707 	sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data, 0);
708 }
709 CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
710 	       sun6i_ahb1_mux_clk_setup);
711 
sun8i_ahb2_clk_setup(struct device_node * node)712 static void __init sun8i_ahb2_clk_setup(struct device_node *node)
713 {
714 	sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data, 0);
715 }
716 CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
717 	       sun8i_ahb2_clk_setup);
718 
719 
720 /*
721  * sunxi_divider_clk_setup() - Setup function for simple divider clocks
722  */
723 
724 struct div_data {
725 	u8	shift;
726 	u8	pow;
727 	u8	width;
728 	const struct clk_div_table *table;
729 };
730 
731 static const struct div_data sun4i_axi_data __initconst = {
732 	.shift	= 0,
733 	.pow	= 0,
734 	.width	= 2,
735 };
736 
737 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
738 	{ .val = 0, .div = 1 },
739 	{ .val = 1, .div = 2 },
740 	{ .val = 2, .div = 3 },
741 	{ .val = 3, .div = 4 },
742 	{ .val = 4, .div = 4 },
743 	{ .val = 5, .div = 4 },
744 	{ .val = 6, .div = 4 },
745 	{ .val = 7, .div = 4 },
746 	{ } /* sentinel */
747 };
748 
749 static const struct div_data sun8i_a23_axi_data __initconst = {
750 	.width	= 3,
751 	.table	= sun8i_a23_axi_table,
752 };
753 
754 static const struct div_data sun4i_ahb_data __initconst = {
755 	.shift	= 4,
756 	.pow	= 1,
757 	.width	= 2,
758 };
759 
760 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
761 	{ .val = 0, .div = 2 },
762 	{ .val = 1, .div = 2 },
763 	{ .val = 2, .div = 4 },
764 	{ .val = 3, .div = 8 },
765 	{ } /* sentinel */
766 };
767 
768 static const struct div_data sun4i_apb0_data __initconst = {
769 	.shift	= 8,
770 	.pow	= 1,
771 	.width	= 2,
772 	.table	= sun4i_apb0_table,
773 };
774 
sunxi_divider_clk_setup(struct device_node * node,const struct div_data * data)775 static void __init sunxi_divider_clk_setup(struct device_node *node,
776 					   const struct div_data *data)
777 {
778 	struct clk *clk;
779 	const char *clk_name = node->name;
780 	const char *clk_parent;
781 	void __iomem *reg;
782 
783 	reg = of_iomap(node, 0);
784 	if (!reg) {
785 		pr_err("Could not map registers for mux-clk: %pOF\n", node);
786 		return;
787 	}
788 
789 	clk_parent = of_clk_get_parent_name(node, 0);
790 
791 	if (of_property_read_string(node, "clock-output-names", &clk_name)) {
792 		pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
793 		       __func__, node);
794 		goto out_unmap;
795 	}
796 
797 	clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
798 					 reg, data->shift, data->width,
799 					 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
800 					 data->table, &clk_lock);
801 	if (IS_ERR(clk)) {
802 		pr_err("%s: failed to register divider clock %s: %ld\n",
803 		       __func__, clk_name, PTR_ERR(clk));
804 		goto out_unmap;
805 	}
806 
807 	if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
808 		pr_err("%s: failed to add clock provider for %s\n",
809 		       __func__, clk_name);
810 		goto out_unregister;
811 	}
812 
813 	if (clk_register_clkdev(clk, clk_name, NULL)) {
814 		of_clk_del_provider(node);
815 		goto out_unregister;
816 	}
817 
818 	return;
819 out_unregister:
820 	clk_unregister_divider(clk);
821 
822 out_unmap:
823 	iounmap(reg);
824 }
825 
sun4i_ahb_clk_setup(struct device_node * node)826 static void __init sun4i_ahb_clk_setup(struct device_node *node)
827 {
828 	sunxi_divider_clk_setup(node, &sun4i_ahb_data);
829 }
830 CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
831 	       sun4i_ahb_clk_setup);
832 
sun4i_apb0_clk_setup(struct device_node * node)833 static void __init sun4i_apb0_clk_setup(struct device_node *node)
834 {
835 	sunxi_divider_clk_setup(node, &sun4i_apb0_data);
836 }
837 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
838 	       sun4i_apb0_clk_setup);
839 
sun4i_axi_clk_setup(struct device_node * node)840 static void __init sun4i_axi_clk_setup(struct device_node *node)
841 {
842 	sunxi_divider_clk_setup(node, &sun4i_axi_data);
843 }
844 CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
845 	       sun4i_axi_clk_setup);
846 
sun8i_axi_clk_setup(struct device_node * node)847 static void __init sun8i_axi_clk_setup(struct device_node *node)
848 {
849 	sunxi_divider_clk_setup(node, &sun8i_a23_axi_data);
850 }
851 CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
852 	       sun8i_axi_clk_setup);
853 
854 
855 /*
856  * sunxi_divs_clk_setup() helper data
857  */
858 
859 #define SUNXI_DIVS_MAX_QTY	4
860 #define SUNXI_DIVISOR_WIDTH	2
861 
862 struct divs_data {
863 	const struct factors_data *factors; /* data for the factor clock */
864 	int ndivs; /* number of outputs */
865 	/*
866 	 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
867 	 * self or base factor clock refers to the output from the pll
868 	 * itself. The remaining refer to fixed or configurable divider
869 	 * outputs.
870 	 */
871 	struct {
872 		u8 self; /* is it the base factor clock? (only one) */
873 		u8 fixed; /* is it a fixed divisor? if not... */
874 		struct clk_div_table *table; /* is it a table based divisor? */
875 		u8 shift; /* otherwise it's a normal divisor with this shift */
876 		u8 pow;   /* is it power-of-two based? */
877 		u8 gate;  /* is it independently gateable? */
878 		bool critical;
879 	} div[SUNXI_DIVS_MAX_QTY];
880 };
881 
882 static struct clk_div_table pll6_sata_tbl[] = {
883 	{ .val = 0, .div = 6, },
884 	{ .val = 1, .div = 12, },
885 	{ .val = 2, .div = 18, },
886 	{ .val = 3, .div = 24, },
887 	{ } /* sentinel */
888 };
889 
890 static const struct divs_data pll5_divs_data __initconst = {
891 	.factors = &sun4i_pll5_data,
892 	.ndivs = 2,
893 	.div = {
894 		/* Protect PLL5_DDR */
895 		{ .shift = 0, .pow = 0, .critical = true }, /* M, DDR */
896 		{ .shift = 16, .pow = 1, }, /* P, other */
897 		/* No output for the base factor clock */
898 	}
899 };
900 
901 static const struct divs_data pll6_divs_data __initconst = {
902 	.factors = &sun4i_pll5_data,
903 	.ndivs = 4,
904 	.div = {
905 		{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
906 		{ .fixed = 2 }, /* P, other */
907 		{ .self = 1 }, /* base factor clock, 2x */
908 		{ .fixed = 4 }, /* pll6 / 4, used as ahb input */
909 	}
910 };
911 
912 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
913 	.factors = &sun6i_a31_pll6_data,
914 	.ndivs = 2,
915 	.div = {
916 		{ .fixed = 2 }, /* normal output */
917 		{ .self = 1 }, /* base factor clock, 2x */
918 	}
919 };
920 
921 /*
922  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
923  *
924  * These clocks look something like this
925  *            ________________________
926  *           |         ___divisor 1---|----> to consumer
927  * parent >--|  pll___/___divisor 2---|----> to consumer
928  *           |        \_______________|____> to consumer
929  *           |________________________|
930  */
931 
sunxi_divs_clk_setup(struct device_node * node,const struct divs_data * data)932 static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
933 						 const struct divs_data *data)
934 {
935 	struct clk_onecell_data *clk_data;
936 	const char *parent;
937 	const char *clk_name;
938 	struct clk **clks, *pclk;
939 	struct clk_hw *gate_hw, *rate_hw;
940 	const struct clk_ops *rate_ops;
941 	struct clk_gate *gate = NULL;
942 	struct clk_fixed_factor *fix_factor;
943 	struct clk_divider *divider;
944 	struct factors_data factors = *data->factors;
945 	char *derived_name = NULL;
946 	void __iomem *reg;
947 	int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
948 	int flags, clkflags;
949 
950 	/* if number of children known, use it */
951 	if (data->ndivs)
952 		ndivs = data->ndivs;
953 
954 	/* Try to find a name for base factor clock */
955 	for (i = 0; i < ndivs; i++) {
956 		if (data->div[i].self) {
957 			of_property_read_string_index(node, "clock-output-names",
958 						      i, &factors.name);
959 			break;
960 		}
961 	}
962 	/* If we don't have a .self clk use the first output-name up to '_' */
963 	if (factors.name == NULL) {
964 		char *endp;
965 
966 		of_property_read_string_index(node, "clock-output-names",
967 						      0, &clk_name);
968 		endp = strchr(clk_name, '_');
969 		if (endp) {
970 			derived_name = kstrndup(clk_name, endp - clk_name,
971 						GFP_KERNEL);
972 			if (!derived_name)
973 				return NULL;
974 			factors.name = derived_name;
975 		} else {
976 			factors.name = clk_name;
977 		}
978 	}
979 
980 	/* Set up factor clock that we will be dividing */
981 	pclk = sunxi_factors_clk_setup(node, &factors);
982 	if (!pclk)
983 		return NULL;
984 
985 	parent = __clk_get_name(pclk);
986 	kfree(derived_name);
987 
988 	reg = of_iomap(node, 0);
989 	if (!reg) {
990 		pr_err("Could not map registers for divs-clk: %pOF\n", node);
991 		return NULL;
992 	}
993 
994 	clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
995 	if (!clk_data)
996 		goto out_unmap;
997 
998 	clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
999 	if (!clks)
1000 		goto free_clkdata;
1001 
1002 	clk_data->clks = clks;
1003 
1004 	/* It's not a good idea to have automatic reparenting changing
1005 	 * our RAM clock! */
1006 	clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1007 
1008 	for (i = 0; i < ndivs; i++) {
1009 		if (of_property_read_string_index(node, "clock-output-names",
1010 						  i, &clk_name) != 0)
1011 			break;
1012 
1013 		/* If this is the base factor clock, only update clks */
1014 		if (data->div[i].self) {
1015 			clk_data->clks[i] = pclk;
1016 			continue;
1017 		}
1018 
1019 		gate_hw = NULL;
1020 		rate_hw = NULL;
1021 		rate_ops = NULL;
1022 
1023 		/* If this leaf clock can be gated, create a gate */
1024 		if (data->div[i].gate) {
1025 			gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1026 			if (!gate)
1027 				goto free_clks;
1028 
1029 			gate->reg = reg;
1030 			gate->bit_idx = data->div[i].gate;
1031 			gate->lock = &clk_lock;
1032 
1033 			gate_hw = &gate->hw;
1034 		}
1035 
1036 		/* Leaves can be fixed or configurable divisors */
1037 		if (data->div[i].fixed) {
1038 			fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1039 			if (!fix_factor)
1040 				goto free_gate;
1041 
1042 			fix_factor->mult = 1;
1043 			fix_factor->div = data->div[i].fixed;
1044 
1045 			rate_hw = &fix_factor->hw;
1046 			rate_ops = &clk_fixed_factor_ops;
1047 		} else {
1048 			divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1049 			if (!divider)
1050 				goto free_gate;
1051 
1052 			flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1053 
1054 			divider->reg = reg;
1055 			divider->shift = data->div[i].shift;
1056 			divider->width = SUNXI_DIVISOR_WIDTH;
1057 			divider->flags = flags;
1058 			divider->lock = &clk_lock;
1059 			divider->table = data->div[i].table;
1060 
1061 			rate_hw = &divider->hw;
1062 			rate_ops = &clk_divider_ops;
1063 		}
1064 
1065 		/* Wrap the (potential) gate and the divisor on a composite
1066 		 * clock to unify them */
1067 		clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1068 						 NULL, NULL,
1069 						 rate_hw, rate_ops,
1070 						 gate_hw, &clk_gate_ops,
1071 						 clkflags |
1072 						 (data->div[i].critical ?
1073 							CLK_IS_CRITICAL : 0));
1074 
1075 		WARN_ON(IS_ERR(clk_data->clks[i]));
1076 	}
1077 
1078 	/* Adjust to the real max */
1079 	clk_data->clk_num = i;
1080 
1081 	if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) {
1082 		pr_err("%s: failed to add clock provider for %s\n",
1083 		       __func__, clk_name);
1084 		goto free_gate;
1085 	}
1086 
1087 	return clks;
1088 free_gate:
1089 	kfree(gate);
1090 free_clks:
1091 	kfree(clks);
1092 free_clkdata:
1093 	kfree(clk_data);
1094 out_unmap:
1095 	iounmap(reg);
1096 	return NULL;
1097 }
1098 
sun4i_pll5_clk_setup(struct device_node * node)1099 static void __init sun4i_pll5_clk_setup(struct device_node *node)
1100 {
1101 	sunxi_divs_clk_setup(node, &pll5_divs_data);
1102 }
1103 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
1104 	       sun4i_pll5_clk_setup);
1105 
sun4i_pll6_clk_setup(struct device_node * node)1106 static void __init sun4i_pll6_clk_setup(struct device_node *node)
1107 {
1108 	sunxi_divs_clk_setup(node, &pll6_divs_data);
1109 }
1110 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1111 	       sun4i_pll6_clk_setup);
1112 
sun6i_pll6_clk_setup(struct device_node * node)1113 static void __init sun6i_pll6_clk_setup(struct device_node *node)
1114 {
1115 	sunxi_divs_clk_setup(node, &sun6i_a31_pll6_divs_data);
1116 }
1117 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
1118 	       sun6i_pll6_clk_setup);
1119 
1120 /*
1121  * sun6i display
1122  *
1123  * rate = parent_rate / (m + 1);
1124  */
sun6i_display_factors(struct factors_request * req)1125 static void sun6i_display_factors(struct factors_request *req)
1126 {
1127 	u8 m;
1128 
1129 	if (req->rate > req->parent_rate)
1130 		req->rate = req->parent_rate;
1131 
1132 	m = DIV_ROUND_UP(req->parent_rate, req->rate);
1133 
1134 	req->rate = req->parent_rate / m;
1135 	req->m = m - 1;
1136 }
1137 
1138 static const struct clk_factors_config sun6i_display_config = {
1139 	.mshift = 0,
1140 	.mwidth = 4,
1141 };
1142 
1143 static const struct factors_data sun6i_display_data __initconst = {
1144 	.enable = 31,
1145 	.mux = 24,
1146 	.muxmask = BIT(2) | BIT(1) | BIT(0),
1147 	.table = &sun6i_display_config,
1148 	.getter = sun6i_display_factors,
1149 };
1150 
sun6i_display_setup(struct device_node * node)1151 static void __init sun6i_display_setup(struct device_node *node)
1152 {
1153 	sunxi_factors_clk_setup(node, &sun6i_display_data);
1154 }
1155 CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk",
1156 	       sun6i_display_setup);
1157