1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/reboot.h> 27 28 #define SWSMU_CODE_LAYER_L3 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "smu_v15_0.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "amdgpu_ras.h" 39 #include "smu_cmn.h" 40 41 #include "asic_reg/thm/thm_15_0_0_offset.h" 42 #include "asic_reg/thm/thm_15_0_0_sh_mask.h" 43 #include "asic_reg/mp/mp_15_0_0_offset.h" 44 #include "asic_reg/mp/mp_15_0_0_sh_mask.h" 45 46 #define regMP1_SMN_IH_SW_INT_mp1_15_0_0 0x0341 47 #define regMP1_SMN_IH_SW_INT_mp1_15_0_0_BASE_IDX 0 48 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0 0x0342 49 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0_BASE_IDX 0 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1 62 63 int smu_v15_0_init_microcode(struct smu_context *smu) 64 { 65 struct amdgpu_device *adev = smu->adev; 66 char ucode_prefix[15]; 67 int err = 0; 68 const struct smc_firmware_header_v1_0 *hdr; 69 const struct common_firmware_header *header; 70 struct amdgpu_firmware_info *ucode = NULL; 71 72 /* doesn't need to load smu firmware in IOV mode */ 73 if (amdgpu_sriov_vf(adev)) 74 return 0; 75 76 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); 77 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, 78 "amdgpu/%s.bin", ucode_prefix); 79 if (err) 80 goto out; 81 82 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 83 amdgpu_ucode_print_smc_hdr(&hdr->header); 84 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 85 86 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 87 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 88 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 89 ucode->fw = adev->pm.fw; 90 header = (const struct common_firmware_header *)ucode->fw->data; 91 adev->firmware.fw_size += 92 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 93 } 94 95 out: 96 if (err) 97 amdgpu_ucode_release(&adev->pm.fw); 98 return err; 99 } 100 101 void smu_v15_0_fini_microcode(struct smu_context *smu) 102 { 103 struct amdgpu_device *adev = smu->adev; 104 105 amdgpu_ucode_release(&adev->pm.fw); 106 adev->pm.fw_version = 0; 107 } 108 109 int smu_v15_0_load_microcode(struct smu_context *smu) 110 { 111 struct amdgpu_device *adev = smu->adev; 112 const uint32_t *src; 113 const struct smc_firmware_header_v1_0 *hdr; 114 uint32_t addr_start = MP1_SRAM; 115 uint32_t i; 116 uint32_t smc_fw_size; 117 uint32_t mp1_fw_flags; 118 119 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 120 src = (const uint32_t *)(adev->pm.fw->data + 121 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 122 smc_fw_size = hdr->header.ucode_size_bytes; 123 124 for (i = 1; i < smc_fw_size/4 - 1; i++) { 125 WREG32_PCIE(addr_start, src[i]); 126 addr_start += 4; 127 } 128 129 130 for (i = 0; i < adev->usec_timeout; i++) { 131 if (smu->is_apu) 132 mp1_fw_flags = RREG32_PCIE(MP1_Public | 133 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 134 135 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 136 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 137 break; 138 udelay(1); 139 } 140 141 if (i == adev->usec_timeout) 142 return -ETIME; 143 144 return 0; 145 } 146 147 int smu_v15_0_init_pptable_microcode(struct smu_context *smu) 148 { 149 struct amdgpu_device *adev = smu->adev; 150 struct amdgpu_firmware_info *ucode = NULL; 151 uint32_t size = 0, pptable_id = 0; 152 int ret = 0; 153 void *table; 154 155 /* doesn't need to load smu firmware in IOV mode */ 156 if (amdgpu_sriov_vf(adev)) 157 return 0; 158 159 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 160 return 0; 161 162 if (!adev->scpm_enabled) 163 return 0; 164 165 /* override pptable_id from driver parameter */ 166 if (amdgpu_smu_pptable_id >= 0) { 167 pptable_id = amdgpu_smu_pptable_id; 168 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 169 } else { 170 pptable_id = smu->smu_table.boot_values.pp_table_id; 171 } 172 173 /* "pptable_id == 0" means vbios carries the pptable. */ 174 if (!pptable_id) 175 return 0; 176 177 ret = smu_v15_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 178 if (ret) 179 return ret; 180 181 smu->pptable_firmware.data = table; 182 smu->pptable_firmware.size = size; 183 184 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE]; 185 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE; 186 ucode->fw = &smu->pptable_firmware; 187 adev->firmware.fw_size += 188 ALIGN(smu->pptable_firmware.size, PAGE_SIZE); 189 190 return 0; 191 } 192 193 int smu_v15_0_check_fw_status(struct smu_context *smu) 194 { 195 struct amdgpu_device *adev = smu->adev; 196 uint32_t mp1_fw_flags = 0; 197 198 if (smu->is_apu) 199 mp1_fw_flags = RREG32_PCIE(MP1_Public | 200 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 201 202 203 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 204 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 205 return 0; 206 207 return -EIO; 208 } 209 210 static int smu_v15_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 211 { 212 struct amdgpu_device *adev = smu->adev; 213 uint32_t ppt_offset_bytes; 214 const struct smc_firmware_header_v2_0 *v2; 215 216 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 217 218 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 219 *size = le32_to_cpu(v2->ppt_size_bytes); 220 *table = (uint8_t *)v2 + ppt_offset_bytes; 221 222 return 0; 223 } 224 225 static int smu_v15_0_set_pptable_v2_1(struct smu_context *smu, void **table, 226 uint32_t *size, uint32_t pptable_id) 227 { 228 struct amdgpu_device *adev = smu->adev; 229 const struct smc_firmware_header_v2_1 *v2_1; 230 struct smc_soft_pptable_entry *entries; 231 uint32_t pptable_count = 0; 232 int i = 0; 233 234 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 235 entries = (struct smc_soft_pptable_entry *) 236 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 237 pptable_count = le32_to_cpu(v2_1->pptable_count); 238 for (i = 0; i < pptable_count; i++) { 239 if (le32_to_cpu(entries[i].id) == pptable_id) { 240 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 241 *size = le32_to_cpu(entries[i].ppt_size_bytes); 242 break; 243 } 244 } 245 246 if (i == pptable_count) 247 return -EINVAL; 248 249 return 0; 250 } 251 252 static int smu_v15_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size) 253 { 254 struct amdgpu_device *adev = smu->adev; 255 uint16_t atom_table_size; 256 uint8_t frev, crev; 257 int ret, index; 258 259 dev_info(adev->dev, "use vbios provided pptable\n"); 260 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 261 powerplayinfo); 262 263 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 264 (uint8_t **)table); 265 if (ret) 266 return ret; 267 268 if (size) 269 *size = atom_table_size; 270 271 return 0; 272 } 273 274 int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu, 275 void **table, 276 uint32_t *size, 277 uint32_t pptable_id) 278 { 279 const struct smc_firmware_header_v1_0 *hdr; 280 struct amdgpu_device *adev = smu->adev; 281 uint16_t version_major, version_minor; 282 int ret; 283 284 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 285 if (!hdr) 286 return -EINVAL; 287 288 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id); 289 290 version_major = le16_to_cpu(hdr->header.header_version_major); 291 version_minor = le16_to_cpu(hdr->header.header_version_minor); 292 if (version_major != 2) { 293 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n", 294 version_major, version_minor); 295 return -EINVAL; 296 } 297 298 switch (version_minor) { 299 case 0: 300 ret = smu_v15_0_set_pptable_v2_0(smu, table, size); 301 break; 302 case 1: 303 ret = smu_v15_0_set_pptable_v2_1(smu, table, size, pptable_id); 304 break; 305 default: 306 ret = -EINVAL; 307 break; 308 } 309 310 return ret; 311 } 312 313 int smu_v15_0_setup_pptable(struct smu_context *smu) 314 { 315 struct amdgpu_device *adev = smu->adev; 316 uint32_t size = 0, pptable_id = 0; 317 void *table; 318 int ret = 0; 319 320 /* override pptable_id from driver parameter */ 321 if (amdgpu_smu_pptable_id >= 0) { 322 pptable_id = amdgpu_smu_pptable_id; 323 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 324 } else { 325 pptable_id = smu->smu_table.boot_values.pp_table_id; 326 } 327 328 /* force using vbios pptable in sriov mode */ 329 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1)) 330 ret = smu_v15_0_get_pptable_from_vbios(smu, &table, &size); 331 else 332 ret = smu_v15_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 333 334 if (ret) 335 return ret; 336 337 if (!smu->smu_table.power_play_table) 338 smu->smu_table.power_play_table = table; 339 if (!smu->smu_table.power_play_table_size) 340 smu->smu_table.power_play_table_size = size; 341 342 return 0; 343 } 344 345 int smu_v15_0_init_smc_tables(struct smu_context *smu) 346 { 347 struct smu_table_context *smu_table = &smu->smu_table; 348 struct smu_table *tables = smu_table->tables; 349 int ret = 0; 350 351 smu_table->driver_pptable = 352 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 353 if (!smu_table->driver_pptable) { 354 ret = -ENOMEM; 355 goto err0_out; 356 } 357 358 smu_table->max_sustainable_clocks = 359 kzalloc_obj(struct smu_15_0_max_sustainable_clocks); 360 if (!smu_table->max_sustainable_clocks) { 361 ret = -ENOMEM; 362 goto err1_out; 363 } 364 365 if (tables[SMU_TABLE_OVERDRIVE].size) { 366 smu_table->overdrive_table = 367 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 368 if (!smu_table->overdrive_table) { 369 ret = -ENOMEM; 370 goto err2_out; 371 } 372 373 smu_table->boot_overdrive_table = 374 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 375 if (!smu_table->boot_overdrive_table) { 376 ret = -ENOMEM; 377 goto err3_out; 378 } 379 380 smu_table->user_overdrive_table = 381 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 382 if (!smu_table->user_overdrive_table) { 383 ret = -ENOMEM; 384 goto err4_out; 385 } 386 } 387 388 smu_table->combo_pptable = 389 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL); 390 if (!smu_table->combo_pptable) { 391 ret = -ENOMEM; 392 goto err5_out; 393 } 394 395 return 0; 396 397 err5_out: 398 kfree(smu_table->user_overdrive_table); 399 err4_out: 400 kfree(smu_table->boot_overdrive_table); 401 err3_out: 402 kfree(smu_table->overdrive_table); 403 err2_out: 404 kfree(smu_table->max_sustainable_clocks); 405 err1_out: 406 kfree(smu_table->driver_pptable); 407 err0_out: 408 return ret; 409 } 410 411 int smu_v15_0_fini_smc_tables(struct smu_context *smu) 412 { 413 struct smu_table_context *smu_table = &smu->smu_table; 414 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 415 416 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); 417 kfree(smu_table->combo_pptable); 418 kfree(smu_table->boot_overdrive_table); 419 kfree(smu_table->overdrive_table); 420 kfree(smu_table->max_sustainable_clocks); 421 kfree(smu_table->driver_pptable); 422 smu_table->combo_pptable = NULL; 423 smu_table->boot_overdrive_table = NULL; 424 smu_table->overdrive_table = NULL; 425 smu_table->max_sustainable_clocks = NULL; 426 smu_table->driver_pptable = NULL; 427 kfree(smu_table->hardcode_pptable); 428 smu_table->hardcode_pptable = NULL; 429 430 kfree(smu_table->ecc_table); 431 kfree(smu_table->metrics_table); 432 kfree(smu_table->watermarks_table); 433 smu_table->ecc_table = NULL; 434 smu_table->metrics_table = NULL; 435 smu_table->watermarks_table = NULL; 436 smu_table->metrics_time = 0; 437 438 kfree(smu_dpm->dpm_context); 439 kfree(smu_dpm->golden_dpm_context); 440 kfree(smu_dpm->dpm_current_power_state); 441 kfree(smu_dpm->dpm_request_power_state); 442 smu_dpm->dpm_context = NULL; 443 smu_dpm->golden_dpm_context = NULL; 444 smu_dpm->dpm_context_size = 0; 445 smu_dpm->dpm_current_power_state = NULL; 446 smu_dpm->dpm_request_power_state = NULL; 447 448 return 0; 449 } 450 451 int smu_v15_0_init_power(struct smu_context *smu) 452 { 453 struct smu_power_context *smu_power = &smu->smu_power; 454 455 if (smu_power->power_context || smu_power->power_context_size != 0) 456 return -EINVAL; 457 458 smu_power->power_context = kzalloc_obj(struct smu_15_0_dpm_context); 459 if (!smu_power->power_context) 460 return -ENOMEM; 461 smu_power->power_context_size = sizeof(struct smu_15_0_dpm_context); 462 463 return 0; 464 } 465 466 int smu_v15_0_fini_power(struct smu_context *smu) 467 { 468 struct smu_power_context *smu_power = &smu->smu_power; 469 470 if (!smu_power->power_context || smu_power->power_context_size == 0) 471 return -EINVAL; 472 473 kfree(smu_power->power_context); 474 smu_power->power_context = NULL; 475 smu_power->power_context_size = 0; 476 477 return 0; 478 } 479 480 int smu_v15_0_get_vbios_bootup_values(struct smu_context *smu) 481 { 482 int ret, index; 483 uint16_t size; 484 uint8_t frev, crev; 485 struct atom_common_table_header *header; 486 struct atom_firmware_info_v3_4 *v_3_4; 487 struct atom_firmware_info_v3_3 *v_3_3; 488 struct atom_firmware_info_v3_1 *v_3_1; 489 struct atom_smu_info_v3_6 *smu_info_v3_6; 490 struct atom_smu_info_v4_0 *smu_info_v4_0; 491 492 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 493 firmwareinfo); 494 495 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 496 (uint8_t **)&header); 497 if (ret) 498 return ret; 499 500 if (header->format_revision != 3) { 501 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu15\n"); 502 return -EINVAL; 503 } 504 505 switch (header->content_revision) { 506 case 0: 507 case 1: 508 case 2: 509 v_3_1 = (struct atom_firmware_info_v3_1 *)header; 510 smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 511 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 512 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 513 smu->smu_table.boot_values.socclk = 0; 514 smu->smu_table.boot_values.dcefclk = 0; 515 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 516 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 517 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 518 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 519 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 520 smu->smu_table.boot_values.pp_table_id = 0; 521 break; 522 case 3: 523 v_3_3 = (struct atom_firmware_info_v3_3 *)header; 524 smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 525 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 526 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 527 smu->smu_table.boot_values.socclk = 0; 528 smu->smu_table.boot_values.dcefclk = 0; 529 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 530 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 531 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 532 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 533 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 534 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 535 break; 536 case 4: 537 default: 538 v_3_4 = (struct atom_firmware_info_v3_4 *)header; 539 smu->smu_table.boot_values.revision = v_3_4->firmware_revision; 540 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; 541 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; 542 smu->smu_table.boot_values.socclk = 0; 543 smu->smu_table.boot_values.dcefclk = 0; 544 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; 545 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; 546 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; 547 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; 548 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; 549 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id; 550 break; 551 } 552 553 smu->smu_table.boot_values.format_revision = header->format_revision; 554 smu->smu_table.boot_values.content_revision = header->content_revision; 555 556 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 557 smu_info); 558 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 559 (uint8_t **)&header)) { 560 561 if ((frev == 3) && (crev == 6)) { 562 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header; 563 564 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; 565 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz; 566 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz; 567 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; 568 } else if ((frev == 3) && (crev == 1)) { 569 return 0; 570 } else if ((frev == 4) && (crev == 0)) { 571 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header; 572 573 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; 574 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; 575 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz; 576 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz; 577 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz; 578 } else { 579 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n", 580 (uint32_t)frev, (uint32_t)crev); 581 } 582 } 583 584 return 0; 585 } 586 587 588 int smu_v15_0_notify_memory_pool_location(struct smu_context *smu) 589 { 590 struct smu_table_context *smu_table = &smu->smu_table; 591 struct smu_table *memory_pool = &smu_table->memory_pool; 592 struct smu_msg_args args = { 593 .msg = SMU_MSG_DramLogSetDramAddr, 594 .num_args = 3, 595 .num_out_args = 0, 596 }; 597 598 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 599 return 0; 600 601 /* SMU_MSG_DramLogSetDramAddr: ARG0=low, ARG1=high, ARG2=size */ 602 args.args[0] = lower_32_bits(memory_pool->mc_address); 603 args.args[1] = upper_32_bits(memory_pool->mc_address); 604 args.args[2] = (u32)memory_pool->size; 605 606 return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); 607 } 608 609 int smu_v15_0_set_driver_table_location(struct smu_context *smu) 610 { 611 struct smu_table *driver_table = &smu->smu_table.driver_table; 612 struct smu_msg_args args = { 613 .msg = SMU_MSG_SetDriverDramAddr, 614 .num_args = 2, 615 .num_out_args = 0, 616 }; 617 618 args.args[0] = lower_32_bits(driver_table->mc_address); 619 args.args[1] = upper_32_bits(driver_table->mc_address); 620 621 return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); 622 } 623 624 int smu_v15_0_set_tool_table_location(struct smu_context *smu) 625 { 626 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 627 struct smu_msg_args args = { 628 .msg = SMU_MSG_SetToolsDramAddr, 629 .num_args = 2, 630 .num_out_args = 0, 631 }; 632 633 /* SMU_MSG_SetToolsDramAddr: ARG0=low, ARG1=high */ 634 args.args[0] = lower_32_bits(tool_table->mc_address); 635 args.args[1] = upper_32_bits(tool_table->mc_address); 636 637 return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); 638 } 639 640 int smu_v15_0_set_allowed_mask(struct smu_context *smu) 641 { 642 struct smu_feature *feature = &smu->smu_feature; 643 int ret = 0; 644 uint32_t feature_mask[2]; 645 646 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 647 feature->feature_num < SMU_FEATURE_NUM_DEFAULT) 648 return -EINVAL; 649 650 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); 651 652 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 653 feature_mask[1], NULL); 654 if (ret) 655 return ret; 656 657 return smu_cmn_send_smc_msg_with_param(smu, 658 SMU_MSG_SetAllowedFeaturesMaskLow, 659 feature_mask[0], 660 NULL); 661 } 662 663 int smu_v15_0_gfx_off_control(struct smu_context *smu, bool enable) 664 { 665 int ret = 0; 666 struct amdgpu_device *adev = smu->adev; 667 668 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 669 case IP_VERSION(15, 0, 0): 670 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 671 return 0; 672 if (enable) 673 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 674 else 675 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 676 break; 677 default: 678 break; 679 } 680 681 return ret; 682 } 683 684 int smu_v15_0_system_features_control(struct smu_context *smu, bool en) 685 { 686 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 687 SMU_MSG_DisableAllSmuFeatures), NULL); 688 } 689 690 int smu_v15_0_notify_display_change(struct smu_context *smu) 691 { 692 int ret = 0; 693 694 if (!smu->pm_enabled) 695 return ret; 696 697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 698 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 699 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 700 701 return ret; 702 } 703 704 int smu_v15_0_get_current_power_limit(struct smu_context *smu, 705 uint32_t *power_limit) 706 { 707 int power_src; 708 int ret = 0; 709 710 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 711 return -EINVAL; 712 713 power_src = smu_cmn_to_asic_specific_index(smu, 714 CMN2ASIC_MAPPING_PWR, 715 smu->adev->pm.ac_power ? 716 SMU_POWER_SOURCE_AC : 717 SMU_POWER_SOURCE_DC); 718 if (power_src < 0) 719 return -EINVAL; 720 721 ret = smu_cmn_send_smc_msg_with_param(smu, 722 SMU_MSG_GetPptLimit, 723 power_src << 16, 724 power_limit); 725 if (ret) 726 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 727 728 return ret; 729 } 730 731 int smu_v15_0_set_power_limit(struct smu_context *smu, 732 enum smu_ppt_limit_type limit_type, 733 uint32_t limit) 734 { 735 int ret = 0; 736 737 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 738 return -EINVAL; 739 740 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 741 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 742 return -EOPNOTSUPP; 743 } 744 745 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL); 746 if (ret) { 747 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 748 return ret; 749 } 750 751 smu->current_power_limit = limit; 752 753 return 0; 754 } 755 756 static int smu_v15_0_set_irq_state(struct amdgpu_device *adev, 757 struct amdgpu_irq_src *source, 758 unsigned tyep, 759 enum amdgpu_interrupt_state state) 760 { 761 struct smu_context *smu = adev->powerplay.pp_handle; 762 uint32_t val = 0; 763 764 switch (state) { 765 case AMDGPU_IRQ_STATE_DISABLE: 766 767 /* For MP1 SW irqs */ 768 if (smu->is_apu) { 769 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0); 770 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 771 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0, val); 772 } else { 773 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 774 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 775 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 776 } 777 778 break; 779 case AMDGPU_IRQ_STATE_ENABLE: 780 /* For MP1 SW irqs */ 781 if (smu->is_apu) { 782 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_15_0_0); 783 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 784 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 785 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_15_0_0, val); 786 787 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0); 788 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 789 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0, val); 790 } else { 791 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); 792 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 793 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 794 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); 795 796 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 797 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 798 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 799 } 800 801 break; 802 default: 803 break; 804 } 805 806 return 0; 807 } 808 809 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 810 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 811 812 static int smu_v15_0_irq_process(struct amdgpu_device *adev, 813 struct amdgpu_irq_src *source, 814 struct amdgpu_iv_entry *entry) 815 { 816 struct smu_context *smu = adev->powerplay.pp_handle; 817 uint32_t client_id = entry->client_id; 818 uint32_t src_id = entry->src_id; 819 820 if (client_id == SOC15_IH_CLIENTID_THM) { 821 switch (src_id) { 822 case THM_11_0__SRCID__THM_DIG_THERM_L2H: 823 schedule_delayed_work(&smu->swctf_delayed_work, 824 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY)); 825 break; 826 case THM_11_0__SRCID__THM_DIG_THERM_H2L: 827 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 828 break; 829 default: 830 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 831 src_id); 832 break; 833 } 834 } 835 836 return 0; 837 } 838 839 static const struct amdgpu_irq_src_funcs smu_v15_0_irq_funcs = { 840 .set = smu_v15_0_set_irq_state, 841 .process = smu_v15_0_irq_process, 842 }; 843 844 int smu_v15_0_register_irq_handler(struct smu_context *smu) 845 { 846 struct amdgpu_device *adev = smu->adev; 847 struct amdgpu_irq_src *irq_src = &smu->irq_source; 848 int ret = 0; 849 850 if (amdgpu_sriov_vf(adev)) 851 return 0; 852 853 irq_src->num_types = 1; 854 irq_src->funcs = &smu_v15_0_irq_funcs; 855 856 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 857 THM_11_0__SRCID__THM_DIG_THERM_L2H, 858 irq_src); 859 if (ret) 860 return ret; 861 862 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 863 THM_11_0__SRCID__THM_DIG_THERM_H2L, 864 irq_src); 865 if (ret) 866 return ret; 867 868 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 869 SMU_IH_INTERRUPT_ID_TO_DRIVER, 870 irq_src); 871 if (ret) 872 return ret; 873 874 return ret; 875 } 876 877 static int smu_v15_0_wait_for_reset_complete(struct smu_context *smu, 878 uint64_t event_arg) 879 { 880 int ret = 0; 881 882 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n"); 883 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL); 884 885 return ret; 886 } 887 888 int smu_v15_0_wait_for_event(struct smu_context *smu, 889 enum smu_event_type event, 890 uint64_t event_arg) 891 { 892 int ret = -EINVAL; 893 894 switch (event) { 895 case SMU_EVENT_RESET_COMPLETE: 896 ret = smu_v15_0_wait_for_reset_complete(smu, event_arg); 897 break; 898 default: 899 break; 900 } 901 902 return ret; 903 } 904 905 int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 906 uint32_t *min, uint32_t *max) 907 { 908 int ret = 0, clk_id = 0; 909 uint32_t param = 0; 910 uint32_t clock_limit; 911 912 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 913 switch (clk_type) { 914 case SMU_MCLK: 915 case SMU_UCLK: 916 clock_limit = smu->smu_table.boot_values.uclk; 917 break; 918 case SMU_GFXCLK: 919 case SMU_SCLK: 920 clock_limit = smu->smu_table.boot_values.gfxclk; 921 break; 922 case SMU_SOCCLK: 923 clock_limit = smu->smu_table.boot_values.socclk; 924 break; 925 default: 926 clock_limit = 0; 927 break; 928 } 929 930 /* clock in Mhz unit */ 931 if (min) 932 *min = clock_limit / 100; 933 if (max) 934 *max = clock_limit / 100; 935 936 return 0; 937 } 938 939 clk_id = smu_cmn_to_asic_specific_index(smu, 940 CMN2ASIC_MAPPING_CLK, 941 clk_type); 942 if (clk_id < 0) { 943 ret = -EINVAL; 944 goto failed; 945 } 946 param = (clk_id & 0xffff) << 16; 947 948 if (max) { 949 if (smu->adev->pm.ac_power) 950 ret = smu_cmn_send_smc_msg_with_param(smu, 951 SMU_MSG_GetMaxDpmFreq, 952 param, 953 max); 954 else 955 ret = smu_cmn_send_smc_msg_with_param(smu, 956 SMU_MSG_GetDcModeMaxDpmFreq, 957 param, 958 max); 959 if (ret) 960 goto failed; 961 } 962 963 if (min) { 964 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 965 if (ret) 966 goto failed; 967 } 968 969 failed: 970 return ret; 971 } 972 973 int smu_v15_0_set_soft_freq_limited_range(struct smu_context *smu, 974 enum smu_clk_type clk_type, 975 uint32_t min, 976 uint32_t max, 977 bool automatic) 978 { 979 int ret = 0, clk_id = 0; 980 uint32_t param; 981 982 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 983 return 0; 984 985 clk_id = smu_cmn_to_asic_specific_index(smu, 986 CMN2ASIC_MAPPING_CLK, 987 clk_type); 988 if (clk_id < 0) 989 return clk_id; 990 991 if (max > 0) { 992 if (automatic) 993 param = (uint32_t)((clk_id << 16) | 0xffff); 994 else 995 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 996 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 997 param, NULL); 998 if (ret) 999 goto out; 1000 } 1001 1002 if (min > 0) { 1003 if (automatic) 1004 param = (uint32_t)((clk_id << 16) | 0); 1005 else 1006 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1007 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1008 param, NULL); 1009 if (ret) 1010 goto out; 1011 } 1012 1013 out: 1014 return ret; 1015 } 1016 1017 int smu_v15_0_set_hard_freq_limited_range(struct smu_context *smu, 1018 enum smu_clk_type clk_type, 1019 uint32_t min, 1020 uint32_t max) 1021 { 1022 int ret = 0, clk_id = 0; 1023 uint32_t param; 1024 1025 if (min <= 0 && max <= 0) 1026 return -EINVAL; 1027 1028 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1029 return 0; 1030 1031 clk_id = smu_cmn_to_asic_specific_index(smu, 1032 CMN2ASIC_MAPPING_CLK, 1033 clk_type); 1034 if (clk_id < 0) 1035 return clk_id; 1036 1037 if (max > 0) { 1038 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1039 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1040 param, NULL); 1041 if (ret) 1042 return ret; 1043 } 1044 1045 if (min > 0) { 1046 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1047 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1048 param, NULL); 1049 if (ret) 1050 return ret; 1051 } 1052 1053 return ret; 1054 } 1055 1056 int smu_v15_0_set_performance_level(struct smu_context *smu, 1057 enum amd_dpm_forced_level level) 1058 { 1059 struct smu_15_0_dpm_context *dpm_context = 1060 smu->smu_dpm.dpm_context; 1061 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; 1062 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; 1063 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; 1064 struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table; 1065 struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table; 1066 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; 1067 struct smu_umd_pstate_table *pstate_table = 1068 &smu->pstate_table; 1069 struct amdgpu_device *adev = smu->adev; 1070 uint32_t sclk_min = 0, sclk_max = 0; 1071 uint32_t mclk_min = 0, mclk_max = 0; 1072 uint32_t socclk_min = 0, socclk_max = 0; 1073 uint32_t vclk_min = 0, vclk_max = 0; 1074 uint32_t dclk_min = 0, dclk_max = 0; 1075 uint32_t fclk_min = 0, fclk_max = 0; 1076 int ret = 0, i; 1077 bool auto_level = false; 1078 1079 switch (level) { 1080 case AMD_DPM_FORCED_LEVEL_HIGH: 1081 sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table); 1082 mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table); 1083 socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table); 1084 vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table); 1085 dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table); 1086 fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table); 1087 break; 1088 case AMD_DPM_FORCED_LEVEL_LOW: 1089 sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table); 1090 mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table); 1091 socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table); 1092 vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table); 1093 dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table); 1094 fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table); 1095 break; 1096 case AMD_DPM_FORCED_LEVEL_AUTO: 1097 sclk_min = SMU_DPM_TABLE_MIN(gfx_table); 1098 sclk_max = SMU_DPM_TABLE_MAX(gfx_table); 1099 mclk_min = SMU_DPM_TABLE_MIN(mem_table); 1100 mclk_max = SMU_DPM_TABLE_MAX(mem_table); 1101 socclk_min = SMU_DPM_TABLE_MIN(soc_table); 1102 socclk_max = SMU_DPM_TABLE_MAX(soc_table); 1103 vclk_min = SMU_DPM_TABLE_MIN(vclk_table); 1104 vclk_max = SMU_DPM_TABLE_MAX(vclk_table); 1105 dclk_min = SMU_DPM_TABLE_MIN(dclk_table); 1106 dclk_max = SMU_DPM_TABLE_MAX(dclk_table); 1107 fclk_min = SMU_DPM_TABLE_MIN(fclk_table); 1108 fclk_max = SMU_DPM_TABLE_MAX(fclk_table); 1109 auto_level = true; 1110 break; 1111 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1112 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1113 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1114 socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1115 vclk_min = vclk_max = pstate_table->vclk_pstate.standard; 1116 dclk_min = dclk_max = pstate_table->dclk_pstate.standard; 1117 fclk_min = fclk_max = pstate_table->fclk_pstate.standard; 1118 break; 1119 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1120 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1121 break; 1122 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1123 mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1124 break; 1125 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1126 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1127 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1128 socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1129 vclk_min = vclk_max = pstate_table->vclk_pstate.peak; 1130 dclk_min = dclk_max = pstate_table->dclk_pstate.peak; 1131 fclk_min = fclk_max = pstate_table->fclk_pstate.peak; 1132 break; 1133 case AMD_DPM_FORCED_LEVEL_MANUAL: 1134 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1135 return 0; 1136 default: 1137 dev_err(adev->dev, "Invalid performance level %d\n", level); 1138 return -EINVAL; 1139 } 1140 1141 if (sclk_min && sclk_max) { 1142 ret = smu_v15_0_set_soft_freq_limited_range(smu, 1143 SMU_GFXCLK, 1144 sclk_min, 1145 sclk_max, 1146 auto_level); 1147 if (ret) 1148 return ret; 1149 1150 pstate_table->gfxclk_pstate.curr.min = sclk_min; 1151 pstate_table->gfxclk_pstate.curr.max = sclk_max; 1152 } 1153 1154 if (mclk_min && mclk_max) { 1155 ret = smu_v15_0_set_soft_freq_limited_range(smu, 1156 SMU_MCLK, 1157 mclk_min, 1158 mclk_max, 1159 auto_level); 1160 if (ret) 1161 return ret; 1162 1163 pstate_table->uclk_pstate.curr.min = mclk_min; 1164 pstate_table->uclk_pstate.curr.max = mclk_max; 1165 } 1166 1167 if (socclk_min && socclk_max) { 1168 ret = smu_v15_0_set_soft_freq_limited_range(smu, 1169 SMU_SOCCLK, 1170 socclk_min, 1171 socclk_max, 1172 auto_level); 1173 if (ret) 1174 return ret; 1175 1176 pstate_table->socclk_pstate.curr.min = socclk_min; 1177 pstate_table->socclk_pstate.curr.max = socclk_max; 1178 } 1179 1180 if (vclk_min && vclk_max) { 1181 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1182 if (adev->vcn.harvest_config & (1 << i)) 1183 continue; 1184 ret = smu_v15_0_set_soft_freq_limited_range(smu, 1185 i ? SMU_VCLK1 : SMU_VCLK, 1186 vclk_min, 1187 vclk_max, 1188 auto_level); 1189 if (ret) 1190 return ret; 1191 } 1192 pstate_table->vclk_pstate.curr.min = vclk_min; 1193 pstate_table->vclk_pstate.curr.max = vclk_max; 1194 } 1195 1196 if (dclk_min && dclk_max) { 1197 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1198 if (adev->vcn.harvest_config & (1 << i)) 1199 continue; 1200 ret = smu_v15_0_set_soft_freq_limited_range(smu, 1201 i ? SMU_DCLK1 : SMU_DCLK, 1202 dclk_min, 1203 dclk_max, 1204 auto_level); 1205 if (ret) 1206 return ret; 1207 } 1208 pstate_table->dclk_pstate.curr.min = dclk_min; 1209 pstate_table->dclk_pstate.curr.max = dclk_max; 1210 } 1211 1212 if (fclk_min && fclk_max) { 1213 ret = smu_v15_0_set_soft_freq_limited_range(smu, 1214 SMU_FCLK, 1215 fclk_min, 1216 fclk_max, 1217 auto_level); 1218 if (ret) 1219 return ret; 1220 1221 pstate_table->fclk_pstate.curr.min = fclk_min; 1222 pstate_table->fclk_pstate.curr.max = fclk_max; 1223 } 1224 1225 return ret; 1226 } 1227 1228 int smu_v15_0_set_power_source(struct smu_context *smu, 1229 enum smu_power_src_type power_src) 1230 { 1231 int pwr_source; 1232 1233 pwr_source = smu_cmn_to_asic_specific_index(smu, 1234 CMN2ASIC_MAPPING_PWR, 1235 (uint32_t)power_src); 1236 if (pwr_source < 0) 1237 return -EINVAL; 1238 1239 return smu_cmn_send_smc_msg_with_param(smu, 1240 SMU_MSG_NotifyPowerSource, 1241 pwr_source, 1242 NULL); 1243 } 1244 1245 static int smu_v15_0_get_dpm_freq_by_index(struct smu_context *smu, 1246 enum smu_clk_type clk_type, 1247 uint16_t level, 1248 uint32_t *value) 1249 { 1250 int ret = 0, clk_id = 0; 1251 uint32_t param; 1252 1253 if (!value) 1254 return -EINVAL; 1255 1256 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1257 return 0; 1258 1259 clk_id = smu_cmn_to_asic_specific_index(smu, 1260 CMN2ASIC_MAPPING_CLK, 1261 clk_type); 1262 if (clk_id < 0) 1263 return clk_id; 1264 1265 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1266 1267 ret = smu_cmn_send_smc_msg_with_param(smu, 1268 SMU_MSG_GetDpmFreqByIndex, 1269 param, 1270 value); 1271 if (ret) 1272 return ret; 1273 1274 *value = *value & 0x7fffffff; 1275 1276 return ret; 1277 } 1278 1279 static int smu_v15_0_get_dpm_level_count(struct smu_context *smu, 1280 enum smu_clk_type clk_type, 1281 uint32_t *value) 1282 { 1283 int ret; 1284 1285 ret = smu_v15_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value); 1286 1287 return ret; 1288 } 1289 1290 static int smu_v15_0_get_fine_grained_status(struct smu_context *smu, 1291 enum smu_clk_type clk_type, 1292 bool *is_fine_grained_dpm) 1293 { 1294 int ret = 0, clk_id = 0; 1295 uint32_t param; 1296 uint32_t value; 1297 1298 if (!is_fine_grained_dpm) 1299 return -EINVAL; 1300 1301 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1302 return 0; 1303 1304 clk_id = smu_cmn_to_asic_specific_index(smu, 1305 CMN2ASIC_MAPPING_CLK, 1306 clk_type); 1307 if (clk_id < 0) 1308 return clk_id; 1309 1310 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff); 1311 1312 ret = smu_cmn_send_smc_msg_with_param(smu, 1313 SMU_MSG_GetDpmFreqByIndex, 1314 param, 1315 &value); 1316 if (ret) 1317 return ret; 1318 1319 /* 1320 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM 1321 * now, we un-support it 1322 */ 1323 *is_fine_grained_dpm = value & 0x80000000; 1324 1325 return 0; 1326 } 1327 1328 int smu_v15_0_set_single_dpm_table(struct smu_context *smu, 1329 enum smu_clk_type clk_type, 1330 struct smu_dpm_table *single_dpm_table) 1331 { 1332 int ret = 0; 1333 uint32_t clk; 1334 bool is_fine_grained; 1335 int i; 1336 1337 ret = smu_v15_0_get_dpm_level_count(smu, 1338 clk_type, 1339 &single_dpm_table->count); 1340 if (ret) { 1341 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 1342 return ret; 1343 } 1344 1345 ret = smu_v15_0_get_fine_grained_status(smu, 1346 clk_type, 1347 &is_fine_grained); 1348 if (ret) { 1349 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); 1350 return ret; 1351 } 1352 1353 if (is_fine_grained) 1354 single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 1355 1356 for (i = 0; i < single_dpm_table->count; i++) { 1357 ret = smu_v15_0_get_dpm_freq_by_index(smu, 1358 clk_type, 1359 i, 1360 &clk); 1361 if (ret) { 1362 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 1363 return ret; 1364 } 1365 1366 single_dpm_table->dpm_levels[i].value = clk; 1367 single_dpm_table->dpm_levels[i].enabled = true; 1368 } 1369 1370 return 0; 1371 } 1372 1373 int smu_v15_0_set_vcn_enable(struct smu_context *smu, 1374 bool enable, 1375 int inst) 1376 { 1377 struct amdgpu_device *adev = smu->adev; 1378 int ret = 0; 1379 1380 if (adev->vcn.harvest_config & (1 << inst)) 1381 return ret; 1382 1383 if (smu->is_apu) { 1384 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1385 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 1386 inst << 16U, NULL); 1387 } 1388 1389 return ret; 1390 } 1391 1392 int smu_v15_0_set_jpeg_enable(struct smu_context *smu, 1393 bool enable) 1394 { 1395 struct amdgpu_device *adev = smu->adev; 1396 int i, ret = 0; 1397 1398 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 1399 if (adev->jpeg.harvest_config & (1 << i)) 1400 continue; 1401 1402 if (smu->is_apu) { 1403 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1404 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, 1405 i << 16U, NULL); 1406 } 1407 1408 if (ret) 1409 return ret; 1410 } 1411 1412 return ret; 1413 } 1414 1415 int smu_v15_0_run_btc(struct smu_context *smu) 1416 { 1417 int res; 1418 1419 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 1420 if (res) 1421 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 1422 1423 return res; 1424 } 1425 1426 int smu_v15_0_gpo_control(struct smu_context *smu, 1427 bool enablement) 1428 { 1429 int res; 1430 1431 res = smu_cmn_send_smc_msg_with_param(smu, 1432 SMU_MSG_AllowGpo, 1433 enablement ? 1 : 0, 1434 NULL); 1435 if (res) 1436 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement); 1437 1438 return res; 1439 } 1440 1441 int smu_v15_0_deep_sleep_control(struct smu_context *smu, 1442 bool enablement) 1443 { 1444 struct amdgpu_device *adev = smu->adev; 1445 int ret = 0; 1446 1447 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 1448 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 1449 if (ret) { 1450 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 1451 return ret; 1452 } 1453 } 1454 1455 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 1456 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 1457 if (ret) { 1458 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 1459 return ret; 1460 } 1461 } 1462 1463 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 1464 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 1465 if (ret) { 1466 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 1467 return ret; 1468 } 1469 } 1470 1471 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 1472 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 1473 if (ret) { 1474 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 1475 return ret; 1476 } 1477 } 1478 1479 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 1480 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 1481 if (ret) { 1482 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 1483 return ret; 1484 } 1485 } 1486 1487 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) { 1488 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement); 1489 if (ret) { 1490 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable"); 1491 return ret; 1492 } 1493 } 1494 1495 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) { 1496 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement); 1497 if (ret) { 1498 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable"); 1499 return ret; 1500 } 1501 } 1502 1503 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) { 1504 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement); 1505 if (ret) { 1506 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable"); 1507 return ret; 1508 } 1509 } 1510 1511 return ret; 1512 } 1513 1514 int smu_v15_0_gfx_ulv_control(struct smu_context *smu, 1515 bool enablement) 1516 { 1517 int ret = 0; 1518 1519 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 1520 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 1521 1522 return ret; 1523 } 1524 1525 int smu_v15_0_baco_set_armd3_sequence(struct smu_context *smu, 1526 enum smu_baco_seq baco_seq) 1527 { 1528 struct smu_baco_context *smu_baco = &smu->smu_baco; 1529 int ret; 1530 1531 ret = smu_cmn_send_smc_msg_with_param(smu, 1532 SMU_MSG_ArmD3, 1533 baco_seq, 1534 NULL); 1535 if (ret) 1536 return ret; 1537 1538 if (baco_seq == BACO_SEQ_BAMACO || 1539 baco_seq == BACO_SEQ_BACO) 1540 smu_baco->state = SMU_BACO_STATE_ENTER; 1541 else 1542 smu_baco->state = SMU_BACO_STATE_EXIT; 1543 1544 return 0; 1545 } 1546 1547 int smu_v15_0_get_bamaco_support(struct smu_context *smu) 1548 { 1549 struct smu_baco_context *smu_baco = &smu->smu_baco; 1550 int bamaco_support = 0; 1551 1552 if (amdgpu_sriov_vf(smu->adev) || 1553 !smu_baco->platform_support) 1554 return 0; 1555 1556 if (smu_baco->maco_support) 1557 bamaco_support |= MACO_SUPPORT; 1558 1559 /* return true if ASIC is in BACO state already */ 1560 if (smu_v15_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER) 1561 return (bamaco_support |= BACO_SUPPORT); 1562 1563 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 1564 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 1565 return 0; 1566 1567 return (bamaco_support |= BACO_SUPPORT); 1568 } 1569 1570 enum smu_baco_state smu_v15_0_baco_get_state(struct smu_context *smu) 1571 { 1572 struct smu_baco_context *smu_baco = &smu->smu_baco; 1573 1574 return smu_baco->state; 1575 } 1576 1577 int smu_v15_0_baco_set_state(struct smu_context *smu, 1578 enum smu_baco_state state) 1579 { 1580 struct smu_baco_context *smu_baco = &smu->smu_baco; 1581 struct amdgpu_device *adev = smu->adev; 1582 int ret = 0; 1583 1584 if (smu_v15_0_baco_get_state(smu) == state) 1585 return 0; 1586 1587 if (state == SMU_BACO_STATE_ENTER) { 1588 ret = smu_cmn_send_smc_msg_with_param(smu, 1589 SMU_MSG_EnterBaco, 1590 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ? 1591 BACO_SEQ_BAMACO : BACO_SEQ_BACO, 1592 NULL); 1593 } else { 1594 ret = smu_cmn_send_smc_msg(smu, 1595 SMU_MSG_ExitBaco, 1596 NULL); 1597 if (ret) 1598 return ret; 1599 1600 /* clear vbios scratch 6 and 7 for coming asic reinit */ 1601 WREG32(adev->bios_scratch_reg_offset + 6, 0); 1602 WREG32(adev->bios_scratch_reg_offset + 7, 0); 1603 } 1604 1605 if (!ret) 1606 smu_baco->state = state; 1607 1608 return ret; 1609 } 1610 1611 int smu_v15_0_baco_enter(struct smu_context *smu) 1612 { 1613 int ret = 0; 1614 1615 ret = smu_v15_0_baco_set_state(smu, 1616 SMU_BACO_STATE_ENTER); 1617 if (ret) 1618 return ret; 1619 1620 msleep(10); 1621 1622 return ret; 1623 } 1624 1625 int smu_v15_0_baco_exit(struct smu_context *smu) 1626 { 1627 return smu_v15_0_baco_set_state(smu, 1628 SMU_BACO_STATE_EXIT); 1629 } 1630 1631 int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu) 1632 { 1633 struct smu_msg_ctl *ctl = &smu->msg_ctl; 1634 struct amdgpu_device *adev = smu->adev; 1635 int ret; 1636 1637 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1638 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu, 1639 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL); 1640 } 1641 1642 mutex_lock(&ctl->lock); 1643 ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu, 1644 ENABLE_IMU_ARG_GFXOFF_ENABLE); 1645 mutex_unlock(&ctl->lock); 1646 1647 return ret; 1648 } 1649 1650 int smu_v15_0_od_edit_dpm_table(struct smu_context *smu, 1651 enum PP_OD_DPM_TABLE_COMMAND type, 1652 long input[], uint32_t size) 1653 { 1654 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1655 int ret = 0; 1656 1657 /* Only allowed in manual mode */ 1658 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1659 return -EINVAL; 1660 1661 switch (type) { 1662 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1663 if (size != 2) { 1664 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1665 return -EINVAL; 1666 } 1667 1668 if (input[0] == 0) { 1669 if (input[1] < smu->gfx_default_hard_min_freq) { 1670 dev_warn(smu->adev->dev, 1671 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1672 input[1], smu->gfx_default_hard_min_freq); 1673 return -EINVAL; 1674 } 1675 smu->gfx_actual_hard_min_freq = input[1]; 1676 } else if (input[0] == 1) { 1677 if (input[1] > smu->gfx_default_soft_max_freq) { 1678 dev_warn(smu->adev->dev, 1679 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1680 input[1], smu->gfx_default_soft_max_freq); 1681 return -EINVAL; 1682 } 1683 smu->gfx_actual_soft_max_freq = input[1]; 1684 } else { 1685 return -EINVAL; 1686 } 1687 break; 1688 case PP_OD_RESTORE_DEFAULT_TABLE: 1689 if (size != 0) { 1690 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1691 return -EINVAL; 1692 } 1693 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1694 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1695 break; 1696 case PP_OD_COMMIT_DPM_TABLE: 1697 if (size != 0) { 1698 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1699 return -EINVAL; 1700 } 1701 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1702 dev_err(smu->adev->dev, 1703 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1704 smu->gfx_actual_hard_min_freq, 1705 smu->gfx_actual_soft_max_freq); 1706 return -EINVAL; 1707 } 1708 1709 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1710 smu->gfx_actual_hard_min_freq, 1711 NULL); 1712 if (ret) { 1713 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1714 return ret; 1715 } 1716 1717 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1718 smu->gfx_actual_soft_max_freq, 1719 NULL); 1720 if (ret) { 1721 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1722 return ret; 1723 } 1724 break; 1725 default: 1726 return -ENOSYS; 1727 } 1728 1729 return ret; 1730 } 1731 1732 static int smu_v15_0_allow_ih_interrupt(struct smu_context *smu) 1733 { 1734 return smu_cmn_send_smc_msg(smu, 1735 SMU_MSG_AllowIHHostInterrupt, 1736 NULL); 1737 } 1738 1739 int smu_v15_0_enable_thermal_alert(struct smu_context *smu) 1740 { 1741 int ret = 0; 1742 1743 if (!smu->irq_source.num_types) 1744 return 0; 1745 1746 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 1747 if (ret) 1748 return ret; 1749 1750 return smu_v15_0_allow_ih_interrupt(smu); 1751 } 1752 1753 int smu_v15_0_disable_thermal_alert(struct smu_context *smu) 1754 { 1755 if (!smu->irq_source.num_types) 1756 return 0; 1757 1758 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1759 } 1760