1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/reboot.h> 27 28 #define SMU_11_0_PARTIAL_PPTABLE 29 #define SWSMU_CODE_LAYER_L3 30 31 #include "amdgpu.h" 32 #include "amdgpu_smu.h" 33 #include "atomfirmware.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_atombios.h" 36 #include "smu_v11_0.h" 37 #include "soc15_common.h" 38 #include "atom.h" 39 #include "amdgpu_ras.h" 40 #include "smu_cmn.h" 41 42 #include "asic_reg/thm/thm_11_0_2_offset.h" 43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h" 44 #include "asic_reg/mp/mp_11_0_offset.h" 45 #include "asic_reg/mp/mp_11_0_sh_mask.h" 46 #include "asic_reg/smuio/smuio_11_0_0_offset.h" 47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h" 48 49 /* 50 * DO NOT use these for err/warn/info/debug messages. 51 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52 * They are more MGPU friendly. 53 */ 54 #undef pr_err 55 #undef pr_warn 56 #undef pr_info 57 #undef pr_debug 58 59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin"); 60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin"); 61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin"); 62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin"); 63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin"); 64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin"); 65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin"); 66 MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin"); 67 68 #define SMU11_VOLTAGE_SCALE 4 69 70 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms 71 72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 73 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L 74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 75 #define smnPCIE_LC_SPEED_CNTL 0x11140290 76 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE 78 79 #define mmTHM_BACO_CNTL_ARCT 0xA7 80 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0 81 82 static void smu_v11_0_poll_baco_exit(struct smu_context *smu) 83 { 84 struct amdgpu_device *adev = smu->adev; 85 uint32_t data, loop = 0; 86 87 do { 88 usleep_range(1000, 1100); 89 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); 90 } while ((data & 0x100) && (++loop < 100)); 91 } 92 93 int smu_v11_0_init_microcode(struct smu_context *smu) 94 { 95 struct amdgpu_device *adev = smu->adev; 96 char ucode_prefix[25]; 97 int err = 0; 98 const struct smc_firmware_header_v1_0 *hdr; 99 const struct common_firmware_header *header; 100 struct amdgpu_firmware_info *ucode = NULL; 101 102 if (amdgpu_sriov_vf(adev) && 103 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) || 104 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)))) 105 return 0; 106 107 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); 108 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, 109 "amdgpu/%s.bin", ucode_prefix); 110 if (err) 111 goto out; 112 113 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 114 amdgpu_ucode_print_smc_hdr(&hdr->header); 115 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 116 117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 118 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 119 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 120 ucode->fw = adev->pm.fw; 121 header = (const struct common_firmware_header *)ucode->fw->data; 122 adev->firmware.fw_size += 123 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 124 } 125 126 out: 127 if (err) 128 amdgpu_ucode_release(&adev->pm.fw); 129 return err; 130 } 131 132 void smu_v11_0_fini_microcode(struct smu_context *smu) 133 { 134 struct amdgpu_device *adev = smu->adev; 135 136 amdgpu_ucode_release(&adev->pm.fw); 137 adev->pm.fw_version = 0; 138 } 139 140 int smu_v11_0_load_microcode(struct smu_context *smu) 141 { 142 struct amdgpu_device *adev = smu->adev; 143 const uint32_t *src; 144 const struct smc_firmware_header_v1_0 *hdr; 145 uint32_t addr_start = MP1_SRAM; 146 uint32_t i; 147 uint32_t smc_fw_size; 148 uint32_t mp1_fw_flags; 149 150 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 151 src = (const uint32_t *)(adev->pm.fw->data + 152 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 153 smc_fw_size = hdr->header.ucode_size_bytes; 154 155 for (i = 1; i < smc_fw_size/4 - 1; i++) { 156 WREG32_PCIE(addr_start, src[i]); 157 addr_start += 4; 158 } 159 160 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 161 1 & MP1_SMN_PUB_CTRL__RESET_MASK); 162 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 163 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); 164 165 for (i = 0; i < adev->usec_timeout; i++) { 166 mp1_fw_flags = RREG32_PCIE(MP1_Public | 167 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 168 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 169 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 170 break; 171 udelay(1); 172 } 173 174 if (i == adev->usec_timeout) 175 return -ETIME; 176 177 return 0; 178 } 179 180 int smu_v11_0_check_fw_status(struct smu_context *smu) 181 { 182 struct amdgpu_device *adev = smu->adev; 183 uint32_t mp1_fw_flags; 184 185 mp1_fw_flags = RREG32_PCIE(MP1_Public | 186 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 187 188 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 189 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 190 return 0; 191 192 return -EIO; 193 } 194 195 int smu_v11_0_check_fw_version(struct smu_context *smu) 196 { 197 struct amdgpu_device *adev = smu->adev; 198 uint32_t if_version = 0xff, smu_version = 0xff; 199 uint8_t smu_program, smu_major, smu_minor, smu_debug; 200 int ret = 0; 201 202 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 203 if (ret) 204 return ret; 205 206 smu_program = (smu_version >> 24) & 0xff; 207 smu_major = (smu_version >> 16) & 0xff; 208 smu_minor = (smu_version >> 8) & 0xff; 209 smu_debug = (smu_version >> 0) & 0xff; 210 if (smu->is_apu) 211 adev->pm.fw_version = smu_version; 212 213 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 214 case IP_VERSION(11, 0, 0): 215 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10; 216 break; 217 case IP_VERSION(11, 0, 9): 218 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12; 219 break; 220 case IP_VERSION(11, 0, 5): 221 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14; 222 break; 223 case IP_VERSION(11, 0, 7): 224 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid; 225 break; 226 case IP_VERSION(11, 0, 11): 227 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder; 228 break; 229 case IP_VERSION(11, 5, 0): 230 case IP_VERSION(11, 5, 2): 231 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH; 232 break; 233 case IP_VERSION(11, 0, 12): 234 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish; 235 break; 236 case IP_VERSION(11, 0, 13): 237 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby; 238 break; 239 case IP_VERSION(11, 0, 8): 240 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish; 241 break; 242 case IP_VERSION(11, 0, 2): 243 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT; 244 break; 245 default: 246 dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n", 247 amdgpu_ip_version(adev, MP1_HWIP, 0)); 248 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV; 249 break; 250 } 251 252 /* 253 * 1. if_version mismatch is not critical as our fw is designed 254 * to be backward compatible. 255 * 2. New fw usually brings some optimizations. But that's visible 256 * only on the paired driver. 257 * Considering above, we just leave user a verbal message instead 258 * of halt driver loading. 259 */ 260 if (if_version != smu->smc_driver_if_version) { 261 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " 262 "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n", 263 smu->smc_driver_if_version, if_version, 264 smu_program, smu_version, smu_major, smu_minor, smu_debug); 265 dev_info(smu->adev->dev, "SMU driver if version not matched\n"); 266 } 267 268 return ret; 269 } 270 271 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 272 { 273 struct amdgpu_device *adev = smu->adev; 274 uint32_t ppt_offset_bytes; 275 const struct smc_firmware_header_v2_0 *v2; 276 277 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 278 279 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 280 *size = le32_to_cpu(v2->ppt_size_bytes); 281 *table = (uint8_t *)v2 + ppt_offset_bytes; 282 283 return 0; 284 } 285 286 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, 287 uint32_t *size, uint32_t pptable_id) 288 { 289 struct amdgpu_device *adev = smu->adev; 290 const struct smc_firmware_header_v2_1 *v2_1; 291 struct smc_soft_pptable_entry *entries; 292 uint32_t pptable_count = 0; 293 int i = 0; 294 295 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 296 entries = (struct smc_soft_pptable_entry *) 297 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 298 pptable_count = le32_to_cpu(v2_1->pptable_count); 299 for (i = 0; i < pptable_count; i++) { 300 if (le32_to_cpu(entries[i].id) == pptable_id) { 301 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 302 *size = le32_to_cpu(entries[i].ppt_size_bytes); 303 break; 304 } 305 } 306 307 if (i == pptable_count) 308 return -EINVAL; 309 310 return 0; 311 } 312 313 int smu_v11_0_setup_pptable(struct smu_context *smu) 314 { 315 struct amdgpu_device *adev = smu->adev; 316 const struct smc_firmware_header_v1_0 *hdr; 317 int ret, index; 318 uint32_t size = 0; 319 uint16_t atom_table_size; 320 uint8_t frev, crev; 321 void *table; 322 uint16_t version_major, version_minor; 323 324 if (!amdgpu_sriov_vf(adev)) { 325 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 326 version_major = le16_to_cpu(hdr->header.header_version_major); 327 version_minor = le16_to_cpu(hdr->header.header_version_minor); 328 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) { 329 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id); 330 switch (version_minor) { 331 case 0: 332 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size); 333 break; 334 case 1: 335 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size, 336 smu->smu_table.boot_values.pp_table_id); 337 break; 338 default: 339 ret = -EINVAL; 340 break; 341 } 342 if (ret) 343 return ret; 344 goto out; 345 } 346 } 347 348 dev_info(adev->dev, "use vbios provided pptable\n"); 349 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 350 powerplayinfo); 351 352 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 353 (uint8_t **)&table); 354 if (ret) 355 return ret; 356 size = atom_table_size; 357 358 out: 359 if (!smu->smu_table.power_play_table) 360 smu->smu_table.power_play_table = table; 361 if (!smu->smu_table.power_play_table_size) 362 smu->smu_table.power_play_table_size = size; 363 364 return 0; 365 } 366 367 int smu_v11_0_init_smc_tables(struct smu_context *smu) 368 { 369 struct smu_table_context *smu_table = &smu->smu_table; 370 struct smu_table *tables = smu_table->tables; 371 int ret = 0; 372 373 smu_table->driver_pptable = 374 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 375 if (!smu_table->driver_pptable) { 376 ret = -ENOMEM; 377 goto err0_out; 378 } 379 380 smu_table->max_sustainable_clocks = 381 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL); 382 if (!smu_table->max_sustainable_clocks) { 383 ret = -ENOMEM; 384 goto err1_out; 385 } 386 387 /* Arcturus does not support OVERDRIVE */ 388 if (tables[SMU_TABLE_OVERDRIVE].size) { 389 smu_table->overdrive_table = 390 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 391 if (!smu_table->overdrive_table) { 392 ret = -ENOMEM; 393 goto err2_out; 394 } 395 396 smu_table->boot_overdrive_table = 397 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 398 if (!smu_table->boot_overdrive_table) { 399 ret = -ENOMEM; 400 goto err3_out; 401 } 402 403 smu_table->user_overdrive_table = 404 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 405 if (!smu_table->user_overdrive_table) { 406 ret = -ENOMEM; 407 goto err4_out; 408 } 409 410 } 411 412 return 0; 413 414 err4_out: 415 kfree(smu_table->boot_overdrive_table); 416 err3_out: 417 kfree(smu_table->overdrive_table); 418 err2_out: 419 kfree(smu_table->max_sustainable_clocks); 420 err1_out: 421 kfree(smu_table->driver_pptable); 422 err0_out: 423 return ret; 424 } 425 426 int smu_v11_0_fini_smc_tables(struct smu_context *smu) 427 { 428 struct smu_table_context *smu_table = &smu->smu_table; 429 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 430 431 kfree(smu_table->gpu_metrics_table); 432 kfree(smu_table->user_overdrive_table); 433 kfree(smu_table->boot_overdrive_table); 434 kfree(smu_table->overdrive_table); 435 kfree(smu_table->max_sustainable_clocks); 436 kfree(smu_table->driver_pptable); 437 kfree(smu_table->clocks_table); 438 smu_table->gpu_metrics_table = NULL; 439 smu_table->user_overdrive_table = NULL; 440 smu_table->boot_overdrive_table = NULL; 441 smu_table->overdrive_table = NULL; 442 smu_table->max_sustainable_clocks = NULL; 443 smu_table->driver_pptable = NULL; 444 smu_table->clocks_table = NULL; 445 kfree(smu_table->hardcode_pptable); 446 smu_table->hardcode_pptable = NULL; 447 448 kfree(smu_table->driver_smu_config_table); 449 kfree(smu_table->ecc_table); 450 kfree(smu_table->metrics_table); 451 kfree(smu_table->watermarks_table); 452 smu_table->driver_smu_config_table = NULL; 453 smu_table->ecc_table = NULL; 454 smu_table->metrics_table = NULL; 455 smu_table->watermarks_table = NULL; 456 smu_table->metrics_time = 0; 457 458 kfree(smu_dpm->dpm_context); 459 kfree(smu_dpm->golden_dpm_context); 460 kfree(smu_dpm->dpm_current_power_state); 461 kfree(smu_dpm->dpm_request_power_state); 462 smu_dpm->dpm_context = NULL; 463 smu_dpm->golden_dpm_context = NULL; 464 smu_dpm->dpm_context_size = 0; 465 smu_dpm->dpm_current_power_state = NULL; 466 smu_dpm->dpm_request_power_state = NULL; 467 468 return 0; 469 } 470 471 int smu_v11_0_init_power(struct smu_context *smu) 472 { 473 struct amdgpu_device *adev = smu->adev; 474 struct smu_power_context *smu_power = &smu->smu_power; 475 u32 ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0); 476 size_t size = ((ip_version == IP_VERSION(11, 5, 0)) || 477 (ip_version == IP_VERSION(11, 5, 2))) ? 478 sizeof(struct smu_11_5_power_context) : 479 sizeof(struct smu_11_0_power_context); 480 481 smu_power->power_context = kzalloc(size, GFP_KERNEL); 482 if (!smu_power->power_context) 483 return -ENOMEM; 484 smu_power->power_context_size = size; 485 486 return 0; 487 } 488 489 int smu_v11_0_fini_power(struct smu_context *smu) 490 { 491 struct smu_power_context *smu_power = &smu->smu_power; 492 493 kfree(smu_power->power_context); 494 smu_power->power_context = NULL; 495 smu_power->power_context_size = 0; 496 497 return 0; 498 } 499 500 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev, 501 uint8_t clk_id, 502 uint8_t syspll_id, 503 uint32_t *clk_freq) 504 { 505 struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; 506 struct atom_get_smu_clock_info_output_parameters_v3_1 *output; 507 int ret, index; 508 509 input.clk_id = clk_id; 510 input.syspll_id = syspll_id; 511 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; 512 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, 513 getsmuclockinfo); 514 515 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 516 (uint32_t *)&input, sizeof(input)); 517 if (ret) 518 return -EINVAL; 519 520 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; 521 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; 522 523 return 0; 524 } 525 526 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) 527 { 528 int ret, index; 529 uint16_t size; 530 uint8_t frev, crev; 531 struct atom_common_table_header *header; 532 struct atom_firmware_info_v3_3 *v_3_3; 533 struct atom_firmware_info_v3_1 *v_3_1; 534 535 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 536 firmwareinfo); 537 538 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 539 (uint8_t **)&header); 540 if (ret) 541 return ret; 542 543 if (header->format_revision != 3) { 544 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n"); 545 return -EINVAL; 546 } 547 548 switch (header->content_revision) { 549 case 0: 550 case 1: 551 case 2: 552 v_3_1 = (struct atom_firmware_info_v3_1 *)header; 553 smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 554 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 555 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 556 smu->smu_table.boot_values.socclk = 0; 557 smu->smu_table.boot_values.dcefclk = 0; 558 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 559 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 560 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 561 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 562 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 563 smu->smu_table.boot_values.pp_table_id = 0; 564 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability; 565 break; 566 case 3: 567 case 4: 568 default: 569 v_3_3 = (struct atom_firmware_info_v3_3 *)header; 570 smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 571 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 572 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 573 smu->smu_table.boot_values.socclk = 0; 574 smu->smu_table.boot_values.dcefclk = 0; 575 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 576 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 577 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 578 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 579 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 580 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 581 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability; 582 } 583 584 smu->smu_table.boot_values.format_revision = header->format_revision; 585 smu->smu_table.boot_values.content_revision = header->content_revision; 586 587 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 588 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID, 589 (uint8_t)0, 590 &smu->smu_table.boot_values.socclk); 591 592 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 593 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID, 594 (uint8_t)0, 595 &smu->smu_table.boot_values.dcefclk); 596 597 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 598 (uint8_t)SMU11_SYSPLL0_ECLK_ID, 599 (uint8_t)0, 600 &smu->smu_table.boot_values.eclk); 601 602 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 603 (uint8_t)SMU11_SYSPLL0_VCLK_ID, 604 (uint8_t)0, 605 &smu->smu_table.boot_values.vclk); 606 607 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 608 (uint8_t)SMU11_SYSPLL0_DCLK_ID, 609 (uint8_t)0, 610 &smu->smu_table.boot_values.dclk); 611 612 if ((smu->smu_table.boot_values.format_revision == 3) && 613 (smu->smu_table.boot_values.content_revision >= 2)) 614 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 615 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID, 616 (uint8_t)SMU11_SYSPLL1_2_ID, 617 &smu->smu_table.boot_values.fclk); 618 619 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 620 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID, 621 (uint8_t)SMU11_SYSPLL3_1_ID, 622 &smu->smu_table.boot_values.lclk); 623 624 return 0; 625 } 626 627 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu) 628 { 629 struct smu_table_context *smu_table = &smu->smu_table; 630 struct smu_table *memory_pool = &smu_table->memory_pool; 631 int ret = 0; 632 uint64_t address; 633 uint32_t address_low, address_high; 634 635 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 636 return ret; 637 638 address = (uintptr_t)memory_pool->cpu_addr; 639 address_high = (uint32_t)upper_32_bits(address); 640 address_low = (uint32_t)lower_32_bits(address); 641 642 ret = smu_cmn_send_smc_msg_with_param(smu, 643 SMU_MSG_SetSystemVirtualDramAddrHigh, 644 address_high, 645 NULL); 646 if (ret) 647 return ret; 648 ret = smu_cmn_send_smc_msg_with_param(smu, 649 SMU_MSG_SetSystemVirtualDramAddrLow, 650 address_low, 651 NULL); 652 if (ret) 653 return ret; 654 655 address = memory_pool->mc_address; 656 address_high = (uint32_t)upper_32_bits(address); 657 address_low = (uint32_t)lower_32_bits(address); 658 659 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 660 address_high, NULL); 661 if (ret) 662 return ret; 663 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 664 address_low, NULL); 665 if (ret) 666 return ret; 667 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 668 (uint32_t)memory_pool->size, NULL); 669 if (ret) 670 return ret; 671 672 return ret; 673 } 674 675 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 676 { 677 int ret; 678 679 ret = smu_cmn_send_smc_msg_with_param(smu, 680 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); 681 if (ret) 682 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!"); 683 684 return ret; 685 } 686 687 int smu_v11_0_set_driver_table_location(struct smu_context *smu) 688 { 689 struct smu_table *driver_table = &smu->smu_table.driver_table; 690 int ret = 0; 691 692 if (driver_table->mc_address) { 693 ret = smu_cmn_send_smc_msg_with_param(smu, 694 SMU_MSG_SetDriverDramAddrHigh, 695 upper_32_bits(driver_table->mc_address), 696 NULL); 697 if (!ret) 698 ret = smu_cmn_send_smc_msg_with_param(smu, 699 SMU_MSG_SetDriverDramAddrLow, 700 lower_32_bits(driver_table->mc_address), 701 NULL); 702 } 703 704 return ret; 705 } 706 707 int smu_v11_0_set_tool_table_location(struct smu_context *smu) 708 { 709 int ret = 0; 710 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 711 712 if (tool_table->mc_address) { 713 ret = smu_cmn_send_smc_msg_with_param(smu, 714 SMU_MSG_SetToolsDramAddrHigh, 715 upper_32_bits(tool_table->mc_address), 716 NULL); 717 if (!ret) 718 ret = smu_cmn_send_smc_msg_with_param(smu, 719 SMU_MSG_SetToolsDramAddrLow, 720 lower_32_bits(tool_table->mc_address), 721 NULL); 722 } 723 724 return ret; 725 } 726 727 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) 728 { 729 struct amdgpu_device *adev = smu->adev; 730 731 /* Navy_Flounder/Dimgrey_Cavefish do not support to change 732 * display num currently 733 */ 734 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11) || 735 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 736 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2) || 737 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 12) || 738 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) 739 return 0; 740 741 return smu_cmn_send_smc_msg_with_param(smu, 742 SMU_MSG_NumOfDisplays, 743 count, 744 NULL); 745 } 746 747 748 int smu_v11_0_set_allowed_mask(struct smu_context *smu) 749 { 750 struct smu_feature *feature = &smu->smu_feature; 751 int ret = 0; 752 uint32_t feature_mask[2]; 753 754 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) { 755 ret = -EINVAL; 756 goto failed; 757 } 758 759 bitmap_to_arr32(feature_mask, feature->allowed, 64); 760 761 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 762 feature_mask[1], NULL); 763 if (ret) 764 goto failed; 765 766 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow, 767 feature_mask[0], NULL); 768 if (ret) 769 goto failed; 770 771 failed: 772 return ret; 773 } 774 775 int smu_v11_0_system_features_control(struct smu_context *smu, 776 bool en) 777 { 778 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 779 SMU_MSG_DisableAllSmuFeatures), NULL); 780 } 781 782 int smu_v11_0_notify_display_change(struct smu_context *smu) 783 { 784 int ret = 0; 785 786 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 787 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 788 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 789 790 return ret; 791 } 792 793 static int 794 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, 795 enum smu_clk_type clock_select) 796 { 797 int ret = 0; 798 int clk_id; 799 800 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || 801 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) 802 return 0; 803 804 clk_id = smu_cmn_to_asic_specific_index(smu, 805 CMN2ASIC_MAPPING_CLK, 806 clock_select); 807 if (clk_id < 0) 808 return -EINVAL; 809 810 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, 811 clk_id << 16, clock); 812 if (ret) { 813 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); 814 return ret; 815 } 816 817 if (*clock != 0) 818 return 0; 819 820 /* if DC limit is zero, return AC limit */ 821 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, 822 clk_id << 16, clock); 823 if (ret) { 824 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!"); 825 return ret; 826 } 827 828 return 0; 829 } 830 831 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu) 832 { 833 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 834 smu->smu_table.max_sustainable_clocks; 835 int ret = 0; 836 837 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; 838 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; 839 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; 840 max_sustainable_clocks->display_clock = 0xFFFFFFFF; 841 max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 842 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 843 844 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 845 ret = smu_v11_0_get_max_sustainable_clock(smu, 846 &(max_sustainable_clocks->uclock), 847 SMU_UCLK); 848 if (ret) { 849 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!", 850 __func__); 851 return ret; 852 } 853 } 854 855 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 856 ret = smu_v11_0_get_max_sustainable_clock(smu, 857 &(max_sustainable_clocks->soc_clock), 858 SMU_SOCCLK); 859 if (ret) { 860 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!", 861 __func__); 862 return ret; 863 } 864 } 865 866 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 867 ret = smu_v11_0_get_max_sustainable_clock(smu, 868 &(max_sustainable_clocks->dcef_clock), 869 SMU_DCEFCLK); 870 if (ret) { 871 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!", 872 __func__); 873 return ret; 874 } 875 876 ret = smu_v11_0_get_max_sustainable_clock(smu, 877 &(max_sustainable_clocks->display_clock), 878 SMU_DISPCLK); 879 if (ret) { 880 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!", 881 __func__); 882 return ret; 883 } 884 ret = smu_v11_0_get_max_sustainable_clock(smu, 885 &(max_sustainable_clocks->phy_clock), 886 SMU_PHYCLK); 887 if (ret) { 888 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!", 889 __func__); 890 return ret; 891 } 892 ret = smu_v11_0_get_max_sustainable_clock(smu, 893 &(max_sustainable_clocks->pixel_clock), 894 SMU_PIXCLK); 895 if (ret) { 896 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!", 897 __func__); 898 return ret; 899 } 900 } 901 902 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 903 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 904 905 return 0; 906 } 907 908 int smu_v11_0_get_current_power_limit(struct smu_context *smu, 909 uint32_t *power_limit) 910 { 911 int power_src; 912 int ret = 0; 913 914 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 915 return -EINVAL; 916 917 power_src = smu_cmn_to_asic_specific_index(smu, 918 CMN2ASIC_MAPPING_PWR, 919 smu->adev->pm.ac_power ? 920 SMU_POWER_SOURCE_AC : 921 SMU_POWER_SOURCE_DC); 922 if (power_src < 0) 923 return -EINVAL; 924 925 /* 926 * BIT 24-31: ControllerId (only PPT0 is supported for now) 927 * BIT 16-23: PowerSource 928 */ 929 ret = smu_cmn_send_smc_msg_with_param(smu, 930 SMU_MSG_GetPptLimit, 931 (0 << 24) | (power_src << 16), 932 power_limit); 933 if (ret) 934 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 935 936 return ret; 937 } 938 939 int smu_v11_0_set_power_limit(struct smu_context *smu, 940 enum smu_ppt_limit_type limit_type, 941 uint32_t limit) 942 { 943 int power_src; 944 int ret = 0; 945 uint32_t limit_param; 946 947 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 948 return -EINVAL; 949 950 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 951 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 952 return -EOPNOTSUPP; 953 } 954 955 power_src = smu_cmn_to_asic_specific_index(smu, 956 CMN2ASIC_MAPPING_PWR, 957 smu->adev->pm.ac_power ? 958 SMU_POWER_SOURCE_AC : 959 SMU_POWER_SOURCE_DC); 960 if (power_src < 0) 961 return -EINVAL; 962 963 /* 964 * BIT 24-31: ControllerId (only PPT0 is supported for now) 965 * BIT 16-23: PowerSource 966 * BIT 0-15: PowerLimit 967 */ 968 limit_param = (limit & 0xFFFF); 969 limit_param |= 0 << 24; 970 limit_param |= (power_src) << 16; 971 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL); 972 if (ret) { 973 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 974 return ret; 975 } 976 977 smu->current_power_limit = limit; 978 979 return 0; 980 } 981 982 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu) 983 { 984 return smu_cmn_send_smc_msg(smu, 985 SMU_MSG_ReenableAcDcInterrupt, 986 NULL); 987 } 988 989 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu) 990 { 991 int ret = 0; 992 993 if (smu->dc_controlled_by_gpio && 994 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) 995 ret = smu_v11_0_ack_ac_dc_interrupt(smu); 996 997 return ret; 998 } 999 1000 void smu_v11_0_interrupt_work(struct smu_context *smu) 1001 { 1002 if (smu_v11_0_ack_ac_dc_interrupt(smu)) 1003 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n"); 1004 } 1005 1006 int smu_v11_0_enable_thermal_alert(struct smu_context *smu) 1007 { 1008 int ret = 0; 1009 1010 if (smu->smu_table.thermal_controller_type) { 1011 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 1012 if (ret) 1013 return ret; 1014 } 1015 1016 /* 1017 * After init there might have been missed interrupts triggered 1018 * before driver registers for interrupt (Ex. AC/DC). 1019 */ 1020 return smu_v11_0_process_pending_interrupt(smu); 1021 } 1022 1023 int smu_v11_0_disable_thermal_alert(struct smu_context *smu) 1024 { 1025 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1026 } 1027 1028 static uint16_t convert_to_vddc(uint8_t vid) 1029 { 1030 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE); 1031 } 1032 1033 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) 1034 { 1035 struct amdgpu_device *adev = smu->adev; 1036 uint32_t vdd = 0, val_vid = 0; 1037 1038 if (!value) 1039 return -EINVAL; 1040 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & 1041 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 1042 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 1043 1044 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); 1045 1046 *value = vdd; 1047 1048 return 0; 1049 1050 } 1051 1052 int 1053 smu_v11_0_display_clock_voltage_request(struct smu_context *smu, 1054 struct pp_display_clock_request 1055 *clock_req) 1056 { 1057 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1058 int ret = 0; 1059 enum smu_clk_type clk_select = 0; 1060 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1061 1062 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || 1063 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1064 switch (clk_type) { 1065 case amd_pp_dcef_clock: 1066 clk_select = SMU_DCEFCLK; 1067 break; 1068 case amd_pp_disp_clock: 1069 clk_select = SMU_DISPCLK; 1070 break; 1071 case amd_pp_pixel_clock: 1072 clk_select = SMU_PIXCLK; 1073 break; 1074 case amd_pp_phy_clock: 1075 clk_select = SMU_PHYCLK; 1076 break; 1077 case amd_pp_mem_clock: 1078 clk_select = SMU_UCLK; 1079 break; 1080 default: 1081 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); 1082 ret = -EINVAL; 1083 break; 1084 } 1085 1086 if (ret) 1087 goto failed; 1088 1089 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) 1090 return 0; 1091 1092 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); 1093 1094 if(clk_select == SMU_UCLK) 1095 smu->hard_min_uclk_req_from_dal = clk_freq; 1096 } 1097 1098 failed: 1099 return ret; 1100 } 1101 1102 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) 1103 { 1104 int ret = 0; 1105 struct amdgpu_device *adev = smu->adev; 1106 1107 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1108 case IP_VERSION(11, 0, 0): 1109 case IP_VERSION(11, 0, 5): 1110 case IP_VERSION(11, 0, 9): 1111 case IP_VERSION(11, 0, 7): 1112 case IP_VERSION(11, 0, 11): 1113 case IP_VERSION(11, 0, 12): 1114 case IP_VERSION(11, 0, 13): 1115 case IP_VERSION(11, 5, 0): 1116 case IP_VERSION(11, 5, 2): 1117 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 1118 return 0; 1119 if (enable) 1120 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 1121 else 1122 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 1123 break; 1124 default: 1125 break; 1126 } 1127 1128 return ret; 1129 } 1130 1131 uint32_t 1132 smu_v11_0_get_fan_control_mode(struct smu_context *smu) 1133 { 1134 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1135 return AMD_FAN_CTRL_AUTO; 1136 else 1137 return smu->user_dpm_profile.fan_mode; 1138 } 1139 1140 static int 1141 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) 1142 { 1143 int ret = 0; 1144 1145 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1146 return 0; 1147 1148 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); 1149 if (ret) 1150 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!", 1151 __func__, (auto_fan_control ? "Start" : "Stop")); 1152 1153 return ret; 1154 } 1155 1156 static int 1157 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) 1158 { 1159 struct amdgpu_device *adev = smu->adev; 1160 1161 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 1162 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 1163 CG_FDO_CTRL2, TMIN, 0)); 1164 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 1165 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 1166 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1167 1168 return 0; 1169 } 1170 1171 int 1172 smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed) 1173 { 1174 struct amdgpu_device *adev = smu->adev; 1175 uint32_t duty100, duty; 1176 uint64_t tmp64; 1177 1178 speed = min_t(uint32_t, speed, 255); 1179 1180 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 1181 CG_FDO_CTRL1, FMAX_DUTY100); 1182 if (!duty100) 1183 return -EINVAL; 1184 1185 tmp64 = (uint64_t)speed * duty100; 1186 do_div(tmp64, 255); 1187 duty = (uint32_t)tmp64; 1188 1189 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, 1190 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), 1191 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1192 1193 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1194 } 1195 1196 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, 1197 uint32_t speed) 1198 { 1199 struct amdgpu_device *adev = smu->adev; 1200 /* 1201 * crystal_clock_freq used for fan speed rpm calculation is 1202 * always 25Mhz. So, hardcode it as 2500(in 10K unit). 1203 */ 1204 uint32_t crystal_clock_freq = 2500; 1205 uint32_t tach_period; 1206 1207 if (speed == 0) 1208 return -EINVAL; 1209 /* 1210 * To prevent from possible overheat, some ASICs may have requirement 1211 * for minimum fan speed: 1212 * - For some NV10 SKU, the fan speed cannot be set lower than 1213 * 700 RPM. 1214 * - For some Sienna Cichlid SKU, the fan speed cannot be set 1215 * lower than 500 RPM. 1216 */ 1217 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1218 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, 1219 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), 1220 CG_TACH_CTRL, TARGET_PERIOD, 1221 tach_period)); 1222 1223 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1224 } 1225 1226 int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu, 1227 uint32_t *speed) 1228 { 1229 struct amdgpu_device *adev = smu->adev; 1230 uint32_t duty100, duty; 1231 uint64_t tmp64; 1232 1233 /* 1234 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1235 * detected via register retrieving. To workaround this, we will 1236 * report the fan speed as 0 PWM if user just requested such. 1237 */ 1238 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM) 1239 && !smu->user_dpm_profile.fan_speed_pwm) { 1240 *speed = 0; 1241 return 0; 1242 } 1243 1244 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 1245 CG_FDO_CTRL1, FMAX_DUTY100); 1246 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), 1247 CG_THERMAL_STATUS, FDO_PWM_DUTY); 1248 if (!duty100) 1249 return -EINVAL; 1250 1251 tmp64 = (uint64_t)duty * 255; 1252 do_div(tmp64, duty100); 1253 *speed = min_t(uint32_t, tmp64, 255); 1254 1255 return 0; 1256 } 1257 1258 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu, 1259 uint32_t *speed) 1260 { 1261 struct amdgpu_device *adev = smu->adev; 1262 uint32_t crystal_clock_freq = 2500; 1263 uint32_t tach_status; 1264 uint64_t tmp64; 1265 1266 /* 1267 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1268 * detected via register retrieving. To workaround this, we will 1269 * report the fan speed as 0 RPM if user just requested such. 1270 */ 1271 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM) 1272 && !smu->user_dpm_profile.fan_speed_rpm) { 1273 *speed = 0; 1274 return 0; 1275 } 1276 1277 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; 1278 1279 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS); 1280 if (tach_status) { 1281 do_div(tmp64, tach_status); 1282 *speed = (uint32_t)tmp64; 1283 } else { 1284 dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n"); 1285 *speed = 0; 1286 } 1287 1288 return 0; 1289 } 1290 1291 int 1292 smu_v11_0_set_fan_control_mode(struct smu_context *smu, 1293 uint32_t mode) 1294 { 1295 int ret = 0; 1296 1297 switch (mode) { 1298 case AMD_FAN_CTRL_NONE: 1299 ret = smu_v11_0_auto_fan_control(smu, 0); 1300 if (!ret) 1301 ret = smu_v11_0_set_fan_speed_pwm(smu, 255); 1302 break; 1303 case AMD_FAN_CTRL_MANUAL: 1304 ret = smu_v11_0_auto_fan_control(smu, 0); 1305 break; 1306 case AMD_FAN_CTRL_AUTO: 1307 ret = smu_v11_0_auto_fan_control(smu, 1); 1308 break; 1309 default: 1310 break; 1311 } 1312 1313 if (ret) { 1314 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__); 1315 return -EINVAL; 1316 } 1317 1318 return ret; 1319 } 1320 1321 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu, 1322 uint32_t pstate) 1323 { 1324 return smu_cmn_send_smc_msg_with_param(smu, 1325 SMU_MSG_SetXgmiMode, 1326 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 1327 NULL); 1328 } 1329 1330 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev, 1331 struct amdgpu_irq_src *source, 1332 unsigned tyep, 1333 enum amdgpu_interrupt_state state) 1334 { 1335 struct smu_context *smu = adev->powerplay.pp_handle; 1336 uint32_t low, high; 1337 uint32_t val = 0; 1338 1339 switch (state) { 1340 case AMDGPU_IRQ_STATE_DISABLE: 1341 /* For THM irqs */ 1342 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 1343 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); 1344 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); 1345 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 1346 1347 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); 1348 1349 /* For MP1 SW irqs */ 1350 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1351 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 1352 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); 1353 1354 break; 1355 case AMDGPU_IRQ_STATE_ENABLE: 1356 /* For THM irqs */ 1357 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 1358 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 1359 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1360 smu->thermal_range.software_shutdown_temp); 1361 1362 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 1363 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 1364 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 1365 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 1366 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 1367 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 1368 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 1369 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1370 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 1371 1372 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 1373 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 1374 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 1375 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); 1376 1377 /* For MP1 SW irqs */ 1378 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT); 1379 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 1380 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 1381 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val); 1382 1383 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1384 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 1385 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); 1386 1387 break; 1388 default: 1389 break; 1390 } 1391 1392 return 0; 1393 } 1394 1395 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 1396 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 1397 1398 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 1399 1400 static int smu_v11_0_irq_process(struct amdgpu_device *adev, 1401 struct amdgpu_irq_src *source, 1402 struct amdgpu_iv_entry *entry) 1403 { 1404 struct smu_context *smu = adev->powerplay.pp_handle; 1405 uint32_t client_id = entry->client_id; 1406 uint32_t src_id = entry->src_id; 1407 /* 1408 * ctxid is used to distinguish different 1409 * events for SMCToHost interrupt. 1410 */ 1411 uint32_t ctxid = entry->src_data[0]; 1412 uint32_t data; 1413 1414 if (client_id == SOC15_IH_CLIENTID_THM) { 1415 switch (src_id) { 1416 case THM_11_0__SRCID__THM_DIG_THERM_L2H: 1417 schedule_delayed_work(&smu->swctf_delayed_work, 1418 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY)); 1419 break; 1420 case THM_11_0__SRCID__THM_DIG_THERM_H2L: 1421 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 1422 break; 1423 default: 1424 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 1425 src_id); 1426 break; 1427 } 1428 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { 1429 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); 1430 /* 1431 * HW CTF just occurred. Shutdown to prevent further damage. 1432 */ 1433 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); 1434 orderly_poweroff(true); 1435 } else if (client_id == SOC15_IH_CLIENTID_MP1) { 1436 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) { 1437 /* ACK SMUToHost interrupt */ 1438 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1439 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); 1440 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data); 1441 1442 switch (ctxid) { 1443 case SMU_IH_INTERRUPT_CONTEXT_ID_AC: 1444 dev_dbg(adev->dev, "Switched to AC mode!\n"); 1445 schedule_work(&smu->interrupt_work); 1446 adev->pm.ac_power = true; 1447 break; 1448 case SMU_IH_INTERRUPT_CONTEXT_ID_DC: 1449 dev_dbg(adev->dev, "Switched to DC mode!\n"); 1450 schedule_work(&smu->interrupt_work); 1451 adev->pm.ac_power = false; 1452 break; 1453 case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING: 1454 /* 1455 * Increment the throttle interrupt counter 1456 */ 1457 atomic64_inc(&smu->throttle_int_counter); 1458 1459 if (!atomic_read(&adev->throttling_logging_enabled)) 1460 return 0; 1461 1462 if (__ratelimit(&adev->throttling_logging_rs)) 1463 schedule_work(&smu->throttling_logging_work); 1464 1465 break; 1466 default: 1467 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n", 1468 ctxid, client_id); 1469 break; 1470 } 1471 } 1472 } 1473 1474 return 0; 1475 } 1476 1477 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs = 1478 { 1479 .set = smu_v11_0_set_irq_state, 1480 .process = smu_v11_0_irq_process, 1481 }; 1482 1483 int smu_v11_0_register_irq_handler(struct smu_context *smu) 1484 { 1485 struct amdgpu_device *adev = smu->adev; 1486 struct amdgpu_irq_src *irq_src = &smu->irq_source; 1487 int ret = 0; 1488 1489 irq_src->num_types = 1; 1490 irq_src->funcs = &smu_v11_0_irq_funcs; 1491 1492 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1493 THM_11_0__SRCID__THM_DIG_THERM_L2H, 1494 irq_src); 1495 if (ret) 1496 return ret; 1497 1498 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1499 THM_11_0__SRCID__THM_DIG_THERM_H2L, 1500 irq_src); 1501 if (ret) 1502 return ret; 1503 1504 /* Register CTF(GPIO_19) interrupt */ 1505 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, 1506 SMUIO_11_0__SRCID__SMUIO_GPIO19, 1507 irq_src); 1508 if (ret) 1509 return ret; 1510 1511 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 1512 SMU_IH_INTERRUPT_ID_TO_DRIVER, 1513 irq_src); 1514 if (ret) 1515 return ret; 1516 1517 return ret; 1518 } 1519 1520 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 1521 struct pp_smu_nv_clock_table *max_clocks) 1522 { 1523 struct smu_table_context *table_context = &smu->smu_table; 1524 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL; 1525 1526 if (!max_clocks || !table_context->max_sustainable_clocks) 1527 return -EINVAL; 1528 1529 sustainable_clocks = table_context->max_sustainable_clocks; 1530 1531 max_clocks->dcfClockInKhz = 1532 (unsigned int) sustainable_clocks->dcef_clock * 1000; 1533 max_clocks->displayClockInKhz = 1534 (unsigned int) sustainable_clocks->display_clock * 1000; 1535 max_clocks->phyClockInKhz = 1536 (unsigned int) sustainable_clocks->phy_clock * 1000; 1537 max_clocks->pixelClockInKhz = 1538 (unsigned int) sustainable_clocks->pixel_clock * 1000; 1539 max_clocks->uClockInKhz = 1540 (unsigned int) sustainable_clocks->uclock * 1000; 1541 max_clocks->socClockInKhz = 1542 (unsigned int) sustainable_clocks->soc_clock * 1000; 1543 max_clocks->dscClockInKhz = 0; 1544 max_clocks->dppClockInKhz = 0; 1545 max_clocks->fabricClockInKhz = 0; 1546 1547 return 0; 1548 } 1549 1550 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu) 1551 { 1552 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); 1553 } 1554 1555 int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, 1556 enum smu_baco_seq baco_seq) 1557 { 1558 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL); 1559 } 1560 1561 int smu_v11_0_get_bamaco_support(struct smu_context *smu) 1562 { 1563 struct smu_baco_context *smu_baco = &smu->smu_baco; 1564 int bamaco_support = 0; 1565 1566 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support) 1567 return 0; 1568 1569 if (smu_baco->maco_support) 1570 bamaco_support |= MACO_SUPPORT; 1571 1572 /* return true if ASIC is in BACO state already */ 1573 if (smu_v11_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER) 1574 return bamaco_support |= BACO_SUPPORT; 1575 1576 /* Arcturus does not support this bit mask */ 1577 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 1578 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 1579 return 0; 1580 1581 return (bamaco_support |= BACO_SUPPORT); 1582 } 1583 1584 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu) 1585 { 1586 struct smu_baco_context *smu_baco = &smu->smu_baco; 1587 1588 return smu_baco->state; 1589 } 1590 1591 #define D3HOT_BACO_SEQUENCE 0 1592 #define D3HOT_BAMACO_SEQUENCE 2 1593 1594 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) 1595 { 1596 struct smu_baco_context *smu_baco = &smu->smu_baco; 1597 struct amdgpu_device *adev = smu->adev; 1598 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1599 uint32_t data; 1600 int ret = 0; 1601 1602 if (smu_v11_0_baco_get_state(smu) == state) 1603 return 0; 1604 1605 if (state == SMU_BACO_STATE_ENTER) { 1606 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1607 case IP_VERSION(11, 0, 7): 1608 case IP_VERSION(11, 0, 11): 1609 case IP_VERSION(11, 0, 12): 1610 case IP_VERSION(11, 0, 13): 1611 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) 1612 ret = smu_cmn_send_smc_msg_with_param(smu, 1613 SMU_MSG_EnterBaco, 1614 D3HOT_BAMACO_SEQUENCE, 1615 NULL); 1616 else 1617 ret = smu_cmn_send_smc_msg_with_param(smu, 1618 SMU_MSG_EnterBaco, 1619 D3HOT_BACO_SEQUENCE, 1620 NULL); 1621 break; 1622 default: 1623 if (!ras || !adev->ras_enabled || 1624 (adev->init_lvl->level == 1625 AMDGPU_INIT_LEVEL_MINIMAL_XGMI)) { 1626 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == 1627 IP_VERSION(11, 0, 2)) { 1628 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT); 1629 data |= 0x80000000; 1630 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data); 1631 } else { 1632 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); 1633 data |= 0x80000000; 1634 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); 1635 } 1636 1637 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL); 1638 } else { 1639 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL); 1640 } 1641 break; 1642 } 1643 1644 } else { 1645 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL); 1646 if (ret) 1647 return ret; 1648 1649 /* clear vbios scratch 6 and 7 for coming asic reinit */ 1650 WREG32(adev->bios_scratch_reg_offset + 6, 0); 1651 WREG32(adev->bios_scratch_reg_offset + 7, 0); 1652 } 1653 1654 if (!ret) 1655 smu_baco->state = state; 1656 1657 return ret; 1658 } 1659 1660 int smu_v11_0_baco_enter(struct smu_context *smu) 1661 { 1662 int ret = 0; 1663 1664 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER); 1665 if (ret) 1666 return ret; 1667 1668 msleep(10); 1669 1670 return ret; 1671 } 1672 1673 int smu_v11_0_baco_exit(struct smu_context *smu) 1674 { 1675 int ret; 1676 1677 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT); 1678 if (!ret) { 1679 /* 1680 * Poll BACO exit status to ensure FW has completed 1681 * BACO exit process to avoid timing issues. 1682 */ 1683 smu_v11_0_poll_baco_exit(smu); 1684 } 1685 1686 return ret; 1687 } 1688 1689 int smu_v11_0_mode1_reset(struct smu_context *smu) 1690 { 1691 int ret = 0; 1692 1693 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1694 if (!ret) 1695 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS); 1696 1697 return ret; 1698 } 1699 1700 int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable) 1701 { 1702 int ret = 0; 1703 1704 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL); 1705 1706 return ret; 1707 } 1708 1709 1710 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1711 uint32_t *min, uint32_t *max) 1712 { 1713 int ret = 0, clk_id = 0; 1714 uint32_t param = 0; 1715 uint32_t clock_limit; 1716 1717 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 1718 switch (clk_type) { 1719 case SMU_MCLK: 1720 case SMU_UCLK: 1721 clock_limit = smu->smu_table.boot_values.uclk; 1722 break; 1723 case SMU_GFXCLK: 1724 case SMU_SCLK: 1725 clock_limit = smu->smu_table.boot_values.gfxclk; 1726 break; 1727 case SMU_SOCCLK: 1728 clock_limit = smu->smu_table.boot_values.socclk; 1729 break; 1730 default: 1731 clock_limit = 0; 1732 break; 1733 } 1734 1735 /* clock in Mhz unit */ 1736 if (min) 1737 *min = clock_limit / 100; 1738 if (max) 1739 *max = clock_limit / 100; 1740 1741 return 0; 1742 } 1743 1744 clk_id = smu_cmn_to_asic_specific_index(smu, 1745 CMN2ASIC_MAPPING_CLK, 1746 clk_type); 1747 if (clk_id < 0) { 1748 ret = -EINVAL; 1749 goto failed; 1750 } 1751 param = (clk_id & 0xffff) << 16; 1752 1753 if (max) { 1754 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max); 1755 if (ret) 1756 goto failed; 1757 } 1758 1759 if (min) { 1760 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 1761 if (ret) 1762 goto failed; 1763 } 1764 1765 failed: 1766 return ret; 1767 } 1768 1769 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, 1770 enum smu_clk_type clk_type, 1771 uint32_t min, 1772 uint32_t max, 1773 bool automatic) 1774 { 1775 int ret = 0, clk_id = 0; 1776 uint32_t param; 1777 1778 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1779 return 0; 1780 1781 clk_id = smu_cmn_to_asic_specific_index(smu, 1782 CMN2ASIC_MAPPING_CLK, 1783 clk_type); 1784 if (clk_id < 0) 1785 return clk_id; 1786 1787 if (max > 0) { 1788 if (automatic) 1789 param = (uint32_t)((clk_id << 16) | 0xffff); 1790 else 1791 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1792 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1793 param, NULL); 1794 if (ret) 1795 goto out; 1796 } 1797 1798 if (min > 0) { 1799 if (automatic) 1800 param = (uint32_t)((clk_id << 16) | 0); 1801 else 1802 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1803 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1804 param, NULL); 1805 if (ret) 1806 goto out; 1807 } 1808 1809 out: 1810 return ret; 1811 } 1812 1813 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu, 1814 enum smu_clk_type clk_type, 1815 uint32_t min, 1816 uint32_t max) 1817 { 1818 int ret = 0, clk_id = 0; 1819 uint32_t param; 1820 1821 if (min <= 0 && max <= 0) 1822 return -EINVAL; 1823 1824 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1825 return 0; 1826 1827 clk_id = smu_cmn_to_asic_specific_index(smu, 1828 CMN2ASIC_MAPPING_CLK, 1829 clk_type); 1830 if (clk_id < 0) 1831 return clk_id; 1832 1833 if (max > 0) { 1834 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1835 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1836 param, NULL); 1837 if (ret) 1838 return ret; 1839 } 1840 1841 if (min > 0) { 1842 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1843 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1844 param, NULL); 1845 if (ret) 1846 return ret; 1847 } 1848 1849 return ret; 1850 } 1851 1852 int smu_v11_0_set_performance_level(struct smu_context *smu, 1853 enum amd_dpm_forced_level level) 1854 { 1855 struct smu_11_0_dpm_context *dpm_context = 1856 smu->smu_dpm.dpm_context; 1857 struct smu_11_0_dpm_table *gfx_table = 1858 &dpm_context->dpm_tables.gfx_table; 1859 struct smu_11_0_dpm_table *mem_table = 1860 &dpm_context->dpm_tables.uclk_table; 1861 struct smu_11_0_dpm_table *soc_table = 1862 &dpm_context->dpm_tables.soc_table; 1863 struct smu_umd_pstate_table *pstate_table = 1864 &smu->pstate_table; 1865 struct amdgpu_device *adev = smu->adev; 1866 uint32_t sclk_min = 0, sclk_max = 0; 1867 uint32_t mclk_min = 0, mclk_max = 0; 1868 uint32_t socclk_min = 0, socclk_max = 0; 1869 int ret = 0; 1870 bool auto_level = false; 1871 1872 switch (level) { 1873 case AMD_DPM_FORCED_LEVEL_HIGH: 1874 sclk_min = sclk_max = gfx_table->max; 1875 mclk_min = mclk_max = mem_table->max; 1876 socclk_min = socclk_max = soc_table->max; 1877 break; 1878 case AMD_DPM_FORCED_LEVEL_LOW: 1879 sclk_min = sclk_max = gfx_table->min; 1880 mclk_min = mclk_max = mem_table->min; 1881 socclk_min = socclk_max = soc_table->min; 1882 break; 1883 case AMD_DPM_FORCED_LEVEL_AUTO: 1884 sclk_min = gfx_table->min; 1885 sclk_max = gfx_table->max; 1886 mclk_min = mem_table->min; 1887 mclk_max = mem_table->max; 1888 socclk_min = soc_table->min; 1889 socclk_max = soc_table->max; 1890 auto_level = true; 1891 break; 1892 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1893 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1894 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1895 socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1896 break; 1897 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1898 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1899 break; 1900 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1901 mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1902 break; 1903 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1904 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1905 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1906 socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1907 break; 1908 case AMD_DPM_FORCED_LEVEL_MANUAL: 1909 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1910 return 0; 1911 default: 1912 dev_err(adev->dev, "Invalid performance level %d\n", level); 1913 return -EINVAL; 1914 } 1915 1916 /* 1917 * Separate MCLK and SOCCLK soft min/max settings are not allowed 1918 * on Arcturus. 1919 */ 1920 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1921 mclk_min = mclk_max = 0; 1922 socclk_min = socclk_max = 0; 1923 auto_level = false; 1924 } 1925 1926 if (sclk_min && sclk_max) { 1927 ret = smu_v11_0_set_soft_freq_limited_range(smu, 1928 SMU_GFXCLK, 1929 sclk_min, 1930 sclk_max, 1931 auto_level); 1932 if (ret) 1933 return ret; 1934 } 1935 1936 if (mclk_min && mclk_max) { 1937 ret = smu_v11_0_set_soft_freq_limited_range(smu, 1938 SMU_MCLK, 1939 mclk_min, 1940 mclk_max, 1941 auto_level); 1942 if (ret) 1943 return ret; 1944 } 1945 1946 if (socclk_min && socclk_max) { 1947 ret = smu_v11_0_set_soft_freq_limited_range(smu, 1948 SMU_SOCCLK, 1949 socclk_min, 1950 socclk_max, 1951 auto_level); 1952 if (ret) 1953 return ret; 1954 } 1955 1956 return ret; 1957 } 1958 1959 int smu_v11_0_set_power_source(struct smu_context *smu, 1960 enum smu_power_src_type power_src) 1961 { 1962 int pwr_source; 1963 1964 pwr_source = smu_cmn_to_asic_specific_index(smu, 1965 CMN2ASIC_MAPPING_PWR, 1966 (uint32_t)power_src); 1967 if (pwr_source < 0) 1968 return -EINVAL; 1969 1970 return smu_cmn_send_smc_msg_with_param(smu, 1971 SMU_MSG_NotifyPowerSource, 1972 pwr_source, 1973 NULL); 1974 } 1975 1976 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu, 1977 enum smu_clk_type clk_type, 1978 uint16_t level, 1979 uint32_t *value) 1980 { 1981 int ret = 0, clk_id = 0; 1982 uint32_t param; 1983 1984 if (!value) 1985 return -EINVAL; 1986 1987 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1988 return 0; 1989 1990 clk_id = smu_cmn_to_asic_specific_index(smu, 1991 CMN2ASIC_MAPPING_CLK, 1992 clk_type); 1993 if (clk_id < 0) 1994 return clk_id; 1995 1996 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1997 1998 ret = smu_cmn_send_smc_msg_with_param(smu, 1999 SMU_MSG_GetDpmFreqByIndex, 2000 param, 2001 value); 2002 if (ret) 2003 return ret; 2004 2005 /* 2006 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM 2007 * now, we un-support it 2008 */ 2009 *value = *value & 0x7fffffff; 2010 2011 return ret; 2012 } 2013 2014 int smu_v11_0_get_dpm_level_count(struct smu_context *smu, 2015 enum smu_clk_type clk_type, 2016 uint32_t *value) 2017 { 2018 return smu_v11_0_get_dpm_freq_by_index(smu, 2019 clk_type, 2020 0xff, 2021 value); 2022 } 2023 2024 int smu_v11_0_set_single_dpm_table(struct smu_context *smu, 2025 enum smu_clk_type clk_type, 2026 struct smu_11_0_dpm_table *single_dpm_table) 2027 { 2028 int ret = 0; 2029 uint32_t clk; 2030 int i; 2031 2032 ret = smu_v11_0_get_dpm_level_count(smu, 2033 clk_type, 2034 &single_dpm_table->count); 2035 if (ret) { 2036 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 2037 return ret; 2038 } 2039 2040 for (i = 0; i < single_dpm_table->count; i++) { 2041 ret = smu_v11_0_get_dpm_freq_by_index(smu, 2042 clk_type, 2043 i, 2044 &clk); 2045 if (ret) { 2046 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 2047 return ret; 2048 } 2049 2050 single_dpm_table->dpm_levels[i].value = clk; 2051 single_dpm_table->dpm_levels[i].enabled = true; 2052 2053 if (i == 0) 2054 single_dpm_table->min = clk; 2055 else if (i == single_dpm_table->count - 1) 2056 single_dpm_table->max = clk; 2057 } 2058 2059 return 0; 2060 } 2061 2062 int smu_v11_0_get_dpm_level_range(struct smu_context *smu, 2063 enum smu_clk_type clk_type, 2064 uint32_t *min_value, 2065 uint32_t *max_value) 2066 { 2067 uint32_t level_count = 0; 2068 int ret = 0; 2069 2070 if (!min_value && !max_value) 2071 return -EINVAL; 2072 2073 if (min_value) { 2074 /* by default, level 0 clock value as min value */ 2075 ret = smu_v11_0_get_dpm_freq_by_index(smu, 2076 clk_type, 2077 0, 2078 min_value); 2079 if (ret) 2080 return ret; 2081 } 2082 2083 if (max_value) { 2084 ret = smu_v11_0_get_dpm_level_count(smu, 2085 clk_type, 2086 &level_count); 2087 if (ret) 2088 return ret; 2089 2090 ret = smu_v11_0_get_dpm_freq_by_index(smu, 2091 clk_type, 2092 level_count - 1, 2093 max_value); 2094 if (ret) 2095 return ret; 2096 } 2097 2098 return ret; 2099 } 2100 2101 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu) 2102 { 2103 struct amdgpu_device *adev = smu->adev; 2104 2105 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2106 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2107 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2108 } 2109 2110 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu) 2111 { 2112 uint32_t width_level; 2113 2114 width_level = smu_v11_0_get_current_pcie_link_width_level(smu); 2115 if (width_level > LINK_WIDTH_MAX) 2116 width_level = 0; 2117 2118 return link_width[width_level]; 2119 } 2120 2121 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu) 2122 { 2123 struct amdgpu_device *adev = smu->adev; 2124 2125 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2126 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2127 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2128 } 2129 2130 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu) 2131 { 2132 uint32_t speed_level; 2133 2134 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu); 2135 if (speed_level > LINK_SPEED_MAX) 2136 speed_level = 0; 2137 2138 return link_speed[speed_level]; 2139 } 2140 2141 int smu_v11_0_gfx_ulv_control(struct smu_context *smu, 2142 bool enablement) 2143 { 2144 int ret = 0; 2145 2146 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 2147 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 2148 2149 return ret; 2150 } 2151 2152 int smu_v11_0_deep_sleep_control(struct smu_context *smu, 2153 bool enablement) 2154 { 2155 struct amdgpu_device *adev = smu->adev; 2156 int ret = 0; 2157 2158 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 2159 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 2160 if (ret) { 2161 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 2162 return ret; 2163 } 2164 } 2165 2166 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 2167 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 2168 if (ret) { 2169 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 2170 return ret; 2171 } 2172 } 2173 2174 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 2175 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 2176 if (ret) { 2177 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 2178 return ret; 2179 } 2180 } 2181 2182 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 2183 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 2184 if (ret) { 2185 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 2186 return ret; 2187 } 2188 } 2189 2190 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 2191 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 2192 if (ret) { 2193 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 2194 return ret; 2195 } 2196 } 2197 2198 return ret; 2199 } 2200 2201 int smu_v11_0_restore_user_od_settings(struct smu_context *smu) 2202 { 2203 struct smu_table_context *table_context = &smu->smu_table; 2204 void *user_od_table = table_context->user_overdrive_table; 2205 int ret = 0; 2206 2207 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true); 2208 if (ret) 2209 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2210 2211 return ret; 2212 } 2213 2214 void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu) 2215 { 2216 struct amdgpu_device *adev = smu->adev; 2217 2218 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2219 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2220 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2221 } 2222