1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AArch64 code 4 * 5 * Copyright (C) 2018, Red Hat, Inc. 6 */ 7 8 #include <linux/compiler.h> 9 #include <assert.h> 10 11 #include "guest_modes.h" 12 #include "kvm_util.h" 13 #include "processor.h" 14 #include "ucall_common.h" 15 #include "vgic.h" 16 17 #include <linux/bitfield.h> 18 #include <linux/sizes.h> 19 20 #define DEFAULT_ARM64_GUEST_STACK_VADDR_MIN 0xac0000 21 22 static vm_vaddr_t exception_handlers; 23 24 static uint64_t pgd_index(struct kvm_vm *vm, vm_vaddr_t gva) 25 { 26 unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; 27 uint64_t mask = (1UL << (vm->va_bits - shift)) - 1; 28 29 return (gva >> shift) & mask; 30 } 31 32 static uint64_t pud_index(struct kvm_vm *vm, vm_vaddr_t gva) 33 { 34 unsigned int shift = 2 * (vm->page_shift - 3) + vm->page_shift; 35 uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; 36 37 TEST_ASSERT(vm->mmu.pgtable_levels == 4, 38 "Mode %d does not have 4 page table levels", vm->mode); 39 40 return (gva >> shift) & mask; 41 } 42 43 static uint64_t pmd_index(struct kvm_vm *vm, vm_vaddr_t gva) 44 { 45 unsigned int shift = (vm->page_shift - 3) + vm->page_shift; 46 uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; 47 48 TEST_ASSERT(vm->mmu.pgtable_levels >= 3, 49 "Mode %d does not have >= 3 page table levels", vm->mode); 50 51 return (gva >> shift) & mask; 52 } 53 54 static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva) 55 { 56 uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; 57 return (gva >> vm->page_shift) & mask; 58 } 59 60 static inline bool use_lpa2_pte_format(struct kvm_vm *vm) 61 { 62 return (vm->page_size == SZ_4K || vm->page_size == SZ_16K) && 63 (vm->pa_bits > 48 || vm->va_bits > 48); 64 } 65 66 static uint64_t addr_pte(struct kvm_vm *vm, uint64_t pa, uint64_t attrs) 67 { 68 uint64_t pte; 69 70 if (use_lpa2_pte_format(vm)) { 71 pte = pa & PTE_ADDR_MASK_LPA2(vm->page_shift); 72 pte |= FIELD_GET(GENMASK(51, 50), pa) << PTE_ADDR_51_50_LPA2_SHIFT; 73 attrs &= ~PTE_ADDR_51_50_LPA2; 74 } else { 75 pte = pa & PTE_ADDR_MASK(vm->page_shift); 76 if (vm->page_shift == 16) 77 pte |= FIELD_GET(GENMASK(51, 48), pa) << PTE_ADDR_51_48_SHIFT; 78 } 79 pte |= attrs; 80 81 return pte; 82 } 83 84 static uint64_t pte_addr(struct kvm_vm *vm, uint64_t pte) 85 { 86 uint64_t pa; 87 88 if (use_lpa2_pte_format(vm)) { 89 pa = pte & PTE_ADDR_MASK_LPA2(vm->page_shift); 90 pa |= FIELD_GET(PTE_ADDR_51_50_LPA2, pte) << 50; 91 } else { 92 pa = pte & PTE_ADDR_MASK(vm->page_shift); 93 if (vm->page_shift == 16) 94 pa |= FIELD_GET(PTE_ADDR_51_48, pte) << 48; 95 } 96 97 return pa; 98 } 99 100 static uint64_t ptrs_per_pgd(struct kvm_vm *vm) 101 { 102 unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; 103 return 1 << (vm->va_bits - shift); 104 } 105 106 static uint64_t __maybe_unused ptrs_per_pte(struct kvm_vm *vm) 107 { 108 return 1 << (vm->page_shift - 3); 109 } 110 111 void virt_arch_pgd_alloc(struct kvm_vm *vm) 112 { 113 size_t nr_pages = vm_page_align(vm, ptrs_per_pgd(vm) * 8) / vm->page_size; 114 115 if (vm->mmu.pgd_created) 116 return; 117 118 vm->mmu.pgd = vm_phy_pages_alloc(vm, nr_pages, 119 KVM_GUEST_PAGE_TABLE_MIN_PADDR, 120 vm->memslots[MEM_REGION_PT]); 121 vm->mmu.pgd_created = true; 122 } 123 124 static void _virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 125 uint64_t flags) 126 { 127 uint8_t attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT); 128 uint64_t pg_attr; 129 uint64_t *ptep; 130 131 TEST_ASSERT((vaddr % vm->page_size) == 0, 132 "Virtual address not on page boundary,\n" 133 " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size); 134 TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, 135 (vaddr >> vm->page_shift)), 136 "Invalid virtual address, vaddr: 0x%lx", vaddr); 137 TEST_ASSERT((paddr % vm->page_size) == 0, 138 "Physical address not on page boundary,\n" 139 " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size); 140 TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, 141 "Physical address beyond beyond maximum supported,\n" 142 " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 143 paddr, vm->max_gfn, vm->page_size); 144 145 ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, vaddr) * 8; 146 if (!*ptep) 147 *ptep = addr_pte(vm, vm_alloc_page_table(vm), 148 PGD_TYPE_TABLE | PTE_VALID); 149 150 switch (vm->mmu.pgtable_levels) { 151 case 4: 152 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, vaddr) * 8; 153 if (!*ptep) 154 *ptep = addr_pte(vm, vm_alloc_page_table(vm), 155 PUD_TYPE_TABLE | PTE_VALID); 156 /* fall through */ 157 case 3: 158 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, vaddr) * 8; 159 if (!*ptep) 160 *ptep = addr_pte(vm, vm_alloc_page_table(vm), 161 PMD_TYPE_TABLE | PTE_VALID); 162 /* fall through */ 163 case 2: 164 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, vaddr) * 8; 165 break; 166 default: 167 TEST_FAIL("Page table levels must be 2, 3, or 4"); 168 } 169 170 pg_attr = PTE_AF | PTE_ATTRINDX(attr_idx) | PTE_TYPE_PAGE | PTE_VALID; 171 if (!use_lpa2_pte_format(vm)) 172 pg_attr |= PTE_SHARED; 173 174 *ptep = addr_pte(vm, paddr, pg_attr); 175 } 176 177 void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) 178 { 179 uint64_t attr_idx = MT_NORMAL; 180 181 _virt_pg_map(vm, vaddr, paddr, attr_idx); 182 } 183 184 uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level) 185 { 186 uint64_t *ptep; 187 188 if (!vm->mmu.pgd_created) 189 goto unmapped_gva; 190 191 ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8; 192 if (!ptep) 193 goto unmapped_gva; 194 if (level == 0) 195 return ptep; 196 197 switch (vm->mmu.pgtable_levels) { 198 case 4: 199 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; 200 if (!ptep) 201 goto unmapped_gva; 202 if (level == 1) 203 break; 204 /* fall through */ 205 case 3: 206 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8; 207 if (!ptep) 208 goto unmapped_gva; 209 if (level == 2) 210 break; 211 /* fall through */ 212 case 2: 213 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8; 214 if (!ptep) 215 goto unmapped_gva; 216 break; 217 default: 218 TEST_FAIL("Page table levels must be 2, 3, or 4"); 219 } 220 221 return ptep; 222 223 unmapped_gva: 224 TEST_FAIL("No mapping for vm virtual address, gva: 0x%lx", gva); 225 exit(EXIT_FAILURE); 226 } 227 228 uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva) 229 { 230 return virt_get_pte_hva_at_level(vm, gva, 3); 231 } 232 233 vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) 234 { 235 uint64_t *ptep = virt_get_pte_hva(vm, gva); 236 237 return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1)); 238 } 239 240 static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level) 241 { 242 #ifdef DEBUG 243 static const char * const type[] = { "", "pud", "pmd", "pte" }; 244 uint64_t pte, *ptep; 245 246 if (level == 4) 247 return; 248 249 for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) { 250 ptep = addr_gpa2hva(vm, pte); 251 if (!*ptep) 252 continue; 253 fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "", type[level], pte, *ptep, ptep); 254 pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level + 1); 255 } 256 #endif 257 } 258 259 void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) 260 { 261 int level = 4 - (vm->mmu.pgtable_levels - 1); 262 uint64_t pgd, *ptep; 263 264 if (!vm->mmu.pgd_created) 265 return; 266 267 for (pgd = vm->mmu.pgd; pgd < vm->mmu.pgd + ptrs_per_pgd(vm) * 8; pgd += 8) { 268 ptep = addr_gpa2hva(vm, pgd); 269 if (!*ptep) 270 continue; 271 fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "", pgd, *ptep, ptep); 272 pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level); 273 } 274 } 275 276 bool vm_supports_el2(struct kvm_vm *vm) 277 { 278 const char *value = getenv("NV"); 279 280 if (value && *value == '0') 281 return false; 282 283 return vm_check_cap(vm, KVM_CAP_ARM_EL2) && vm->arch.has_gic; 284 } 285 286 void kvm_get_default_vcpu_target(struct kvm_vm *vm, struct kvm_vcpu_init *init) 287 { 288 struct kvm_vcpu_init preferred = {}; 289 290 vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &preferred); 291 if (vm_supports_el2(vm)) 292 preferred.features[0] |= BIT(KVM_ARM_VCPU_HAS_EL2); 293 294 *init = preferred; 295 } 296 297 void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init) 298 { 299 struct kvm_vcpu_init default_init = { .target = -1, }; 300 struct kvm_vm *vm = vcpu->vm; 301 uint64_t sctlr_el1, tcr_el1, ttbr0_el1; 302 303 if (!init) { 304 kvm_get_default_vcpu_target(vm, &default_init); 305 init = &default_init; 306 } 307 308 vcpu_ioctl(vcpu, KVM_ARM_VCPU_INIT, init); 309 vcpu->init = *init; 310 311 /* 312 * Enable FP/ASIMD to avoid trapping when accessing Q0-Q15 313 * registers, which the variable argument list macros do. 314 */ 315 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_CPACR_EL1), 3 << 20); 316 317 sctlr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1)); 318 tcr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1)); 319 320 /* Configure base granule size */ 321 switch (vm->mode) { 322 case VM_MODE_PXXVYY_4K: 323 TEST_FAIL("AArch64 does not support 4K sized pages " 324 "with ANY-bit physical address ranges"); 325 case VM_MODE_P52V48_64K: 326 case VM_MODE_P48V48_64K: 327 case VM_MODE_P40V48_64K: 328 case VM_MODE_P36V48_64K: 329 tcr_el1 |= TCR_TG0_64K; 330 break; 331 case VM_MODE_P52V48_16K: 332 case VM_MODE_P48V48_16K: 333 case VM_MODE_P40V48_16K: 334 case VM_MODE_P36V48_16K: 335 case VM_MODE_P36V47_16K: 336 tcr_el1 |= TCR_TG0_16K; 337 break; 338 case VM_MODE_P52V48_4K: 339 case VM_MODE_P48V48_4K: 340 case VM_MODE_P40V48_4K: 341 case VM_MODE_P36V48_4K: 342 tcr_el1 |= TCR_TG0_4K; 343 break; 344 default: 345 TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); 346 } 347 348 ttbr0_el1 = vm->mmu.pgd & GENMASK(47, vm->page_shift); 349 350 /* Configure output size */ 351 switch (vm->mode) { 352 case VM_MODE_P52V48_4K: 353 case VM_MODE_P52V48_16K: 354 case VM_MODE_P52V48_64K: 355 tcr_el1 |= TCR_IPS_52_BITS; 356 ttbr0_el1 |= FIELD_GET(GENMASK(51, 48), vm->mmu.pgd) << 2; 357 break; 358 case VM_MODE_P48V48_4K: 359 case VM_MODE_P48V48_16K: 360 case VM_MODE_P48V48_64K: 361 tcr_el1 |= TCR_IPS_48_BITS; 362 break; 363 case VM_MODE_P40V48_4K: 364 case VM_MODE_P40V48_16K: 365 case VM_MODE_P40V48_64K: 366 tcr_el1 |= TCR_IPS_40_BITS; 367 break; 368 case VM_MODE_P36V48_4K: 369 case VM_MODE_P36V48_16K: 370 case VM_MODE_P36V48_64K: 371 case VM_MODE_P36V47_16K: 372 tcr_el1 |= TCR_IPS_36_BITS; 373 break; 374 default: 375 TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); 376 } 377 378 sctlr_el1 |= SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_I; 379 380 tcr_el1 |= TCR_IRGN0_WBWA | TCR_ORGN0_WBWA | TCR_SH0_INNER; 381 tcr_el1 |= TCR_T0SZ(vm->va_bits); 382 tcr_el1 |= TCR_TBI1; 383 tcr_el1 |= TCR_EPD1_MASK; 384 if (use_lpa2_pte_format(vm)) 385 tcr_el1 |= TCR_DS; 386 387 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1), sctlr_el1); 388 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1), tcr_el1); 389 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_MAIR_EL1), DEFAULT_MAIR_EL1); 390 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TTBR0_EL1), ttbr0_el1); 391 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TPIDR_EL1), vcpu->id); 392 393 if (!vcpu_has_el2(vcpu)) 394 return; 395 396 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_HCR_EL2), 397 HCR_EL2_RW | HCR_EL2_TGE | HCR_EL2_E2H); 398 } 399 400 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) 401 { 402 uint64_t pstate, pc; 403 404 pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate)); 405 pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)); 406 407 fprintf(stream, "%*spstate: 0x%.16lx pc: 0x%.16lx\n", 408 indent, "", pstate, pc); 409 } 410 411 void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) 412 { 413 vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (uint64_t)guest_code); 414 } 415 416 static struct kvm_vcpu *__aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, 417 struct kvm_vcpu_init *init) 418 { 419 size_t stack_size; 420 uint64_t stack_vaddr; 421 struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id); 422 423 stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size : 424 vm->page_size; 425 stack_vaddr = __vm_vaddr_alloc(vm, stack_size, 426 DEFAULT_ARM64_GUEST_STACK_VADDR_MIN, 427 MEM_REGION_DATA); 428 429 aarch64_vcpu_setup(vcpu, init); 430 431 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), stack_vaddr + stack_size); 432 return vcpu; 433 } 434 435 struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, 436 struct kvm_vcpu_init *init, void *guest_code) 437 { 438 struct kvm_vcpu *vcpu = __aarch64_vcpu_add(vm, vcpu_id, init); 439 440 vcpu_arch_set_entry_point(vcpu, guest_code); 441 442 return vcpu; 443 } 444 445 struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) 446 { 447 return __aarch64_vcpu_add(vm, vcpu_id, NULL); 448 } 449 450 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) 451 { 452 va_list ap; 453 int i; 454 455 TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n" 456 " num: %u", num); 457 458 va_start(ap, num); 459 460 for (i = 0; i < num; i++) { 461 vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.regs[i]), 462 va_arg(ap, uint64_t)); 463 } 464 465 va_end(ap); 466 } 467 468 void kvm_exit_unexpected_exception(int vector, uint64_t ec, bool valid_ec) 469 { 470 ucall(UCALL_UNHANDLED, 3, vector, ec, valid_ec); 471 while (1) 472 ; 473 } 474 475 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu) 476 { 477 struct ucall uc; 478 479 if (get_ucall(vcpu, &uc) != UCALL_UNHANDLED) 480 return; 481 482 if (uc.args[2]) /* valid_ec */ { 483 assert(VECTOR_IS_SYNC(uc.args[0])); 484 TEST_FAIL("Unexpected exception (vector:0x%lx, ec:0x%lx)", 485 uc.args[0], uc.args[1]); 486 } else { 487 assert(!VECTOR_IS_SYNC(uc.args[0])); 488 TEST_FAIL("Unexpected exception (vector:0x%lx)", 489 uc.args[0]); 490 } 491 } 492 493 struct handlers { 494 handler_fn exception_handlers[VECTOR_NUM][ESR_ELx_EC_MAX + 1]; 495 }; 496 497 void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu) 498 { 499 extern char vectors; 500 501 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_VBAR_EL1), (uint64_t)&vectors); 502 } 503 504 void route_exception(struct ex_regs *regs, int vector) 505 { 506 struct handlers *handlers = (struct handlers *)exception_handlers; 507 bool valid_ec; 508 int ec = 0; 509 510 switch (vector) { 511 case VECTOR_SYNC_CURRENT: 512 case VECTOR_SYNC_LOWER_64: 513 ec = ESR_ELx_EC(read_sysreg(esr_el1)); 514 valid_ec = true; 515 break; 516 case VECTOR_IRQ_CURRENT: 517 case VECTOR_IRQ_LOWER_64: 518 case VECTOR_FIQ_CURRENT: 519 case VECTOR_FIQ_LOWER_64: 520 case VECTOR_ERROR_CURRENT: 521 case VECTOR_ERROR_LOWER_64: 522 ec = 0; 523 valid_ec = false; 524 break; 525 default: 526 valid_ec = false; 527 goto unexpected_exception; 528 } 529 530 if (handlers && handlers->exception_handlers[vector][ec]) 531 return handlers->exception_handlers[vector][ec](regs); 532 533 unexpected_exception: 534 kvm_exit_unexpected_exception(vector, ec, valid_ec); 535 } 536 537 void vm_init_descriptor_tables(struct kvm_vm *vm) 538 { 539 vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers), 540 vm->page_size, MEM_REGION_DATA); 541 542 *(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers; 543 } 544 545 void vm_install_sync_handler(struct kvm_vm *vm, int vector, int ec, 546 void (*handler)(struct ex_regs *)) 547 { 548 struct handlers *handlers = addr_gva2hva(vm, vm->handlers); 549 550 assert(VECTOR_IS_SYNC(vector)); 551 assert(vector < VECTOR_NUM); 552 assert(ec <= ESR_ELx_EC_MAX); 553 handlers->exception_handlers[vector][ec] = handler; 554 } 555 556 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 557 void (*handler)(struct ex_regs *)) 558 { 559 struct handlers *handlers = addr_gva2hva(vm, vm->handlers); 560 561 assert(!VECTOR_IS_SYNC(vector)); 562 assert(vector < VECTOR_NUM); 563 handlers->exception_handlers[vector][0] = handler; 564 } 565 566 uint32_t guest_get_vcpuid(void) 567 { 568 return read_sysreg(tpidr_el1); 569 } 570 571 static uint32_t max_ipa_for_page_size(uint32_t vm_ipa, uint32_t gran, 572 uint32_t not_sup_val, uint32_t ipa52_min_val) 573 { 574 if (gran == not_sup_val) 575 return 0; 576 else if (gran >= ipa52_min_val && vm_ipa >= 52) 577 return 52; 578 else 579 return min(vm_ipa, 48U); 580 } 581 582 void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k, 583 uint32_t *ipa16k, uint32_t *ipa64k) 584 { 585 struct kvm_vcpu_init preferred_init; 586 int kvm_fd, vm_fd, vcpu_fd, err; 587 uint64_t val; 588 uint32_t gran; 589 struct kvm_one_reg reg = { 590 .id = KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), 591 .addr = (uint64_t)&val, 592 }; 593 594 kvm_fd = open_kvm_dev_path_or_exit(); 595 vm_fd = __kvm_ioctl(kvm_fd, KVM_CREATE_VM, (void *)(unsigned long)ipa); 596 TEST_ASSERT(vm_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd)); 597 598 vcpu_fd = ioctl(vm_fd, KVM_CREATE_VCPU, 0); 599 TEST_ASSERT(vcpu_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd)); 600 601 err = ioctl(vm_fd, KVM_ARM_PREFERRED_TARGET, &preferred_init); 602 TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_ARM_PREFERRED_TARGET, err)); 603 err = ioctl(vcpu_fd, KVM_ARM_VCPU_INIT, &preferred_init); 604 TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_ARM_VCPU_INIT, err)); 605 606 err = ioctl(vcpu_fd, KVM_GET_ONE_REG, ®); 607 TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd)); 608 609 gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN4, val); 610 *ipa4k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN4_NI, 611 ID_AA64MMFR0_EL1_TGRAN4_52_BIT); 612 613 gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN64, val); 614 *ipa64k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN64_NI, 615 ID_AA64MMFR0_EL1_TGRAN64_IMP); 616 617 gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN16, val); 618 *ipa16k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN16_NI, 619 ID_AA64MMFR0_EL1_TGRAN16_52_BIT); 620 621 close(vcpu_fd); 622 close(vm_fd); 623 close(kvm_fd); 624 } 625 626 #define __smccc_call(insn, function_id, arg0, arg1, arg2, arg3, arg4, arg5, \ 627 arg6, res) \ 628 asm volatile("mov w0, %w[function_id]\n" \ 629 "mov x1, %[arg0]\n" \ 630 "mov x2, %[arg1]\n" \ 631 "mov x3, %[arg2]\n" \ 632 "mov x4, %[arg3]\n" \ 633 "mov x5, %[arg4]\n" \ 634 "mov x6, %[arg5]\n" \ 635 "mov x7, %[arg6]\n" \ 636 #insn "#0\n" \ 637 "mov %[res0], x0\n" \ 638 "mov %[res1], x1\n" \ 639 "mov %[res2], x2\n" \ 640 "mov %[res3], x3\n" \ 641 : [res0] "=r"(res->a0), [res1] "=r"(res->a1), \ 642 [res2] "=r"(res->a2), [res3] "=r"(res->a3) \ 643 : [function_id] "r"(function_id), [arg0] "r"(arg0), \ 644 [arg1] "r"(arg1), [arg2] "r"(arg2), [arg3] "r"(arg3), \ 645 [arg4] "r"(arg4), [arg5] "r"(arg5), [arg6] "r"(arg6) \ 646 : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7") 647 648 649 void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1, 650 uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, 651 uint64_t arg6, struct arm_smccc_res *res) 652 { 653 __smccc_call(hvc, function_id, arg0, arg1, arg2, arg3, arg4, arg5, 654 arg6, res); 655 } 656 657 void smccc_smc(uint32_t function_id, uint64_t arg0, uint64_t arg1, 658 uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, 659 uint64_t arg6, struct arm_smccc_res *res) 660 { 661 __smccc_call(smc, function_id, arg0, arg1, arg2, arg3, arg4, arg5, 662 arg6, res); 663 } 664 665 void kvm_selftest_arch_init(void) 666 { 667 /* 668 * arm64 doesn't have a true default mode, so start by computing the 669 * available IPA space and page sizes early. 670 */ 671 guest_modes_append_default(); 672 } 673 674 void vm_vaddr_populate_bitmap(struct kvm_vm *vm) 675 { 676 /* 677 * arm64 selftests use only TTBR0_EL1, meaning that the valid VA space 678 * is [0, 2^(64 - TCR_EL1.T0SZ)). 679 */ 680 sparsebit_set_num(vm->vpages_valid, 0, 681 (1ULL << vm->va_bits) >> vm->page_shift); 682 } 683 684 /* Helper to call wfi instruction. */ 685 void wfi(void) 686 { 687 asm volatile("wfi"); 688 } 689 690 static bool request_mte; 691 static bool request_vgic = true; 692 693 void test_wants_mte(void) 694 { 695 request_mte = true; 696 } 697 698 void test_disable_default_vgic(void) 699 { 700 request_vgic = false; 701 } 702 703 void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus) 704 { 705 if (request_mte && vm_check_cap(vm, KVM_CAP_ARM_MTE)) 706 vm_enable_cap(vm, KVM_CAP_ARM_MTE, 0); 707 708 if (request_vgic && kvm_supports_vgic_v3()) { 709 vm->arch.gic_fd = __vgic_v3_setup(vm, nr_vcpus, 64); 710 vm->arch.has_gic = true; 711 } 712 } 713 714 void kvm_arch_vm_finalize_vcpus(struct kvm_vm *vm) 715 { 716 if (vm->arch.has_gic) 717 __vgic_v3_init(vm->arch.gic_fd); 718 } 719 720 void kvm_arch_vm_release(struct kvm_vm *vm) 721 { 722 if (vm->arch.has_gic) 723 close(vm->arch.gic_fd); 724 } 725 726 bool kvm_arch_has_default_irqchip(void) 727 { 728 return request_vgic && kvm_supports_vgic_v3(); 729 } 730