1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/V2N CPG driver 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G056_SPI_CLK_SPI, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 CLK_PLLETH, 32 CLK_PLLGPU, 33 34 /* Internal Core Clocks */ 35 CLK_PLLCM33_DIV3, 36 CLK_PLLCM33_DIV4, 37 CLK_PLLCM33_DIV5, 38 CLK_PLLCM33_DIV16, 39 CLK_PLLCM33_GEAR, 40 CLK_SMUX2_XSPI_CLK0, 41 CLK_SMUX2_XSPI_CLK1, 42 CLK_PLLCM33_XSPI, 43 CLK_PLLCLN_DIV2, 44 CLK_PLLCLN_DIV8, 45 CLK_PLLCLN_DIV16, 46 CLK_PLLDTY_ACPU, 47 CLK_PLLDTY_ACPU_DIV2, 48 CLK_PLLDTY_ACPU_DIV4, 49 CLK_PLLDTY_DIV8, 50 CLK_PLLETH_DIV_250_FIX, 51 CLK_PLLETH_DIV_125_FIX, 52 CLK_CSDIV_PLLETH_GBE0, 53 CLK_CSDIV_PLLETH_GBE1, 54 CLK_SMUX2_GBE0_TXCLK, 55 CLK_SMUX2_GBE0_RXCLK, 56 CLK_SMUX2_GBE1_TXCLK, 57 CLK_SMUX2_GBE1_RXCLK, 58 CLK_PLLGPU_GEAR, 59 60 /* Module Clocks */ 61 MOD_CLK_BASE, 62 }; 63 64 static const struct clk_div_table dtable_1_8[] = { 65 {0, 1}, 66 {1, 2}, 67 {2, 4}, 68 {3, 8}, 69 {0, 0}, 70 }; 71 72 static const struct clk_div_table dtable_2_16[] = { 73 {0, 2}, 74 {1, 4}, 75 {2, 8}, 76 {3, 16}, 77 {0, 0}, 78 }; 79 80 static const struct clk_div_table dtable_2_64[] = { 81 {0, 2}, 82 {1, 4}, 83 {2, 8}, 84 {3, 16}, 85 {4, 64}, 86 {0, 0}, 87 }; 88 89 static const struct clk_div_table dtable_2_100[] = { 90 {0, 2}, 91 {1, 10}, 92 {2, 100}, 93 {0, 0}, 94 }; 95 96 /* Mux clock tables */ 97 static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" }; 98 static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" }; 99 static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" }; 100 static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" }; 101 static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" }; 102 static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" }; 103 104 static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 105 /* External Clock Inputs */ 106 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 107 DEF_INPUT("rtxin", CLK_RTXIN), 108 DEF_INPUT("qextal", CLK_QEXTAL), 109 110 /* PLL Clocks */ 111 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 112 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 113 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 114 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), 115 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), 116 DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), 117 118 /* Internal Core Clocks */ 119 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3), 120 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), 121 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), 122 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 123 DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), 124 DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0), 125 DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1), 126 DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3, 127 dtable_2_16), 128 129 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 130 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 131 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 132 133 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 134 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 135 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 136 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), 137 138 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), 139 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2), 140 DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, 141 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100), 142 DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, 143 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100), 144 DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk), 145 DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk), 146 DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk), 147 DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk), 148 149 DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64), 150 151 /* Core Clocks */ 152 DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 153 DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55, 154 CDDIV1_DIVCTL0, dtable_1_8), 155 DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55, 156 CDDIV1_DIVCTL1, dtable_1_8), 157 DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55, 158 CDDIV1_DIVCTL2, dtable_1_8), 159 DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55, 160 CDDIV1_DIVCTL3, dtable_1_8), 161 DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 162 DEF_FIXED("usb2_0_clk_core0", R9A09G056_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1), 163 DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G056_GBETH_0_CLK_PTP_REF_I, 164 CLK_PLLETH_DIV_125_FIX, 1, 1), 165 DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G056_GBETH_1_CLK_PTP_REF_I, 166 CLK_PLLETH_DIV_125_FIX, 1, 1), 167 DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G056_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2, 168 FIXED_MOD_CONF_XSPI), 169 }; 170 171 static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 172 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 173 BUS_MSTOP(3, BIT(5))), 174 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, 175 BUS_MSTOP(5, BIT(10))), 176 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, 177 BUS_MSTOP(5, BIT(11))), 178 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, 179 BUS_MSTOP(2, BIT(13))), 180 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, 181 BUS_MSTOP(2, BIT(14))), 182 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, 183 BUS_MSTOP(11, BIT(13))), 184 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, 185 BUS_MSTOP(11, BIT(14))), 186 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, 187 BUS_MSTOP(11, BIT(15))), 188 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, 189 BUS_MSTOP(12, BIT(0))), 190 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, 191 BUS_MSTOP(3, BIT(10))), 192 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, 193 BUS_MSTOP(3, BIT(10))), 194 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 195 BUS_MSTOP(1, BIT(0))), 196 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 197 BUS_MSTOP(1, BIT(0))), 198 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 199 BUS_MSTOP(5, BIT(12))), 200 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 201 BUS_MSTOP(5, BIT(12))), 202 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 203 BUS_MSTOP(5, BIT(13))), 204 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 205 BUS_MSTOP(5, BIT(13))), 206 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 207 BUS_MSTOP(3, BIT(14))), 208 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16, 209 BUS_MSTOP(10, BIT(15))), 210 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17, 211 BUS_MSTOP(10, BIT(15))), 212 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18, 213 BUS_MSTOP(10, BIT(15))), 214 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 215 BUS_MSTOP(3, BIT(13))), 216 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 217 BUS_MSTOP(1, BIT(1))), 218 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 219 BUS_MSTOP(1, BIT(2))), 220 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 221 BUS_MSTOP(1, BIT(3))), 222 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 223 BUS_MSTOP(1, BIT(4))), 224 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 225 BUS_MSTOP(1, BIT(5))), 226 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 227 BUS_MSTOP(1, BIT(6))), 228 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 229 BUS_MSTOP(1, BIT(7))), 230 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 231 BUS_MSTOP(1, BIT(8))), 232 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31, 233 BUS_MSTOP(4, BIT(5))), 234 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0, 235 BUS_MSTOP(4, BIT(5))), 236 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2, 237 BUS_MSTOP(4, BIT(5))), 238 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 239 BUS_MSTOP(8, BIT(2))), 240 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 241 BUS_MSTOP(8, BIT(2))), 242 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 243 BUS_MSTOP(8, BIT(2))), 244 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 245 BUS_MSTOP(8, BIT(2))), 246 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 247 BUS_MSTOP(8, BIT(3))), 248 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 249 BUS_MSTOP(8, BIT(3))), 250 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 251 BUS_MSTOP(8, BIT(3))), 252 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 253 BUS_MSTOP(8, BIT(3))), 254 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 255 BUS_MSTOP(8, BIT(4))), 256 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 257 BUS_MSTOP(8, BIT(4))), 258 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 259 BUS_MSTOP(8, BIT(4))), 260 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 261 BUS_MSTOP(8, BIT(4))), 262 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19, 263 BUS_MSTOP(7, BIT(7))), 264 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21, 265 BUS_MSTOP(7, BIT(9))), 266 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22, 267 BUS_MSTOP(7, BIT(10))), 268 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24, 269 BUS_MSTOP(8, BIT(5)), 1), 270 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25, 271 BUS_MSTOP(8, BIT(5)), 1), 272 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26, 273 BUS_MSTOP(8, BIT(5)), 1), 274 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27, 275 BUS_MSTOP(8, BIT(5)), 1), 276 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, 277 BUS_MSTOP(8, BIT(5))), 278 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, 279 BUS_MSTOP(8, BIT(5))), 280 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30, 281 BUS_MSTOP(8, BIT(6)), 1), 282 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31, 283 BUS_MSTOP(8, BIT(6)), 1), 284 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0, 285 BUS_MSTOP(8, BIT(6)), 1), 286 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1, 287 BUS_MSTOP(8, BIT(6)), 1), 288 DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, 289 BUS_MSTOP(8, BIT(6))), 290 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, 291 BUS_MSTOP(8, BIT(6))), 292 DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16, 293 BUS_MSTOP(3, BIT(4))), 294 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, 295 BUS_MSTOP(3, BIT(4))), 296 DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, 297 BUS_MSTOP(3, BIT(4))), 298 }; 299 300 static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 301 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 302 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 303 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 304 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ 305 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ 306 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ 307 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */ 308 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */ 309 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ 310 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 311 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 312 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */ 313 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 314 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 315 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 316 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 317 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */ 318 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */ 319 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 320 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 321 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 322 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 323 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 324 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 325 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 326 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 327 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 328 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */ 329 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */ 330 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 331 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 332 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 333 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */ 334 DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */ 335 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ 336 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ 337 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ 338 DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ 339 DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ 340 DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ 341 }; 342 343 const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = { 344 /* Core Clocks */ 345 .core_clks = r9a09g056_core_clks, 346 .num_core_clks = ARRAY_SIZE(r9a09g056_core_clks), 347 .last_dt_core_clk = LAST_DT_CORE_CLK, 348 .num_total_core_clks = MOD_CLK_BASE, 349 350 /* Module Clocks */ 351 .mod_clks = r9a09g056_mod_clks, 352 .num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks), 353 .num_hw_mod_clks = 25 * 16, 354 355 /* Resets */ 356 .resets = r9a09g056_resets, 357 .num_resets = ARRAY_SIZE(r9a09g056_resets), 358 359 .num_mstop_bits = 192, 360 }; 361