1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G3E CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 CLK_PLLVDO, 32 CLK_PLLETH, 33 34 /* Internal Core Clocks */ 35 CLK_PLLCM33_DIV3, 36 CLK_PLLCM33_DIV4, 37 CLK_PLLCM33_DIV5, 38 CLK_PLLCM33_DIV16, 39 CLK_PLLCM33_GEAR, 40 CLK_SMUX2_XSPI_CLK0, 41 CLK_SMUX2_XSPI_CLK1, 42 CLK_PLLCM33_XSPI, 43 CLK_PLLCLN_DIV2, 44 CLK_PLLCLN_DIV8, 45 CLK_PLLCLN_DIV16, 46 CLK_PLLCLN_DIV20, 47 CLK_PLLDTY_ACPU, 48 CLK_PLLDTY_ACPU_DIV2, 49 CLK_PLLDTY_ACPU_DIV4, 50 CLK_PLLDTY_DIV8, 51 CLK_PLLDTY_RCPU, 52 CLK_PLLDTY_RCPU_DIV4, 53 CLK_PLLETH_DIV_250_FIX, 54 CLK_PLLETH_DIV_125_FIX, 55 CLK_CSDIV_PLLETH_GBE0, 56 CLK_CSDIV_PLLETH_GBE1, 57 CLK_SMUX2_GBE0_TXCLK, 58 CLK_SMUX2_GBE0_RXCLK, 59 CLK_SMUX2_GBE1_TXCLK, 60 CLK_SMUX2_GBE1_RXCLK, 61 CLK_PLLDTY_DIV16, 62 CLK_PLLVDO_CRU0, 63 CLK_PLLVDO_GPU, 64 65 /* Module Clocks */ 66 MOD_CLK_BASE, 67 }; 68 69 static const struct clk_div_table dtable_1_8[] = { 70 {0, 1}, 71 {1, 2}, 72 {2, 4}, 73 {3, 8}, 74 {0, 0}, 75 }; 76 77 static const struct clk_div_table dtable_2_4[] = { 78 {0, 2}, 79 {1, 4}, 80 {0, 0}, 81 }; 82 83 static const struct clk_div_table dtable_2_16[] = { 84 {0, 2}, 85 {1, 4}, 86 {2, 8}, 87 {3, 16}, 88 {0, 0}, 89 }; 90 91 static const struct clk_div_table dtable_2_64[] = { 92 {0, 2}, 93 {1, 4}, 94 {2, 8}, 95 {3, 16}, 96 {4, 64}, 97 {0, 0}, 98 }; 99 100 static const struct clk_div_table dtable_2_100[] = { 101 {0, 2}, 102 {1, 10}, 103 {2, 100}, 104 {0, 0}, 105 }; 106 107 /* Mux clock tables */ 108 static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" }; 109 static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" }; 110 static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" }; 111 static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" }; 112 static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" }; 113 static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" }; 114 115 static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 116 /* External Clock Inputs */ 117 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 118 DEF_INPUT("rtxin", CLK_RTXIN), 119 DEF_INPUT("qextal", CLK_QEXTAL), 120 121 /* PLL Clocks */ 122 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 123 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 124 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 125 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), 126 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), 127 DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), 128 129 /* Internal Core Clocks */ 130 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3), 131 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), 132 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), 133 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 134 135 DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), 136 137 DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0), 138 DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1), 139 DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3, 140 dtable_2_16), 141 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 142 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 143 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 144 DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20), 145 146 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 147 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 148 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 149 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), 150 151 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), 152 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2), 153 DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX, 154 CSDIV0_DIVCTL0, dtable_2_100), 155 DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX, 156 CSDIV0_DIVCTL1, dtable_2_100), 157 DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk), 158 DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk), 159 DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk), 160 DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk), 161 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), 162 DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64), 163 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4), 164 165 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), 166 DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64), 167 168 /* Core Clocks */ 169 DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 170 DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55, 171 CDDIV1_DIVCTL0, dtable_1_8), 172 DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55, 173 CDDIV1_DIVCTL1, dtable_1_8), 174 DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55, 175 CDDIV1_DIVCTL2, dtable_1_8), 176 DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55, 177 CDDIV1_DIVCTL3, dtable_1_8), 178 DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 179 DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2), 180 DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I, 181 CLK_PLLETH_DIV_125_FIX, 1, 1), 182 DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I, 183 CLK_PLLETH_DIV_125_FIX, 1, 1), 184 DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1), 185 DEF_FIXED("usb3_0_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1), 186 }; 187 188 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 189 DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0, 190 BUS_MSTOP(5, BIT(9))), 191 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1, 192 BUS_MSTOP(3, BIT(2))), 193 DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2, 194 BUS_MSTOP(3, BIT(3))), 195 DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3, 196 BUS_MSTOP(10, BIT(11))), 197 DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4, 198 BUS_MSTOP(10, BIT(12))), 199 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 200 BUS_MSTOP_NONE), 201 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 202 BUS_MSTOP(3, BIT(5))), 203 DEF_MOD("gpt_0_pclk_sfr", CLK_PLLCLN_DIV8, 3, 1, 1, 17, 204 BUS_MSTOP(6, BIT(11))), 205 DEF_MOD("gpt_1_pclk_sfr", CLK_PLLCLN_DIV8, 3, 2, 1, 18, 206 BUS_MSTOP(6, BIT(12))), 207 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 208 BUS_MSTOP(1, BIT(0))), 209 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 210 BUS_MSTOP(1, BIT(0))), 211 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 212 BUS_MSTOP(5, BIT(12))), 213 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 214 BUS_MSTOP(5, BIT(12))), 215 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 216 BUS_MSTOP(5, BIT(13))), 217 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 218 BUS_MSTOP(5, BIT(13))), 219 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 220 BUS_MSTOP(3, BIT(14))), 221 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16, 222 BUS_MSTOP(10, BIT(15))), 223 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17, 224 BUS_MSTOP(10, BIT(15))), 225 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18, 226 BUS_MSTOP(10, BIT(15))), 227 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 228 BUS_MSTOP(3, BIT(13))), 229 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 230 BUS_MSTOP(1, BIT(1))), 231 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 232 BUS_MSTOP(1, BIT(2))), 233 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 234 BUS_MSTOP(1, BIT(3))), 235 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 236 BUS_MSTOP(1, BIT(4))), 237 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 238 BUS_MSTOP(1, BIT(5))), 239 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 240 BUS_MSTOP(1, BIT(6))), 241 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 242 BUS_MSTOP(1, BIT(7))), 243 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 244 BUS_MSTOP(1, BIT(8))), 245 DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28, 246 BUS_MSTOP(10, BIT(14))), 247 DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29, 248 BUS_MSTOP(10, BIT(14))), 249 DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30, 250 BUS_MSTOP(10, BIT(14))), 251 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31, 252 BUS_MSTOP(4, BIT(5))), 253 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0, 254 BUS_MSTOP(4, BIT(5))), 255 DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2, 256 BUS_MSTOP(4, BIT(5))), 257 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 258 BUS_MSTOP(8, BIT(2))), 259 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 260 BUS_MSTOP(8, BIT(2))), 261 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 262 BUS_MSTOP(8, BIT(2))), 263 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 264 BUS_MSTOP(8, BIT(2))), 265 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 266 BUS_MSTOP(8, BIT(3))), 267 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 268 BUS_MSTOP(8, BIT(3))), 269 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 270 BUS_MSTOP(8, BIT(3))), 271 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 272 BUS_MSTOP(8, BIT(3))), 273 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 274 BUS_MSTOP(8, BIT(4))), 275 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 276 BUS_MSTOP(8, BIT(4))), 277 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 278 BUS_MSTOP(8, BIT(4))), 279 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 280 BUS_MSTOP(8, BIT(4))), 281 DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15, 282 BUS_MSTOP(7, BIT(12))), 283 DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16, 284 BUS_MSTOP(7, BIT(14))), 285 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24, 286 BUS_MSTOP(8, BIT(5)), 1), 287 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25, 288 BUS_MSTOP(8, BIT(5)), 1), 289 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26, 290 BUS_MSTOP(8, BIT(5)), 1), 291 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27, 292 BUS_MSTOP(8, BIT(5)), 1), 293 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, 294 BUS_MSTOP(8, BIT(5))), 295 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, 296 BUS_MSTOP(8, BIT(5))), 297 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30, 298 BUS_MSTOP(8, BIT(6)), 1), 299 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31, 300 BUS_MSTOP(8, BIT(6)), 1), 301 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0, 302 BUS_MSTOP(8, BIT(6)), 1), 303 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1, 304 BUS_MSTOP(8, BIT(6)), 1), 305 DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, 306 BUS_MSTOP(8, BIT(6))), 307 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, 308 BUS_MSTOP(8, BIT(6))), 309 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 310 BUS_MSTOP(9, BIT(4))), 311 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 312 BUS_MSTOP(9, BIT(4))), 313 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 314 BUS_MSTOP(9, BIT(4))), 315 DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16, 316 BUS_MSTOP(3, BIT(4))), 317 DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, 318 BUS_MSTOP(3, BIT(4))), 319 DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, 320 BUS_MSTOP(3, BIT(4))), 321 DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, 322 BUS_MSTOP(2, BIT(15))), 323 }; 324 325 static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 326 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 327 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */ 328 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */ 329 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */ 330 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */ 331 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */ 332 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 333 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 334 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 335 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */ 336 DEF_RST(5, 10, 2, 11), /* GPT_0_RST_S_REG */ 337 DEF_RST(5, 11, 2, 12), /* GPT_1_RST_P_REG */ 338 DEF_RST(5, 12, 2, 13), /* GPT_1_RST_S_REG */ 339 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 340 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 341 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 342 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 343 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */ 344 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */ 345 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 346 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 347 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 348 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 349 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 350 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 351 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 352 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 353 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 354 DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */ 355 DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */ 356 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */ 357 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */ 358 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 359 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 360 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 361 DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */ 362 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ 363 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ 364 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ 365 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ 366 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ 367 DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */ 368 DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */ 369 DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */ 370 DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ 371 }; 372 373 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { 374 /* Core Clocks */ 375 .core_clks = r9a09g047_core_clks, 376 .num_core_clks = ARRAY_SIZE(r9a09g047_core_clks), 377 .last_dt_core_clk = LAST_DT_CORE_CLK, 378 .num_total_core_clks = MOD_CLK_BASE, 379 380 /* Module Clocks */ 381 .mod_clks = r9a09g047_mod_clks, 382 .num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks), 383 .num_hw_mod_clks = 28 * 16, 384 385 /* Resets */ 386 .resets = r9a09g047_resets, 387 .num_resets = ARRAY_SIZE(r9a09g047_resets), 388 389 .num_mstop_bits = 208, 390 }; 391