1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
4 *
5 * Authors: Shlomi Gridish <gridish@freescale.com>
6 * Li Yang <leoli@freescale.com>
7 * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
8 *
9 * Description:
10 * General Purpose functions for the global management of the
11 * QUICC Engine (QE).
12 */
13 #include <linux/bitmap.h>
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
17 #include <linux/param.h>
18 #include <linux/string.h>
19 #include <linux/spinlock.h>
20 #include <linux/mm.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/iopoll.h>
26 #include <linux/crc32.h>
27 #include <linux/of.h>
28 #include <linux/platform_device.h>
29 #include <soc/fsl/qe/immap_qe.h>
30 #include <soc/fsl/qe/qe.h>
31
32 static void qe_snums_init(void);
33 static int qe_sdma_init(void);
34
35 static DEFINE_SPINLOCK(qe_lock);
36 DEFINE_SPINLOCK(cmxgcr_lock);
37 EXPORT_SYMBOL(cmxgcr_lock);
38
39 /* We allocate this here because it is used almost exclusively for
40 * the communication processor devices.
41 */
42 struct qe_immap __iomem *qe_immr;
43 EXPORT_SYMBOL(qe_immr);
44
45 static u8 snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
46 static DECLARE_BITMAP(snum_state, QE_NUM_OF_SNUM);
47 static unsigned int qe_num_of_snum;
48
49 static phys_addr_t qebase = -1;
50
qe_get_device_node(void)51 static struct device_node *qe_get_device_node(void)
52 {
53 struct device_node *qe;
54
55 /*
56 * Newer device trees have an "fsl,qe" compatible property for the QE
57 * node, but we still need to support older device trees.
58 */
59 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
60 if (qe)
61 return qe;
62 return of_find_node_by_type(NULL, "qe");
63 }
64
get_qe_base(void)65 static phys_addr_t get_qe_base(void)
66 {
67 struct device_node *qe;
68 int ret;
69 struct resource res;
70
71 if (qebase != -1)
72 return qebase;
73
74 qe = qe_get_device_node();
75 if (!qe)
76 return qebase;
77
78 ret = of_address_to_resource(qe, 0, &res);
79 if (!ret)
80 qebase = res.start;
81 of_node_put(qe);
82
83 return qebase;
84 }
85
qe_reset(void)86 void qe_reset(void)
87 {
88 if (qe_immr == NULL)
89 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
90
91 if (!qe_immr)
92 panic("QE:ioremap failed!");
93
94 qe_snums_init();
95
96 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
97 QE_CR_PROTOCOL_UNSPECIFIED, 0);
98
99 /* Reclaim the MURAM memory for our use. */
100 qe_muram_init();
101
102 if (qe_sdma_init())
103 panic("sdma init failed!");
104 }
105
qe_issue_cmd(u32 cmd,u32 device,u8 mcn_protocol,u32 cmd_input)106 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
107 {
108 unsigned long flags;
109 u8 mcn_shift = 0, dev_shift = 0;
110 u32 val;
111 int ret;
112
113 spin_lock_irqsave(&qe_lock, flags);
114 if (cmd == QE_RESET) {
115 iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
116 } else {
117 if (cmd == QE_ASSIGN_PAGE) {
118 /* Here device is the SNUM, not sub-block */
119 dev_shift = QE_CR_SNUM_SHIFT;
120 } else if (cmd == QE_ASSIGN_RISC) {
121 /* Here device is the SNUM, and mcnProtocol is
122 * e_QeCmdRiscAssignment value */
123 dev_shift = QE_CR_SNUM_SHIFT;
124 mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
125 } else {
126 if (device == QE_CR_SUBBLOCK_USB)
127 mcn_shift = QE_CR_MCN_USB_SHIFT;
128 else
129 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
130 }
131
132 iowrite32be(cmd_input, &qe_immr->cp.cecdr);
133 iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
134 &qe_immr->cp.cecr);
135 }
136
137 /* wait for the QE_CR_FLG to clear */
138 ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val,
139 (val & QE_CR_FLG) == 0, 0, 100);
140 /* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
141 spin_unlock_irqrestore(&qe_lock, flags);
142
143 return ret == 0;
144 }
145 EXPORT_SYMBOL(qe_issue_cmd);
146
147 /* Set a baud rate generator. This needs lots of work. There are
148 * 16 BRGs, which can be connected to the QE channels or output
149 * as clocks. The BRGs are in two different block of internal
150 * memory mapped space.
151 * The BRG clock is the QE clock divided by 2.
152 * It was set up long ago during the initial boot phase and is
153 * given to us.
154 * Baud rate clocks are zero-based in the driver code (as that maps
155 * to port numbers). Documentation uses 1-based numbering.
156 */
157 static unsigned int brg_clk = 0;
158
159 #define CLK_GRAN (1000)
160 #define CLK_GRAN_LIMIT (5)
161
qe_get_brg_clk(void)162 unsigned int qe_get_brg_clk(void)
163 {
164 struct device_node *qe;
165 u32 brg;
166 unsigned int mod;
167
168 if (brg_clk)
169 return brg_clk;
170
171 qe = qe_get_device_node();
172 if (!qe)
173 return brg_clk;
174
175 if (!of_property_read_u32(qe, "brg-frequency", &brg))
176 brg_clk = brg;
177
178 of_node_put(qe);
179
180 /* round this if near to a multiple of CLK_GRAN */
181 mod = brg_clk % CLK_GRAN;
182 if (mod) {
183 if (mod < CLK_GRAN_LIMIT)
184 brg_clk -= mod;
185 else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
186 brg_clk += CLK_GRAN - mod;
187 }
188
189 return brg_clk;
190 }
191 EXPORT_SYMBOL(qe_get_brg_clk);
192
193 #define PVR_VER_836x 0x8083
194 #define PVR_VER_832x 0x8084
195
qe_general4_errata(void)196 static bool qe_general4_errata(void)
197 {
198 #ifdef CONFIG_PPC32
199 return pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x);
200 #endif
201 return false;
202 }
203
204 /* Program the BRG to the given sampling rate and multiplier
205 *
206 * @brg: the BRG, QE_BRG1 - QE_BRG16
207 * @rate: the desired sampling rate
208 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
209 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
210 * then 'multiplier' should be 8.
211 */
qe_setbrg(enum qe_clock brg,unsigned int rate,unsigned int multiplier)212 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
213 {
214 u32 divisor, tempval;
215 u32 div16 = 0;
216
217 if ((brg < QE_BRG1) || (brg > QE_BRG16))
218 return -EINVAL;
219
220 divisor = qe_get_brg_clk() / (rate * multiplier);
221
222 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
223 div16 = QE_BRGC_DIV16;
224 divisor /= 16;
225 }
226
227 /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
228 that the BRG divisor must be even if you're not using divide-by-16
229 mode. */
230 if (qe_general4_errata())
231 if (!div16 && (divisor & 1) && (divisor > 3))
232 divisor++;
233
234 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
235 QE_BRGC_ENABLE | div16;
236
237 iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
238
239 return 0;
240 }
241 EXPORT_SYMBOL(qe_setbrg);
242
243 /* Convert a string to a QE clock source enum
244 *
245 * This function takes a string, typically from a property in the device
246 * tree, and returns the corresponding "enum qe_clock" value.
247 */
qe_clock_source(const char * source)248 enum qe_clock qe_clock_source(const char *source)
249 {
250 unsigned int i;
251
252 if (strcasecmp(source, "none") == 0)
253 return QE_CLK_NONE;
254
255 if (strcmp(source, "tsync_pin") == 0)
256 return QE_TSYNC_PIN;
257
258 if (strcmp(source, "rsync_pin") == 0)
259 return QE_RSYNC_PIN;
260
261 if (strncasecmp(source, "brg", 3) == 0) {
262 i = simple_strtoul(source + 3, NULL, 10);
263 if ((i >= 1) && (i <= 16))
264 return (QE_BRG1 - 1) + i;
265 else
266 return QE_CLK_DUMMY;
267 }
268
269 if (strncasecmp(source, "clk", 3) == 0) {
270 i = simple_strtoul(source + 3, NULL, 10);
271 if ((i >= 1) && (i <= 24))
272 return (QE_CLK1 - 1) + i;
273 else
274 return QE_CLK_DUMMY;
275 }
276
277 return QE_CLK_DUMMY;
278 }
279 EXPORT_SYMBOL(qe_clock_source);
280
281 /* Initialize SNUMs (thread serial numbers) according to
282 * QE Module Control chapter, SNUM table
283 */
qe_snums_init(void)284 static void qe_snums_init(void)
285 {
286 static const u8 snum_init_76[] = {
287 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
288 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
289 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
290 0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
291 0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
292 0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
293 0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
294 0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
295 0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
296 0xF4, 0xF5, 0xFC, 0xFD,
297 };
298 static const u8 snum_init_46[] = {
299 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
300 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
301 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
302 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
303 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
304 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
305 };
306 struct device_node *qe;
307 const u8 *snum_init;
308 int i;
309
310 bitmap_zero(snum_state, QE_NUM_OF_SNUM);
311 qe_num_of_snum = 28; /* The default number of snum for threads is 28 */
312 qe = qe_get_device_node();
313 if (qe) {
314 i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
315 snums, 1, QE_NUM_OF_SNUM);
316 if (i > 0) {
317 of_node_put(qe);
318 qe_num_of_snum = i;
319 return;
320 }
321 /*
322 * Fall back to legacy binding of using the value of
323 * fsl,qe-num-snums to choose one of the static arrays
324 * above.
325 */
326 of_property_read_u32(qe, "fsl,qe-num-snums", &qe_num_of_snum);
327 of_node_put(qe);
328 }
329
330 if (qe_num_of_snum == 76) {
331 snum_init = snum_init_76;
332 } else if (qe_num_of_snum == 28 || qe_num_of_snum == 46) {
333 snum_init = snum_init_46;
334 } else {
335 pr_err("QE: unsupported value of fsl,qe-num-snums: %u\n", qe_num_of_snum);
336 return;
337 }
338 memcpy(snums, snum_init, qe_num_of_snum);
339 }
340
qe_get_snum(void)341 int qe_get_snum(void)
342 {
343 unsigned long flags;
344 int snum = -EBUSY;
345 int i;
346
347 spin_lock_irqsave(&qe_lock, flags);
348 i = find_first_zero_bit(snum_state, qe_num_of_snum);
349 if (i < qe_num_of_snum) {
350 set_bit(i, snum_state);
351 snum = snums[i];
352 }
353 spin_unlock_irqrestore(&qe_lock, flags);
354
355 return snum;
356 }
357 EXPORT_SYMBOL(qe_get_snum);
358
qe_put_snum(u8 snum)359 void qe_put_snum(u8 snum)
360 {
361 const u8 *p = memchr(snums, snum, qe_num_of_snum);
362
363 if (p)
364 clear_bit(p - snums, snum_state);
365 }
366 EXPORT_SYMBOL(qe_put_snum);
367
qe_sdma_init(void)368 static int qe_sdma_init(void)
369 {
370 struct sdma __iomem *sdma = &qe_immr->sdma;
371 static s32 sdma_buf_offset = -ENOMEM;
372
373 /* allocate 2 internal temporary buffers (512 bytes size each) for
374 * the SDMA */
375 if (sdma_buf_offset < 0) {
376 sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
377 if (sdma_buf_offset < 0)
378 return -ENOMEM;
379 }
380
381 iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK,
382 &sdma->sdebcr);
383 iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
384 &sdma->sdmr);
385
386 return 0;
387 }
388
389 /* The maximum number of RISCs we support */
390 #define MAX_QE_RISC 4
391
392 /* Firmware information stored here for qe_get_firmware_info() */
393 static struct qe_firmware_info qe_firmware_info;
394
395 /*
396 * Set to 1 if QE firmware has been uploaded, and therefore
397 * qe_firmware_info contains valid data.
398 */
399 static int qe_firmware_uploaded;
400
401 /*
402 * Upload a QE microcode
403 *
404 * This function is a worker function for qe_upload_firmware(). It does
405 * the actual uploading of the microcode.
406 */
qe_upload_microcode(const void * base,const struct qe_microcode * ucode)407 static void qe_upload_microcode(const void *base,
408 const struct qe_microcode *ucode)
409 {
410 const __be32 *code = base + be32_to_cpu(ucode->code_offset);
411 unsigned int i;
412
413 if (ucode->major || ucode->minor || ucode->revision)
414 printk(KERN_INFO "qe-firmware: "
415 "uploading microcode '%s' version %u.%u.%u\n",
416 ucode->id, ucode->major, ucode->minor, ucode->revision);
417 else
418 printk(KERN_INFO "qe-firmware: "
419 "uploading microcode '%s'\n", ucode->id);
420
421 /* Use auto-increment */
422 iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
423 &qe_immr->iram.iadd);
424
425 for (i = 0; i < be32_to_cpu(ucode->count); i++)
426 iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
427
428 /* Set I-RAM Ready Register */
429 iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
430 }
431
432 /*
433 * Upload a microcode to the I-RAM at a specific address.
434 *
435 * See Documentation/arch/powerpc/qe_firmware.rst for information on QE microcode
436 * uploading.
437 *
438 * Currently, only version 1 is supported, so the 'version' field must be
439 * set to 1.
440 *
441 * The SOC model and revision are not validated, they are only displayed for
442 * informational purposes.
443 *
444 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
445 * all of the microcode structures, minus the CRC.
446 *
447 * 'length' is the size that the structure says it is, including the CRC.
448 */
qe_upload_firmware(const struct qe_firmware * firmware)449 int qe_upload_firmware(const struct qe_firmware *firmware)
450 {
451 unsigned int i;
452 unsigned int j;
453 u32 crc;
454 size_t calc_size;
455 size_t length;
456 const struct qe_header *hdr;
457
458 if (!firmware) {
459 printk(KERN_ERR "qe-firmware: invalid pointer\n");
460 return -EINVAL;
461 }
462
463 hdr = &firmware->header;
464 length = be32_to_cpu(hdr->length);
465
466 /* Check the magic */
467 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
468 (hdr->magic[2] != 'F')) {
469 printk(KERN_ERR "qe-firmware: not a microcode\n");
470 return -EPERM;
471 }
472
473 /* Check the version */
474 if (hdr->version != 1) {
475 printk(KERN_ERR "qe-firmware: unsupported version\n");
476 return -EPERM;
477 }
478
479 /* Validate some of the fields */
480 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
481 printk(KERN_ERR "qe-firmware: invalid data\n");
482 return -EINVAL;
483 }
484
485 /* Validate the length and check if there's a CRC */
486 calc_size = struct_size(firmware, microcode, firmware->count);
487
488 for (i = 0; i < firmware->count; i++)
489 /*
490 * For situations where the second RISC uses the same microcode
491 * as the first, the 'code_offset' and 'count' fields will be
492 * zero, so it's okay to add those.
493 */
494 calc_size += sizeof(__be32) *
495 be32_to_cpu(firmware->microcode[i].count);
496
497 /* Validate the length */
498 if (length != calc_size + sizeof(__be32)) {
499 printk(KERN_ERR "qe-firmware: invalid length\n");
500 return -EPERM;
501 }
502
503 /* Validate the CRC */
504 crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
505 if (crc != crc32(0, firmware, calc_size)) {
506 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
507 return -EIO;
508 }
509
510 /*
511 * If the microcode calls for it, split the I-RAM.
512 */
513 if (!firmware->split)
514 qe_setbits_be16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
515
516 if (firmware->soc.model)
517 printk(KERN_INFO
518 "qe-firmware: firmware '%s' for %u V%u.%u\n",
519 firmware->id, be16_to_cpu(firmware->soc.model),
520 firmware->soc.major, firmware->soc.minor);
521 else
522 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
523 firmware->id);
524
525 /*
526 * The QE only supports one microcode per RISC, so clear out all the
527 * saved microcode information and put in the new.
528 */
529 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
530 strscpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
531 qe_firmware_info.extended_modes = be64_to_cpu(firmware->extended_modes);
532 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
533 sizeof(firmware->vtraps));
534
535 /* Loop through each microcode. */
536 for (i = 0; i < firmware->count; i++) {
537 const struct qe_microcode *ucode = &firmware->microcode[i];
538
539 /* Upload a microcode if it's present */
540 if (ucode->code_offset)
541 qe_upload_microcode(firmware, ucode);
542
543 /* Program the traps for this processor */
544 for (j = 0; j < 16; j++) {
545 u32 trap = be32_to_cpu(ucode->traps[j]);
546
547 if (trap)
548 iowrite32be(trap,
549 &qe_immr->rsp[i].tibcr[j]);
550 }
551
552 /* Enable traps */
553 iowrite32be(be32_to_cpu(ucode->eccr),
554 &qe_immr->rsp[i].eccr);
555 }
556
557 qe_firmware_uploaded = 1;
558
559 return 0;
560 }
561 EXPORT_SYMBOL(qe_upload_firmware);
562
563 /*
564 * Get info on the currently-loaded firmware
565 *
566 * This function also checks the device tree to see if the boot loader has
567 * uploaded a firmware already.
568 */
qe_get_firmware_info(void)569 struct qe_firmware_info *qe_get_firmware_info(void)
570 {
571 static int initialized;
572 struct device_node *qe;
573 struct device_node *fw = NULL;
574 const char *sprop;
575
576 /*
577 * If we haven't checked yet, and a driver hasn't uploaded a firmware
578 * yet, then check the device tree for information.
579 */
580 if (qe_firmware_uploaded)
581 return &qe_firmware_info;
582
583 if (initialized)
584 return NULL;
585
586 initialized = 1;
587
588 qe = qe_get_device_node();
589 if (!qe)
590 return NULL;
591
592 /* Find the 'firmware' child node */
593 fw = of_get_child_by_name(qe, "firmware");
594 of_node_put(qe);
595
596 /* Did we find the 'firmware' node? */
597 if (!fw)
598 return NULL;
599
600 qe_firmware_uploaded = 1;
601
602 /* Copy the data into qe_firmware_info*/
603 sprop = of_get_property(fw, "id", NULL);
604 if (sprop)
605 strscpy(qe_firmware_info.id, sprop,
606 sizeof(qe_firmware_info.id));
607
608 of_property_read_u64(fw, "extended-modes",
609 &qe_firmware_info.extended_modes);
610
611 of_property_read_u32_array(fw, "virtual-traps", qe_firmware_info.vtraps,
612 ARRAY_SIZE(qe_firmware_info.vtraps));
613
614 of_node_put(fw);
615
616 return &qe_firmware_info;
617 }
618 EXPORT_SYMBOL(qe_get_firmware_info);
619
qe_get_num_of_risc(void)620 unsigned int qe_get_num_of_risc(void)
621 {
622 struct device_node *qe;
623 unsigned int num_of_risc = 0;
624
625 qe = qe_get_device_node();
626 if (!qe)
627 return num_of_risc;
628
629 of_property_read_u32(qe, "fsl,qe-num-riscs", &num_of_risc);
630
631 of_node_put(qe);
632
633 return num_of_risc;
634 }
635 EXPORT_SYMBOL(qe_get_num_of_risc);
636
qe_get_num_of_snums(void)637 unsigned int qe_get_num_of_snums(void)
638 {
639 return qe_num_of_snum;
640 }
641 EXPORT_SYMBOL(qe_get_num_of_snums);
642
qe_init(void)643 static int __init qe_init(void)
644 {
645 struct device_node *np;
646
647 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
648 if (!np)
649 return -ENODEV;
650 qe_reset();
651 of_node_put(np);
652 return 0;
653 }
654 subsys_initcall(qe_init);
655
656 #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
qe_resume(struct platform_device * ofdev)657 static int qe_resume(struct platform_device *ofdev)
658 {
659 if (!qe_alive_during_sleep())
660 qe_reset();
661 return 0;
662 }
663
qe_probe(struct platform_device * ofdev)664 static int qe_probe(struct platform_device *ofdev)
665 {
666 return 0;
667 }
668
669 static const struct of_device_id qe_ids[] = {
670 { .compatible = "fsl,qe", },
671 { },
672 };
673
674 static struct platform_driver qe_driver = {
675 .driver = {
676 .name = "fsl-qe",
677 .of_match_table = qe_ids,
678 },
679 .probe = qe_probe,
680 .resume = qe_resume,
681 };
682
683 builtin_platform_driver(qe_driver);
684 #endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */
685