1 /*
2 * Copyright 2025 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v15_0.h"
30
31 #include "mp/mp_15_0_0_offset.h"
32 #include "mp/mp_15_0_0_sh_mask.h"
33
34 MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc.bin");
35 MODULE_FIRMWARE("amdgpu/psp_15_0_0_ta.bin");
36 MODULE_FIRMWARE("amdgpu/psp_15_0_5_toc.bin");
37 MODULE_FIRMWARE("amdgpu/psp_15_0_5_ta.bin");
38 MODULE_FIRMWARE("amdgpu/psp_15_0_9_toc.bin");
39 MODULE_FIRMWARE("amdgpu/psp_15_0_9_ta.bin");
40
41 #define regMPASP_PCRU0_MPASP_C2PMSG_64 0x4280
42 #define regMPASP_PCRU0_MPASP_C2PMSG_64_BASE_IDX 2
43 #define regMPASP_PCRU0_MPASP_C2PMSG_67 0x4283
44 #define regMPASP_PCRU0_MPASP_C2PMSG_67_BASE_IDX 2
45 #define regMPASP_PCRU0_MPASP_C2PMSG_69 0x4285
46 #define regMPASP_PCRU0_MPASP_C2PMSG_69_BASE_IDX 2
47 #define regMPASP_PCRU0_MPASP_C2PMSG_70 0x4286
48 #define regMPASP_PCRU0_MPASP_C2PMSG_70_BASE_IDX 2
49 #define regMPASP_PCRU0_MPASP_C2PMSG_71 0x4287
50 #define regMPASP_PCRU0_MPASP_C2PMSG_71_BASE_IDX 2
51
psp_v15_0_0_init_microcode(struct psp_context * psp)52 static int psp_v15_0_0_init_microcode(struct psp_context *psp)
53 {
54 struct amdgpu_device *adev = psp->adev;
55 char ucode_prefix[30];
56 int err = 0;
57
58 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
59
60 err = psp_init_toc_microcode(psp, ucode_prefix);
61 if (err)
62 return err;
63
64 err = psp_init_ta_microcode(psp, ucode_prefix);
65 if (err)
66 return err;
67
68 return 0;
69 }
70
psp_v15_0_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)71 static int psp_v15_0_0_ring_stop(struct psp_context *psp,
72 enum psp_ring_type ring_type)
73 {
74 int ret = 0;
75 struct amdgpu_device *adev = psp->adev;
76
77 if (amdgpu_sriov_vf(adev)) {
78 /* Write the ring destroy command*/
79 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
80 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
81 /* there might be handshake issue with hardware which needs delay */
82 mdelay(20);
83 /* Wait for response flag (bit 31) */
84 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
85 0x80000000, 0x80000000, false);
86 } else {
87 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5)) {
88 /* Write the ring destroy command*/
89 WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64,
90 GFX_CTRL_CMD_ID_DESTROY_RINGS);
91 /* there might be handshake issue with hardware which needs delay */
92 mdelay(20);
93 /* Wait for response flag (bit 31) */
94 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64),
95 0x80000000, 0x80000000, false);
96 } else {
97 /* Write the ring destroy command*/
98 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64,
99 GFX_CTRL_CMD_ID_DESTROY_RINGS);
100 /* there might be handshake issue with hardware which needs delay */
101 mdelay(20);
102 /* Wait for response flag (bit 31) */
103 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
104 0x80000000, 0x80000000, false);
105 }
106 }
107
108 return ret;
109 }
110
psp_v15_0_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)111 static int psp_v15_0_0_ring_create(struct psp_context *psp,
112 enum psp_ring_type ring_type)
113 {
114 int ret = 0;
115 unsigned int psp_ring_reg = 0;
116 struct psp_ring *ring = &psp->km_ring;
117 struct amdgpu_device *adev = psp->adev;
118
119 if (amdgpu_sriov_vf(adev)) {
120 ret = psp_v15_0_0_ring_stop(psp, ring_type);
121 if (ret) {
122 DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n");
123 return ret;
124 }
125
126 /* Write low address of the ring to C2PMSG_102 */
127 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
128 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg);
129 /* Write high address of the ring to C2PMSG_103 */
130 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
131 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg);
132
133 /* Write the ring initialization command to C2PMSG_101 */
134 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
135 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
136
137 /* there might be handshake issue with hardware which needs delay */
138 mdelay(20);
139
140 /* Wait for response flag (bit 31) in C2PMSG_101 */
141 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
142 0x80000000, 0x8000FFFF, false);
143
144 } else {
145 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5)) {
146 /* Wait for sOS ready for ring creation */
147 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64),
148 0x80000000, 0x80000000, false);
149 if (ret) {
150 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
151 return ret;
152 }
153
154 /* Write low address of the ring to C2PMSG_69 */
155 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
156 WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_69, psp_ring_reg);
157 /* Write high address of the ring to C2PMSG_70 */
158 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
159 WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_70, psp_ring_reg);
160 /* Write size of ring to C2PMSG_71 */
161 psp_ring_reg = ring->ring_size;
162 WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_71, psp_ring_reg);
163 /* Write the ring initialization command to C2PMSG_64 */
164 psp_ring_reg = ring_type;
165 psp_ring_reg = psp_ring_reg << 16;
166 WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64, psp_ring_reg);
167
168 /* there might be handshake issue with hardware which needs delay */
169 mdelay(20);
170
171 /* Wait for response flag (bit 31) in C2PMSG_64 */
172 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64),
173 0x80000000, 0x8000FFFF, false);
174 } else {
175 /* Wait for sOS ready for ring creation */
176 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
177 0x80000000, 0x80000000, false);
178 if (ret) {
179 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
180 return ret;
181 }
182
183 /* Write low address of the ring to C2PMSG_69 */
184 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
185 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg);
186 /* Write high address of the ring to C2PMSG_70 */
187 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
188 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg);
189 /* Write size of ring to C2PMSG_71 */
190 psp_ring_reg = ring->ring_size;
191 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg);
192 /* Write the ring initialization command to C2PMSG_64 */
193 psp_ring_reg = ring_type;
194 psp_ring_reg = psp_ring_reg << 16;
195 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg);
196
197 /* there might be handshake issue with hardware which needs delay */
198 mdelay(20);
199
200 /* Wait for response flag (bit 31) in C2PMSG_64 */
201 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
202 0x80000000, 0x8000FFFF, false);
203 }
204 }
205
206 return ret;
207 }
208
psp_v15_0_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)209 static int psp_v15_0_0_ring_destroy(struct psp_context *psp,
210 enum psp_ring_type ring_type)
211 {
212 int ret = 0;
213 struct psp_ring *ring = &psp->km_ring;
214 struct amdgpu_device *adev = psp->adev;
215
216 ret = psp_v15_0_0_ring_stop(psp, ring_type);
217 if (ret)
218 DRM_ERROR("Fail to stop psp ring\n");
219
220 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
221 &ring->ring_mem_mc_addr,
222 (void **)&ring->ring_mem);
223
224 return ret;
225 }
226
psp_v15_0_0_ring_get_wptr(struct psp_context * psp)227 static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp)
228 {
229 uint32_t data;
230 struct amdgpu_device *adev = psp->adev;
231
232 if (amdgpu_sriov_vf(adev))
233 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
234 else {
235 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5))
236 data = RREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_67);
237 else
238 data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67);
239 }
240
241 return data;
242 }
243
psp_v15_0_0_ring_set_wptr(struct psp_context * psp,uint32_t value)244 static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
245 {
246 struct amdgpu_device *adev = psp->adev;
247
248 if (amdgpu_sriov_vf(adev)) {
249 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value);
250 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
251 GFX_CTRL_CMD_ID_CONSUME_CMD);
252 } else {
253 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5))
254 WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_67, value);
255 else
256 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value);
257 }
258 }
259
260 static const struct psp_funcs psp_v15_0_0_funcs = {
261 .init_microcode = psp_v15_0_0_init_microcode,
262 .ring_create = psp_v15_0_0_ring_create,
263 .ring_stop = psp_v15_0_0_ring_stop,
264 .ring_destroy = psp_v15_0_0_ring_destroy,
265 .ring_get_wptr = psp_v15_0_0_ring_get_wptr,
266 .ring_set_wptr = psp_v15_0_0_ring_set_wptr,
267 };
268
psp_v15_0_0_set_psp_funcs(struct psp_context * psp)269 void psp_v15_0_0_set_psp_funcs(struct psp_context *psp)
270 {
271 psp->funcs = &psp_v15_0_0_funcs;
272 }
273