1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include "hal_desc.h" 8 #include "../dp_mon.h" 9 #include "dp_mon.h" 10 #include "../debug.h" 11 #include "hal_qcn9274.h" 12 #include "dp_rx.h" 13 #include "../dp_tx.h" 14 #include "../peer.h" 15 16 static void 17 ath12k_wifi7_dp_mon_hal_aggr_tlv(struct hal_rx_mon_ppdu_info *ppdu_info, 18 u16 tlv_len, const void *tlv_data) 19 { 20 if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) { 21 memcpy(ppdu_info->tlv_aggr.buf + ppdu_info->tlv_aggr.cur_len, 22 tlv_data, tlv_len); 23 ppdu_info->tlv_aggr.cur_len += tlv_len; 24 } 25 } 26 27 static void 28 ath12k_wifi7_dp_mon_rx_memset_ppdu_info(struct hal_rx_mon_ppdu_info *ppdu_info) 29 { 30 memset(ppdu_info, 0, sizeof(*ppdu_info)); 31 ppdu_info->peer_id = HAL_INVALID_PEERID; 32 } 33 34 /* Hardware fill buffer with 128 bytes aligned. So need to reap it 35 * with 128 bytes aligned. 36 */ 37 #define RXDMA_DATA_DMA_BLOCK_SIZE 128 38 39 static void 40 ath12k_wifi7_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info, 41 bool *is_frag, u32 *total_len, 42 u32 *frag_len, u32 *msdu_cnt) 43 { 44 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) { 45 *is_frag = true; 46 *frag_len = (RX_MON_STATUS_BASE_BUF_SIZE - 47 sizeof(struct hal_rx_desc)) & 48 ~(RXDMA_DATA_DMA_BLOCK_SIZE - 1); 49 *total_len += *frag_len; 50 } else { 51 if (*is_frag) 52 *frag_len = info->msdu_len - *total_len; 53 else 54 *frag_len = info->msdu_len; 55 56 *msdu_cnt -= 1; 57 } 58 } 59 60 static void 61 ath12k_wifi7_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats *ppdu_end_user, 62 struct hal_rx_user_status *rx_user_status) 63 { 64 rx_user_status->ul_ofdma_user_v0_word0 = 65 __le32_to_cpu(ppdu_end_user->usr_resp_ref); 66 rx_user_status->ul_ofdma_user_v0_word1 = 67 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext); 68 } 69 70 static void 71 ath12k_wifi7_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats, 72 void *ppduinfo, 73 struct hal_rx_user_status *rx_user_status) 74 { 75 rx_user_status->mpdu_ok_byte_count = 76 le32_get_bits(stats->info7, 77 HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT); 78 rx_user_status->mpdu_err_byte_count = 79 le32_get_bits(stats->info8, 80 HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT); 81 } 82 83 static void 84 ath12k_wifi7_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats *rx_tlv, 85 struct hal_rx_mon_ppdu_info *ppdu_info, 86 struct hal_rx_user_status *rx_user_status) 87 { 88 rx_user_status->ast_index = ppdu_info->ast_index; 89 rx_user_status->tid = ppdu_info->tid; 90 rx_user_status->tcp_ack_msdu_count = 91 ppdu_info->tcp_ack_msdu_count; 92 rx_user_status->tcp_msdu_count = 93 ppdu_info->tcp_msdu_count; 94 rx_user_status->udp_msdu_count = 95 ppdu_info->udp_msdu_count; 96 rx_user_status->other_msdu_count = 97 ppdu_info->other_msdu_count; 98 rx_user_status->frame_control = ppdu_info->frame_control; 99 rx_user_status->frame_control_info_valid = 100 ppdu_info->frame_control_info_valid; 101 rx_user_status->data_sequence_control_info_valid = 102 ppdu_info->data_sequence_control_info_valid; 103 rx_user_status->first_data_seq_ctrl = 104 ppdu_info->first_data_seq_ctrl; 105 rx_user_status->preamble_type = ppdu_info->preamble_type; 106 rx_user_status->ht_flags = ppdu_info->ht_flags; 107 rx_user_status->vht_flags = ppdu_info->vht_flags; 108 rx_user_status->he_flags = ppdu_info->he_flags; 109 rx_user_status->rs_flags = ppdu_info->rs_flags; 110 111 rx_user_status->mpdu_cnt_fcs_ok = 112 ppdu_info->num_mpdu_fcs_ok; 113 rx_user_status->mpdu_cnt_fcs_err = 114 ppdu_info->num_mpdu_fcs_err; 115 memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0], 116 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 117 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0])); 118 119 ath12k_wifi7_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status); 120 } 121 122 static inline enum ath12k_eht_ru_size 123 hal_rx_mon_hal_ru_size_to_ath12k_ru_size(u32 hal_ru_size) 124 { 125 switch (hal_ru_size) { 126 case HAL_EHT_RU_26: 127 return ATH12K_EHT_RU_26; 128 case HAL_EHT_RU_52: 129 return ATH12K_EHT_RU_52; 130 case HAL_EHT_RU_78: 131 return ATH12K_EHT_RU_52_26; 132 case HAL_EHT_RU_106: 133 return ATH12K_EHT_RU_106; 134 case HAL_EHT_RU_132: 135 return ATH12K_EHT_RU_106_26; 136 case HAL_EHT_RU_242: 137 return ATH12K_EHT_RU_242; 138 case HAL_EHT_RU_484: 139 return ATH12K_EHT_RU_484; 140 case HAL_EHT_RU_726: 141 return ATH12K_EHT_RU_484_242; 142 case HAL_EHT_RU_996: 143 return ATH12K_EHT_RU_996; 144 case HAL_EHT_RU_996x2: 145 return ATH12K_EHT_RU_996x2; 146 case HAL_EHT_RU_996x3: 147 return ATH12K_EHT_RU_996x3; 148 case HAL_EHT_RU_996x4: 149 return ATH12K_EHT_RU_996x4; 150 case HAL_EHT_RU_NONE: 151 return ATH12K_EHT_RU_INVALID; 152 case HAL_EHT_RU_996_484: 153 return ATH12K_EHT_RU_996_484; 154 case HAL_EHT_RU_996x2_484: 155 return ATH12K_EHT_RU_996x2_484; 156 case HAL_EHT_RU_996x3_484: 157 return ATH12K_EHT_RU_996x3_484; 158 case HAL_EHT_RU_996_484_242: 159 return ATH12K_EHT_RU_996_484_242; 160 default: 161 return ATH12K_EHT_RU_INVALID; 162 } 163 } 164 165 static inline u32 166 hal_rx_ul_ofdma_ru_size_to_width(enum ath12k_eht_ru_size ru_size) 167 { 168 switch (ru_size) { 169 case ATH12K_EHT_RU_26: 170 return RU_26; 171 case ATH12K_EHT_RU_52: 172 return RU_52; 173 case ATH12K_EHT_RU_52_26: 174 return RU_52_26; 175 case ATH12K_EHT_RU_106: 176 return RU_106; 177 case ATH12K_EHT_RU_106_26: 178 return RU_106_26; 179 case ATH12K_EHT_RU_242: 180 return RU_242; 181 case ATH12K_EHT_RU_484: 182 return RU_484; 183 case ATH12K_EHT_RU_484_242: 184 return RU_484_242; 185 case ATH12K_EHT_RU_996: 186 return RU_996; 187 case ATH12K_EHT_RU_996_484: 188 return RU_996_484; 189 case ATH12K_EHT_RU_996_484_242: 190 return RU_996_484_242; 191 case ATH12K_EHT_RU_996x2: 192 return RU_2X996; 193 case ATH12K_EHT_RU_996x2_484: 194 return RU_2X996_484; 195 case ATH12K_EHT_RU_996x3: 196 return RU_3X996; 197 case ATH12K_EHT_RU_996x3_484: 198 return RU_3X996_484; 199 case ATH12K_EHT_RU_996x4: 200 return RU_4X996; 201 default: 202 return RU_INVALID; 203 } 204 } 205 206 static void 207 ath12k_wifi7_dp_mon_hal_rx_parse_user_info(const struct hal_receive_user_info *rx_usr_info, 208 u16 user_id, 209 struct hal_rx_mon_ppdu_info *ppdu_info) 210 { 211 struct hal_rx_user_status *mon_rx_user_status = NULL; 212 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht; 213 enum ath12k_eht_ru_size rtap_ru_size = ATH12K_EHT_RU_INVALID; 214 u32 ru_width, reception_type, ru_index = HAL_EHT_RU_INVALID; 215 u32 ru_type_80_0, ru_start_index_80_0; 216 u32 ru_type_80_1, ru_start_index_80_1; 217 u32 ru_type_80_2, ru_start_index_80_2; 218 u32 ru_type_80_3, ru_start_index_80_3; 219 u32 ru_size = 0, num_80mhz_with_ru = 0; 220 u64 ru_index_320mhz = 0; 221 u32 ru_index_per80mhz; 222 223 reception_type = le32_get_bits(rx_usr_info->info0, 224 HAL_RX_USR_INFO0_RECEPTION_TYPE); 225 226 switch (reception_type) { 227 case HAL_RECEPTION_TYPE_SU: 228 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 229 break; 230 case HAL_RECEPTION_TYPE_DL_MU_MIMO: 231 case HAL_RECEPTION_TYPE_UL_MU_MIMO: 232 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 233 break; 234 case HAL_RECEPTION_TYPE_DL_MU_OFMA: 235 case HAL_RECEPTION_TYPE_UL_MU_OFDMA: 236 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; 237 break; 238 case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: 239 case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: 240 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO; 241 } 242 243 ppdu_info->is_stbc = le32_get_bits(rx_usr_info->info0, HAL_RX_USR_INFO0_STBC); 244 ppdu_info->ldpc = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_LDPC); 245 ppdu_info->dcm = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_STA_DCM); 246 ppdu_info->bw = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_RX_BW); 247 ppdu_info->mcs = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_MCS); 248 ppdu_info->nss = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_NSS) + 1; 249 250 if (user_id < HAL_MAX_UL_MU_USERS) { 251 mon_rx_user_status = &ppdu_info->userstats[user_id]; 252 mon_rx_user_status->mcs = ppdu_info->mcs; 253 mon_rx_user_status->nss = ppdu_info->nss; 254 } 255 256 if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO || 257 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA || 258 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)) 259 return; 260 261 /* RU allocation present only for OFDMA reception */ 262 ru_type_80_0 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_0); 263 ru_start_index_80_0 = le32_get_bits(rx_usr_info->info3, 264 HAL_RX_USR_INFO3_RU_START_IDX_80_0); 265 if (ru_type_80_0 != HAL_EHT_RU_NONE) { 266 ru_size += ru_type_80_0; 267 ru_index_per80mhz = ru_start_index_80_0; 268 ru_index = ru_index_per80mhz; 269 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_0, 0, ru_index_per80mhz); 270 num_80mhz_with_ru++; 271 } 272 273 ru_type_80_1 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_1); 274 ru_start_index_80_1 = le32_get_bits(rx_usr_info->info3, 275 HAL_RX_USR_INFO3_RU_START_IDX_80_1); 276 if (ru_type_80_1 != HAL_EHT_RU_NONE) { 277 ru_size += ru_type_80_1; 278 ru_index_per80mhz = ru_start_index_80_1; 279 ru_index = ru_index_per80mhz; 280 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_1, 1, ru_index_per80mhz); 281 num_80mhz_with_ru++; 282 } 283 284 ru_type_80_2 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_2); 285 ru_start_index_80_2 = le32_get_bits(rx_usr_info->info3, 286 HAL_RX_USR_INFO3_RU_START_IDX_80_2); 287 if (ru_type_80_2 != HAL_EHT_RU_NONE) { 288 ru_size += ru_type_80_2; 289 ru_index_per80mhz = ru_start_index_80_2; 290 ru_index = ru_index_per80mhz; 291 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_2, 2, ru_index_per80mhz); 292 num_80mhz_with_ru++; 293 } 294 295 ru_type_80_3 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_3); 296 ru_start_index_80_3 = le32_get_bits(rx_usr_info->info2, 297 HAL_RX_USR_INFO3_RU_START_IDX_80_3); 298 if (ru_type_80_3 != HAL_EHT_RU_NONE) { 299 ru_size += ru_type_80_3; 300 ru_index_per80mhz = ru_start_index_80_3; 301 ru_index = ru_index_per80mhz; 302 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_3, 3, ru_index_per80mhz); 303 num_80mhz_with_ru++; 304 } 305 306 if (num_80mhz_with_ru > 1) { 307 /* Calculate the MRU index */ 308 switch (ru_index_320mhz) { 309 case HAL_EHT_RU_996_484_0: 310 case HAL_EHT_RU_996x2_484_0: 311 case HAL_EHT_RU_996x3_484_0: 312 ru_index = 0; 313 break; 314 case HAL_EHT_RU_996_484_1: 315 case HAL_EHT_RU_996x2_484_1: 316 case HAL_EHT_RU_996x3_484_1: 317 ru_index = 1; 318 break; 319 case HAL_EHT_RU_996_484_2: 320 case HAL_EHT_RU_996x2_484_2: 321 case HAL_EHT_RU_996x3_484_2: 322 ru_index = 2; 323 break; 324 case HAL_EHT_RU_996_484_3: 325 case HAL_EHT_RU_996x2_484_3: 326 case HAL_EHT_RU_996x3_484_3: 327 ru_index = 3; 328 break; 329 case HAL_EHT_RU_996_484_4: 330 case HAL_EHT_RU_996x2_484_4: 331 case HAL_EHT_RU_996x3_484_4: 332 ru_index = 4; 333 break; 334 case HAL_EHT_RU_996_484_5: 335 case HAL_EHT_RU_996x2_484_5: 336 case HAL_EHT_RU_996x3_484_5: 337 ru_index = 5; 338 break; 339 case HAL_EHT_RU_996_484_6: 340 case HAL_EHT_RU_996x2_484_6: 341 case HAL_EHT_RU_996x3_484_6: 342 ru_index = 6; 343 break; 344 case HAL_EHT_RU_996_484_7: 345 case HAL_EHT_RU_996x2_484_7: 346 case HAL_EHT_RU_996x3_484_7: 347 ru_index = 7; 348 break; 349 case HAL_EHT_RU_996x2_484_8: 350 ru_index = 8; 351 break; 352 case HAL_EHT_RU_996x2_484_9: 353 ru_index = 9; 354 break; 355 case HAL_EHT_RU_996x2_484_10: 356 ru_index = 10; 357 break; 358 case HAL_EHT_RU_996x2_484_11: 359 ru_index = 11; 360 break; 361 default: 362 ru_index = HAL_EHT_RU_INVALID; 363 break; 364 } 365 366 ru_size += 4; 367 } 368 369 rtap_ru_size = hal_rx_mon_hal_ru_size_to_ath12k_ru_size(ru_size); 370 if (rtap_ru_size != ATH12K_EHT_RU_INVALID) { 371 u32 known, data; 372 373 known = __le32_to_cpu(eht->known); 374 known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_SIZE_OM; 375 eht->known = cpu_to_le32(known); 376 377 data = __le32_to_cpu(eht->data[1]); 378 data |= u32_encode_bits(rtap_ru_size, 379 IEEE80211_RADIOTAP_EHT_DATA1_RU_SIZE); 380 eht->data[1] = cpu_to_le32(data); 381 } 382 383 if (ru_index != HAL_EHT_RU_INVALID) { 384 u32 known, data; 385 386 known = __le32_to_cpu(eht->known); 387 known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_INDEX_OM; 388 eht->known = cpu_to_le32(known); 389 390 data = __le32_to_cpu(eht->data[1]); 391 data |= u32_encode_bits(rtap_ru_size, 392 IEEE80211_RADIOTAP_EHT_DATA1_RU_INDEX); 393 eht->data[1] = cpu_to_le32(data); 394 } 395 396 if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID && 397 rtap_ru_size != ATH12K_EHT_RU_INVALID) { 398 mon_rx_user_status->ul_ofdma_ru_start_index = ru_index; 399 mon_rx_user_status->ul_ofdma_ru_size = rtap_ru_size; 400 401 ru_width = hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size); 402 403 mon_rx_user_status->ul_ofdma_ru_width = ru_width; 404 mon_rx_user_status->ofdma_info_valid = 1; 405 } 406 } 407 408 static __always_inline u8 409 ath12k_wifi7_hal_mon_map_legacy_rate_to_hw_rate(u8 rate) 410 { 411 u8 ath12k_rate; 412 413 /* Map hal_rx_legacy_rate to ath12k_hw_rate_cck */ 414 switch (rate) { 415 case HAL_RX_LEGACY_RATE_LP_1_MBPS: 416 ath12k_rate = ATH12K_HW_RATE_CCK_LP_1M; 417 break; 418 case HAL_RX_LEGACY_RATE_LP_2_MBPS: 419 ath12k_rate = ATH12K_HW_RATE_CCK_LP_2M; 420 break; 421 case HAL_RX_LEGACY_RATE_LP_5_5_MBPS: 422 ath12k_rate = ATH12K_HW_RATE_CCK_LP_5_5M; 423 break; 424 case HAL_RX_LEGACY_RATE_LP_11_MBPS: 425 ath12k_rate = ATH12K_HW_RATE_CCK_LP_11M; 426 break; 427 case HAL_RX_LEGACY_RATE_SP_2_MBPS: 428 ath12k_rate = ATH12K_HW_RATE_CCK_SP_2M; 429 break; 430 case HAL_RX_LEGACY_RATE_SP_5_5_MBPS: 431 ath12k_rate = ATH12K_HW_RATE_CCK_SP_5_5M; 432 break; 433 case HAL_RX_LEGACY_RATE_SP_11_MBPS: 434 ath12k_rate = ATH12K_HW_RATE_CCK_SP_11M; 435 break; 436 default: 437 ath12k_rate = rate; 438 break; 439 } 440 441 return ath12k_rate; 442 } 443 444 static void 445 ath12k_wifi7_dp_mon_parse_l_sig_b(const struct hal_rx_lsig_b_info *lsigb, 446 struct hal_rx_mon_ppdu_info *ppdu_info) 447 { 448 u32 info0 = __le32_to_cpu(lsigb->info0); 449 u8 rate; 450 451 rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE); 452 switch (rate) { 453 case 1: 454 rate = HAL_RX_LEGACY_RATE_LP_1_MBPS; 455 break; 456 case 2: 457 rate = HAL_RX_LEGACY_RATE_LP_2_MBPS; 458 break; 459 case 3: 460 rate = HAL_RX_LEGACY_RATE_LP_5_5_MBPS; 461 break; 462 case 4: 463 rate = HAL_RX_LEGACY_RATE_LP_11_MBPS; 464 break; 465 case 5: 466 rate = HAL_RX_LEGACY_RATE_SP_2_MBPS; 467 break; 468 case 6: 469 rate = HAL_RX_LEGACY_RATE_SP_5_5_MBPS; 470 break; 471 case 7: 472 rate = HAL_RX_LEGACY_RATE_SP_11_MBPS; 473 break; 474 default: 475 rate = HAL_RX_LEGACY_RATE_INVALID; 476 break; 477 } 478 479 ppdu_info->rate = ath12k_wifi7_hal_mon_map_legacy_rate_to_hw_rate(rate); 480 ppdu_info->cck_flag = 1; 481 } 482 483 static void 484 ath12k_wifi7_dp_mon_parse_l_sig_a(const struct hal_rx_lsig_a_info *lsiga, 485 struct hal_rx_mon_ppdu_info *ppdu_info) 486 { 487 u32 info0 = __le32_to_cpu(lsiga->info0); 488 u8 rate; 489 490 rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE); 491 switch (rate) { 492 case 8: 493 rate = HAL_RX_LEGACY_RATE_OFDM_48_MBPS; 494 break; 495 case 9: 496 rate = HAL_RX_LEGACY_RATE_OFDM_24_MBPS; 497 break; 498 case 10: 499 rate = HAL_RX_LEGACY_RATE_OFDM_12_MBPS; 500 break; 501 case 11: 502 rate = HAL_RX_LEGACY_RATE_OFDM_6_MBPS; 503 break; 504 case 12: 505 rate = HAL_RX_LEGACY_RATE_OFDM_54_MBPS; 506 break; 507 case 13: 508 rate = HAL_RX_LEGACY_RATE_OFDM_36_MBPS; 509 break; 510 case 14: 511 rate = HAL_RX_LEGACY_RATE_OFDM_18_MBPS; 512 break; 513 case 15: 514 rate = HAL_RX_LEGACY_RATE_OFDM_9_MBPS; 515 break; 516 default: 517 rate = HAL_RX_LEGACY_RATE_OFDM_INVALID; 518 break; 519 } 520 521 ppdu_info->rate = rate; 522 } 523 524 static void 525 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn(const struct hal_mon_usig_cmn *cmn, 526 struct hal_rx_mon_ppdu_info *ppdu_info) 527 { 528 u32 common; 529 530 ppdu_info->u_sig_info.bw = le32_get_bits(cmn->info0, 531 HAL_RX_USIG_CMN_INFO0_BW); 532 ppdu_info->u_sig_info.ul_dl = le32_get_bits(cmn->info0, 533 HAL_RX_USIG_CMN_INFO0_UL_DL); 534 535 common = __le32_to_cpu(ppdu_info->u_sig_info.usig.common); 536 common |= IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER_KNOWN | 537 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN | 538 IEEE80211_RADIOTAP_EHT_USIG_COMMON_UL_DL_KNOWN | 539 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR_KNOWN | 540 IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP_KNOWN | 541 ATH12K_LE32_DEC_ENC(cmn->info0, 542 HAL_RX_USIG_CMN_INFO0_PHY_VERSION, 543 IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER) | 544 u32_encode_bits(ppdu_info->u_sig_info.bw, 545 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW) | 546 u32_encode_bits(ppdu_info->u_sig_info.ul_dl, 547 IEEE80211_RADIOTAP_EHT_USIG_COMMON_UL_DL) | 548 ATH12K_LE32_DEC_ENC(cmn->info0, 549 HAL_RX_USIG_CMN_INFO0_BSS_COLOR, 550 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR) | 551 ATH12K_LE32_DEC_ENC(cmn->info0, 552 HAL_RX_USIG_CMN_INFO0_TXOP, 553 IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP); 554 ppdu_info->u_sig_info.usig.common = cpu_to_le32(common); 555 556 switch (ppdu_info->u_sig_info.bw) { 557 default: 558 fallthrough; 559 case HAL_EHT_BW_20: 560 ppdu_info->bw = HAL_RX_BW_20MHZ; 561 break; 562 case HAL_EHT_BW_40: 563 ppdu_info->bw = HAL_RX_BW_40MHZ; 564 break; 565 case HAL_EHT_BW_80: 566 ppdu_info->bw = HAL_RX_BW_80MHZ; 567 break; 568 case HAL_EHT_BW_160: 569 ppdu_info->bw = HAL_RX_BW_160MHZ; 570 break; 571 case HAL_EHT_BW_320_1: 572 case HAL_EHT_BW_320_2: 573 ppdu_info->bw = HAL_RX_BW_320MHZ; 574 break; 575 } 576 } 577 578 static void 579 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_tb(const struct hal_mon_usig_tb *usig_tb, 580 struct hal_rx_mon_ppdu_info *ppdu_info) 581 { 582 struct ieee80211_radiotap_eht_usig *usig = &ppdu_info->u_sig_info.usig; 583 enum ieee80211_radiotap_eht_usig_tb spatial_reuse1, spatial_reuse2; 584 u32 common, value, mask; 585 586 spatial_reuse1 = IEEE80211_RADIOTAP_EHT_USIG2_TB_B3_B6_SPATIAL_REUSE_1; 587 spatial_reuse2 = IEEE80211_RADIOTAP_EHT_USIG2_TB_B7_B10_SPATIAL_REUSE_2; 588 589 common = __le32_to_cpu(usig->common); 590 value = __le32_to_cpu(usig->value); 591 mask = __le32_to_cpu(usig->mask); 592 593 ppdu_info->u_sig_info.ppdu_type_comp_mode = 594 le32_get_bits(usig_tb->info0, 595 HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE); 596 597 common |= ATH12K_LE32_DEC_ENC(usig_tb->info0, 598 HAL_RX_USIG_TB_INFO0_RX_INTEG_CHECK_PASS, 599 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BAD_USIG_CRC); 600 601 value |= IEEE80211_RADIOTAP_EHT_USIG1_TB_B20_B25_DISREGARD | 602 u32_encode_bits(ppdu_info->u_sig_info.ppdu_type_comp_mode, 603 IEEE80211_RADIOTAP_EHT_USIG2_TB_B0_B1_PPDU_TYPE) | 604 IEEE80211_RADIOTAP_EHT_USIG2_TB_B2_VALIDATE | 605 ATH12K_LE32_DEC_ENC(usig_tb->info0, 606 HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1, 607 spatial_reuse1) | 608 ATH12K_LE32_DEC_ENC(usig_tb->info0, 609 HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2, 610 spatial_reuse2) | 611 IEEE80211_RADIOTAP_EHT_USIG2_TB_B11_B15_DISREGARD | 612 ATH12K_LE32_DEC_ENC(usig_tb->info0, 613 HAL_RX_USIG_TB_INFO0_CRC, 614 IEEE80211_RADIOTAP_EHT_USIG2_TB_B16_B19_CRC) | 615 ATH12K_LE32_DEC_ENC(usig_tb->info0, 616 HAL_RX_USIG_TB_INFO0_TAIL, 617 IEEE80211_RADIOTAP_EHT_USIG2_TB_B20_B25_TAIL); 618 619 mask |= IEEE80211_RADIOTAP_EHT_USIG1_TB_B20_B25_DISREGARD | 620 IEEE80211_RADIOTAP_EHT_USIG2_TB_B0_B1_PPDU_TYPE | 621 IEEE80211_RADIOTAP_EHT_USIG2_TB_B2_VALIDATE | 622 spatial_reuse1 | spatial_reuse2 | 623 IEEE80211_RADIOTAP_EHT_USIG2_TB_B11_B15_DISREGARD | 624 IEEE80211_RADIOTAP_EHT_USIG2_TB_B16_B19_CRC | 625 IEEE80211_RADIOTAP_EHT_USIG2_TB_B20_B25_TAIL; 626 627 usig->common = cpu_to_le32(common); 628 usig->value = cpu_to_le32(value); 629 usig->mask = cpu_to_le32(mask); 630 } 631 632 static void 633 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_mu(const struct hal_mon_usig_mu *usig_mu, 634 struct hal_rx_mon_ppdu_info *ppdu_info) 635 { 636 struct ieee80211_radiotap_eht_usig *usig = &ppdu_info->u_sig_info.usig; 637 enum ieee80211_radiotap_eht_usig_mu sig_symb, punc; 638 u32 common, value, mask; 639 640 sig_symb = IEEE80211_RADIOTAP_EHT_USIG2_MU_B11_B15_EHT_SIG_SYMBOLS; 641 punc = IEEE80211_RADIOTAP_EHT_USIG2_MU_B3_B7_PUNCTURED_INFO; 642 643 common = __le32_to_cpu(usig->common); 644 value = __le32_to_cpu(usig->value); 645 mask = __le32_to_cpu(usig->mask); 646 647 ppdu_info->u_sig_info.ppdu_type_comp_mode = 648 le32_get_bits(usig_mu->info0, 649 HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE); 650 ppdu_info->u_sig_info.eht_sig_mcs = 651 le32_get_bits(usig_mu->info0, 652 HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS); 653 ppdu_info->u_sig_info.num_eht_sig_sym = 654 le32_get_bits(usig_mu->info0, 655 HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM); 656 657 common |= ATH12K_LE32_DEC_ENC(usig_mu->info0, 658 HAL_RX_USIG_MU_INFO0_RX_INTEG_CHECK_PASS, 659 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BAD_USIG_CRC); 660 661 value |= IEEE80211_RADIOTAP_EHT_USIG1_MU_B20_B24_DISREGARD | 662 IEEE80211_RADIOTAP_EHT_USIG1_MU_B25_VALIDATE | 663 u32_encode_bits(ppdu_info->u_sig_info.ppdu_type_comp_mode, 664 IEEE80211_RADIOTAP_EHT_USIG2_MU_B0_B1_PPDU_TYPE) | 665 IEEE80211_RADIOTAP_EHT_USIG2_MU_B2_VALIDATE | 666 ATH12K_LE32_DEC_ENC(usig_mu->info0, 667 HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO, 668 punc) | 669 IEEE80211_RADIOTAP_EHT_USIG2_MU_B8_VALIDATE | 670 u32_encode_bits(ppdu_info->u_sig_info.eht_sig_mcs, 671 IEEE80211_RADIOTAP_EHT_USIG2_MU_B9_B10_SIG_MCS) | 672 u32_encode_bits(ppdu_info->u_sig_info.num_eht_sig_sym, 673 sig_symb) | 674 ATH12K_LE32_DEC_ENC(usig_mu->info0, 675 HAL_RX_USIG_MU_INFO0_CRC, 676 IEEE80211_RADIOTAP_EHT_USIG2_MU_B16_B19_CRC) | 677 ATH12K_LE32_DEC_ENC(usig_mu->info0, 678 HAL_RX_USIG_MU_INFO0_TAIL, 679 IEEE80211_RADIOTAP_EHT_USIG2_MU_B20_B25_TAIL); 680 681 mask |= IEEE80211_RADIOTAP_EHT_USIG1_MU_B20_B24_DISREGARD | 682 IEEE80211_RADIOTAP_EHT_USIG1_MU_B25_VALIDATE | 683 IEEE80211_RADIOTAP_EHT_USIG2_MU_B0_B1_PPDU_TYPE | 684 IEEE80211_RADIOTAP_EHT_USIG2_MU_B2_VALIDATE | 685 punc | 686 IEEE80211_RADIOTAP_EHT_USIG2_MU_B8_VALIDATE | 687 IEEE80211_RADIOTAP_EHT_USIG2_MU_B9_B10_SIG_MCS | 688 sig_symb | 689 IEEE80211_RADIOTAP_EHT_USIG2_MU_B16_B19_CRC | 690 IEEE80211_RADIOTAP_EHT_USIG2_MU_B20_B25_TAIL; 691 692 usig->common = cpu_to_le32(common); 693 usig->value = cpu_to_le32(value); 694 usig->mask = cpu_to_le32(mask); 695 } 696 697 static void 698 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_hdr(const struct hal_mon_usig_hdr *usig, 699 struct hal_rx_mon_ppdu_info *ppdu_info) 700 { 701 u8 comp_mode; 702 703 ppdu_info->eht_usig = true; 704 705 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn(&usig->cmn, ppdu_info); 706 707 comp_mode = le32_get_bits(usig->non_cmn.mu.info0, 708 HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE); 709 710 if (comp_mode == 0 && ppdu_info->u_sig_info.ul_dl) 711 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_tb(&usig->non_cmn.tb, ppdu_info); 712 else 713 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_mu(&usig->non_cmn.mu, ppdu_info); 714 } 715 716 static void 717 ath12k_wifi7_dp_mon_parse_vht_sig_a(const struct hal_rx_vht_sig_a_info *vht_sig, 718 struct hal_rx_mon_ppdu_info *ppdu_info) 719 { 720 u32 nsts, info0, info1; 721 u8 gi_setting; 722 723 info0 = __le32_to_cpu(vht_sig->info0); 724 info1 = __le32_to_cpu(vht_sig->info1); 725 726 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING); 727 ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS); 728 gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING); 729 switch (gi_setting) { 730 case HAL_RX_VHT_SIG_A_NORMAL_GI: 731 ppdu_info->gi = HAL_RX_GI_0_8_US; 732 break; 733 case HAL_RX_VHT_SIG_A_SHORT_GI: 734 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY: 735 ppdu_info->gi = HAL_RX_GI_0_4_US; 736 break; 737 } 738 739 ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC); 740 nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS); 741 if (ppdu_info->is_stbc && nsts > 0) 742 nsts = ((nsts + 1) >> 1) - 1; 743 744 ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK) + 1; 745 ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW); 746 ppdu_info->beamformed = u32_get_bits(info1, 747 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED); 748 ppdu_info->vht_flag_values5 = u32_get_bits(info0, 749 HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID); 750 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) | 751 ppdu_info->nss); 752 ppdu_info->vht_flag_values2 = ppdu_info->bw; 753 ppdu_info->vht_flag_values4 = 754 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING); 755 } 756 757 static void 758 ath12k_wifi7_dp_mon_parse_ht_sig(const struct hal_rx_ht_sig_info *ht_sig, 759 struct hal_rx_mon_ppdu_info *ppdu_info) 760 { 761 u32 info0 = __le32_to_cpu(ht_sig->info0); 762 u32 info1 = __le32_to_cpu(ht_sig->info1); 763 764 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS); 765 ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW); 766 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC); 767 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING); 768 ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI); 769 ppdu_info->nss = (ppdu_info->mcs >> 3) + 1; 770 } 771 772 static void 773 ath12k_wifi7_dp_mon_parse_he_sig_b2_ofdma(const struct hal_rx_he_sig_b2_ofdma_info *ofdma, 774 struct hal_rx_mon_ppdu_info *ppdu_info) 775 { 776 u32 info0, value; 777 778 info0 = __le32_to_cpu(ofdma->info0); 779 780 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN; 781 782 /* HE-data2 */ 783 ppdu_info->he_data2 |= HE_TXBF_KNOWN; 784 785 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS); 786 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT; 787 ppdu_info->he_data3 |= value; 788 789 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM); 790 value = value << HE_DCM_SHIFT; 791 ppdu_info->he_data3 |= value; 792 793 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING); 794 ppdu_info->ldpc = value; 795 value = value << HE_CODING_SHIFT; 796 ppdu_info->he_data3 |= value; 797 798 /* HE-data4 */ 799 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID); 800 value = value << HE_STA_ID_SHIFT; 801 ppdu_info->he_data4 |= value; 802 803 ppdu_info->nss = 804 u32_get_bits(info0, 805 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS) + 1; 806 ppdu_info->beamformed = u32_get_bits(info0, 807 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF); 808 } 809 810 static void 811 ath12k_wifi7_dp_mon_parse_he_sig_b2_mu(const struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu, 812 struct hal_rx_mon_ppdu_info *ppdu_info) 813 { 814 u32 info0, value; 815 816 info0 = __le32_to_cpu(he_sig_b2_mu->info0); 817 818 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN; 819 820 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS); 821 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT; 822 ppdu_info->he_data3 |= value; 823 824 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING); 825 ppdu_info->ldpc = value; 826 value = value << HE_CODING_SHIFT; 827 ppdu_info->he_data3 |= value; 828 829 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID); 830 value = value << HE_STA_ID_SHIFT; 831 ppdu_info->he_data4 |= value; 832 833 ppdu_info->nss = 834 u32_get_bits(info0, 835 HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS) + 1; 836 } 837 838 static void 839 ath12k_wifi7_dp_mon_parse_he_sig_b1_mu(const struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu, 840 struct hal_rx_mon_ppdu_info *ppdu_info) 841 { 842 u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0); 843 u16 ru_tones; 844 845 ru_tones = u32_get_bits(info0, 846 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION); 847 ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); 848 ppdu_info->he_RU[0] = ru_tones; 849 } 850 851 static void 852 ath12k_wifi7_dp_mon_parse_he_sig_mu(const struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl, 853 struct hal_rx_mon_ppdu_info *ppdu_info) 854 { 855 u32 info0, info1, value; 856 u16 he_gi = 0, he_ltf = 0; 857 858 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0); 859 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1); 860 861 ppdu_info->he_mu_flags = 1; 862 863 ppdu_info->he_data1 = HE_MU_FORMAT_TYPE; 864 ppdu_info->he_data1 |= 865 HE_BSS_COLOR_KNOWN | 866 HE_DL_UL_KNOWN | 867 HE_LDPC_EXTRA_SYMBOL_KNOWN | 868 HE_STBC_KNOWN | 869 HE_DATA_BW_RU_KNOWN | 870 HE_DOPPLER_KNOWN; 871 872 ppdu_info->he_data2 = 873 HE_GI_KNOWN | 874 HE_LTF_SYMBOLS_KNOWN | 875 HE_PRE_FEC_PADDING_KNOWN | 876 HE_PE_DISAMBIGUITY_KNOWN | 877 HE_TXOP_KNOWN | 878 HE_MIDABLE_PERIODICITY_KNOWN; 879 880 /* data3 */ 881 ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR); 882 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG); 883 value = value << HE_DL_UL_SHIFT; 884 ppdu_info->he_data3 |= value; 885 886 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA); 887 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT; 888 ppdu_info->he_data3 |= value; 889 890 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC); 891 value = value << HE_STBC_SHIFT; 892 ppdu_info->he_data3 |= value; 893 894 /* data4 */ 895 ppdu_info->he_data4 = u32_get_bits(info0, 896 HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE); 897 ppdu_info->he_data4 = value; 898 899 /* data5 */ 900 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW); 901 ppdu_info->he_data5 = value; 902 ppdu_info->bw = value; 903 904 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE); 905 switch (value) { 906 case 0: 907 he_gi = HE_GI_0_8; 908 he_ltf = HE_LTF_4_X; 909 break; 910 case 1: 911 he_gi = HE_GI_0_8; 912 he_ltf = HE_LTF_2_X; 913 break; 914 case 2: 915 he_gi = HE_GI_1_6; 916 he_ltf = HE_LTF_2_X; 917 break; 918 case 3: 919 he_gi = HE_GI_3_2; 920 he_ltf = HE_LTF_4_X; 921 break; 922 } 923 924 ppdu_info->gi = he_gi; 925 value = he_gi << HE_GI_SHIFT; 926 ppdu_info->he_data5 |= value; 927 928 value = he_ltf << HE_LTF_SIZE_SHIFT; 929 ppdu_info->he_data5 |= value; 930 931 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB); 932 value = (value << HE_LTF_SYM_SHIFT); 933 ppdu_info->he_data5 |= value; 934 935 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR); 936 value = value << HE_PRE_FEC_PAD_SHIFT; 937 ppdu_info->he_data5 |= value; 938 939 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM); 940 value = value << HE_PE_DISAMBIGUITY_SHIFT; 941 ppdu_info->he_data5 |= value; 942 943 /*data6*/ 944 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION); 945 value = value << HE_DOPPLER_SHIFT; 946 ppdu_info->he_data6 |= value; 947 948 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION); 949 value = value << HE_TXOP_SHIFT; 950 ppdu_info->he_data6 |= value; 951 952 /* HE-MU Flags */ 953 /* HE-MU-flags1 */ 954 ppdu_info->he_flags1 = 955 HE_SIG_B_MCS_KNOWN | 956 HE_SIG_B_DCM_KNOWN | 957 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN | 958 HE_SIG_B_SYM_NUM_KNOWN | 959 HE_RU_0_KNOWN; 960 961 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB); 962 ppdu_info->he_flags1 |= value; 963 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB); 964 value = value << HE_DCM_FLAG_1_SHIFT; 965 ppdu_info->he_flags1 |= value; 966 967 /* HE-MU-flags2 */ 968 ppdu_info->he_flags2 = HE_BW_KNOWN; 969 970 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW); 971 ppdu_info->he_flags2 |= value; 972 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB); 973 value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT; 974 ppdu_info->he_flags2 |= value; 975 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB); 976 value = value - 1; 977 value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT; 978 ppdu_info->he_flags2 |= value; 979 980 ppdu_info->is_stbc = info1 & 981 HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC; 982 } 983 984 static void 985 ath12k_wifi7_dp_mon_parse_he_sig_su(const struct hal_rx_he_sig_a_su_info *he_sig_a, 986 struct hal_rx_mon_ppdu_info *ppdu_info) 987 { 988 u32 info0, info1, value; 989 u32 dcm; 990 u8 he_dcm = 0, he_stbc = 0; 991 u16 he_gi = 0, he_ltf = 0; 992 993 ppdu_info->he_flags = 1; 994 995 info0 = __le32_to_cpu(he_sig_a->info0); 996 info1 = __le32_to_cpu(he_sig_a->info1); 997 998 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND); 999 if (value == 0) 1000 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE; 1001 else 1002 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE; 1003 1004 ppdu_info->he_data1 |= 1005 HE_BSS_COLOR_KNOWN | 1006 HE_BEAM_CHANGE_KNOWN | 1007 HE_DL_UL_KNOWN | 1008 HE_MCS_KNOWN | 1009 HE_DCM_KNOWN | 1010 HE_CODING_KNOWN | 1011 HE_LDPC_EXTRA_SYMBOL_KNOWN | 1012 HE_STBC_KNOWN | 1013 HE_DATA_BW_RU_KNOWN | 1014 HE_DOPPLER_KNOWN; 1015 1016 ppdu_info->he_data2 |= 1017 HE_GI_KNOWN | 1018 HE_TXBF_KNOWN | 1019 HE_PE_DISAMBIGUITY_KNOWN | 1020 HE_TXOP_KNOWN | 1021 HE_LTF_SYMBOLS_KNOWN | 1022 HE_PRE_FEC_PADDING_KNOWN | 1023 HE_MIDABLE_PERIODICITY_KNOWN; 1024 1025 ppdu_info->he_data3 = u32_get_bits(info0, 1026 HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR); 1027 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE); 1028 value = value << HE_BEAM_CHANGE_SHIFT; 1029 ppdu_info->he_data3 |= value; 1030 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG); 1031 value = value << HE_DL_UL_SHIFT; 1032 ppdu_info->he_data3 |= value; 1033 1034 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS); 1035 ppdu_info->mcs = value; 1036 value = value << HE_TRANSMIT_MCS_SHIFT; 1037 ppdu_info->he_data3 |= value; 1038 1039 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM); 1040 he_dcm = value; 1041 value = value << HE_DCM_SHIFT; 1042 ppdu_info->he_data3 |= value; 1043 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING); 1044 value = value << HE_CODING_SHIFT; 1045 ppdu_info->he_data3 |= value; 1046 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA); 1047 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT; 1048 ppdu_info->he_data3 |= value; 1049 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC); 1050 he_stbc = value; 1051 value = value << HE_STBC_SHIFT; 1052 ppdu_info->he_data3 |= value; 1053 1054 /* data4 */ 1055 ppdu_info->he_data4 = u32_get_bits(info0, 1056 HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE); 1057 1058 /* data5 */ 1059 value = u32_get_bits(info0, 1060 HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW); 1061 ppdu_info->he_data5 = value; 1062 ppdu_info->bw = value; 1063 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE); 1064 switch (value) { 1065 case 0: 1066 he_gi = HE_GI_0_8; 1067 he_ltf = HE_LTF_1_X; 1068 break; 1069 case 1: 1070 he_gi = HE_GI_0_8; 1071 he_ltf = HE_LTF_2_X; 1072 break; 1073 case 2: 1074 he_gi = HE_GI_1_6; 1075 he_ltf = HE_LTF_2_X; 1076 break; 1077 case 3: 1078 if (he_dcm && he_stbc) { 1079 he_gi = HE_GI_0_8; 1080 he_ltf = HE_LTF_4_X; 1081 } else { 1082 he_gi = HE_GI_3_2; 1083 he_ltf = HE_LTF_4_X; 1084 } 1085 break; 1086 } 1087 ppdu_info->gi = he_gi; 1088 value = he_gi << HE_GI_SHIFT; 1089 ppdu_info->he_data5 |= value; 1090 value = he_ltf << HE_LTF_SIZE_SHIFT; 1091 ppdu_info->ltf_size = he_ltf; 1092 ppdu_info->he_data5 |= value; 1093 1094 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 1095 value = (value << HE_LTF_SYM_SHIFT); 1096 ppdu_info->he_data5 |= value; 1097 1098 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR); 1099 value = value << HE_PRE_FEC_PAD_SHIFT; 1100 ppdu_info->he_data5 |= value; 1101 1102 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF); 1103 value = value << HE_TXBF_SHIFT; 1104 ppdu_info->he_data5 |= value; 1105 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM); 1106 value = value << HE_PE_DISAMBIGUITY_SHIFT; 1107 ppdu_info->he_data5 |= value; 1108 1109 /* data6 */ 1110 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 1111 value++; 1112 ppdu_info->he_data6 = value; 1113 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND); 1114 value = value << HE_DOPPLER_SHIFT; 1115 ppdu_info->he_data6 |= value; 1116 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION); 1117 value = value << HE_TXOP_SHIFT; 1118 ppdu_info->he_data6 |= value; 1119 1120 ppdu_info->mcs = 1121 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS); 1122 ppdu_info->bw = 1123 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW); 1124 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING); 1125 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC); 1126 ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF); 1127 dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM); 1128 ppdu_info->nss = u32_get_bits(info0, 1129 HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS) + 1; 1130 ppdu_info->dcm = dcm; 1131 } 1132 1133 static inline bool 1134 ath12k_wifi7_dp_mon_hal_rx_is_non_ofdma(const struct hal_rx_u_sig_info *usig_info) 1135 { 1136 u32 ppdu_type_comp_mode = usig_info->ppdu_type_comp_mode; 1137 u32 ul_dl = usig_info->ul_dl; 1138 1139 if ((ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_MIMO && ul_dl == 0) || 1140 (ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_OFDMA && ul_dl == 0) || 1141 (ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_MIMO && ul_dl == 1)) 1142 return true; 1143 1144 return false; 1145 } 1146 1147 static inline bool 1148 ath12k_wifi7_dp_mon_hal_rx_is_ofdma(const struct hal_rx_u_sig_info *usig_info) 1149 { 1150 if (usig_info->ppdu_type_comp_mode == 0 && usig_info->ul_dl == 0) 1151 return true; 1152 1153 return false; 1154 } 1155 1156 static inline bool 1157 ath12k_wifi7_dp_mon_hal_rx_is_frame_type_ndp(const struct hal_rx_u_sig_info *usig_info) 1158 { 1159 if (usig_info->ppdu_type_comp_mode == 1 && 1160 usig_info->eht_sig_mcs == 0 && 1161 usig_info->num_eht_sig_sym == 0) 1162 return true; 1163 1164 return false; 1165 } 1166 1167 static void 1168 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ndp(const struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp, 1169 struct hal_rx_mon_ppdu_info *ppdu_info) 1170 { 1171 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht; 1172 u32 known, data; 1173 1174 known = __le32_to_cpu(eht->known); 1175 known |= IEEE80211_RADIOTAP_EHT_KNOWN_SPATIAL_REUSE | 1176 IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF | 1177 IEEE80211_RADIOTAP_EHT_KNOWN_NSS_S | 1178 IEEE80211_RADIOTAP_EHT_KNOWN_BEAMFORMED_S | 1179 IEEE80211_RADIOTAP_EHT_KNOWN_DISREGARD_S | 1180 IEEE80211_RADIOTAP_EHT_KNOWN_CRC1 | 1181 IEEE80211_RADIOTAP_EHT_KNOWN_TAIL1; 1182 eht->known = cpu_to_le32(known); 1183 1184 data = __le32_to_cpu(eht->data[0]); 1185 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, 1186 HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE, 1187 IEEE80211_RADIOTAP_EHT_DATA0_SPATIAL_REUSE); 1188 /* GI and LTF size are separately indicated in radiotap header 1189 * and hence will be parsed from other TLV 1190 */ 1191 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, 1192 HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM, 1193 IEEE80211_RADIOTAP_EHT_DATA0_EHT_LTF); 1194 1195 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, 1196 HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC, 1197 IEEE80211_RADIOTAP_EHT_DATA0_CRC1_O); 1198 1199 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, 1200 HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD, 1201 IEEE80211_RADIOTAP_EHT_DATA0_DISREGARD_S); 1202 eht->data[0] = cpu_to_le32(data); 1203 1204 data = __le32_to_cpu(eht->data[7]); 1205 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, 1206 HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS, 1207 IEEE80211_RADIOTAP_EHT_DATA7_NSS_S); 1208 1209 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, 1210 HAL_RX_EHT_SIG_NDP_CMN_INFO0_BEAMFORMED, 1211 IEEE80211_RADIOTAP_EHT_DATA7_BEAMFORMED_S); 1212 eht->data[7] = cpu_to_le32(data); 1213 } 1214 1215 static void 1216 ath12k_wifi7_dp_mon_hal_rx_parse_usig_overflow(const struct hal_eht_sig_usig_overflow *ovflow, 1217 struct hal_rx_mon_ppdu_info *ppdu_info) 1218 { 1219 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht; 1220 u32 known, data; 1221 1222 known = __le32_to_cpu(eht->known); 1223 known |= IEEE80211_RADIOTAP_EHT_KNOWN_SPATIAL_REUSE | 1224 IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF | 1225 IEEE80211_RADIOTAP_EHT_KNOWN_LDPC_EXTRA_SYM_OM | 1226 IEEE80211_RADIOTAP_EHT_KNOWN_PRE_PADD_FACOR_OM | 1227 IEEE80211_RADIOTAP_EHT_KNOWN_PE_DISAMBIGUITY_OM | 1228 IEEE80211_RADIOTAP_EHT_KNOWN_DISREGARD_O; 1229 eht->known = cpu_to_le32(known); 1230 1231 data = __le32_to_cpu(eht->data[0]); 1232 data |= ATH12K_LE32_DEC_ENC(ovflow->info0, 1233 HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE, 1234 IEEE80211_RADIOTAP_EHT_DATA0_SPATIAL_REUSE); 1235 1236 /* GI and LTF size are separately indicated in radiotap header 1237 * and hence will be parsed from other TLV 1238 */ 1239 data |= ATH12K_LE32_DEC_ENC(ovflow->info0, 1240 HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM, 1241 IEEE80211_RADIOTAP_EHT_DATA0_EHT_LTF); 1242 1243 data |= ATH12K_LE32_DEC_ENC(ovflow->info0, 1244 HAL_RX_EHT_SIG_OVERFLOW_INFO0_LDPC_EXTA_SYM, 1245 IEEE80211_RADIOTAP_EHT_DATA0_LDPC_EXTRA_SYM_OM); 1246 1247 data |= ATH12K_LE32_DEC_ENC(ovflow->info0, 1248 HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR, 1249 IEEE80211_RADIOTAP_EHT_DATA0_PRE_PADD_FACOR_OM); 1250 1251 data |= ATH12K_LE32_DEC_ENC(ovflow->info0, 1252 HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISAMBIGUITY, 1253 IEEE80211_RADIOTAP_EHT_DATA0_PE_DISAMBIGUITY_OM); 1254 1255 data |= ATH12K_LE32_DEC_ENC(ovflow->info0, 1256 HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD, 1257 IEEE80211_RADIOTAP_EHT_DATA0_DISREGARD_O); 1258 eht->data[0] = cpu_to_le32(data); 1259 } 1260 1261 static void 1262 ath12k_wifi7_dp_mon_hal_rx_parse_non_ofdma_users(const struct hal_eht_sig_non_ofdma_cmn_eb *eb, 1263 struct hal_rx_mon_ppdu_info *ppdu_info) 1264 { 1265 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht; 1266 u32 known, data; 1267 1268 known = __le32_to_cpu(eht->known); 1269 known |= IEEE80211_RADIOTAP_EHT_KNOWN_NR_NON_OFDMA_USERS_M; 1270 eht->known = cpu_to_le32(known); 1271 1272 data = __le32_to_cpu(eht->data[7]); 1273 data |= ATH12K_LE32_DEC_ENC(eb->info0, 1274 HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS, 1275 IEEE80211_RADIOTAP_EHT_DATA7_NUM_OF_NON_OFDMA_USERS); 1276 eht->data[7] = cpu_to_le32(data); 1277 } 1278 1279 static void 1280 ath12k_wifi7_dp_mon_hal_rx_parse_eht_mumimo_user(const struct hal_eht_sig_mu_mimo *user, 1281 struct hal_rx_mon_ppdu_info *ppdu_info) 1282 { 1283 struct hal_rx_eht_info *eht_info = &ppdu_info->eht_info; 1284 u32 user_idx; 1285 1286 if (eht_info->num_user_info >= ARRAY_SIZE(eht_info->user_info)) 1287 return; 1288 1289 user_idx = eht_info->num_user_info++; 1290 1291 eht_info->user_info[user_idx] |= 1292 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID_KNOWN | 1293 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 1294 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN | 1295 IEEE80211_RADIOTAP_EHT_USER_INFO_SPATIAL_CONFIG_KNOWN_M | 1296 ATH12K_LE32_DEC_ENC(user->info0, 1297 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID, 1298 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID) | 1299 ATH12K_LE32_DEC_ENC(user->info0, 1300 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CODING, 1301 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING) | 1302 ATH12K_LE32_DEC_ENC(user->info0, 1303 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS, 1304 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 1305 ATH12K_LE32_DEC_ENC(user->info0, 1306 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING, 1307 IEEE80211_RADIOTAP_EHT_USER_INFO_SPATIAL_CONFIG_M); 1308 1309 ppdu_info->mcs = le32_get_bits(user->info0, 1310 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS); 1311 } 1312 1313 static void 1314 ath12k_wifi7_dp_mon_hal_rx_parse_eht_non_mumimo_user(const struct hal_eht_sig_non_mu_mimo *user, 1315 struct hal_rx_mon_ppdu_info *ppdu_info) 1316 { 1317 struct hal_rx_eht_info *eht_info = &ppdu_info->eht_info; 1318 u32 user_idx; 1319 1320 if (eht_info->num_user_info >= ARRAY_SIZE(eht_info->user_info)) 1321 return; 1322 1323 user_idx = eht_info->num_user_info++; 1324 1325 eht_info->user_info[user_idx] |= 1326 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID_KNOWN | 1327 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 1328 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN | 1329 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 1330 IEEE80211_RADIOTAP_EHT_USER_INFO_BEAMFORMING_KNOWN_O | 1331 ATH12K_LE32_DEC_ENC(user->info0, 1332 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID, 1333 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID) | 1334 ATH12K_LE32_DEC_ENC(user->info0, 1335 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CODING, 1336 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING) | 1337 ATH12K_LE32_DEC_ENC(user->info0, 1338 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS, 1339 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 1340 ATH12K_LE32_DEC_ENC(user->info0, 1341 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS, 1342 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O) | 1343 ATH12K_LE32_DEC_ENC(user->info0, 1344 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_BEAMFORMED, 1345 IEEE80211_RADIOTAP_EHT_USER_INFO_BEAMFORMING_O); 1346 1347 ppdu_info->mcs = le32_get_bits(user->info0, 1348 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS); 1349 1350 ppdu_info->nss = le32_get_bits(user->info0, 1351 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS) + 1; 1352 } 1353 1354 static inline bool 1355 ath12k_wifi7_dp_mon_hal_rx_is_mu_mimo_user(const struct hal_rx_u_sig_info *usig_info) 1356 { 1357 if (usig_info->ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_SU && 1358 usig_info->ul_dl == 1) 1359 return true; 1360 1361 return false; 1362 } 1363 1364 static void 1365 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_non_ofdma(const void *tlv, 1366 struct hal_rx_mon_ppdu_info *ppdu_info) 1367 { 1368 const struct hal_eht_sig_non_ofdma_cmn_eb *eb = tlv; 1369 1370 ath12k_wifi7_dp_mon_hal_rx_parse_usig_overflow(tlv, ppdu_info); 1371 ath12k_wifi7_dp_mon_hal_rx_parse_non_ofdma_users(eb, ppdu_info); 1372 1373 if (ath12k_wifi7_dp_mon_hal_rx_is_mu_mimo_user(&ppdu_info->u_sig_info)) 1374 ath12k_wifi7_dp_mon_hal_rx_parse_eht_mumimo_user(&eb->user_field.mu_mimo, 1375 ppdu_info); 1376 else 1377 ath12k_wifi7_dp_mon_hal_rx_parse_eht_non_mumimo_user(&eb->user_field.n_mu_mimo, 1378 ppdu_info); 1379 } 1380 1381 static void 1382 ath12k_wifi7_dp_mon_hal_rx_parse_ru_allocation(const struct hal_eht_sig_ofdma_cmn_eb *eb, 1383 struct hal_rx_mon_ppdu_info *ppdu_info) 1384 { 1385 const struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1 = &eb->eb1; 1386 const struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2 = &eb->eb2; 1387 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht; 1388 enum ieee80211_radiotap_eht_data ru_123, ru_124, ru_125, ru_126; 1389 enum ieee80211_radiotap_eht_data ru_121, ru_122, ru_112, ru_111; 1390 u32 data; 1391 1392 ru_123 = IEEE80211_RADIOTAP_EHT_DATA4_RU_ALLOC_CC_1_2_3; 1393 ru_124 = IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_4; 1394 ru_125 = IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_5; 1395 ru_126 = IEEE80211_RADIOTAP_EHT_DATA6_RU_ALLOC_CC_1_2_6; 1396 ru_121 = IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_1; 1397 ru_122 = IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_2; 1398 ru_112 = IEEE80211_RADIOTAP_EHT_DATA2_RU_ALLOC_CC_1_1_2; 1399 ru_111 = IEEE80211_RADIOTAP_EHT_DATA1_RU_ALLOC_CC_1_1_1; 1400 1401 switch (ppdu_info->u_sig_info.bw) { 1402 case HAL_EHT_BW_320_2: 1403 case HAL_EHT_BW_320_1: 1404 data = __le32_to_cpu(eht->data[4]); 1405 /* CC1 2::3 */ 1406 data |= IEEE80211_RADIOTAP_EHT_DATA4_RU_ALLOC_CC_1_2_3_KNOWN | 1407 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, 1408 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3, 1409 ru_123); 1410 eht->data[4] = cpu_to_le32(data); 1411 1412 data = __le32_to_cpu(eht->data[5]); 1413 /* CC1 2::4 */ 1414 data |= IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_4_KNOWN | 1415 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, 1416 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4, 1417 ru_124); 1418 1419 /* CC1 2::5 */ 1420 data |= IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_5_KNOWN | 1421 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, 1422 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5, 1423 ru_125); 1424 eht->data[5] = cpu_to_le32(data); 1425 1426 data = __le32_to_cpu(eht->data[6]); 1427 /* CC1 2::6 */ 1428 data |= IEEE80211_RADIOTAP_EHT_DATA6_RU_ALLOC_CC_1_2_6_KNOWN | 1429 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, 1430 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6, 1431 ru_126); 1432 eht->data[6] = cpu_to_le32(data); 1433 1434 fallthrough; 1435 case HAL_EHT_BW_160: 1436 data = __le32_to_cpu(eht->data[3]); 1437 /* CC1 2::1 */ 1438 data |= IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_1_KNOWN | 1439 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, 1440 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1, 1441 ru_121); 1442 /* CC1 2::2 */ 1443 data |= IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_2_KNOWN | 1444 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, 1445 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2, 1446 ru_122); 1447 eht->data[3] = cpu_to_le32(data); 1448 1449 fallthrough; 1450 case HAL_EHT_BW_80: 1451 data = __le32_to_cpu(eht->data[2]); 1452 /* CC1 1::2 */ 1453 data |= IEEE80211_RADIOTAP_EHT_DATA2_RU_ALLOC_CC_1_1_2_KNOWN | 1454 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb1->info0, 1455 HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2, 1456 ru_112); 1457 eht->data[2] = cpu_to_le32(data); 1458 1459 fallthrough; 1460 case HAL_EHT_BW_40: 1461 fallthrough; 1462 case HAL_EHT_BW_20: 1463 data = __le32_to_cpu(eht->data[1]); 1464 /* CC1 1::1 */ 1465 data |= IEEE80211_RADIOTAP_EHT_DATA1_RU_ALLOC_CC_1_1_1_KNOWN | 1466 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb1->info0, 1467 HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1, 1468 ru_111); 1469 eht->data[1] = cpu_to_le32(data); 1470 break; 1471 default: 1472 break; 1473 } 1474 } 1475 1476 static void 1477 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ofdma(const void *tlv, 1478 struct hal_rx_mon_ppdu_info *ppdu_info) 1479 { 1480 const struct hal_eht_sig_ofdma_cmn_eb *ofdma = tlv; 1481 1482 ath12k_wifi7_dp_mon_hal_rx_parse_usig_overflow(tlv, ppdu_info); 1483 ath12k_wifi7_dp_mon_hal_rx_parse_ru_allocation(ofdma, ppdu_info); 1484 1485 ath12k_wifi7_dp_mon_hal_rx_parse_eht_non_mumimo_user(&ofdma->user_field.n_mu_mimo, 1486 ppdu_info); 1487 } 1488 1489 static void 1490 ath12k_wifi7_dp_mon_parse_eht_sig_hdr(struct hal_rx_mon_ppdu_info *ppdu_info, 1491 const void *tlv_data) 1492 { 1493 ppdu_info->is_eht = true; 1494 1495 if (ath12k_wifi7_dp_mon_hal_rx_is_frame_type_ndp(&ppdu_info->u_sig_info)) 1496 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ndp(tlv_data, ppdu_info); 1497 else if (ath12k_wifi7_dp_mon_hal_rx_is_non_ofdma(&ppdu_info->u_sig_info)) 1498 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_non_ofdma(tlv_data, ppdu_info); 1499 else if (ath12k_wifi7_dp_mon_hal_rx_is_ofdma(&ppdu_info->u_sig_info)) 1500 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ofdma(tlv_data, ppdu_info); 1501 } 1502 1503 static void ath12k_wifi7_dp_mon_parse_rx_msdu_end_err(u32 info, u32 *errmap) 1504 { 1505 if (info & RX_MSDU_END_INFO13_FCS_ERR) 1506 *errmap |= HAL_RX_MPDU_ERR_FCS; 1507 1508 if (info & RX_MSDU_END_INFO13_DECRYPT_ERR) 1509 *errmap |= HAL_RX_MPDU_ERR_DECRYPT; 1510 1511 if (info & RX_MSDU_END_INFO13_TKIP_MIC_ERR) 1512 *errmap |= HAL_RX_MPDU_ERR_TKIP_MIC; 1513 1514 if (info & RX_MSDU_END_INFO13_A_MSDU_ERROR) 1515 *errmap |= HAL_RX_MPDU_ERR_AMSDU_ERR; 1516 1517 if (info & RX_MSDU_END_INFO13_OVERFLOW_ERR) 1518 *errmap |= HAL_RX_MPDU_ERR_OVERFLOW; 1519 1520 if (info & RX_MSDU_END_INFO13_MSDU_LEN_ERR) 1521 *errmap |= HAL_RX_MPDU_ERR_MSDU_LEN; 1522 1523 if (info & RX_MSDU_END_INFO13_MPDU_LEN_ERR) 1524 *errmap |= HAL_RX_MPDU_ERR_MPDU_LEN; 1525 } 1526 1527 static void 1528 ath12k_wifi7_parse_cmn_usr_info(const struct hal_phyrx_common_user_info *cmn_usr_info, 1529 struct hal_rx_mon_ppdu_info *ppdu_info) 1530 { 1531 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht; 1532 u32 known, data, cp_setting, ltf_size; 1533 1534 known = __le32_to_cpu(eht->known); 1535 known |= IEEE80211_RADIOTAP_EHT_KNOWN_GI | 1536 IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF; 1537 eht->known = cpu_to_le32(known); 1538 1539 cp_setting = le32_get_bits(cmn_usr_info->info0, 1540 HAL_RX_CMN_USR_INFO0_CP_SETTING); 1541 ltf_size = le32_get_bits(cmn_usr_info->info0, 1542 HAL_RX_CMN_USR_INFO0_LTF_SIZE); 1543 1544 data = __le32_to_cpu(eht->data[0]); 1545 data |= u32_encode_bits(cp_setting, IEEE80211_RADIOTAP_EHT_DATA0_GI); 1546 data |= u32_encode_bits(ltf_size, IEEE80211_RADIOTAP_EHT_DATA0_LTF); 1547 eht->data[0] = cpu_to_le32(data); 1548 1549 if (!ppdu_info->ltf_size) 1550 ppdu_info->ltf_size = ltf_size; 1551 if (!ppdu_info->gi) 1552 ppdu_info->gi = cp_setting; 1553 } 1554 1555 static void 1556 ath12k_wifi7_dp_mon_parse_status_msdu_end(struct ath12k_mon_data *pmon, 1557 const struct hal_rx_msdu_end *msdu_end) 1558 { 1559 ath12k_wifi7_dp_mon_parse_rx_msdu_end_err(__le32_to_cpu(msdu_end->info2), 1560 &pmon->err_bitmap); 1561 pmon->decap_format = le32_get_bits(msdu_end->info1, 1562 RX_MSDU_END_INFO11_DECAP_FORMAT); 1563 } 1564 1565 static enum hal_rx_mon_status 1566 ath12k_wifi7_dp_mon_rx_parse_status_tlv(struct ath12k_pdev_dp *dp_pdev, 1567 struct ath12k_mon_data *pmon, 1568 const struct hal_tlv_64_hdr *tlv) 1569 { 1570 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 1571 const void *tlv_data = tlv->value; 1572 u32 info[7], userid; 1573 u16 tlv_tag, tlv_len; 1574 1575 tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG); 1576 tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN); 1577 userid = le64_get_bits(tlv->tl, HAL_TLV_64_USR_ID); 1578 1579 if (ppdu_info->tlv_aggr.in_progress && ppdu_info->tlv_aggr.tlv_tag != tlv_tag) { 1580 ath12k_wifi7_dp_mon_parse_eht_sig_hdr(ppdu_info, 1581 ppdu_info->tlv_aggr.buf); 1582 1583 ppdu_info->tlv_aggr.in_progress = false; 1584 ppdu_info->tlv_aggr.cur_len = 0; 1585 } 1586 1587 switch (tlv_tag) { 1588 case HAL_RX_PPDU_START: { 1589 const struct hal_rx_ppdu_start *ppdu_start = tlv_data; 1590 1591 u64 ppdu_ts = ath12k_le32hilo_to_u64(ppdu_start->ppdu_start_ts_63_32, 1592 ppdu_start->ppdu_start_ts_31_0); 1593 1594 info[0] = __le32_to_cpu(ppdu_start->info0); 1595 1596 ppdu_info->ppdu_id = u32_get_bits(info[0], 1597 HAL_RX_PPDU_START_INFO0_PPDU_ID); 1598 1599 info[1] = __le32_to_cpu(ppdu_start->info1); 1600 ppdu_info->chan_num = u32_get_bits(info[1], 1601 HAL_RX_PPDU_START_INFO1_CHAN_NUM); 1602 ppdu_info->freq = u32_get_bits(info[1], 1603 HAL_RX_PPDU_START_INFO1_CHAN_FREQ); 1604 ppdu_info->ppdu_ts = ppdu_ts; 1605 1606 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) { 1607 ppdu_info->last_ppdu_id = ppdu_info->ppdu_id; 1608 ppdu_info->num_users = 0; 1609 memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0, 1610 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 1611 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0])); 1612 } 1613 break; 1614 } 1615 case HAL_RX_PPDU_END_USER_STATS: { 1616 const struct hal_rx_ppdu_end_user_stats *eu_stats = tlv_data; 1617 u32 tid_bitmap; 1618 1619 info[0] = __le32_to_cpu(eu_stats->info0); 1620 info[1] = __le32_to_cpu(eu_stats->info1); 1621 info[2] = __le32_to_cpu(eu_stats->info2); 1622 info[4] = __le32_to_cpu(eu_stats->info4); 1623 info[5] = __le32_to_cpu(eu_stats->info5); 1624 info[6] = __le32_to_cpu(eu_stats->info6); 1625 1626 ppdu_info->ast_index = 1627 u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX); 1628 ppdu_info->fc_valid = 1629 u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID); 1630 tid_bitmap = u32_get_bits(info[6], 1631 HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP); 1632 ppdu_info->tid = ffs(tid_bitmap) - 1; 1633 ppdu_info->tcp_msdu_count = 1634 u32_get_bits(info[4], 1635 HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT); 1636 ppdu_info->udp_msdu_count = 1637 u32_get_bits(info[4], 1638 HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT); 1639 ppdu_info->other_msdu_count = 1640 u32_get_bits(info[5], 1641 HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT); 1642 ppdu_info->tcp_ack_msdu_count = 1643 u32_get_bits(info[5], 1644 HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT); 1645 ppdu_info->preamble_type = 1646 u32_get_bits(info[1], 1647 HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE); 1648 ppdu_info->num_mpdu_fcs_ok = 1649 u32_get_bits(info[1], 1650 HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK); 1651 ppdu_info->num_mpdu_fcs_err = 1652 u32_get_bits(info[0], 1653 HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR); 1654 ppdu_info->peer_id = 1655 u32_get_bits(info[0], HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID); 1656 1657 switch (ppdu_info->preamble_type) { 1658 case HAL_RX_PREAMBLE_11N: 1659 ppdu_info->ht_flags = 1; 1660 break; 1661 case HAL_RX_PREAMBLE_11AC: 1662 ppdu_info->vht_flags = 1; 1663 break; 1664 case HAL_RX_PREAMBLE_11AX: 1665 ppdu_info->he_flags = 1; 1666 break; 1667 case HAL_RX_PREAMBLE_11BE: 1668 ppdu_info->is_eht = true; 1669 break; 1670 default: 1671 break; 1672 } 1673 1674 if (userid < HAL_MAX_UL_MU_USERS) { 1675 struct hal_rx_user_status *rxuser_stats = 1676 &ppdu_info->userstats[userid]; 1677 1678 if (ppdu_info->num_mpdu_fcs_ok > 1 || 1679 ppdu_info->num_mpdu_fcs_err > 1) 1680 ppdu_info->userstats[userid].ampdu_present = true; 1681 1682 ppdu_info->num_users += 1; 1683 1684 ath12k_wifi7_dp_mon_rx_handle_ofdma_info(eu_stats, rxuser_stats); 1685 ath12k_wifi7_dp_mon_rx_populate_mu_user_info(eu_stats, ppdu_info, 1686 rxuser_stats); 1687 } 1688 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]); 1689 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]); 1690 break; 1691 } 1692 case HAL_RX_PPDU_END_USER_STATS_EXT: { 1693 const struct hal_rx_ppdu_end_user_stats_ext *eu_stats = tlv_data; 1694 1695 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1); 1696 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2); 1697 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3); 1698 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4); 1699 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5); 1700 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6); 1701 break; 1702 } 1703 case HAL_PHYRX_HT_SIG: 1704 ath12k_wifi7_dp_mon_parse_ht_sig(tlv_data, ppdu_info); 1705 break; 1706 1707 case HAL_PHYRX_L_SIG_B: 1708 ath12k_wifi7_dp_mon_parse_l_sig_b(tlv_data, ppdu_info); 1709 break; 1710 1711 case HAL_PHYRX_L_SIG_A: 1712 ath12k_wifi7_dp_mon_parse_l_sig_a(tlv_data, ppdu_info); 1713 break; 1714 1715 case HAL_PHYRX_VHT_SIG_A: 1716 ath12k_wifi7_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info); 1717 break; 1718 1719 case HAL_PHYRX_HE_SIG_A_SU: 1720 ath12k_wifi7_dp_mon_parse_he_sig_su(tlv_data, ppdu_info); 1721 break; 1722 1723 case HAL_PHYRX_HE_SIG_A_MU_DL: 1724 ath12k_wifi7_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info); 1725 break; 1726 1727 case HAL_PHYRX_HE_SIG_B1_MU: 1728 ath12k_wifi7_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info); 1729 break; 1730 1731 case HAL_PHYRX_HE_SIG_B2_MU: 1732 ath12k_wifi7_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info); 1733 break; 1734 1735 case HAL_PHYRX_HE_SIG_B2_OFDMA: 1736 ath12k_wifi7_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info); 1737 break; 1738 1739 case HAL_PHYRX_RSSI_LEGACY: { 1740 const struct hal_rx_phyrx_rssi_legacy_info *rssi = tlv_data; 1741 1742 info[0] = __le32_to_cpu(rssi->info0); 1743 info[2] = __le32_to_cpu(rssi->info2); 1744 1745 /* TODO: Please note that the combined rssi will not be accurate 1746 * in MU case. Rssi in MU needs to be retrieved from 1747 * PHYRX_OTHER_RECEIVE_INFO TLV. 1748 */ 1749 ppdu_info->rssi_comb = 1750 u32_get_bits(info[2], 1751 HAL_RX_RSSI_LEGACY_INFO_INFO2_RSSI_COMB_PPDU); 1752 1753 ppdu_info->bw = u32_get_bits(info[0], 1754 HAL_RX_RSSI_LEGACY_INFO_INFO0_RX_BW); 1755 break; 1756 } 1757 case HAL_PHYRX_COMMON_USER_INFO: { 1758 ath12k_wifi7_parse_cmn_usr_info(tlv_data, ppdu_info); 1759 break; 1760 } 1761 case HAL_RX_PPDU_START_USER_INFO: 1762 ath12k_wifi7_dp_mon_hal_rx_parse_user_info(tlv_data, userid, ppdu_info); 1763 break; 1764 1765 case HAL_RXPCU_PPDU_END_INFO: { 1766 const struct hal_rx_ppdu_end_duration *ppdu_rx_duration = tlv_data; 1767 1768 info[0] = __le32_to_cpu(ppdu_rx_duration->info0); 1769 ppdu_info->rx_duration = 1770 u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION); 1771 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]); 1772 ppdu_info->tsft = (ppdu_info->tsft << 32) | 1773 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]); 1774 break; 1775 } 1776 case HAL_RX_MPDU_START: { 1777 const struct hal_rx_mpdu_start *mpdu_start = tlv_data; 1778 u16 peer_id; 1779 1780 info[1] = __le32_to_cpu(mpdu_start->info1); 1781 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID); 1782 if (peer_id) 1783 ppdu_info->peer_id = peer_id; 1784 1785 ppdu_info->mpdu_len += u32_get_bits(info[1], 1786 HAL_RX_MPDU_START_INFO2_MPDU_LEN); 1787 if (userid < HAL_MAX_UL_MU_USERS) { 1788 info[0] = __le32_to_cpu(mpdu_start->info0); 1789 ppdu_info->userid = userid; 1790 ppdu_info->userstats[userid].ampdu_id = 1791 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO0_PPDU_ID); 1792 } 1793 1794 return HAL_RX_MON_STATUS_MPDU_START; 1795 } 1796 case HAL_RX_MSDU_START: 1797 /* TODO: add msdu start parsing logic */ 1798 break; 1799 case HAL_MON_BUF_ADDR: 1800 return HAL_RX_MON_STATUS_BUF_ADDR; 1801 case HAL_RX_MSDU_END: 1802 ath12k_wifi7_dp_mon_parse_status_msdu_end(pmon, tlv_data); 1803 return HAL_RX_MON_STATUS_MSDU_END; 1804 case HAL_RX_MPDU_END: 1805 return HAL_RX_MON_STATUS_MPDU_END; 1806 case HAL_PHYRX_GENERIC_U_SIG: 1807 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_hdr(tlv_data, ppdu_info); 1808 break; 1809 case HAL_PHYRX_GENERIC_EHT_SIG: 1810 /* Handle the case where aggregation is in progress 1811 * or the current TLV is one of the TLVs which should be 1812 * aggregated 1813 */ 1814 if (!ppdu_info->tlv_aggr.in_progress) { 1815 ppdu_info->tlv_aggr.in_progress = true; 1816 ppdu_info->tlv_aggr.tlv_tag = tlv_tag; 1817 ppdu_info->tlv_aggr.cur_len = 0; 1818 } 1819 1820 ppdu_info->is_eht = true; 1821 1822 ath12k_wifi7_dp_mon_hal_aggr_tlv(ppdu_info, tlv_len, tlv_data); 1823 break; 1824 case HAL_DUMMY: 1825 return HAL_RX_MON_STATUS_BUF_DONE; 1826 case HAL_RX_PPDU_END_STATUS_DONE: 1827 case 0: 1828 return HAL_RX_MON_STATUS_PPDU_DONE; 1829 default: 1830 break; 1831 } 1832 1833 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 1834 } 1835 1836 static int 1837 ath12k_wifi7_dp_mon_parse_rx_dest_tlv(struct ath12k_pdev_dp *dp_pdev, 1838 struct ath12k_mon_data *pmon, 1839 enum hal_rx_mon_status hal_status, 1840 const void *tlv_data) 1841 { 1842 switch (hal_status) { 1843 case HAL_RX_MON_STATUS_MPDU_START: 1844 if (WARN_ON_ONCE(pmon->mon_mpdu)) 1845 break; 1846 1847 pmon->mon_mpdu = kzalloc_obj(*pmon->mon_mpdu, GFP_ATOMIC); 1848 if (!pmon->mon_mpdu) 1849 return -ENOMEM; 1850 break; 1851 case HAL_RX_MON_STATUS_BUF_ADDR: 1852 return ath12k_dp_mon_parse_status_buf(dp_pdev, pmon, tlv_data); 1853 case HAL_RX_MON_STATUS_MPDU_END: 1854 /* If no MSDU then free empty MPDU */ 1855 if (pmon->mon_mpdu->tail) { 1856 pmon->mon_mpdu->tail->next = NULL; 1857 list_add_tail(&pmon->mon_mpdu->list, &pmon->dp_rx_mon_mpdu_list); 1858 } else { 1859 kfree(pmon->mon_mpdu); 1860 } 1861 pmon->mon_mpdu = NULL; 1862 break; 1863 case HAL_RX_MON_STATUS_MSDU_END: 1864 pmon->mon_mpdu->decap_format = pmon->decap_format; 1865 pmon->mon_mpdu->err_bitmap = pmon->err_bitmap; 1866 break; 1867 default: 1868 break; 1869 } 1870 1871 return 0; 1872 } 1873 1874 static struct dp_mon_tx_ppdu_info * 1875 ath12k_wifi7_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon, 1876 unsigned int ppdu_id, 1877 enum dp_mon_tx_ppdu_info_type type) 1878 { 1879 struct dp_mon_tx_ppdu_info *tx_ppdu_info; 1880 1881 if (type == DP_MON_TX_PROT_PPDU_INFO) { 1882 tx_ppdu_info = pmon->tx_prot_ppdu_info; 1883 1884 if (tx_ppdu_info && !tx_ppdu_info->is_used) 1885 return tx_ppdu_info; 1886 kfree(tx_ppdu_info); 1887 } else { 1888 tx_ppdu_info = pmon->tx_data_ppdu_info; 1889 1890 if (tx_ppdu_info && !tx_ppdu_info->is_used) 1891 return tx_ppdu_info; 1892 kfree(tx_ppdu_info); 1893 } 1894 1895 /* allocate new tx_ppdu_info */ 1896 tx_ppdu_info = kzalloc_obj(*tx_ppdu_info, GFP_ATOMIC); 1897 if (!tx_ppdu_info) 1898 return NULL; 1899 1900 tx_ppdu_info->is_used = 0; 1901 tx_ppdu_info->ppdu_id = ppdu_id; 1902 1903 if (type == DP_MON_TX_PROT_PPDU_INFO) 1904 pmon->tx_prot_ppdu_info = tx_ppdu_info; 1905 else 1906 pmon->tx_data_ppdu_info = tx_ppdu_info; 1907 1908 return tx_ppdu_info; 1909 } 1910 1911 static struct dp_mon_tx_ppdu_info * 1912 ath12k_wifi7_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon, 1913 u16 tlv_tag) 1914 { 1915 switch (tlv_tag) { 1916 case HAL_TX_FES_SETUP: 1917 case HAL_TX_FLUSH: 1918 case HAL_PCU_PPDU_SETUP_INIT: 1919 case HAL_TX_PEER_ENTRY: 1920 case HAL_TX_QUEUE_EXTENSION: 1921 case HAL_TX_MPDU_START: 1922 case HAL_TX_MSDU_START: 1923 case HAL_TX_DATA: 1924 case HAL_MON_BUF_ADDR: 1925 case HAL_TX_MPDU_END: 1926 case HAL_TX_LAST_MPDU_FETCHED: 1927 case HAL_TX_LAST_MPDU_END: 1928 case HAL_COEX_TX_REQ: 1929 case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP: 1930 case HAL_SCH_CRITICAL_TLV_REFERENCE: 1931 case HAL_TX_FES_SETUP_COMPLETE: 1932 case HAL_TQM_MPDU_GLOBAL_START: 1933 case HAL_SCHEDULER_END: 1934 case HAL_TX_FES_STATUS_USER_PPDU: 1935 break; 1936 case HAL_TX_FES_STATUS_PROT: { 1937 if (!pmon->tx_prot_ppdu_info->is_used) 1938 pmon->tx_prot_ppdu_info->is_used = true; 1939 1940 return pmon->tx_prot_ppdu_info; 1941 } 1942 } 1943 1944 if (!pmon->tx_data_ppdu_info->is_used) 1945 pmon->tx_data_ppdu_info->is_used = true; 1946 1947 return pmon->tx_data_ppdu_info; 1948 } 1949 1950 #define MAX_MONITOR_HEADER 512 1951 #define MAX_DUMMY_FRM_BODY 128 1952 1953 static struct 1954 sk_buff *ath12k_wifi7_dp_mon_tx_alloc_skb(void) 1955 { 1956 struct sk_buff *skb; 1957 1958 skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY); 1959 if (!skb) 1960 return NULL; 1961 1962 skb_reserve(skb, MAX_MONITOR_HEADER); 1963 1964 if (!IS_ALIGNED((unsigned long)skb->data, 4)) 1965 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data); 1966 1967 return skb; 1968 } 1969 1970 static int 1971 ath12k_wifi7_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1972 { 1973 struct sk_buff *skb; 1974 struct ieee80211_cts *cts; 1975 1976 skb = ath12k_wifi7_dp_mon_tx_alloc_skb(); 1977 if (!skb) 1978 return -ENOMEM; 1979 1980 cts = (struct ieee80211_cts *)skb->data; 1981 memset(cts, 0, MAX_DUMMY_FRM_BODY); 1982 cts->frame_control = 1983 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS); 1984 cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1985 memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra)); 1986 1987 skb_put(skb, sizeof(*cts)); 1988 tx_ppdu_info->tx_mon_mpdu->head = skb; 1989 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1990 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1991 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1992 1993 return 0; 1994 } 1995 1996 static int 1997 ath12k_wifi7_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1998 { 1999 struct sk_buff *skb; 2000 struct ieee80211_rts *rts; 2001 2002 skb = ath12k_wifi7_dp_mon_tx_alloc_skb(); 2003 if (!skb) 2004 return -ENOMEM; 2005 2006 rts = (struct ieee80211_rts *)skb->data; 2007 memset(rts, 0, MAX_DUMMY_FRM_BODY); 2008 rts->frame_control = 2009 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS); 2010 rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 2011 memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra)); 2012 memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta)); 2013 2014 skb_put(skb, sizeof(*rts)); 2015 tx_ppdu_info->tx_mon_mpdu->head = skb; 2016 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 2017 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 2018 &tx_ppdu_info->dp_tx_mon_mpdu_list); 2019 2020 return 0; 2021 } 2022 2023 static int 2024 ath12k_wifi7_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 2025 { 2026 struct sk_buff *skb; 2027 struct ieee80211_qos_hdr *qhdr; 2028 2029 skb = ath12k_wifi7_dp_mon_tx_alloc_skb(); 2030 if (!skb) 2031 return -ENOMEM; 2032 2033 qhdr = (struct ieee80211_qos_hdr *)skb->data; 2034 memset(qhdr, 0, MAX_DUMMY_FRM_BODY); 2035 qhdr->frame_control = 2036 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC); 2037 qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 2038 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 2039 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN); 2040 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN); 2041 2042 skb_put(skb, sizeof(*qhdr)); 2043 tx_ppdu_info->tx_mon_mpdu->head = skb; 2044 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 2045 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 2046 &tx_ppdu_info->dp_tx_mon_mpdu_list); 2047 2048 return 0; 2049 } 2050 2051 static int 2052 ath12k_wifi7_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 2053 { 2054 struct sk_buff *skb; 2055 struct dp_mon_qosframe_addr4 *qhdr; 2056 2057 skb = ath12k_wifi7_dp_mon_tx_alloc_skb(); 2058 if (!skb) 2059 return -ENOMEM; 2060 2061 qhdr = (struct dp_mon_qosframe_addr4 *)skb->data; 2062 memset(qhdr, 0, MAX_DUMMY_FRM_BODY); 2063 qhdr->frame_control = 2064 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC); 2065 qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 2066 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 2067 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN); 2068 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN); 2069 memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN); 2070 2071 skb_put(skb, sizeof(*qhdr)); 2072 tx_ppdu_info->tx_mon_mpdu->head = skb; 2073 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 2074 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 2075 &tx_ppdu_info->dp_tx_mon_mpdu_list); 2076 2077 return 0; 2078 } 2079 2080 static int 2081 ath12k_wifi7_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 2082 { 2083 struct sk_buff *skb; 2084 struct dp_mon_frame_min_one *fbmhdr; 2085 2086 skb = ath12k_wifi7_dp_mon_tx_alloc_skb(); 2087 if (!skb) 2088 return -ENOMEM; 2089 2090 fbmhdr = (struct dp_mon_frame_min_one *)skb->data; 2091 memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY); 2092 fbmhdr->frame_control = 2093 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK); 2094 memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 2095 2096 /* set duration zero for ack frame */ 2097 fbmhdr->duration = 0; 2098 2099 skb_put(skb, sizeof(*fbmhdr)); 2100 tx_ppdu_info->tx_mon_mpdu->head = skb; 2101 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 2102 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 2103 &tx_ppdu_info->dp_tx_mon_mpdu_list); 2104 2105 return 0; 2106 } 2107 2108 static int 2109 ath12k_wifi7_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 2110 { 2111 int ret = 0; 2112 2113 switch (tx_ppdu_info->rx_status.medium_prot_type) { 2114 case DP_MON_TX_MEDIUM_RTS_LEGACY: 2115 case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW: 2116 case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW: 2117 ret = ath12k_wifi7_dp_mon_tx_gen_rts_frame(tx_ppdu_info); 2118 break; 2119 case DP_MON_TX_MEDIUM_CTS2SELF: 2120 ret = ath12k_wifi7_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info); 2121 break; 2122 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR: 2123 ret = ath12k_wifi7_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info); 2124 break; 2125 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR: 2126 ret = ath12k_wifi7_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info); 2127 break; 2128 } 2129 2130 return ret; 2131 } 2132 2133 static enum dp_mon_tx_tlv_status 2134 ath12k_wifi7_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab, 2135 struct ath12k_mon_data *pmon, 2136 u16 tlv_tag, const void *tlv_data, 2137 u32 userid) 2138 { 2139 struct dp_mon_tx_ppdu_info *tx_ppdu_info; 2140 enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 2141 u32 info[7]; 2142 2143 tx_ppdu_info = ath12k_wifi7_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag); 2144 2145 switch (tlv_tag) { 2146 case HAL_TX_FES_SETUP: { 2147 const struct hal_tx_fes_setup *tx_fes_setup = tlv_data; 2148 2149 info[0] = __le32_to_cpu(tx_fes_setup->info0); 2150 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id); 2151 tx_ppdu_info->num_users = 2152 u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS); 2153 status = DP_MON_TX_FES_SETUP; 2154 break; 2155 } 2156 2157 case HAL_TX_FES_STATUS_END: { 2158 const struct hal_tx_fes_status_end *tx_fes_status_end = tlv_data; 2159 u32 tst_15_0, tst_31_16; 2160 2161 info[0] = __le32_to_cpu(tx_fes_status_end->info0); 2162 tst_15_0 = 2163 u32_get_bits(info[0], 2164 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0); 2165 tst_31_16 = 2166 u32_get_bits(info[0], 2167 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16); 2168 2169 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16)); 2170 status = DP_MON_TX_FES_STATUS_END; 2171 break; 2172 } 2173 2174 case HAL_RX_RESPONSE_REQUIRED_INFO: { 2175 const struct hal_rx_resp_req_info *rx_resp_req_info = tlv_data; 2176 u32 addr_32; 2177 u16 addr_16; 2178 2179 info[0] = __le32_to_cpu(rx_resp_req_info->info0); 2180 info[1] = __le32_to_cpu(rx_resp_req_info->info1); 2181 info[2] = __le32_to_cpu(rx_resp_req_info->info2); 2182 info[3] = __le32_to_cpu(rx_resp_req_info->info3); 2183 info[4] = __le32_to_cpu(rx_resp_req_info->info4); 2184 info[5] = __le32_to_cpu(rx_resp_req_info->info5); 2185 2186 tx_ppdu_info->rx_status.ppdu_id = 2187 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID); 2188 tx_ppdu_info->rx_status.reception_type = 2189 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE); 2190 tx_ppdu_info->rx_status.rx_duration = 2191 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION); 2192 tx_ppdu_info->rx_status.mcs = 2193 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS); 2194 tx_ppdu_info->rx_status.sgi = 2195 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI); 2196 tx_ppdu_info->rx_status.is_stbc = 2197 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC); 2198 tx_ppdu_info->rx_status.ldpc = 2199 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC); 2200 tx_ppdu_info->rx_status.is_ampdu = 2201 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU); 2202 tx_ppdu_info->rx_status.num_users = 2203 u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER); 2204 2205 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0); 2206 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32); 2207 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 2208 2209 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0); 2210 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16); 2211 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2); 2212 2213 if (tx_ppdu_info->rx_status.reception_type == 0) 2214 ath12k_wifi7_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info); 2215 status = DP_MON_RX_RESPONSE_REQUIRED_INFO; 2216 break; 2217 } 2218 2219 case HAL_PCU_PPDU_SETUP_INIT: { 2220 const struct hal_tx_pcu_ppdu_setup_init *ppdu_setup = tlv_data; 2221 u32 addr_32; 2222 u16 addr_16; 2223 2224 info[0] = __le32_to_cpu(ppdu_setup->info0); 2225 info[1] = __le32_to_cpu(ppdu_setup->info1); 2226 info[2] = __le32_to_cpu(ppdu_setup->info2); 2227 info[3] = __le32_to_cpu(ppdu_setup->info3); 2228 info[4] = __le32_to_cpu(ppdu_setup->info4); 2229 info[5] = __le32_to_cpu(ppdu_setup->info5); 2230 info[6] = __le32_to_cpu(ppdu_setup->info6); 2231 2232 /* protection frame address 1 */ 2233 addr_32 = u32_get_bits(info[1], 2234 HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0); 2235 addr_16 = u32_get_bits(info[2], 2236 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32); 2237 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 2238 2239 /* protection frame address 2 */ 2240 addr_16 = u32_get_bits(info[2], 2241 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0); 2242 addr_32 = u32_get_bits(info[3], 2243 HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16); 2244 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2); 2245 2246 /* protection frame address 3 */ 2247 addr_32 = u32_get_bits(info[4], 2248 HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0); 2249 addr_16 = u32_get_bits(info[5], 2250 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32); 2251 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3); 2252 2253 /* protection frame address 4 */ 2254 addr_16 = u32_get_bits(info[5], 2255 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0); 2256 addr_32 = u32_get_bits(info[6], 2257 HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16); 2258 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4); 2259 2260 status = u32_get_bits(info[0], 2261 HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE); 2262 break; 2263 } 2264 2265 case HAL_TX_QUEUE_EXTENSION: { 2266 const struct hal_tx_queue_exten *tx_q_exten = tlv_data; 2267 2268 info[0] = __le32_to_cpu(tx_q_exten->info0); 2269 2270 tx_ppdu_info->rx_status.frame_control = 2271 u32_get_bits(info[0], 2272 HAL_TX_Q_EXT_INFO0_FRAME_CTRL); 2273 tx_ppdu_info->rx_status.fc_valid = true; 2274 break; 2275 } 2276 2277 case HAL_TX_FES_STATUS_START: { 2278 const struct hal_tx_fes_status_start *tx_fes_start = tlv_data; 2279 2280 info[0] = __le32_to_cpu(tx_fes_start->info0); 2281 2282 tx_ppdu_info->rx_status.medium_prot_type = 2283 u32_get_bits(info[0], 2284 HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE); 2285 break; 2286 } 2287 2288 case HAL_TX_FES_STATUS_PROT: { 2289 const struct hal_tx_fes_status_prot *tx_fes_status = tlv_data; 2290 u32 start_timestamp; 2291 u32 end_timestamp; 2292 2293 info[0] = __le32_to_cpu(tx_fes_status->info0); 2294 info[1] = __le32_to_cpu(tx_fes_status->info1); 2295 2296 start_timestamp = 2297 u32_get_bits(info[0], 2298 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0); 2299 start_timestamp |= 2300 u32_get_bits(info[0], 2301 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15; 2302 end_timestamp = 2303 u32_get_bits(info[1], 2304 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0); 2305 end_timestamp |= 2306 u32_get_bits(info[1], 2307 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15; 2308 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp; 2309 2310 ath12k_wifi7_dp_mon_tx_gen_prot_frame(tx_ppdu_info); 2311 break; 2312 } 2313 2314 case HAL_TX_FES_STATUS_START_PPDU: 2315 case HAL_TX_FES_STATUS_START_PROT: { 2316 const struct hal_tx_fes_status_start_prot *tx_fes_stat_start = tlv_data; 2317 u64 ppdu_ts; 2318 2319 info[0] = __le32_to_cpu(tx_fes_stat_start->info0); 2320 2321 tx_ppdu_info->rx_status.ppdu_ts = 2322 u32_get_bits(info[0], 2323 HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32); 2324 ppdu_ts = (u32_get_bits(info[1], 2325 HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32)); 2326 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32; 2327 break; 2328 } 2329 2330 case HAL_TX_FES_STATUS_USER_PPDU: { 2331 const struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu = tlv_data; 2332 2333 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0); 2334 2335 tx_ppdu_info->rx_status.rx_duration = 2336 u32_get_bits(info[0], 2337 HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION); 2338 break; 2339 } 2340 2341 case HAL_MACTX_HE_SIG_A_SU: 2342 ath12k_wifi7_dp_mon_parse_he_sig_su(tlv_data, 2343 &tx_ppdu_info->rx_status); 2344 break; 2345 2346 case HAL_MACTX_HE_SIG_A_MU_DL: 2347 ath12k_wifi7_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status); 2348 break; 2349 2350 case HAL_MACTX_HE_SIG_B1_MU: 2351 ath12k_wifi7_dp_mon_parse_he_sig_b1_mu(tlv_data, 2352 &tx_ppdu_info->rx_status); 2353 break; 2354 2355 case HAL_MACTX_HE_SIG_B2_MU: 2356 ath12k_wifi7_dp_mon_parse_he_sig_b2_mu(tlv_data, 2357 &tx_ppdu_info->rx_status); 2358 break; 2359 2360 case HAL_MACTX_HE_SIG_B2_OFDMA: 2361 ath12k_wifi7_dp_mon_parse_he_sig_b2_ofdma(tlv_data, 2362 &tx_ppdu_info->rx_status); 2363 break; 2364 2365 case HAL_MACTX_VHT_SIG_A: 2366 ath12k_wifi7_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status); 2367 break; 2368 2369 case HAL_MACTX_L_SIG_A: 2370 ath12k_wifi7_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status); 2371 break; 2372 2373 case HAL_MACTX_L_SIG_B: 2374 ath12k_wifi7_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status); 2375 break; 2376 2377 case HAL_RX_FRAME_BITMAP_ACK: { 2378 const struct hal_rx_frame_bitmap_ack *fbm_ack = tlv_data; 2379 u32 addr_32; 2380 u16 addr_16; 2381 2382 info[0] = __le32_to_cpu(fbm_ack->info0); 2383 info[1] = __le32_to_cpu(fbm_ack->info1); 2384 2385 addr_32 = u32_get_bits(info[0], 2386 HAL_RX_FBM_ACK_INFO0_ADDR1_31_0); 2387 addr_16 = u32_get_bits(info[1], 2388 HAL_RX_FBM_ACK_INFO1_ADDR1_47_32); 2389 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 2390 2391 ath12k_wifi7_dp_mon_tx_gen_ack_frame(tx_ppdu_info); 2392 break; 2393 } 2394 2395 case HAL_MACTX_PHY_DESC: { 2396 const struct hal_tx_phy_desc *tx_phy_desc = tlv_data; 2397 2398 info[0] = __le32_to_cpu(tx_phy_desc->info0); 2399 info[1] = __le32_to_cpu(tx_phy_desc->info1); 2400 info[2] = __le32_to_cpu(tx_phy_desc->info2); 2401 info[3] = __le32_to_cpu(tx_phy_desc->info3); 2402 2403 tx_ppdu_info->rx_status.beamformed = 2404 u32_get_bits(info[0], 2405 HAL_TX_PHY_DESC_INFO0_BF_TYPE); 2406 tx_ppdu_info->rx_status.preamble_type = 2407 u32_get_bits(info[0], 2408 HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B); 2409 tx_ppdu_info->rx_status.mcs = 2410 u32_get_bits(info[1], 2411 HAL_TX_PHY_DESC_INFO1_MCS); 2412 tx_ppdu_info->rx_status.ltf_size = 2413 u32_get_bits(info[3], 2414 HAL_TX_PHY_DESC_INFO3_LTF_SIZE); 2415 tx_ppdu_info->rx_status.nss = 2416 u32_get_bits(info[2], 2417 HAL_TX_PHY_DESC_INFO2_NSS); 2418 tx_ppdu_info->rx_status.chan_num = 2419 u32_get_bits(info[3], 2420 HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL); 2421 tx_ppdu_info->rx_status.bw = 2422 u32_get_bits(info[0], 2423 HAL_TX_PHY_DESC_INFO0_BANDWIDTH); 2424 break; 2425 } 2426 2427 case HAL_TX_MPDU_START: { 2428 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu; 2429 2430 mon_mpdu = kzalloc_obj(*mon_mpdu, GFP_ATOMIC); 2431 if (!mon_mpdu) 2432 return DP_MON_TX_STATUS_PPDU_NOT_DONE; 2433 status = DP_MON_TX_MPDU_START; 2434 break; 2435 } 2436 2437 case HAL_TX_MPDU_END: 2438 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 2439 &tx_ppdu_info->dp_tx_mon_mpdu_list); 2440 break; 2441 } 2442 2443 return status; 2444 } 2445 2446 static enum dp_mon_tx_tlv_status 2447 ath12k_wifi7_dp_mon_tx_status_get_num_user(u16 tlv_tag, 2448 struct hal_tlv_hdr *tx_tlv, 2449 u8 *num_users) 2450 { 2451 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 2452 u32 info0; 2453 2454 switch (tlv_tag) { 2455 case HAL_TX_FES_SETUP: { 2456 struct hal_tx_fes_setup *tx_fes_setup = 2457 (struct hal_tx_fes_setup *)tx_tlv; 2458 2459 info0 = __le32_to_cpu(tx_fes_setup->info0); 2460 2461 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS); 2462 tlv_status = DP_MON_TX_FES_SETUP; 2463 break; 2464 } 2465 2466 case HAL_RX_RESPONSE_REQUIRED_INFO: { 2467 /* TODO: need to update *num_users */ 2468 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO; 2469 break; 2470 } 2471 } 2472 2473 return tlv_status; 2474 } 2475 2476 static int 2477 ath12k_wifi7_dp_mon_rx_deliver(struct ath12k_pdev_dp *dp_pdev, 2478 struct dp_mon_mpdu *mon_mpdu, 2479 struct hal_rx_mon_ppdu_info *ppduinfo, 2480 struct napi_struct *napi) 2481 { 2482 struct sk_buff *mon_skb, *skb_next, *header; 2483 struct ieee80211_rx_status *rxs = &dp_pdev->rx_status; 2484 u8 decap = DP_RX_DECAP_TYPE_RAW; 2485 2486 mon_skb = ath12k_dp_mon_rx_merg_msdus(dp_pdev, mon_mpdu, ppduinfo, rxs); 2487 if (!mon_skb) 2488 goto mon_deliver_fail; 2489 2490 header = mon_skb; 2491 rxs->flag = 0; 2492 2493 if (mon_mpdu->err_bitmap & HAL_RX_MPDU_ERR_FCS) 2494 rxs->flag = RX_FLAG_FAILED_FCS_CRC; 2495 2496 do { 2497 skb_next = mon_skb->next; 2498 if (!skb_next) 2499 rxs->flag &= ~RX_FLAG_AMSDU_MORE; 2500 else 2501 rxs->flag |= RX_FLAG_AMSDU_MORE; 2502 2503 if (mon_skb == header) { 2504 header = NULL; 2505 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 2506 } else { 2507 rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 2508 } 2509 rxs->flag |= RX_FLAG_ONLY_MONITOR; 2510 2511 if (!(rxs->flag & RX_FLAG_ONLY_MONITOR)) 2512 decap = mon_mpdu->decap_format; 2513 2514 ath12k_dp_mon_update_radiotap(dp_pdev, ppduinfo, mon_skb, rxs); 2515 ath12k_dp_mon_rx_deliver_msdu(dp_pdev, napi, mon_skb, ppduinfo, 2516 rxs, decap); 2517 mon_skb = skb_next; 2518 } while (mon_skb); 2519 rxs->flag = 0; 2520 2521 return 0; 2522 2523 mon_deliver_fail: 2524 mon_skb = mon_mpdu->head; 2525 while (mon_skb) { 2526 skb_next = mon_skb->next; 2527 dev_kfree_skb_any(mon_skb); 2528 mon_skb = skb_next; 2529 } 2530 return -EINVAL; 2531 } 2532 2533 static void 2534 ath12k_wifi7_dp_mon_tx_process_ppdu_info(struct ath12k_pdev_dp *dp_pdev, 2535 struct napi_struct *napi, 2536 struct dp_mon_tx_ppdu_info *tx_ppdu_info) 2537 { 2538 struct dp_mon_mpdu *tmp, *mon_mpdu; 2539 2540 list_for_each_entry_safe(mon_mpdu, tmp, 2541 &tx_ppdu_info->dp_tx_mon_mpdu_list, list) { 2542 list_del(&mon_mpdu->list); 2543 2544 if (mon_mpdu->head) 2545 ath12k_wifi7_dp_mon_rx_deliver(dp_pdev, mon_mpdu, 2546 &tx_ppdu_info->rx_status, napi); 2547 2548 kfree(mon_mpdu); 2549 } 2550 } 2551 2552 enum hal_rx_mon_status 2553 ath12k_wifi7_dp_mon_tx_parse_mon_status(struct ath12k_pdev_dp *dp_pdev, 2554 struct ath12k_mon_data *pmon, 2555 struct sk_buff *skb, 2556 struct napi_struct *napi, 2557 u32 ppdu_id) 2558 { 2559 struct ath12k_dp *dp = dp_pdev->dp; 2560 struct ath12k_base *ab = dp->ab; 2561 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info; 2562 struct hal_tlv_hdr *tlv; 2563 u8 *ptr = skb->data; 2564 u16 tlv_tag; 2565 u16 tlv_len; 2566 u32 tlv_userid = 0; 2567 u8 num_user; 2568 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 2569 2570 tx_prot_ppdu_info = 2571 ath12k_wifi7_dp_mon_tx_get_ppdu_info(pmon, ppdu_id, 2572 DP_MON_TX_PROT_PPDU_INFO); 2573 if (!tx_prot_ppdu_info) 2574 return -ENOMEM; 2575 2576 tlv = (struct hal_tlv_hdr *)ptr; 2577 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 2578 2579 tlv_status = ath12k_wifi7_dp_mon_tx_status_get_num_user(tlv_tag, tlv, 2580 &num_user); 2581 if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user) 2582 return -EINVAL; 2583 2584 tx_data_ppdu_info = 2585 ath12k_wifi7_dp_mon_tx_get_ppdu_info(pmon, ppdu_id, 2586 DP_MON_TX_DATA_PPDU_INFO); 2587 if (!tx_data_ppdu_info) 2588 return -ENOMEM; 2589 2590 do { 2591 tlv = (struct hal_tlv_hdr *)ptr; 2592 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 2593 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN); 2594 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID); 2595 2596 tlv_status = ath12k_wifi7_dp_mon_tx_parse_status_tlv(ab, pmon, 2597 tlv_tag, ptr, 2598 tlv_userid); 2599 ptr += tlv_len; 2600 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); 2601 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE) 2602 break; 2603 } while (tlv_status != DP_MON_TX_FES_STATUS_END); 2604 2605 ath12k_wifi7_dp_mon_tx_process_ppdu_info(dp_pdev, napi, tx_data_ppdu_info); 2606 ath12k_wifi7_dp_mon_tx_process_ppdu_info(dp_pdev, napi, tx_prot_ppdu_info); 2607 2608 return tlv_status; 2609 } 2610 2611 static void 2612 ath12k_wifi7_dp_mon_next_link_desc_get(struct ath12k_base *ab, 2613 struct hal_rx_msdu_link *msdu_link, 2614 dma_addr_t *paddr, u32 *sw_cookie, u8 *rbm, 2615 struct ath12k_buffer_addr **pp_buf_addr_info) 2616 { 2617 struct ath12k_buffer_addr *buf_addr_info; 2618 2619 buf_addr_info = &msdu_link->buf_addr_info; 2620 2621 ath12k_wifi7_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm); 2622 2623 *pp_buf_addr_info = buf_addr_info; 2624 } 2625 2626 static u32 2627 ath12k_wifi7_dp_rx_mon_mpdu_pop(struct ath12k *ar, int mac_id, 2628 void *ring_entry, struct sk_buff **head_msdu, 2629 struct sk_buff **tail_msdu, 2630 struct list_head *used_list, 2631 u32 *npackets, u32 *ppdu_id) 2632 { 2633 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&ar->dp.mon_data; 2634 struct ath12k_base *ab = ar->ab; 2635 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 2636 struct ath12k_buffer_addr *p_buf_addr_info, *p_last_buf_addr_info; 2637 u32 msdu_ppdu_id = 0, msdu_cnt = 0, total_len = 0, frag_len = 0; 2638 u32 rx_buf_size, rx_pkt_offset, sw_cookie; 2639 bool is_frag, is_first_msdu, drop_mpdu = false; 2640 struct hal_reo_entrance_ring *ent_desc = 2641 (struct hal_reo_entrance_ring *)ring_entry; 2642 u32 rx_bufs_used = 0, i = 0, desc_bank = 0; 2643 struct hal_rx_desc *rx_desc, *tail_rx_desc; 2644 struct hal_rx_msdu_link *msdu_link_desc; 2645 struct sk_buff *msdu = NULL, *last = NULL; 2646 struct ath12k_rx_desc_info *desc_info; 2647 struct ath12k_buffer_addr buf_info; 2648 struct hal_rx_msdu_list msdu_list; 2649 struct ath12k_skb_rxcb *rxcb; 2650 u16 num_msdus = 0; 2651 dma_addr_t paddr; 2652 u8 rbm; 2653 2654 ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr, 2655 &sw_cookie, 2656 &p_last_buf_addr_info, 2657 &rbm, 2658 &msdu_cnt); 2659 2660 spin_lock_bh(&pmon->mon_lock); 2661 2662 if (le32_get_bits(ent_desc->info1, 2663 HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON) == 2664 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 2665 u8 rxdma_err = le32_get_bits(ent_desc->info1, 2666 HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE); 2667 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 2668 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 2669 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 2670 drop_mpdu = true; 2671 pmon->rx_mon_stats.dest_mpdu_drop++; 2672 } 2673 } 2674 2675 is_frag = false; 2676 is_first_msdu = true; 2677 rx_pkt_offset = sizeof(struct hal_rx_desc); 2678 2679 do { 2680 if (pmon->mon_last_linkdesc_paddr == paddr) { 2681 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++; 2682 spin_unlock_bh(&pmon->mon_lock); 2683 return rx_bufs_used; 2684 } 2685 2686 desc_bank = u32_get_bits(sw_cookie, DP_LINK_DESC_BANK_MASK); 2687 msdu_link_desc = 2688 dp->link_desc_banks[desc_bank].vaddr + 2689 (paddr - dp->link_desc_banks[desc_bank].paddr); 2690 2691 ath12k_wifi7_hal_rx_msdu_list_get(ar, msdu_link_desc, &msdu_list, 2692 &num_msdus); 2693 desc_info = ath12k_dp_get_rx_desc(ar->ab->dp, 2694 msdu_list.sw_cookie[num_msdus - 1]); 2695 tail_rx_desc = (struct hal_rx_desc *)(desc_info->skb)->data; 2696 2697 for (i = 0; i < num_msdus; i++) { 2698 u32 l2_hdr_offset; 2699 2700 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) { 2701 ath12k_dbg(ar->ab, ATH12K_DBG_DATA, 2702 "i %d last_cookie %d is same\n", 2703 i, pmon->mon_last_buf_cookie); 2704 drop_mpdu = true; 2705 pmon->rx_mon_stats.dup_mon_buf_cnt++; 2706 continue; 2707 } 2708 2709 desc_info = 2710 ath12k_dp_get_rx_desc(ar->ab->dp, msdu_list.sw_cookie[i]); 2711 msdu = desc_info->skb; 2712 2713 if (!msdu) { 2714 ath12k_dbg(ar->ab, ATH12K_DBG_DATA, 2715 "msdu_pop: invalid msdu (%d/%d)\n", 2716 i + 1, num_msdus); 2717 goto next_msdu; 2718 } 2719 rxcb = ATH12K_SKB_RXCB(msdu); 2720 if (rxcb->paddr != msdu_list.paddr[i]) { 2721 ath12k_dbg(ar->ab, ATH12K_DBG_DATA, 2722 "i %d paddr %lx != %lx\n", 2723 i, (unsigned long)rxcb->paddr, 2724 (unsigned long)msdu_list.paddr[i]); 2725 drop_mpdu = true; 2726 continue; 2727 } 2728 if (!rxcb->unmapped) { 2729 dma_unmap_single(ar->ab->dev, rxcb->paddr, 2730 msdu->len + 2731 skb_tailroom(msdu), 2732 DMA_FROM_DEVICE); 2733 rxcb->unmapped = 1; 2734 } 2735 if (drop_mpdu) { 2736 ath12k_dbg(ar->ab, ATH12K_DBG_DATA, 2737 "i %d drop msdu %p *ppdu_id %x\n", 2738 i, msdu, *ppdu_id); 2739 dev_kfree_skb_any(msdu); 2740 msdu = NULL; 2741 goto next_msdu; 2742 } 2743 2744 rx_desc = (struct hal_rx_desc *)msdu->data; 2745 l2_hdr_offset = ath12k_dp_rx_h_l3pad(ar->ab, tail_rx_desc); 2746 if (is_first_msdu) { 2747 if (!ath12k_wifi7_dp_rxdesc_mpdu_valid(ar->ab, 2748 rx_desc)) { 2749 drop_mpdu = true; 2750 dev_kfree_skb_any(msdu); 2751 msdu = NULL; 2752 pmon->mon_last_linkdesc_paddr = paddr; 2753 goto next_msdu; 2754 } 2755 msdu_ppdu_id = 2756 ath12k_dp_rxdesc_get_ppduid(ar->ab, rx_desc); 2757 2758 if (ath12k_dp_mon_comp_ppduid(msdu_ppdu_id, 2759 ppdu_id)) { 2760 spin_unlock_bh(&pmon->mon_lock); 2761 return rx_bufs_used; 2762 } 2763 pmon->mon_last_linkdesc_paddr = paddr; 2764 is_first_msdu = false; 2765 } 2766 ath12k_wifi7_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 2767 &is_frag, &total_len, 2768 &frag_len, &msdu_cnt); 2769 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 2770 2771 if (ath12k_dp_pkt_set_pktlen(msdu, rx_buf_size)) { 2772 dev_kfree_skb_any(msdu); 2773 goto next_msdu; 2774 } 2775 2776 if (!(*head_msdu)) 2777 *head_msdu = msdu; 2778 else if (last) 2779 last->next = msdu; 2780 2781 last = msdu; 2782 next_msdu: 2783 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i]; 2784 rx_bufs_used++; 2785 desc_info->skb = NULL; 2786 list_add_tail(&desc_info->list, used_list); 2787 } 2788 2789 ath12k_wifi7_hal_rx_buf_addr_info_set(&buf_info, paddr, 2790 sw_cookie, rbm); 2791 2792 ath12k_wifi7_dp_mon_next_link_desc_get(ab, 2793 msdu_link_desc, &paddr, 2794 &sw_cookie, &rbm, 2795 &p_buf_addr_info); 2796 2797 ath12k_dp_arch_rx_link_desc_return(ar->ab->dp, &buf_info, 2798 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 2799 2800 p_last_buf_addr_info = p_buf_addr_info; 2801 2802 } while (paddr && msdu_cnt); 2803 2804 spin_unlock_bh(&pmon->mon_lock); 2805 2806 if (last) 2807 last->next = NULL; 2808 2809 *tail_msdu = msdu; 2810 2811 if (msdu_cnt == 0) 2812 *npackets = 1; 2813 2814 return rx_bufs_used; 2815 } 2816 2817 /* The destination ring processing is stuck if the destination is not 2818 * moving while status ring moves 16 PPDU. The destination ring processing 2819 * skips this destination ring PPDU as a workaround. 2820 */ 2821 #define MON_DEST_RING_STUCK_MAX_CNT 16 2822 2823 static void 2824 ath12k_wifi7_dp_rx_mon_dest_process(struct ath12k *ar, int mac_id, 2825 u32 quota, struct napi_struct *napi) 2826 { 2827 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&ar->dp.mon_data; 2828 struct ath12k_pdev_mon_stats *rx_mon_stats; 2829 u32 ppdu_id, rx_bufs_used = 0, ring_id; 2830 u32 mpdu_rx_bufs_used, npackets = 0; 2831 struct ath12k_base *ab = ar->ab; 2832 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 2833 void *ring_entry, *mon_dst_srng; 2834 struct dp_mon_mpdu *tmp_mpdu; 2835 LIST_HEAD(rx_desc_used_list); 2836 struct hal_srng *srng; 2837 2838 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id; 2839 srng = &ab->hal.srng_list[ring_id]; 2840 2841 mon_dst_srng = &ab->hal.srng_list[ring_id]; 2842 2843 spin_lock_bh(&srng->lock); 2844 2845 ath12k_hal_srng_access_begin(ab, mon_dst_srng); 2846 2847 ppdu_id = pmon->mon_ppdu_info.ppdu_id; 2848 rx_mon_stats = &pmon->rx_mon_stats; 2849 2850 while ((ring_entry = ath12k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 2851 struct sk_buff *head_msdu, *tail_msdu; 2852 2853 head_msdu = NULL; 2854 tail_msdu = NULL; 2855 2856 mpdu_rx_bufs_used = ath12k_wifi7_dp_rx_mon_mpdu_pop(ar, mac_id, 2857 ring_entry, 2858 &head_msdu, 2859 &tail_msdu, 2860 &rx_desc_used_list, 2861 &npackets, 2862 &ppdu_id); 2863 2864 rx_bufs_used += mpdu_rx_bufs_used; 2865 2866 if (mpdu_rx_bufs_used) { 2867 dp->mon_dest_ring_stuck_cnt = 0; 2868 } else { 2869 dp->mon_dest_ring_stuck_cnt++; 2870 rx_mon_stats->dest_mon_not_reaped++; 2871 } 2872 2873 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) { 2874 rx_mon_stats->dest_mon_stuck++; 2875 ath12k_dbg(ar->ab, ATH12K_DBG_DATA, 2876 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n", 2877 pmon->mon_ppdu_info.ppdu_id, ppdu_id, 2878 dp->mon_dest_ring_stuck_cnt, 2879 rx_mon_stats->dest_mon_not_reaped, 2880 rx_mon_stats->dest_mon_stuck); 2881 spin_lock_bh(&pmon->mon_lock); 2882 pmon->mon_ppdu_info.ppdu_id = ppdu_id; 2883 spin_unlock_bh(&pmon->mon_lock); 2884 continue; 2885 } 2886 2887 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) { 2888 spin_lock_bh(&pmon->mon_lock); 2889 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 2890 spin_unlock_bh(&pmon->mon_lock); 2891 ath12k_dbg(ar->ab, ATH12K_DBG_DATA, 2892 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n", 2893 ppdu_id, pmon->mon_ppdu_info.ppdu_id, 2894 rx_mon_stats->dest_mon_not_reaped, 2895 rx_mon_stats->dest_mon_stuck); 2896 break; 2897 } 2898 2899 if (head_msdu && tail_msdu) { 2900 tmp_mpdu = kzalloc_obj(*tmp_mpdu, GFP_ATOMIC); 2901 if (!tmp_mpdu) 2902 break; 2903 2904 tmp_mpdu->head = head_msdu; 2905 tmp_mpdu->tail = tail_msdu; 2906 tmp_mpdu->err_bitmap = pmon->err_bitmap; 2907 tmp_mpdu->decap_format = pmon->decap_format; 2908 ath12k_wifi7_dp_mon_rx_deliver(&ar->dp, tmp_mpdu, 2909 &pmon->mon_ppdu_info, napi); 2910 rx_mon_stats->dest_mpdu_done++; 2911 kfree(tmp_mpdu); 2912 } 2913 2914 ring_entry = ath12k_hal_srng_dst_get_next_entry(ar->ab, 2915 mon_dst_srng); 2916 } 2917 ath12k_hal_srng_access_end(ar->ab, mon_dst_srng); 2918 2919 spin_unlock_bh(&srng->lock); 2920 2921 if (rx_bufs_used) { 2922 rx_mon_stats->dest_ppdu_done++; 2923 ath12k_dp_rx_bufs_replenish(ar->ab->dp, 2924 &dp->rx_refill_buf_ring, 2925 &rx_desc_used_list, 2926 rx_bufs_used); 2927 } 2928 } 2929 2930 static enum dp_mon_status_buf_state 2931 ath12k_wifi7_dp_rx_mon_buf_done(struct ath12k_base *ab, struct hal_srng *srng, 2932 struct dp_rxdma_mon_ring *rx_ring) 2933 { 2934 struct ath12k_skb_rxcb *rxcb; 2935 struct hal_tlv_64_hdr *tlv; 2936 struct sk_buff *skb; 2937 void *status_desc; 2938 dma_addr_t paddr; 2939 u32 cookie; 2940 int buf_id; 2941 u8 rbm; 2942 2943 status_desc = ath12k_hal_srng_src_next_peek(ab, srng); 2944 if (!status_desc) 2945 return DP_MON_STATUS_NO_DMA; 2946 2947 ath12k_wifi7_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm); 2948 2949 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); 2950 2951 spin_lock_bh(&rx_ring->idr_lock); 2952 skb = idr_find(&rx_ring->bufs_idr, buf_id); 2953 spin_unlock_bh(&rx_ring->idr_lock); 2954 2955 if (!skb) 2956 return DP_MON_STATUS_NO_DMA; 2957 2958 rxcb = ATH12K_SKB_RXCB(skb); 2959 dma_sync_single_for_cpu(ab->dev, rxcb->paddr, 2960 skb->len + skb_tailroom(skb), 2961 DMA_FROM_DEVICE); 2962 2963 tlv = (struct hal_tlv_64_hdr *)skb->data; 2964 if (le64_get_bits(tlv->tl, HAL_TLV_HDR_TAG) != HAL_RX_STATUS_BUFFER_DONE) 2965 return DP_MON_STATUS_NO_DMA; 2966 2967 return DP_MON_STATUS_REPLINISH; 2968 } 2969 2970 static enum hal_rx_mon_status 2971 ath12k_wifi7_dp_mon_parse_rx_dest(struct ath12k_pdev_dp *dp_pdev, 2972 struct ath12k_mon_data *pmon, 2973 struct sk_buff *skb) 2974 { 2975 struct ath12k *ar = ath12k_pdev_dp_to_ar(dp_pdev); 2976 struct hal_tlv_64_hdr *tlv; 2977 struct ath12k_skb_rxcb *rxcb; 2978 enum hal_rx_mon_status hal_status; 2979 u16 tlv_tag, tlv_len; 2980 u8 *ptr = skb->data; 2981 2982 do { 2983 tlv = (struct hal_tlv_64_hdr *)ptr; 2984 tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG); 2985 2986 /* The actual length of PPDU_END is the combined length of many PHY 2987 * TLVs that follow. Skip the TLV header and 2988 * rx_rxpcu_classification_overview that follows the header to get to 2989 * next TLV. 2990 */ 2991 2992 if (tlv_tag == HAL_RX_PPDU_END) 2993 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview); 2994 else 2995 tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN); 2996 2997 hal_status = ath12k_wifi7_dp_mon_rx_parse_status_tlv(dp_pdev, pmon, 2998 tlv); 2999 3000 if (ar->monitor_started && ar->ab->hw_params->rxdma1_enable && 3001 ath12k_wifi7_dp_mon_parse_rx_dest_tlv(dp_pdev, pmon, hal_status, 3002 tlv->value)) 3003 return HAL_RX_MON_STATUS_PPDU_DONE; 3004 3005 ptr += sizeof(*tlv) + tlv_len; 3006 ptr = PTR_ALIGN(ptr, HAL_TLV_64_ALIGN); 3007 3008 if ((ptr - skb->data) > skb->len) 3009 break; 3010 3011 } while ((hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE) || 3012 (hal_status == HAL_RX_MON_STATUS_BUF_ADDR) || 3013 (hal_status == HAL_RX_MON_STATUS_MPDU_START) || 3014 (hal_status == HAL_RX_MON_STATUS_MPDU_END) || 3015 (hal_status == HAL_RX_MON_STATUS_MSDU_END)); 3016 3017 rxcb = ATH12K_SKB_RXCB(skb); 3018 if (rxcb->is_end_of_ppdu) 3019 hal_status = HAL_RX_MON_STATUS_PPDU_DONE; 3020 3021 return hal_status; 3022 } 3023 3024 static enum hal_rx_mon_status 3025 ath12k_wifi7_dp_mon_rx_parse_mon_status(struct ath12k_pdev_dp *dp_pdev, 3026 struct ath12k_mon_data *pmon, 3027 struct sk_buff *skb, 3028 struct napi_struct *napi) 3029 { 3030 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 3031 struct dp_mon_mpdu *tmp; 3032 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 3033 enum hal_rx_mon_status hal_status; 3034 3035 hal_status = ath12k_wifi7_dp_mon_parse_rx_dest(dp_pdev, pmon, skb); 3036 if (hal_status != HAL_RX_MON_STATUS_PPDU_DONE) 3037 return hal_status; 3038 3039 list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) { 3040 list_del(&mon_mpdu->list); 3041 3042 if (mon_mpdu->head && mon_mpdu->tail) 3043 ath12k_wifi7_dp_mon_rx_deliver(dp_pdev, mon_mpdu, 3044 ppdu_info, napi); 3045 3046 kfree(mon_mpdu); 3047 } 3048 3049 return hal_status; 3050 } 3051 3052 static int 3053 ath12k_wifi7_dp_rx_reap_mon_status_ring(struct ath12k_base *ab, int mac_id, 3054 int *budget, struct sk_buff_head *skb_list) 3055 { 3056 const struct ath12k_hw_hal_params *hal_params; 3057 int buf_id, srng_id, num_buffs_reaped = 0; 3058 enum dp_mon_status_buf_state reap_status; 3059 struct dp_rxdma_mon_ring *rx_ring; 3060 struct ath12k_mon_data *pmon; 3061 struct ath12k_skb_rxcb *rxcb; 3062 struct hal_tlv_64_hdr *tlv; 3063 void *rx_mon_status_desc; 3064 struct hal_srng *srng; 3065 struct ath12k_dp *dp; 3066 struct sk_buff *skb; 3067 struct ath12k *ar; 3068 dma_addr_t paddr; 3069 u32 cookie; 3070 u8 rbm; 3071 3072 ar = ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 3073 dp = ath12k_ab_to_dp(ab); 3074 pmon = &ar->dp.mon_data; 3075 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); 3076 rx_ring = &dp->rx_mon_status_refill_ring[srng_id]; 3077 3078 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 3079 3080 spin_lock_bh(&srng->lock); 3081 3082 ath12k_hal_srng_access_begin(ab, srng); 3083 3084 while (*budget) { 3085 *budget -= 1; 3086 rx_mon_status_desc = ath12k_hal_srng_src_peek(ab, srng); 3087 if (!rx_mon_status_desc) { 3088 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3089 break; 3090 } 3091 ath12k_wifi7_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr, 3092 &cookie, &rbm); 3093 if (paddr) { 3094 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); 3095 3096 spin_lock_bh(&rx_ring->idr_lock); 3097 skb = idr_find(&rx_ring->bufs_idr, buf_id); 3098 spin_unlock_bh(&rx_ring->idr_lock); 3099 3100 if (!skb) { 3101 ath12k_warn(ab, "rx monitor status with invalid buf_id %d\n", 3102 buf_id); 3103 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3104 goto move_next; 3105 } 3106 3107 rxcb = ATH12K_SKB_RXCB(skb); 3108 3109 dma_sync_single_for_cpu(ab->dev, rxcb->paddr, 3110 skb->len + skb_tailroom(skb), 3111 DMA_FROM_DEVICE); 3112 3113 tlv = (struct hal_tlv_64_hdr *)skb->data; 3114 if (le64_get_bits(tlv->tl, HAL_TLV_HDR_TAG) != 3115 HAL_RX_STATUS_BUFFER_DONE) { 3116 pmon->buf_state = DP_MON_STATUS_NO_DMA; 3117 ath12k_warn(ab, 3118 "mon status DONE not set %llx, buf_id %d\n", 3119 le64_get_bits(tlv->tl, HAL_TLV_HDR_TAG), 3120 buf_id); 3121 /* RxDMA status done bit might not be set even 3122 * though tp is moved by HW. 3123 */ 3124 3125 /* If done status is missing: 3126 * 1. As per MAC team's suggestion, 3127 * when HP + 1 entry is peeked and if DMA 3128 * is not done and if HP + 2 entry's DMA done 3129 * is set. skip HP + 1 entry and 3130 * start processing in next interrupt. 3131 * 2. If HP + 2 entry's DMA done is not set, 3132 * poll onto HP + 1 entry DMA done to be set. 3133 * Check status for same buffer for next time 3134 * dp_rx_mon_status_srng_process 3135 */ 3136 reap_status = ath12k_wifi7_dp_rx_mon_buf_done(ab, srng, 3137 rx_ring); 3138 if (reap_status == DP_MON_STATUS_NO_DMA) 3139 continue; 3140 3141 spin_lock_bh(&rx_ring->idr_lock); 3142 idr_remove(&rx_ring->bufs_idr, buf_id); 3143 spin_unlock_bh(&rx_ring->idr_lock); 3144 3145 dma_unmap_single(ab->dev, rxcb->paddr, 3146 skb->len + skb_tailroom(skb), 3147 DMA_FROM_DEVICE); 3148 3149 dev_kfree_skb_any(skb); 3150 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3151 goto move_next; 3152 } 3153 3154 spin_lock_bh(&rx_ring->idr_lock); 3155 idr_remove(&rx_ring->bufs_idr, buf_id); 3156 spin_unlock_bh(&rx_ring->idr_lock); 3157 3158 dma_unmap_single(ab->dev, rxcb->paddr, 3159 skb->len + skb_tailroom(skb), 3160 DMA_FROM_DEVICE); 3161 3162 if (ath12k_dp_pkt_set_pktlen(skb, RX_MON_STATUS_BUF_SIZE)) { 3163 dev_kfree_skb_any(skb); 3164 goto move_next; 3165 } 3166 __skb_queue_tail(skb_list, skb); 3167 } else { 3168 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3169 } 3170 move_next: 3171 skb = ath12k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 3172 &buf_id); 3173 hal_params = ab->hal.hal_params; 3174 3175 if (!skb) { 3176 ath12k_warn(ab, "failed to alloc buffer for status ring\n"); 3177 ath12k_wifi7_hal_rx_buf_addr_info_set(rx_mon_status_desc, 3178 0, 0, 3179 hal_params->rx_buf_rbm); 3180 num_buffs_reaped++; 3181 break; 3182 } 3183 rxcb = ATH12K_SKB_RXCB(skb); 3184 3185 cookie = u32_encode_bits(mac_id, DP_RXDMA_BUF_COOKIE_PDEV_ID) | 3186 u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID); 3187 3188 ath12k_wifi7_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr, 3189 cookie, hal_params->rx_buf_rbm); 3190 ath12k_hal_srng_src_get_next_entry(ab, srng); 3191 num_buffs_reaped++; 3192 } 3193 ath12k_hal_srng_access_end(ab, srng); 3194 spin_unlock_bh(&srng->lock); 3195 3196 return num_buffs_reaped; 3197 } 3198 3199 static int 3200 __ath12k_wifi7_dp_mon_process_ring(struct ath12k *ar, int mac_id, 3201 struct napi_struct *napi, int *budget) 3202 { 3203 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&ar->dp.mon_data; 3204 struct ath12k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats; 3205 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 3206 enum hal_rx_mon_status hal_status; 3207 struct sk_buff_head skb_list; 3208 int num_buffs_reaped; 3209 struct sk_buff *skb; 3210 3211 __skb_queue_head_init(&skb_list); 3212 3213 num_buffs_reaped = ath12k_wifi7_dp_rx_reap_mon_status_ring(ar->ab, mac_id, 3214 budget, &skb_list); 3215 if (!num_buffs_reaped) 3216 goto exit; 3217 3218 while ((skb = __skb_dequeue(&skb_list))) { 3219 memset(ppdu_info, 0, sizeof(*ppdu_info)); 3220 ppdu_info->peer_id = HAL_INVALID_PEERID; 3221 3222 hal_status = ath12k_wifi7_dp_mon_parse_rx_dest(&ar->dp, pmon, skb); 3223 3224 if (ar->monitor_started && 3225 pmon->mon_ppdu_status == DP_PPDU_STATUS_START && 3226 hal_status == HAL_TLV_STATUS_PPDU_DONE) { 3227 rx_mon_stats->status_ppdu_done++; 3228 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE; 3229 ath12k_wifi7_dp_rx_mon_dest_process(ar, mac_id, *budget, napi); 3230 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 3231 } 3232 3233 dev_kfree_skb_any(skb); 3234 } 3235 3236 exit: 3237 return num_buffs_reaped; 3238 } 3239 3240 static int 3241 ath12k_wifi7_dp_mon_srng_process(struct ath12k_pdev_dp *pdev_dp, int *budget, 3242 struct napi_struct *napi) 3243 { 3244 struct ath12k_dp *dp = pdev_dp->dp; 3245 struct ath12k_base *ab = dp->ab; 3246 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data; 3247 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 3248 struct hal_mon_dest_desc *mon_dst_desc; 3249 struct sk_buff *skb; 3250 struct ath12k_skb_rxcb *rxcb; 3251 struct dp_srng *mon_dst_ring; 3252 struct hal_srng *srng; 3253 struct dp_rxdma_mon_ring *buf_ring; 3254 struct ath12k_dp_link_peer *peer; 3255 struct sk_buff_head skb_list; 3256 u64 cookie; 3257 int num_buffs_reaped = 0, srng_id, buf_id; 3258 u32 hal_status, end_offset, info0, end_reason; 3259 u8 pdev_idx = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, pdev_dp->mac_id); 3260 3261 __skb_queue_head_init(&skb_list); 3262 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, pdev_idx); 3263 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; 3264 buf_ring = &dp->rxdma_mon_buf_ring; 3265 3266 srng = &ab->hal.srng_list[mon_dst_ring->ring_id]; 3267 spin_lock_bh(&srng->lock); 3268 ath12k_hal_srng_access_begin(ab, srng); 3269 3270 while (likely(*budget)) { 3271 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng); 3272 if (unlikely(!mon_dst_desc)) 3273 break; 3274 3275 /* In case of empty descriptor, the cookie in the ring descriptor 3276 * is invalid. Therefore, this entry is skipped, and ring processing 3277 * continues. 3278 */ 3279 info0 = le32_to_cpu(mon_dst_desc->info0); 3280 if (u32_get_bits(info0, HAL_MON_DEST_INFO0_EMPTY_DESC)) 3281 goto move_next; 3282 3283 cookie = le32_to_cpu(mon_dst_desc->cookie); 3284 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); 3285 3286 spin_lock_bh(&buf_ring->idr_lock); 3287 skb = idr_remove(&buf_ring->bufs_idr, buf_id); 3288 spin_unlock_bh(&buf_ring->idr_lock); 3289 3290 if (unlikely(!skb)) { 3291 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", 3292 buf_id); 3293 goto move_next; 3294 } 3295 3296 rxcb = ATH12K_SKB_RXCB(skb); 3297 dma_unmap_single(ab->dev, rxcb->paddr, 3298 skb->len + skb_tailroom(skb), 3299 DMA_FROM_DEVICE); 3300 3301 end_reason = u32_get_bits(info0, HAL_MON_DEST_INFO0_END_REASON); 3302 3303 /* HAL_MON_FLUSH_DETECTED implies that an rx flush received at the end of 3304 * rx PPDU and HAL_MON_PPDU_TRUNCATED implies that the PPDU got 3305 * truncated due to a system level error. In both the cases, buffer data 3306 * can be discarded 3307 */ 3308 if ((end_reason == HAL_MON_FLUSH_DETECTED) || 3309 (end_reason == HAL_MON_PPDU_TRUNCATED)) { 3310 ath12k_dbg(ab, ATH12K_DBG_DATA, 3311 "Monitor dest descriptor end reason %d", end_reason); 3312 dev_kfree_skb_any(skb); 3313 goto move_next; 3314 } 3315 3316 /* Calculate the budget when the ring descriptor with the 3317 * HAL_MON_END_OF_PPDU to ensure that one PPDU worth of data is always 3318 * reaped. This helps to efficiently utilize the NAPI budget. 3319 */ 3320 if (end_reason == HAL_MON_END_OF_PPDU) { 3321 *budget -= 1; 3322 rxcb->is_end_of_ppdu = true; 3323 } 3324 3325 end_offset = u32_get_bits(info0, HAL_MON_DEST_INFO0_END_OFFSET); 3326 if (likely(end_offset <= DP_RX_BUFFER_SIZE)) { 3327 skb_put(skb, end_offset); 3328 } else { 3329 ath12k_warn(ab, 3330 "invalid offset on mon stats destination %u\n", 3331 end_offset); 3332 skb_put(skb, DP_RX_BUFFER_SIZE); 3333 } 3334 3335 __skb_queue_tail(&skb_list, skb); 3336 3337 move_next: 3338 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 3339 ath12k_hal_srng_dst_get_next_entry(ab, srng); 3340 num_buffs_reaped++; 3341 } 3342 3343 ath12k_hal_srng_access_end(ab, srng); 3344 spin_unlock_bh(&srng->lock); 3345 3346 if (!num_buffs_reaped) 3347 return 0; 3348 3349 /* In some cases, one PPDU worth of data can be spread across multiple NAPI 3350 * schedules, To avoid losing existing parsed ppdu_info information, skip 3351 * the memset of the ppdu_info structure and continue processing it. 3352 */ 3353 if (!ppdu_info->ppdu_continuation) 3354 ath12k_wifi7_dp_mon_rx_memset_ppdu_info(ppdu_info); 3355 3356 while ((skb = __skb_dequeue(&skb_list))) { 3357 hal_status = ath12k_wifi7_dp_mon_rx_parse_mon_status(pdev_dp, pmon, 3358 skb, napi); 3359 if (hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 3360 ppdu_info->ppdu_continuation = true; 3361 dev_kfree_skb_any(skb); 3362 continue; 3363 } 3364 3365 if (ppdu_info->peer_id == HAL_INVALID_PEERID) 3366 goto free_skb; 3367 3368 rcu_read_lock(); 3369 peer = ath12k_dp_link_peer_find_by_peerid(pdev_dp, ppdu_info->peer_id); 3370 if (!peer || !peer->sta) { 3371 ath12k_dbg(ab, ATH12K_DBG_DATA, 3372 "failed to find the peer with monitor peer_id %d\n", 3373 ppdu_info->peer_id); 3374 goto next_skb; 3375 } 3376 3377 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) { 3378 ath12k_dp_mon_rx_update_peer_su_stats(peer, ppdu_info); 3379 } else if ((ppdu_info->fc_valid) && 3380 (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) { 3381 ath12k_dp_mon_rx_process_ulofdma(ppdu_info); 3382 ath12k_dp_mon_rx_update_peer_mu_stats(ab, ppdu_info); 3383 } 3384 3385 next_skb: 3386 rcu_read_unlock(); 3387 free_skb: 3388 dev_kfree_skb_any(skb); 3389 ath12k_wifi7_dp_mon_rx_memset_ppdu_info(ppdu_info); 3390 } 3391 3392 return num_buffs_reaped; 3393 } 3394 3395 int ath12k_wifi7_dp_mon_process_ring(struct ath12k_dp *dp, int mac_id, 3396 struct napi_struct *napi, int budget, 3397 enum dp_monitor_mode monitor_mode) 3398 { 3399 u8 pdev_idx = ath12k_hw_mac_id_to_pdev_id(dp->hw_params, mac_id); 3400 struct ath12k_pdev_dp *dp_pdev; 3401 struct ath12k *ar; 3402 int num_buffs_reaped = 0; 3403 3404 rcu_read_lock(); 3405 3406 dp_pdev = ath12k_dp_to_pdev_dp(dp, pdev_idx); 3407 if (!dp_pdev) { 3408 rcu_read_unlock(); 3409 return 0; 3410 } 3411 3412 if (dp->hw_params->rxdma1_enable) { 3413 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) 3414 num_buffs_reaped = ath12k_wifi7_dp_mon_srng_process(dp_pdev, 3415 &budget, 3416 napi); 3417 } else { 3418 ar = ath12k_pdev_dp_to_ar(dp_pdev); 3419 3420 if (ar->monitor_started) 3421 num_buffs_reaped = 3422 __ath12k_wifi7_dp_mon_process_ring(ar, mac_id, napi, 3423 &budget); 3424 } 3425 3426 rcu_read_unlock(); 3427 3428 return num_buffs_reaped; 3429 } 3430