xref: /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3  * Copyright 2019 Raptor Engineering, LLC
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include <linux/slab.h>
28 
29 #include "dm_services.h"
30 #include "dc.h"
31 
32 #include "dcn21/dcn21_init.h"
33 
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn21/dcn21_resource.h"
38 
39 #include "dml/dcn20/dcn20_fpu.h"
40 
41 #include "clk_mgr.h"
42 #include "dcn10/dcn10_hubp.h"
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn20/dcn20_hubbub.h"
45 #include "dcn20/dcn20_mpc.h"
46 #include "dcn20/dcn20_hubp.h"
47 #include "dcn21/dcn21_hubp.h"
48 #include "irq/dcn21/irq_service_dcn21.h"
49 #include "dcn20/dcn20_dpp.h"
50 #include "dcn20/dcn20_optc.h"
51 #include "dcn21/dcn21_hwseq.h"
52 #include "dce110/dce110_hwseq.h"
53 #include "dcn20/dcn20_opp.h"
54 #include "dcn20/dcn20_dsc.h"
55 #include "dcn21/dcn21_link_encoder.h"
56 #include "dcn20/dcn20_stream_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "virtual/virtual_stream_encoder.h"
61 #include "dml/display_mode_vba.h"
62 #include "dcn20/dcn20_dccg.h"
63 #include "dcn21/dcn21_dccg.h"
64 #include "dcn21/dcn21_hubbub.h"
65 #include "dcn10/dcn10_resource.h"
66 #include "dce/dce_panel_cntl.h"
67 
68 #include "dcn20/dcn20_dwb.h"
69 #include "dcn20/dcn20_mmhubbub.h"
70 #include "dpcs/dpcs_2_1_0_offset.h"
71 #include "dpcs/dpcs_2_1_0_sh_mask.h"
72 
73 #include "renoir_ip_offset.h"
74 #include "dcn/dcn_2_1_0_offset.h"
75 #include "dcn/dcn_2_1_0_sh_mask.h"
76 
77 #include "nbio/nbio_7_0_offset.h"
78 
79 #include "mmhub/mmhub_2_0_0_offset.h"
80 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81 
82 #include "reg_helper.h"
83 #include "dce/dce_abm.h"
84 #include "dce/dce_dmcu.h"
85 #include "dce/dce_aux.h"
86 #include "dce/dce_i2c.h"
87 #include "dcn21_resource.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "dce/dmub_psr.h"
91 #include "dce/dmub_abm.h"
92 
93 /* begin *********************
94  * macros to expend register list macro defined in HW object header file */
95 
96 /* DCN */
97 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
98 
99 #define BASE(seg) BASE_INNER(seg)
100 
101 #define SR(reg_name)\
102 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
103 					mm ## reg_name
104 
105 #define SRI(reg_name, block, id)\
106 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
107 					mm ## block ## id ## _ ## reg_name
108 
109 #define SRIR(var_name, reg_name, block, id)\
110 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
111 					mm ## block ## id ## _ ## reg_name
112 
113 #define SRII(reg_name, block, id)\
114 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
115 					mm ## block ## id ## _ ## reg_name
116 
117 #define DCCG_SRII(reg_name, block, id)\
118 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
119 					mm ## block ## id ## _ ## reg_name
120 
121 #define VUPDATE_SRII(reg_name, block, id)\
122 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
123 					mm ## reg_name ## _ ## block ## id
124 
125 /* NBIO */
126 #define NBIO_BASE_INNER(seg) \
127 	NBIF0_BASE__INST0_SEG ## seg
128 
129 #define NBIO_BASE(seg) \
130 	NBIO_BASE_INNER(seg)
131 
132 #define NBIO_SR(reg_name)\
133 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
134 					mm ## reg_name
135 
136 /* MMHUB */
137 #define MMHUB_BASE_INNER(seg) \
138 	MMHUB_BASE__INST0_SEG ## seg
139 
140 #define MMHUB_BASE(seg) \
141 	MMHUB_BASE_INNER(seg)
142 
143 #define MMHUB_SR(reg_name)\
144 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
145 					mmMM ## reg_name
146 
147 #define clk_src_regs(index, pllid)\
148 [index] = {\
149 	CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
150 }
151 
152 static const struct dce110_clk_src_regs clk_src_regs[] = {
153 	clk_src_regs(0, A),
154 	clk_src_regs(1, B),
155 	clk_src_regs(2, C),
156 	clk_src_regs(3, D),
157 	clk_src_regs(4, E),
158 };
159 
160 static const struct dce110_clk_src_shift cs_shift = {
161 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
162 };
163 
164 static const struct dce110_clk_src_mask cs_mask = {
165 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
166 };
167 
168 static const struct bios_registers bios_regs = {
169 		NBIO_SR(BIOS_SCRATCH_3),
170 		NBIO_SR(BIOS_SCRATCH_6)
171 };
172 
173 static const struct dce_dmcu_registers dmcu_regs = {
174 		DMCU_DCN20_REG_LIST()
175 };
176 
177 static const struct dce_dmcu_shift dmcu_shift = {
178 		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
179 };
180 
181 static const struct dce_dmcu_mask dmcu_mask = {
182 		DMCU_MASK_SH_LIST_DCN10(_MASK)
183 };
184 
185 static const struct dce_abm_registers abm_regs = {
186 		ABM_DCN20_REG_LIST()
187 };
188 
189 static const struct dce_abm_shift abm_shift = {
190 		ABM_MASK_SH_LIST_DCN20(__SHIFT)
191 };
192 
193 static const struct dce_abm_mask abm_mask = {
194 		ABM_MASK_SH_LIST_DCN20(_MASK)
195 };
196 
197 #define audio_regs(id)\
198 [id] = {\
199 		AUD_COMMON_REG_LIST(id)\
200 }
201 
202 static const struct dce_audio_registers audio_regs[] = {
203 	audio_regs(0),
204 	audio_regs(1),
205 	audio_regs(2),
206 	audio_regs(3),
207 	audio_regs(4),
208 	audio_regs(5),
209 };
210 
211 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
212 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
213 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
214 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
215 
216 static const struct dce_audio_shift audio_shift = {
217 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
218 };
219 
220 static const struct dce_audio_mask audio_mask = {
221 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
222 };
223 
224 static const struct dccg_registers dccg_regs = {
225 		DCCG_COMMON_REG_LIST_DCN_BASE()
226 };
227 
228 static const struct dccg_shift dccg_shift = {
229 		DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
230 };
231 
232 static const struct dccg_mask dccg_mask = {
233 		DCCG_MASK_SH_LIST_DCN2_1(_MASK)
234 };
235 
236 #define opp_regs(id)\
237 [id] = {\
238 	OPP_REG_LIST_DCN20(id),\
239 }
240 
241 static const struct dcn20_opp_registers opp_regs[] = {
242 	opp_regs(0),
243 	opp_regs(1),
244 	opp_regs(2),
245 	opp_regs(3),
246 	opp_regs(4),
247 	opp_regs(5),
248 };
249 
250 static const struct dcn20_opp_shift opp_shift = {
251 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
252 };
253 
254 static const struct dcn20_opp_mask opp_mask = {
255 		OPP_MASK_SH_LIST_DCN20(_MASK)
256 };
257 
258 #define tg_regs(id)\
259 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
260 
261 static const struct dcn_optc_registers tg_regs[] = {
262 	tg_regs(0),
263 	tg_regs(1),
264 	tg_regs(2),
265 	tg_regs(3)
266 };
267 
268 static const struct dcn_optc_shift tg_shift = {
269 	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
270 };
271 
272 static const struct dcn_optc_mask tg_mask = {
273 	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
274 };
275 
276 static const struct dcn20_mpc_registers mpc_regs = {
277 		MPC_REG_LIST_DCN2_0(0),
278 		MPC_REG_LIST_DCN2_0(1),
279 		MPC_REG_LIST_DCN2_0(2),
280 		MPC_REG_LIST_DCN2_0(3),
281 		MPC_REG_LIST_DCN2_0(4),
282 		MPC_REG_LIST_DCN2_0(5),
283 		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
284 		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
285 		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
286 		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
287 		MPC_DBG_REG_LIST_DCN2_0()
288 };
289 
290 static const struct dcn20_mpc_shift mpc_shift = {
291 	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
292 	MPC_DEBUG_REG_LIST_SH_DCN20
293 };
294 
295 static const struct dcn20_mpc_mask mpc_mask = {
296 	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
297 	MPC_DEBUG_REG_LIST_MASK_DCN20
298 };
299 
300 #define hubp_regs(id)\
301 [id] = {\
302 	HUBP_REG_LIST_DCN21(id)\
303 }
304 
305 static const struct dcn_hubp2_registers hubp_regs[] = {
306 		hubp_regs(0),
307 		hubp_regs(1),
308 		hubp_regs(2),
309 		hubp_regs(3)
310 };
311 
312 static const struct dcn_hubp2_shift hubp_shift = {
313 		HUBP_MASK_SH_LIST_DCN21(__SHIFT)
314 };
315 
316 static const struct dcn_hubp2_mask hubp_mask = {
317 		HUBP_MASK_SH_LIST_DCN21(_MASK)
318 };
319 
320 static const struct dcn_hubbub_registers hubbub_reg = {
321 		HUBBUB_REG_LIST_DCN21()
322 };
323 
324 static const struct dcn_hubbub_shift hubbub_shift = {
325 		HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
326 };
327 
328 static const struct dcn_hubbub_mask hubbub_mask = {
329 		HUBBUB_MASK_SH_LIST_DCN21(_MASK)
330 };
331 
332 
333 #define vmid_regs(id)\
334 [id] = {\
335 		DCN20_VMID_REG_LIST(id)\
336 }
337 
338 static const struct dcn_vmid_registers vmid_regs[] = {
339 	vmid_regs(0),
340 	vmid_regs(1),
341 	vmid_regs(2),
342 	vmid_regs(3),
343 	vmid_regs(4),
344 	vmid_regs(5),
345 	vmid_regs(6),
346 	vmid_regs(7),
347 	vmid_regs(8),
348 	vmid_regs(9),
349 	vmid_regs(10),
350 	vmid_regs(11),
351 	vmid_regs(12),
352 	vmid_regs(13),
353 	vmid_regs(14),
354 	vmid_regs(15)
355 };
356 
357 static const struct dcn20_vmid_shift vmid_shifts = {
358 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
359 };
360 
361 static const struct dcn20_vmid_mask vmid_masks = {
362 		DCN20_VMID_MASK_SH_LIST(_MASK)
363 };
364 
365 #define dsc_regsDCN20(id)\
366 [id] = {\
367 	DSC_REG_LIST_DCN20(id)\
368 }
369 
370 static const struct dcn20_dsc_registers dsc_regs[] = {
371 	dsc_regsDCN20(0),
372 	dsc_regsDCN20(1),
373 	dsc_regsDCN20(2),
374 	dsc_regsDCN20(3),
375 	dsc_regsDCN20(4),
376 	dsc_regsDCN20(5)
377 };
378 
379 static const struct dcn20_dsc_shift dsc_shift = {
380 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
381 };
382 
383 static const struct dcn20_dsc_mask dsc_mask = {
384 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
385 };
386 
387 #define ipp_regs(id)\
388 [id] = {\
389 	IPP_REG_LIST_DCN20(id),\
390 }
391 
392 static const struct dcn10_ipp_registers ipp_regs[] = {
393 	ipp_regs(0),
394 	ipp_regs(1),
395 	ipp_regs(2),
396 	ipp_regs(3),
397 };
398 
399 static const struct dcn10_ipp_shift ipp_shift = {
400 		IPP_MASK_SH_LIST_DCN20(__SHIFT)
401 };
402 
403 static const struct dcn10_ipp_mask ipp_mask = {
404 		IPP_MASK_SH_LIST_DCN20(_MASK),
405 };
406 
407 #define opp_regs(id)\
408 [id] = {\
409 	OPP_REG_LIST_DCN20(id),\
410 }
411 
412 
413 #define aux_engine_regs(id)\
414 [id] = {\
415 	AUX_COMMON_REG_LIST0(id), \
416 	.AUXN_IMPCAL = 0, \
417 	.AUXP_IMPCAL = 0, \
418 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
419 }
420 
421 static const struct dce110_aux_registers aux_engine_regs[] = {
422 		aux_engine_regs(0),
423 		aux_engine_regs(1),
424 		aux_engine_regs(2),
425 		aux_engine_regs(3),
426 		aux_engine_regs(4),
427 };
428 
429 #define tf_regs(id)\
430 [id] = {\
431 	TF_REG_LIST_DCN20(id),\
432 	TF_REG_LIST_DCN20_COMMON_APPEND(id),\
433 }
434 
435 static const struct dcn2_dpp_registers tf_regs[] = {
436 	tf_regs(0),
437 	tf_regs(1),
438 	tf_regs(2),
439 	tf_regs(3),
440 };
441 
442 static const struct dcn2_dpp_shift tf_shift = {
443 		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
444 		TF_DEBUG_REG_LIST_SH_DCN20
445 };
446 
447 static const struct dcn2_dpp_mask tf_mask = {
448 		TF_REG_LIST_SH_MASK_DCN20(_MASK),
449 		TF_DEBUG_REG_LIST_MASK_DCN20
450 };
451 
452 #define stream_enc_regs(id)\
453 [id] = {\
454 	SE_DCN2_REG_LIST(id)\
455 }
456 
457 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
458 	stream_enc_regs(0),
459 	stream_enc_regs(1),
460 	stream_enc_regs(2),
461 	stream_enc_regs(3),
462 	stream_enc_regs(4),
463 };
464 
465 static const struct dce110_aux_registers_shift aux_shift = {
466 	DCN_AUX_MASK_SH_LIST(__SHIFT)
467 };
468 
469 static const struct dce110_aux_registers_mask aux_mask = {
470 	DCN_AUX_MASK_SH_LIST(_MASK)
471 };
472 
473 static const struct dcn10_stream_encoder_shift se_shift = {
474 		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
475 };
476 
477 static const struct dcn10_stream_encoder_mask se_mask = {
478 		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
479 };
480 
481 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
482 
dcn21_ipp_create(struct dc_context * ctx,uint32_t inst)483 static struct input_pixel_processor *dcn21_ipp_create(
484 	struct dc_context *ctx, uint32_t inst)
485 {
486 	struct dcn10_ipp *ipp =
487 		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
488 
489 	if (!ipp) {
490 		BREAK_TO_DEBUGGER();
491 		return NULL;
492 	}
493 
494 	dcn20_ipp_construct(ipp, ctx, inst,
495 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
496 	return &ipp->base;
497 }
498 
dcn21_dpp_create(struct dc_context * ctx,uint32_t inst)499 static struct dpp *dcn21_dpp_create(
500 	struct dc_context *ctx,
501 	uint32_t inst)
502 {
503 	struct dcn20_dpp *dpp =
504 		kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
505 
506 	if (!dpp)
507 		return NULL;
508 
509 	if (dpp2_construct(dpp, ctx, inst,
510 			&tf_regs[inst], &tf_shift, &tf_mask))
511 		return &dpp->base;
512 
513 	BREAK_TO_DEBUGGER();
514 	kfree(dpp);
515 	return NULL;
516 }
517 
dcn21_aux_engine_create(struct dc_context * ctx,uint32_t inst)518 static struct dce_aux *dcn21_aux_engine_create(
519 	struct dc_context *ctx,
520 	uint32_t inst)
521 {
522 	struct aux_engine_dce110 *aux_engine =
523 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
524 
525 	if (!aux_engine)
526 		return NULL;
527 
528 	dce110_aux_engine_construct(aux_engine, ctx, inst,
529 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
530 				    &aux_engine_regs[inst],
531 					&aux_mask,
532 					&aux_shift,
533 					ctx->dc->caps.extended_aux_timeout_support);
534 
535 	return &aux_engine->base;
536 }
537 
538 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
539 
540 static const struct dce_i2c_registers i2c_hw_regs[] = {
541 		i2c_inst_regs(1),
542 		i2c_inst_regs(2),
543 		i2c_inst_regs(3),
544 		i2c_inst_regs(4),
545 		i2c_inst_regs(5),
546 };
547 
548 static const struct dce_i2c_shift i2c_shifts = {
549 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
550 };
551 
552 static const struct dce_i2c_mask i2c_masks = {
553 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
554 };
555 
dcn21_i2c_hw_create(struct dc_context * ctx,uint32_t inst)556 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
557 					      uint32_t inst)
558 {
559 	struct dce_i2c_hw *dce_i2c_hw =
560 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
561 
562 	if (!dce_i2c_hw)
563 		return NULL;
564 
565 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
566 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
567 
568 	return dce_i2c_hw;
569 }
570 
571 static const struct resource_caps res_cap_rn = {
572 		.num_timing_generator = 4,
573 		.num_opp = 4,
574 		.num_video_plane = 4,
575 		.num_audio = 4, // 4 audio endpoints.  4 audio streams
576 		.num_stream_encoder = 5,
577 		.num_pll = 5,  // maybe 3 because the last two used for USB-c
578 		.num_dwb = 1,
579 		.num_ddc = 5,
580 		.num_vmid = 16,
581 		.num_dsc = 3,
582 };
583 
584 static const struct dc_plane_cap plane_cap = {
585 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
586 	.per_pixel_alpha = true,
587 
588 	.pixel_format_support = {
589 			.argb8888 = true,
590 			.nv12 = true,
591 			.fp16 = true,
592 			.p010 = true
593 	},
594 
595 	.max_upscale_factor = {
596 			.argb8888 = 16000,
597 			.nv12 = 16000,
598 			.fp16 = 16000
599 	},
600 
601 	.max_downscale_factor = {
602 			.argb8888 = 250,
603 			.nv12 = 250,
604 			.fp16 = 250
605 	},
606 	64,
607 	64
608 };
609 
610 static const struct dc_debug_options debug_defaults_drv = {
611 		.disable_dmcu = false,
612 		.force_abm_enable = false,
613 		.clock_trace = true,
614 		.disable_pplib_clock_request = true,
615 		.min_disp_clk_khz = 100000,
616 		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
617 		.force_single_disp_pipe_split = false,
618 		.disable_dcc = DCC_ENABLE,
619 		.vsr_support = true,
620 		.performance_trace = false,
621 		.max_downscale_src_width = 4096,
622 		.disable_pplib_wm_range = false,
623 		.scl_reset_length10 = true,
624 		.sanity_checks = true,
625 		.disable_48mhz_pwrdwn = false,
626 		.usbc_combo_phy_reset_wa = true,
627 		.dmub_command_table = true,
628 		.use_max_lb = true,
629 		.enable_legacy_fast_update = true,
630 		.using_dml2 = false,
631 };
632 
633 static const struct dc_panel_config panel_config_defaults = {
634 		.psr = {
635 			.disable_psr = false,
636 			.disallow_psrsu = false,
637 			.disallow_replay = false,
638 		},
639 		.ilr = {
640 			.optimize_edp_link_rate = true,
641 		},
642 };
643 
644 enum dcn20_clk_src_array_id {
645 	DCN20_CLK_SRC_PLL0,
646 	DCN20_CLK_SRC_PLL1,
647 	DCN20_CLK_SRC_PLL2,
648 	DCN20_CLK_SRC_PLL3,
649 	DCN20_CLK_SRC_PLL4,
650 	DCN20_CLK_SRC_TOTAL_DCN21
651 };
652 
dcn21_resource_destruct(struct dcn21_resource_pool * pool)653 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
654 {
655 	unsigned int i;
656 
657 	for (i = 0; i < pool->base.stream_enc_count; i++) {
658 		if (pool->base.stream_enc[i] != NULL) {
659 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
660 			pool->base.stream_enc[i] = NULL;
661 		}
662 	}
663 
664 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
665 		if (pool->base.dscs[i] != NULL)
666 			dcn20_dsc_destroy(&pool->base.dscs[i]);
667 	}
668 
669 	if (pool->base.mpc != NULL) {
670 		kfree(TO_DCN20_MPC(pool->base.mpc));
671 		pool->base.mpc = NULL;
672 	}
673 	if (pool->base.hubbub != NULL) {
674 		kfree(pool->base.hubbub);
675 		pool->base.hubbub = NULL;
676 	}
677 	for (i = 0; i < pool->base.pipe_count; i++) {
678 		if (pool->base.dpps[i] != NULL)
679 			dcn20_dpp_destroy(&pool->base.dpps[i]);
680 
681 		if (pool->base.ipps[i] != NULL)
682 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
683 
684 		if (pool->base.hubps[i] != NULL) {
685 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
686 			pool->base.hubps[i] = NULL;
687 		}
688 
689 		if (pool->base.irqs != NULL)
690 			dal_irq_service_destroy(&pool->base.irqs);
691 	}
692 
693 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
694 		if (pool->base.engines[i] != NULL)
695 			dce110_engine_destroy(&pool->base.engines[i]);
696 		if (pool->base.hw_i2cs[i] != NULL) {
697 			kfree(pool->base.hw_i2cs[i]);
698 			pool->base.hw_i2cs[i] = NULL;
699 		}
700 		if (pool->base.sw_i2cs[i] != NULL) {
701 			kfree(pool->base.sw_i2cs[i]);
702 			pool->base.sw_i2cs[i] = NULL;
703 		}
704 	}
705 
706 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
707 		if (pool->base.opps[i] != NULL)
708 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
709 	}
710 
711 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
712 		if (pool->base.timing_generators[i] != NULL)	{
713 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
714 			pool->base.timing_generators[i] = NULL;
715 		}
716 	}
717 
718 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
719 		if (pool->base.dwbc[i] != NULL) {
720 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
721 			pool->base.dwbc[i] = NULL;
722 		}
723 		if (pool->base.mcif_wb[i] != NULL) {
724 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
725 			pool->base.mcif_wb[i] = NULL;
726 		}
727 	}
728 
729 	for (i = 0; i < pool->base.audio_count; i++) {
730 		if (pool->base.audios[i])
731 			dce_aud_destroy(&pool->base.audios[i]);
732 	}
733 
734 	for (i = 0; i < pool->base.clk_src_count; i++) {
735 		if (pool->base.clock_sources[i] != NULL) {
736 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
737 			pool->base.clock_sources[i] = NULL;
738 		}
739 	}
740 
741 	if (pool->base.dp_clock_source != NULL) {
742 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
743 		pool->base.dp_clock_source = NULL;
744 	}
745 
746 	if (pool->base.abm != NULL) {
747 		if (pool->base.abm->ctx->dc->config.disable_dmcu)
748 			dmub_abm_destroy(&pool->base.abm);
749 		else
750 			dce_abm_destroy(&pool->base.abm);
751 	}
752 
753 	if (pool->base.dmcu != NULL)
754 		dce_dmcu_destroy(&pool->base.dmcu);
755 
756 	if (pool->base.psr != NULL)
757 		dmub_psr_destroy(&pool->base.psr);
758 
759 	if (pool->base.dccg != NULL)
760 		dcn_dccg_destroy(&pool->base.dccg);
761 
762 	if (pool->base.pp_smu != NULL)
763 		dcn21_pp_smu_destroy(&pool->base.pp_smu);
764 }
765 
dcn21_fast_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * pipe_split_from,int * vlevel_out,bool fast_validate)766 bool dcn21_fast_validate_bw(struct dc *dc,
767 			    struct dc_state *context,
768 			    display_e2e_pipe_params_st *pipes,
769 			    int *pipe_cnt_out,
770 			    int *pipe_split_from,
771 			    int *vlevel_out,
772 			    bool fast_validate)
773 {
774 	bool out = false;
775 	int split[MAX_PIPES] = { 0 };
776 	bool merge[MAX_PIPES] = { false };
777 	int pipe_cnt, i, pipe_idx, vlevel;
778 
779 	ASSERT(pipes);
780 	if (!pipes)
781 		return false;
782 
783 	dcn20_merge_pipes_for_validate(dc, context);
784 
785 	DC_FP_START();
786 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
787 	DC_FP_END();
788 
789 	*pipe_cnt_out = pipe_cnt;
790 
791 	if (!pipe_cnt) {
792 		out = true;
793 		goto validate_out;
794 	}
795 	/*
796 	 * DML favors voltage over p-state, but we're more interested in
797 	 * supporting p-state over voltage. We can't support p-state in
798 	 * prefetch mode > 0 so try capping the prefetch mode to start.
799 	 */
800 	context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
801 				dm_allow_self_refresh_and_mclk_switch;
802 	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
803 
804 	if (vlevel > context->bw_ctx.dml.soc.num_states) {
805 		/*
806 		 * If mode is unsupported or there's still no p-state support then
807 		 * fall back to favoring voltage.
808 		 *
809 		 * We don't actually support prefetch mode 2, so require that we
810 		 * at least support prefetch mode 1.
811 		 */
812 		context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
813 					dm_allow_self_refresh;
814 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
815 		if (vlevel > context->bw_ctx.dml.soc.num_states)
816 			goto validate_fail;
817 	}
818 
819 	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
820 
821 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
822 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
823 		struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
824 		struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
825 
826 		if (!pipe->stream)
827 			continue;
828 
829 		/* We only support full screen mpo with ODM */
830 		if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
831 				&& pipe->plane_state && mpo_pipe
832 				&& memcmp(&mpo_pipe->plane_state->clip_rect,
833 						&pipe->stream->src,
834 						sizeof(struct rect)) != 0) {
835 			ASSERT(mpo_pipe->plane_state != pipe->plane_state);
836 			goto validate_fail;
837 		}
838 		pipe_idx++;
839 	}
840 
841 	/*initialize pipe_just_split_from to invalid idx*/
842 	for (i = 0; i < MAX_PIPES; i++)
843 		pipe_split_from[i] = -1;
844 
845 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
846 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
847 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
848 
849 		if (!pipe->stream || pipe_split_from[i] >= 0)
850 			continue;
851 
852 		pipe_idx++;
853 
854 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
855 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
856 			ASSERT(hsplit_pipe);
857 			if (!dcn20_split_stream_for_odm(
858 					dc, &context->res_ctx,
859 					pipe, hsplit_pipe))
860 				goto validate_fail;
861 			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
862 			dcn20_build_mapped_resource(dc, context, pipe->stream);
863 		}
864 
865 		if (!pipe->plane_state)
866 			continue;
867 		/* Skip 2nd half of already split pipe */
868 		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
869 			continue;
870 
871 		if (split[i] == 2) {
872 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
873 				/* pipe not split previously needs split */
874 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
875 				ASSERT(hsplit_pipe);
876 				if (!hsplit_pipe) {
877 					DC_FP_START();
878 					dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
879 					DC_FP_END();
880 					continue;
881 				}
882 				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
883 					if (!dcn20_split_stream_for_odm(
884 							dc, &context->res_ctx,
885 							pipe, hsplit_pipe))
886 						goto validate_fail;
887 					dcn20_build_mapped_resource(dc, context, pipe->stream);
888 				} else {
889 					dcn20_split_stream_for_mpc(
890 							&context->res_ctx, dc->res_pool,
891 							pipe, hsplit_pipe);
892 					resource_build_scaling_params(pipe);
893 					resource_build_scaling_params(hsplit_pipe);
894 				}
895 				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
896 			}
897 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
898 			/* merge should already have been done */
899 			ASSERT(0);
900 		}
901 	}
902 	/* Actual dsc count per stream dsc validation*/
903 	if (!dcn20_validate_dsc(dc, context)) {
904 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
905 				DML_FAIL_DSC_VALIDATION_FAILURE;
906 		goto validate_fail;
907 	}
908 
909 	*vlevel_out = vlevel;
910 
911 	out = true;
912 	goto validate_out;
913 
914 validate_fail:
915 	out = false;
916 
917 validate_out:
918 	return out;
919 }
920 
921 /*
922  * Some of the functions further below use the FPU, so we need to wrap this
923  * with DC_FP_START()/DC_FP_END(). Use the same approach as for
924  * dcn20_validate_bandwidth in dcn20_resource.c.
925  */
dcn21_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)926 static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
927 		bool fast_validate)
928 {
929 	bool voltage_supported;
930 	display_e2e_pipe_params_st *pipes;
931 
932 	pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
933 	if (!pipes)
934 		return false;
935 
936 	DC_FP_START();
937 	voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate, pipes);
938 	DC_FP_END();
939 
940 	kfree(pipes);
941 	return voltage_supported;
942 }
943 
dcn21_destroy_resource_pool(struct resource_pool ** pool)944 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
945 {
946 	struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
947 
948 	dcn21_resource_destruct(dcn21_pool);
949 	kfree(dcn21_pool);
950 	*pool = NULL;
951 }
952 
dcn21_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)953 static struct clock_source *dcn21_clock_source_create(
954 		struct dc_context *ctx,
955 		struct dc_bios *bios,
956 		enum clock_source_id id,
957 		const struct dce110_clk_src_regs *regs,
958 		bool dp_clk_src)
959 {
960 	struct dce110_clk_src *clk_src =
961 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
962 
963 	if (!clk_src)
964 		return NULL;
965 
966 	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
967 			regs, &cs_shift, &cs_mask)) {
968 		clk_src->base.dp_clk_src = dp_clk_src;
969 		return &clk_src->base;
970 	}
971 
972 	kfree(clk_src);
973 	BREAK_TO_DEBUGGER();
974 	return NULL;
975 }
976 
dcn21_hubp_create(struct dc_context * ctx,uint32_t inst)977 static struct hubp *dcn21_hubp_create(
978 	struct dc_context *ctx,
979 	uint32_t inst)
980 {
981 	struct dcn21_hubp *hubp21 =
982 		kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
983 
984 	if (!hubp21)
985 		return NULL;
986 
987 	if (hubp21_construct(hubp21, ctx, inst,
988 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
989 		return &hubp21->base;
990 
991 	BREAK_TO_DEBUGGER();
992 	kfree(hubp21);
993 	return NULL;
994 }
995 
dcn21_hubbub_create(struct dc_context * ctx)996 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
997 {
998 	int i;
999 
1000 	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1001 					  GFP_KERNEL);
1002 
1003 	if (!hubbub)
1004 		return NULL;
1005 
1006 	hubbub21_construct(hubbub, ctx,
1007 			&hubbub_reg,
1008 			&hubbub_shift,
1009 			&hubbub_mask);
1010 
1011 	for (i = 0; i < res_cap_rn.num_vmid; i++) {
1012 		struct dcn20_vmid *vmid = &hubbub->vmid[i];
1013 
1014 		vmid->ctx = ctx;
1015 
1016 		vmid->regs = &vmid_regs[i];
1017 		vmid->shifts = &vmid_shifts;
1018 		vmid->masks = &vmid_masks;
1019 	}
1020 	hubbub->num_vmid = res_cap_rn.num_vmid;
1021 
1022 	return &hubbub->base;
1023 }
1024 
dcn21_opp_create(struct dc_context * ctx,uint32_t inst)1025 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1026 						       uint32_t inst)
1027 {
1028 	struct dcn20_opp *opp =
1029 		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1030 
1031 	if (!opp) {
1032 		BREAK_TO_DEBUGGER();
1033 		return NULL;
1034 	}
1035 
1036 	dcn20_opp_construct(opp, ctx, inst,
1037 			&opp_regs[inst], &opp_shift, &opp_mask);
1038 	return &opp->base;
1039 }
1040 
dcn21_timing_generator_create(struct dc_context * ctx,uint32_t instance)1041 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1042 							      uint32_t instance)
1043 {
1044 	struct optc *tgn10 =
1045 		kzalloc(sizeof(struct optc), GFP_KERNEL);
1046 
1047 	if (!tgn10)
1048 		return NULL;
1049 
1050 	tgn10->base.inst = instance;
1051 	tgn10->base.ctx = ctx;
1052 
1053 	tgn10->tg_regs = &tg_regs[instance];
1054 	tgn10->tg_shift = &tg_shift;
1055 	tgn10->tg_mask = &tg_mask;
1056 
1057 	dcn20_timing_generator_init(tgn10);
1058 
1059 	return &tgn10->base;
1060 }
1061 
dcn21_mpc_create(struct dc_context * ctx)1062 static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1063 {
1064 	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1065 					  GFP_KERNEL);
1066 
1067 	if (!mpc20)
1068 		return NULL;
1069 
1070 	dcn20_mpc_construct(mpc20, ctx,
1071 			&mpc_regs,
1072 			&mpc_shift,
1073 			&mpc_mask,
1074 			6);
1075 
1076 	return &mpc20->base;
1077 }
1078 
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1079 static void read_dce_straps(
1080 	struct dc_context *ctx,
1081 	struct resource_straps *straps)
1082 {
1083 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1084 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1085 
1086 }
1087 
1088 
dcn21_dsc_create(struct dc_context * ctx,uint32_t inst)1089 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1090 							  uint32_t inst)
1091 {
1092 	struct dcn20_dsc *dsc =
1093 		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1094 
1095 	if (!dsc) {
1096 		BREAK_TO_DEBUGGER();
1097 		return NULL;
1098 	}
1099 
1100 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1101 	return &dsc->base;
1102 }
1103 
dcn21_pp_smu_create(struct dc_context * ctx)1104 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1105 {
1106 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1107 
1108 	if (!pp_smu)
1109 		return pp_smu;
1110 
1111 	dm_pp_get_funcs(ctx, pp_smu);
1112 
1113 	if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1114 		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1115 
1116 
1117 	return pp_smu;
1118 }
1119 
dcn21_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)1120 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1121 {
1122 	if (pp_smu && *pp_smu) {
1123 		kfree(*pp_smu);
1124 		*pp_smu = NULL;
1125 	}
1126 }
1127 
dcn21_create_audio(struct dc_context * ctx,unsigned int inst)1128 static struct audio *dcn21_create_audio(
1129 		struct dc_context *ctx, unsigned int inst)
1130 {
1131 	return dce_audio_create(ctx, inst,
1132 			&audio_regs[inst], &audio_shift, &audio_mask);
1133 }
1134 
1135 static struct dc_cap_funcs cap_funcs = {
1136 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1137 };
1138 
dcn21_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1139 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1140 							  struct dc_context *ctx)
1141 {
1142 	struct dcn10_stream_encoder *enc1 =
1143 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1144 
1145 	if (!enc1)
1146 		return NULL;
1147 
1148 	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1149 					&stream_enc_regs[eng_id],
1150 					&se_shift, &se_mask);
1151 
1152 	return &enc1->base;
1153 }
1154 
1155 static const struct dce_hwseq_registers hwseq_reg = {
1156 		HWSEQ_DCN21_REG_LIST()
1157 };
1158 
1159 static const struct dce_hwseq_shift hwseq_shift = {
1160 		HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1161 };
1162 
1163 static const struct dce_hwseq_mask hwseq_mask = {
1164 		HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1165 };
1166 
dcn21_hwseq_create(struct dc_context * ctx)1167 static struct dce_hwseq *dcn21_hwseq_create(
1168 	struct dc_context *ctx)
1169 {
1170 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1171 
1172 	if (hws) {
1173 		hws->ctx = ctx;
1174 		hws->regs = &hwseq_reg;
1175 		hws->shifts = &hwseq_shift;
1176 		hws->masks = &hwseq_mask;
1177 		hws->wa.DEGVIDCN21 = true;
1178 		hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1179 	}
1180 	return hws;
1181 }
1182 
1183 static const struct resource_create_funcs res_create_funcs = {
1184 	.read_dce_straps = read_dce_straps,
1185 	.create_audio = dcn21_create_audio,
1186 	.create_stream_encoder = dcn21_stream_encoder_create,
1187 	.create_hwseq = dcn21_hwseq_create,
1188 };
1189 
1190 static const struct encoder_feature_support link_enc_feature = {
1191 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1192 		.max_hdmi_pixel_clock = 600000,
1193 		.hdmi_ycbcr420_supported = true,
1194 		.dp_ycbcr420_supported = true,
1195 		.fec_supported = true,
1196 		.flags.bits.IS_HBR2_CAPABLE = true,
1197 		.flags.bits.IS_HBR3_CAPABLE = true,
1198 		.flags.bits.IS_TPS3_CAPABLE = true,
1199 		.flags.bits.IS_TPS4_CAPABLE = true
1200 };
1201 
1202 
1203 #define link_regs(id, phyid)\
1204 [id] = {\
1205 	LE_DCN2_REG_LIST(id), \
1206 	UNIPHY_DCN2_REG_LIST(phyid), \
1207 	DPCS_DCN21_REG_LIST(id), \
1208 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1209 }
1210 
1211 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1212 	link_regs(0, A),
1213 	link_regs(1, B),
1214 	link_regs(2, C),
1215 	link_regs(3, D),
1216 	link_regs(4, E),
1217 };
1218 
1219 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1220 	{ DCN_PANEL_CNTL_REG_LIST() }
1221 };
1222 
1223 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1224 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1225 };
1226 
1227 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1228 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1229 };
1230 
1231 #define aux_regs(id)\
1232 [id] = {\
1233 	DCN2_AUX_REG_LIST(id)\
1234 }
1235 
1236 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1237 		aux_regs(0),
1238 		aux_regs(1),
1239 		aux_regs(2),
1240 		aux_regs(3),
1241 		aux_regs(4)
1242 };
1243 
1244 #define hpd_regs(id)\
1245 [id] = {\
1246 	HPD_REG_LIST(id)\
1247 }
1248 
1249 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1250 		hpd_regs(0),
1251 		hpd_regs(1),
1252 		hpd_regs(2),
1253 		hpd_regs(3),
1254 		hpd_regs(4)
1255 };
1256 
1257 static const struct dcn10_link_enc_shift le_shift = {
1258 	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1259 	DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1260 };
1261 
1262 static const struct dcn10_link_enc_mask le_mask = {
1263 	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1264 	DPCS_DCN21_MASK_SH_LIST(_MASK)
1265 };
1266 
map_transmitter_id_to_phy_instance(enum transmitter transmitter)1267 static int map_transmitter_id_to_phy_instance(
1268 	enum transmitter transmitter)
1269 {
1270 	switch (transmitter) {
1271 	case TRANSMITTER_UNIPHY_A:
1272 		return 0;
1273 	break;
1274 	case TRANSMITTER_UNIPHY_B:
1275 		return 1;
1276 	break;
1277 	case TRANSMITTER_UNIPHY_C:
1278 		return 2;
1279 	break;
1280 	case TRANSMITTER_UNIPHY_D:
1281 		return 3;
1282 	break;
1283 	case TRANSMITTER_UNIPHY_E:
1284 		return 4;
1285 	break;
1286 	default:
1287 		ASSERT(0);
1288 		return 0;
1289 	}
1290 }
1291 
dcn21_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1292 static struct link_encoder *dcn21_link_encoder_create(
1293 	struct dc_context *ctx,
1294 	const struct encoder_init_data *enc_init_data)
1295 {
1296 	struct dcn21_link_encoder *enc21 =
1297 		kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1298 	int link_regs_id;
1299 
1300 	if (!enc21 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1301 		return NULL;
1302 
1303 	link_regs_id =
1304 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1305 
1306 	dcn21_link_encoder_construct(enc21,
1307 				      enc_init_data,
1308 				      &link_enc_feature,
1309 				      &link_enc_regs[link_regs_id],
1310 				      &link_enc_aux_regs[enc_init_data->channel - 1],
1311 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
1312 				      &le_shift,
1313 				      &le_mask);
1314 
1315 	return &enc21->enc10.base;
1316 }
1317 
dcn21_panel_cntl_create(const struct panel_cntl_init_data * init_data)1318 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1319 {
1320 	struct dce_panel_cntl *panel_cntl =
1321 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1322 
1323 	if (!panel_cntl)
1324 		return NULL;
1325 
1326 	dce_panel_cntl_construct(panel_cntl,
1327 			init_data,
1328 			&panel_cntl_regs[init_data->inst],
1329 			&panel_cntl_shift,
1330 			&panel_cntl_mask);
1331 
1332 	return &panel_cntl->base;
1333 }
1334 
dcn21_get_panel_config_defaults(struct dc_panel_config * panel_config)1335 static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config)
1336 {
1337 	*panel_config = panel_config_defaults;
1338 }
1339 
1340 #define CTX ctx
1341 
1342 #define REG(reg_name) \
1343 	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1344 
read_pipe_fuses(struct dc_context * ctx)1345 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1346 {
1347 	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1348 	/* RV1 support max 4 pipes */
1349 	value = value & 0xf;
1350 	return value;
1351 }
1352 
dcn21_patch_unknown_plane_state(struct dc_plane_state * plane_state)1353 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1354 {
1355 	if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1356 		plane_state->dcc.enable = 1;
1357 		/* align to our worst case block width */
1358 		plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1359 	}
1360 
1361 	return dcn20_patch_unknown_plane_state(plane_state);
1362 }
1363 
1364 static const struct resource_funcs dcn21_res_pool_funcs = {
1365 	.destroy = dcn21_destroy_resource_pool,
1366 	.link_enc_create = dcn21_link_encoder_create,
1367 	.panel_cntl_create = dcn21_panel_cntl_create,
1368 	.validate_bandwidth = dcn21_validate_bandwidth,
1369 	.populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1370 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
1371 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1372 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1373 	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1374 	.release_pipe = dcn20_release_pipe,
1375 	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1376 	.patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1377 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
1378 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1379 	.update_bw_bounding_box = dcn21_update_bw_bounding_box,
1380 	.get_panel_config_defaults = dcn21_get_panel_config_defaults,
1381 };
1382 
dcn21_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn21_resource_pool * pool)1383 static bool dcn21_resource_construct(
1384 	uint8_t num_virtual_links,
1385 	struct dc *dc,
1386 	struct dcn21_resource_pool *pool)
1387 {
1388 	int i, j;
1389 	struct dc_context *ctx = dc->ctx;
1390 	struct irq_service_init_data init_data;
1391 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1392 	uint32_t num_pipes = 0;
1393 
1394 	ctx->dc_bios->regs = &bios_regs;
1395 
1396 	pool->base.res_cap = &res_cap_rn;
1397 
1398 	pool->base.funcs = &dcn21_res_pool_funcs;
1399 
1400 	/*************************************************
1401 	 *  Resource + asic cap harcoding                *
1402 	 *************************************************/
1403 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1404 
1405 	/* max pipe num for ASIC before check pipe fuses */
1406 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1407 
1408 	dc->caps.max_downscale_ratio = 200;
1409 	dc->caps.i2c_speed_in_khz = 100;
1410 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1411 	dc->caps.max_cursor_size = 256;
1412 	dc->caps.min_horizontal_blanking_period = 80;
1413 	dc->caps.dmdata_alloc_size = 2048;
1414 
1415 	dc->caps.max_slave_planes = 1;
1416 	dc->caps.max_slave_yuv_planes = 1;
1417 	dc->caps.max_slave_rgb_planes = 1;
1418 	dc->caps.post_blend_color_processing = true;
1419 	dc->caps.force_dp_tps4_for_cp2520 = true;
1420 	dc->caps.extended_aux_timeout_support = true;
1421 	dc->caps.dmcub_support = true;
1422 	dc->caps.is_apu = true;
1423 
1424 	/* Color pipeline capabilities */
1425 	dc->caps.color.dpp.dcn_arch = 1;
1426 	dc->caps.color.dpp.input_lut_shared = 0;
1427 	dc->caps.color.dpp.icsc = 1;
1428 	dc->caps.color.dpp.dgam_ram = 1;
1429 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1430 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1431 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1432 	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1433 	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1434 	dc->caps.color.dpp.post_csc = 0;
1435 	dc->caps.color.dpp.gamma_corr = 0;
1436 	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1437 
1438 	dc->caps.color.dpp.hw_3d_lut = 1;
1439 	dc->caps.color.dpp.ogam_ram = 1;
1440 	// no OGAM ROM on DCN2
1441 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1442 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1443 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1444 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1445 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1446 	dc->caps.color.dpp.ocsc = 0;
1447 
1448 	dc->caps.color.mpc.gamut_remap = 0;
1449 	dc->caps.color.mpc.num_3dluts = 0;
1450 	dc->caps.color.mpc.shared_3d_lut = 0;
1451 	dc->caps.color.mpc.ogam_ram = 1;
1452 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1453 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1454 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1455 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1456 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1457 	dc->caps.color.mpc.ocsc = 1;
1458 
1459 	dc->caps.dp_hdmi21_pcon_support = true;
1460 
1461 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1462 		dc->debug = debug_defaults_drv;
1463 
1464 	// Init the vm_helper
1465 	if (dc->vm_helper)
1466 		vm_helper_init(dc->vm_helper, 16);
1467 
1468 	/*************************************************
1469 	 *  Create resources                             *
1470 	 *************************************************/
1471 
1472 	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1473 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1474 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1475 				&clk_src_regs[0], false);
1476 	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1477 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1478 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1479 				&clk_src_regs[1], false);
1480 	pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1481 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1482 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1483 				&clk_src_regs[2], false);
1484 	pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1485 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1486 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1487 				&clk_src_regs[3], false);
1488 	pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1489 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1490 				CLOCK_SOURCE_COMBO_PHY_PLL4,
1491 				&clk_src_regs[4], false);
1492 
1493 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1494 
1495 	/* todo: not reuse phy_pll registers */
1496 	pool->base.dp_clock_source =
1497 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1498 				CLOCK_SOURCE_ID_DP_DTO,
1499 				&clk_src_regs[0], true);
1500 
1501 	for (i = 0; i < pool->base.clk_src_count; i++) {
1502 		if (pool->base.clock_sources[i] == NULL) {
1503 			dm_error("DC: failed to create clock sources!\n");
1504 			BREAK_TO_DEBUGGER();
1505 			goto create_fail;
1506 		}
1507 	}
1508 
1509 	pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1510 	if (pool->base.dccg == NULL) {
1511 		dm_error("DC: failed to create dccg!\n");
1512 		BREAK_TO_DEBUGGER();
1513 		goto create_fail;
1514 	}
1515 
1516 	if (!dc->config.disable_dmcu) {
1517 		pool->base.dmcu = dcn21_dmcu_create(ctx,
1518 				&dmcu_regs,
1519 				&dmcu_shift,
1520 				&dmcu_mask);
1521 		if (pool->base.dmcu == NULL) {
1522 			dm_error("DC: failed to create dmcu!\n");
1523 			BREAK_TO_DEBUGGER();
1524 			goto create_fail;
1525 		}
1526 
1527 		dc->debug.dmub_command_table = false;
1528 	}
1529 
1530 	if (dc->config.disable_dmcu) {
1531 		pool->base.psr = dmub_psr_create(ctx);
1532 
1533 		if (pool->base.psr == NULL) {
1534 			dm_error("DC: failed to create psr obj!\n");
1535 			BREAK_TO_DEBUGGER();
1536 			goto create_fail;
1537 		}
1538 	}
1539 
1540 	if (dc->config.disable_dmcu)
1541 		pool->base.abm = dmub_abm_create(ctx,
1542 			&abm_regs,
1543 			&abm_shift,
1544 			&abm_mask);
1545 	else
1546 		pool->base.abm = dce_abm_create(ctx,
1547 			&abm_regs,
1548 			&abm_shift,
1549 			&abm_mask);
1550 
1551 	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1552 
1553 	num_pipes = dcn2_1_ip.max_num_dpp;
1554 
1555 	for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1556 		if (pipe_fuses & 1 << i)
1557 			num_pipes--;
1558 	dcn2_1_ip.max_num_dpp = num_pipes;
1559 	dcn2_1_ip.max_num_otg = num_pipes;
1560 
1561 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1562 
1563 	init_data.ctx = dc->ctx;
1564 	pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1565 	if (!pool->base.irqs)
1566 		goto create_fail;
1567 
1568 	j = 0;
1569 	/* mem input -> ipp -> dpp -> opp -> TG */
1570 	for (i = 0; i < pool->base.pipe_count; i++) {
1571 		/* if pipe is disabled, skip instance of HW pipe,
1572 		 * i.e, skip ASIC register instance
1573 		 */
1574 		if ((pipe_fuses & (1 << i)) != 0)
1575 			continue;
1576 
1577 		pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1578 		if (pool->base.hubps[j] == NULL) {
1579 			BREAK_TO_DEBUGGER();
1580 			dm_error(
1581 				"DC: failed to create memory input!\n");
1582 			goto create_fail;
1583 		}
1584 
1585 		pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1586 		if (pool->base.ipps[j] == NULL) {
1587 			BREAK_TO_DEBUGGER();
1588 			dm_error(
1589 				"DC: failed to create input pixel processor!\n");
1590 			goto create_fail;
1591 		}
1592 
1593 		pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1594 		if (pool->base.dpps[j] == NULL) {
1595 			BREAK_TO_DEBUGGER();
1596 			dm_error(
1597 				"DC: failed to create dpps!\n");
1598 			goto create_fail;
1599 		}
1600 
1601 		pool->base.opps[j] = dcn21_opp_create(ctx, i);
1602 		if (pool->base.opps[j] == NULL) {
1603 			BREAK_TO_DEBUGGER();
1604 			dm_error(
1605 				"DC: failed to create output pixel processor!\n");
1606 			goto create_fail;
1607 		}
1608 
1609 		pool->base.timing_generators[j] = dcn21_timing_generator_create(
1610 				ctx, i);
1611 		if (pool->base.timing_generators[j] == NULL) {
1612 			BREAK_TO_DEBUGGER();
1613 			dm_error("DC: failed to create tg!\n");
1614 			goto create_fail;
1615 		}
1616 		j++;
1617 	}
1618 
1619 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1620 		pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1621 		if (pool->base.engines[i] == NULL) {
1622 			BREAK_TO_DEBUGGER();
1623 			dm_error(
1624 				"DC:failed to create aux engine!!\n");
1625 			goto create_fail;
1626 		}
1627 		pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1628 		if (pool->base.hw_i2cs[i] == NULL) {
1629 			BREAK_TO_DEBUGGER();
1630 			dm_error(
1631 				"DC:failed to create hw i2c!!\n");
1632 			goto create_fail;
1633 		}
1634 		pool->base.sw_i2cs[i] = NULL;
1635 	}
1636 
1637 	pool->base.timing_generator_count = j;
1638 	pool->base.pipe_count = j;
1639 	pool->base.mpcc_count = j;
1640 
1641 	pool->base.mpc = dcn21_mpc_create(ctx);
1642 	if (pool->base.mpc == NULL) {
1643 		BREAK_TO_DEBUGGER();
1644 		dm_error("DC: failed to create mpc!\n");
1645 		goto create_fail;
1646 	}
1647 
1648 	pool->base.hubbub = dcn21_hubbub_create(ctx);
1649 	if (pool->base.hubbub == NULL) {
1650 		BREAK_TO_DEBUGGER();
1651 		dm_error("DC: failed to create hubbub!\n");
1652 		goto create_fail;
1653 	}
1654 
1655 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1656 		pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1657 		if (pool->base.dscs[i] == NULL) {
1658 			BREAK_TO_DEBUGGER();
1659 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1660 			goto create_fail;
1661 		}
1662 	}
1663 
1664 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
1665 		BREAK_TO_DEBUGGER();
1666 		dm_error("DC: failed to create dwbc!\n");
1667 		goto create_fail;
1668 	}
1669 	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1670 		BREAK_TO_DEBUGGER();
1671 		dm_error("DC: failed to create mcif_wb!\n");
1672 		goto create_fail;
1673 	}
1674 
1675 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1676 			&res_create_funcs))
1677 		goto create_fail;
1678 
1679 	dcn21_hw_sequencer_construct(dc);
1680 
1681 	dc->caps.max_planes =  pool->base.pipe_count;
1682 
1683 	for (i = 0; i < dc->caps.max_planes; ++i)
1684 		dc->caps.planes[i] = plane_cap;
1685 
1686 	dc->cap_funcs = cap_funcs;
1687 
1688 	return true;
1689 
1690 create_fail:
1691 
1692 	dcn21_resource_destruct(pool);
1693 
1694 	return false;
1695 }
1696 
dcn21_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1697 struct resource_pool *dcn21_create_resource_pool(
1698 		const struct dc_init_data *init_data,
1699 		struct dc *dc)
1700 {
1701 	struct dcn21_resource_pool *pool =
1702 		kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1703 
1704 	if (!pool)
1705 		return NULL;
1706 
1707 	if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1708 		return &pool->base;
1709 
1710 	BREAK_TO_DEBUGGER();
1711 	kfree(pool);
1712 	return NULL;
1713 }
1714