1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #include <linux/etherdevice.h>
9 #include <net/ip.h>
10 #include <net/tso.h>
11 #include <linux/bpf.h>
12 #include <linux/bpf_trace.h>
13 #include <net/ip6_checksum.h>
14
15 #include "otx2_reg.h"
16 #include "otx2_common.h"
17 #include "otx2_struct.h"
18 #include "otx2_txrx.h"
19 #include "otx2_ptp.h"
20 #include "cn10k.h"
21
22 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx)))
23 #define PTP_PORT 0x13F
24 /* PTPv2 header Original Timestamp starts at byte offset 34 and
25 * contains 6 byte seconds field and 4 byte nano seconds field.
26 */
27 #define PTP_SYNC_SEC_OFFSET 34
28
29 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf,
30 struct bpf_prog *prog,
31 struct nix_cqe_rx_s *cqe,
32 struct otx2_cq_queue *cq,
33 bool *need_xdp_flush);
34
otx2_nix_cq_op_status(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)35 static int otx2_nix_cq_op_status(struct otx2_nic *pfvf,
36 struct otx2_cq_queue *cq)
37 {
38 u64 incr = (u64)(cq->cq_idx) << 32;
39 u64 status;
40
41 status = otx2_atomic64_fetch_add(incr, pfvf->cq_op_addr);
42
43 if (unlikely(status & BIT_ULL(CQ_OP_STAT_OP_ERR) ||
44 status & BIT_ULL(CQ_OP_STAT_CQ_ERR))) {
45 dev_err(pfvf->dev, "CQ stopped due to error");
46 return -EINVAL;
47 }
48
49 cq->cq_tail = status & 0xFFFFF;
50 cq->cq_head = (status >> 20) & 0xFFFFF;
51 if (cq->cq_tail < cq->cq_head)
52 cq->pend_cqe = (cq->cqe_cnt - cq->cq_head) +
53 cq->cq_tail;
54 else
55 cq->pend_cqe = cq->cq_tail - cq->cq_head;
56
57 return 0;
58 }
59
otx2_get_next_cqe(struct otx2_cq_queue * cq)60 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq)
61 {
62 struct nix_cqe_hdr_s *cqe_hdr;
63
64 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head);
65 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID)
66 return NULL;
67
68 cq->cq_head++;
69 cq->cq_head &= (cq->cqe_cnt - 1);
70
71 return cqe_hdr;
72 }
73
frag_num(unsigned int i)74 static unsigned int frag_num(unsigned int i)
75 {
76 #ifdef __BIG_ENDIAN
77 return (i & ~3) + 3 - (i & 3);
78 #else
79 return i;
80 #endif
81 }
82
otx2_dma_map_skb_frag(struct otx2_nic * pfvf,struct sk_buff * skb,int seg,int * len)83 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf,
84 struct sk_buff *skb, int seg, int *len)
85 {
86 const skb_frag_t *frag;
87 struct page *page;
88 int offset;
89
90 /* First segment is always skb->data */
91 if (!seg) {
92 page = virt_to_page(skb->data);
93 offset = offset_in_page(skb->data);
94 *len = skb_headlen(skb);
95 } else {
96 frag = &skb_shinfo(skb)->frags[seg - 1];
97 page = skb_frag_page(frag);
98 offset = skb_frag_off(frag);
99 *len = skb_frag_size(frag);
100 }
101 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE);
102 }
103
otx2_dma_unmap_skb_frags(struct otx2_nic * pfvf,struct sg_list * sg)104 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg)
105 {
106 int seg;
107
108 for (seg = 0; seg < sg->num_segs; seg++) {
109 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg],
110 sg->size[seg], DMA_TO_DEVICE);
111 }
112 sg->num_segs = 0;
113 }
114
otx2_xdp_snd_pkt_handler(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct nix_cqe_tx_s * cqe)115 static void otx2_xdp_snd_pkt_handler(struct otx2_nic *pfvf,
116 struct otx2_snd_queue *sq,
117 struct nix_cqe_tx_s *cqe)
118 {
119 struct nix_send_comp_s *snd_comp = &cqe->comp;
120 struct sg_list *sg;
121 struct page *page;
122 u64 pa;
123
124 sg = &sq->sg[snd_comp->sqe_id];
125
126 pa = otx2_iova_to_phys(pfvf->iommu_domain, sg->dma_addr[0]);
127 otx2_dma_unmap_page(pfvf, sg->dma_addr[0],
128 sg->size[0], DMA_TO_DEVICE);
129 page = virt_to_page(phys_to_virt(pa));
130 put_page(page);
131 }
132
otx2_snd_pkt_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,struct otx2_snd_queue * sq,struct nix_cqe_tx_s * cqe,int budget,int * tx_pkts,int * tx_bytes)133 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf,
134 struct otx2_cq_queue *cq,
135 struct otx2_snd_queue *sq,
136 struct nix_cqe_tx_s *cqe,
137 int budget, int *tx_pkts, int *tx_bytes)
138 {
139 struct nix_send_comp_s *snd_comp = &cqe->comp;
140 struct skb_shared_hwtstamps ts;
141 struct sk_buff *skb = NULL;
142 u64 timestamp, tsns;
143 struct sg_list *sg;
144 int err;
145
146 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf))
147 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n",
148 pfvf->netdev->name, cq->cint_idx,
149 snd_comp->status);
150
151 sg = &sq->sg[snd_comp->sqe_id];
152 skb = (struct sk_buff *)sg->skb;
153 if (unlikely(!skb))
154 return;
155
156 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) {
157 timestamp = ((u64 *)sq->timestamps->base)[snd_comp->sqe_id];
158 if (timestamp != 1) {
159 timestamp = pfvf->ptp->convert_tx_ptp_tstmp(timestamp);
160 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
161 if (!err) {
162 memset(&ts, 0, sizeof(ts));
163 ts.hwtstamp = ns_to_ktime(tsns);
164 skb_tstamp_tx(skb, &ts);
165 }
166 }
167 }
168
169 *tx_bytes += skb->len;
170 (*tx_pkts)++;
171 otx2_dma_unmap_skb_frags(pfvf, sg);
172 napi_consume_skb(skb, budget);
173 sg->skb = (u64)NULL;
174 }
175
otx2_set_rxtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,void * data)176 static void otx2_set_rxtstamp(struct otx2_nic *pfvf,
177 struct sk_buff *skb, void *data)
178 {
179 u64 timestamp, tsns;
180 int err;
181
182 if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED))
183 return;
184
185 timestamp = pfvf->ptp->convert_rx_ptp_tstmp(*(u64 *)data);
186 /* The first 8 bytes is the timestamp */
187 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
188 if (err)
189 return;
190
191 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns);
192 }
193
otx2_skb_add_frag(struct otx2_nic * pfvf,struct sk_buff * skb,u64 iova,int len,struct nix_rx_parse_s * parse,int qidx)194 static bool otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb,
195 u64 iova, int len, struct nix_rx_parse_s *parse,
196 int qidx)
197 {
198 struct page *page;
199 int off = 0;
200 void *va;
201
202 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova));
203
204 if (likely(!skb_shinfo(skb)->nr_frags)) {
205 /* Check if data starts at some nonzero offset
206 * from the start of the buffer. For now the
207 * only possible offset is 8 bytes in the case
208 * where packet is prepended by a timestamp.
209 */
210 if (parse->laptr) {
211 otx2_set_rxtstamp(pfvf, skb, va);
212 off = OTX2_HW_TIMESTAMP_LEN;
213 }
214 }
215
216 page = virt_to_page(va);
217 if (likely(skb_shinfo(skb)->nr_frags < MAX_SKB_FRAGS)) {
218 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
219 va - page_address(page) + off,
220 len - off, pfvf->rbsize);
221 return true;
222 }
223
224 /* If more than MAX_SKB_FRAGS fragments are received then
225 * give back those buffer pointers to hardware for reuse.
226 */
227 pfvf->hw_ops->aura_freeptr(pfvf, qidx, iova & ~0x07ULL);
228
229 return false;
230 }
231
otx2_set_rxhash(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,struct sk_buff * skb)232 static void otx2_set_rxhash(struct otx2_nic *pfvf,
233 struct nix_cqe_rx_s *cqe, struct sk_buff *skb)
234 {
235 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE;
236 struct otx2_rss_info *rss;
237 u32 hash = 0;
238
239 if (!(pfvf->netdev->features & NETIF_F_RXHASH))
240 return;
241
242 rss = &pfvf->hw.rss_info;
243 if (rss->flowkey_cfg) {
244 if (rss->flowkey_cfg &
245 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6))
246 hash_type = PKT_HASH_TYPE_L4;
247 else
248 hash_type = PKT_HASH_TYPE_L3;
249 hash = cqe->hdr.flow_tag;
250 }
251 skb_set_hash(skb, hash, hash_type);
252 }
253
otx2_free_rcv_seg(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)254 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe,
255 int qidx)
256 {
257 struct nix_rx_sg_s *sg = &cqe->sg;
258 void *end, *start;
259 u64 *seg_addr;
260 int seg;
261
262 start = (void *)sg;
263 end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
264 while (start < end) {
265 sg = (struct nix_rx_sg_s *)start;
266 seg_addr = &sg->seg_addr;
267 for (seg = 0; seg < sg->segs; seg++, seg_addr++)
268 pfvf->hw_ops->aura_freeptr(pfvf, qidx,
269 *seg_addr & ~0x07ULL);
270 start += sizeof(*sg);
271 }
272 }
273
otx2_check_rcv_errors(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)274 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf,
275 struct nix_cqe_rx_s *cqe, int qidx)
276 {
277 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats;
278 struct nix_rx_parse_s *parse = &cqe->parse;
279
280 if (netif_msg_rx_err(pfvf))
281 netdev_err(pfvf->netdev,
282 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n",
283 qidx, parse->errlev, parse->errcode);
284
285 if (parse->errlev == NPC_ERRLVL_RE) {
286 switch (parse->errcode) {
287 case ERRCODE_FCS:
288 case ERRCODE_FCS_RCV:
289 atomic_inc(&stats->rx_fcs_errs);
290 break;
291 case ERRCODE_UNDERSIZE:
292 atomic_inc(&stats->rx_undersize_errs);
293 break;
294 case ERRCODE_OVERSIZE:
295 atomic_inc(&stats->rx_oversize_errs);
296 break;
297 case ERRCODE_OL2_LEN_MISMATCH:
298 atomic_inc(&stats->rx_len_errs);
299 break;
300 default:
301 atomic_inc(&stats->rx_other_errs);
302 break;
303 }
304 } else if (parse->errlev == NPC_ERRLVL_NIX) {
305 switch (parse->errcode) {
306 case ERRCODE_OL3_LEN:
307 case ERRCODE_OL4_LEN:
308 case ERRCODE_IL3_LEN:
309 case ERRCODE_IL4_LEN:
310 atomic_inc(&stats->rx_len_errs);
311 break;
312 case ERRCODE_OL4_CSUM:
313 case ERRCODE_IL4_CSUM:
314 atomic_inc(&stats->rx_csum_errs);
315 break;
316 default:
317 atomic_inc(&stats->rx_other_errs);
318 break;
319 }
320 } else {
321 atomic_inc(&stats->rx_other_errs);
322 /* For now ignore all the NPC parser errors and
323 * pass the packets to stack.
324 */
325 return false;
326 }
327
328 /* If RXALL is enabled pass on packets to stack. */
329 if (pfvf->netdev->features & NETIF_F_RXALL)
330 return false;
331
332 /* Free buffer back to pool */
333 if (cqe->sg.segs)
334 otx2_free_rcv_seg(pfvf, cqe, qidx);
335 return true;
336 }
337
otx2_rcv_pkt_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,struct nix_cqe_rx_s * cqe,bool * need_xdp_flush)338 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf,
339 struct napi_struct *napi,
340 struct otx2_cq_queue *cq,
341 struct nix_cqe_rx_s *cqe, bool *need_xdp_flush)
342 {
343 struct nix_rx_parse_s *parse = &cqe->parse;
344 struct nix_rx_sg_s *sg = &cqe->sg;
345 struct sk_buff *skb = NULL;
346 void *end, *start;
347 u64 *seg_addr;
348 u16 *seg_size;
349 int seg;
350
351 if (unlikely(parse->errlev || parse->errcode)) {
352 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx))
353 return;
354 }
355
356 if (pfvf->xdp_prog)
357 if (otx2_xdp_rcv_pkt_handler(pfvf, pfvf->xdp_prog, cqe, cq, need_xdp_flush))
358 return;
359
360 skb = napi_get_frags(napi);
361 if (unlikely(!skb))
362 return;
363
364 start = (void *)sg;
365 end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
366 while (start < end) {
367 sg = (struct nix_rx_sg_s *)start;
368 seg_addr = &sg->seg_addr;
369 seg_size = (void *)sg;
370 for (seg = 0; seg < sg->segs; seg++, seg_addr++) {
371 if (otx2_skb_add_frag(pfvf, skb, *seg_addr,
372 seg_size[seg], parse, cq->cq_idx))
373 cq->pool_ptrs++;
374 }
375 start += sizeof(*sg);
376 }
377 otx2_set_rxhash(pfvf, cqe, skb);
378
379 if (!(pfvf->flags & OTX2_FLAG_REP_MODE_ENABLED)) {
380 skb_record_rx_queue(skb, cq->cq_idx);
381 if (pfvf->netdev->features & NETIF_F_RXCSUM)
382 skb->ip_summed = CHECKSUM_UNNECESSARY;
383 }
384
385 if (pfvf->flags & OTX2_FLAG_TC_MARK_ENABLED)
386 skb->mark = parse->match_id;
387
388 skb_mark_for_recycle(skb);
389
390 napi_gro_frags(napi);
391 }
392
otx2_rx_napi_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,int budget)393 static int otx2_rx_napi_handler(struct otx2_nic *pfvf,
394 struct napi_struct *napi,
395 struct otx2_cq_queue *cq, int budget)
396 {
397 bool need_xdp_flush = false;
398 struct nix_cqe_rx_s *cqe;
399 int processed_cqe = 0;
400
401 if (cq->pend_cqe >= budget)
402 goto process_cqe;
403
404 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
405 return 0;
406
407 process_cqe:
408 while (likely(processed_cqe < budget) && cq->pend_cqe) {
409 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head);
410 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID ||
411 !cqe->sg.seg_addr) {
412 if (!processed_cqe)
413 return 0;
414 break;
415 }
416 cq->cq_head++;
417 cq->cq_head &= (cq->cqe_cnt - 1);
418
419 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe, &need_xdp_flush);
420
421 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
422 cqe->sg.seg_addr = 0x00;
423 processed_cqe++;
424 cq->pend_cqe--;
425 }
426 if (need_xdp_flush)
427 xdp_do_flush();
428
429 /* Free CQEs to HW */
430 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
431 ((u64)cq->cq_idx << 32) | processed_cqe);
432
433 return processed_cqe;
434 }
435
otx2_refill_pool_ptrs(void * dev,struct otx2_cq_queue * cq)436 int otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq)
437 {
438 struct otx2_nic *pfvf = dev;
439 int cnt = cq->pool_ptrs;
440 dma_addr_t bufptr;
441
442 while (cq->pool_ptrs) {
443 if (otx2_alloc_buffer(pfvf, cq, &bufptr))
444 break;
445 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM);
446 cq->pool_ptrs--;
447 }
448
449 return cnt - cq->pool_ptrs;
450 }
451
otx2_tx_napi_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,int budget)452 static int otx2_tx_napi_handler(struct otx2_nic *pfvf,
453 struct otx2_cq_queue *cq, int budget)
454 {
455 int tx_pkts = 0, tx_bytes = 0, qidx;
456 struct otx2_snd_queue *sq;
457 struct nix_cqe_tx_s *cqe;
458 struct net_device *ndev;
459 int processed_cqe = 0;
460
461 if (cq->pend_cqe >= budget)
462 goto process_cqe;
463
464 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
465 return 0;
466
467 process_cqe:
468 qidx = cq->cq_idx - pfvf->hw.rx_queues;
469 sq = &pfvf->qset.sq[qidx];
470
471 while (likely(processed_cqe < budget) && cq->pend_cqe) {
472 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
473 if (unlikely(!cqe)) {
474 if (!processed_cqe)
475 return 0;
476 break;
477 }
478
479 qidx = cq->cq_idx - pfvf->hw.rx_queues;
480
481 if (cq->cq_type == CQ_XDP)
482 otx2_xdp_snd_pkt_handler(pfvf, sq, cqe);
483 else
484 otx2_snd_pkt_handler(pfvf, cq, &pfvf->qset.sq[qidx],
485 cqe, budget, &tx_pkts, &tx_bytes);
486
487 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
488 processed_cqe++;
489 cq->pend_cqe--;
490
491 sq->cons_head++;
492 sq->cons_head &= (sq->sqe_cnt - 1);
493 }
494
495 /* Free CQEs to HW */
496 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
497 ((u64)cq->cq_idx << 32) | processed_cqe);
498
499 #if IS_ENABLED(CONFIG_RVU_ESWITCH)
500 if (pfvf->flags & OTX2_FLAG_REP_MODE_ENABLED)
501 ndev = pfvf->reps[qidx]->netdev;
502 else
503 #endif
504 ndev = pfvf->netdev;
505
506 if (likely(tx_pkts)) {
507 struct netdev_queue *txq;
508
509 qidx = cq->cq_idx - pfvf->hw.rx_queues;
510
511 if (qidx >= pfvf->hw.tx_queues)
512 qidx -= pfvf->hw.xdp_queues;
513 if (pfvf->flags & OTX2_FLAG_REP_MODE_ENABLED)
514 qidx = 0;
515 txq = netdev_get_tx_queue(ndev, qidx);
516 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
517 /* Check if queue was stopped earlier due to ring full */
518 smp_mb();
519 if (netif_tx_queue_stopped(txq) &&
520 netif_carrier_ok(ndev))
521 netif_tx_wake_queue(txq);
522 }
523 return 0;
524 }
525
otx2_adjust_adaptive_coalese(struct otx2_nic * pfvf,struct otx2_cq_poll * cq_poll)526 static void otx2_adjust_adaptive_coalese(struct otx2_nic *pfvf, struct otx2_cq_poll *cq_poll)
527 {
528 struct dim_sample dim_sample = { 0 };
529 u64 rx_frames, rx_bytes;
530 u64 tx_frames, tx_bytes;
531
532 rx_frames = OTX2_GET_RX_STATS(RX_BCAST) + OTX2_GET_RX_STATS(RX_MCAST) +
533 OTX2_GET_RX_STATS(RX_UCAST);
534 rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
535 tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
536 tx_frames = OTX2_GET_TX_STATS(TX_UCAST);
537
538 dim_update_sample(pfvf->napi_events,
539 rx_frames + tx_frames,
540 rx_bytes + tx_bytes,
541 &dim_sample);
542 net_dim(&cq_poll->dim, &dim_sample);
543 }
544
otx2_napi_handler(struct napi_struct * napi,int budget)545 int otx2_napi_handler(struct napi_struct *napi, int budget)
546 {
547 struct otx2_cq_queue *rx_cq = NULL;
548 struct otx2_cq_poll *cq_poll;
549 int workdone = 0, cq_idx, i;
550 struct otx2_cq_queue *cq;
551 struct otx2_qset *qset;
552 struct otx2_nic *pfvf;
553 int filled_cnt = -1;
554
555 cq_poll = container_of(napi, struct otx2_cq_poll, napi);
556 pfvf = (struct otx2_nic *)cq_poll->dev;
557 qset = &pfvf->qset;
558
559 for (i = 0; i < CQS_PER_CINT; i++) {
560 cq_idx = cq_poll->cq_ids[i];
561 if (unlikely(cq_idx == CINT_INVALID_CQ))
562 continue;
563 cq = &qset->cq[cq_idx];
564 if (cq->cq_type == CQ_RX) {
565 rx_cq = cq;
566 workdone += otx2_rx_napi_handler(pfvf, napi,
567 cq, budget);
568 } else {
569 workdone += otx2_tx_napi_handler(pfvf, cq, budget);
570 }
571 }
572
573 if (rx_cq && rx_cq->pool_ptrs)
574 filled_cnt = pfvf->hw_ops->refill_pool_ptrs(pfvf, rx_cq);
575 /* Clear the IRQ */
576 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0));
577
578 if (workdone < budget && napi_complete_done(napi, workdone)) {
579 /* If interface is going down, don't re-enable IRQ */
580 if (pfvf->flags & OTX2_FLAG_INTF_DOWN)
581 return workdone;
582
583 /* Adjust irq coalese using net_dim */
584 if (pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED)
585 otx2_adjust_adaptive_coalese(pfvf, cq_poll);
586
587 if (unlikely(!filled_cnt)) {
588 struct refill_work *work;
589 struct delayed_work *dwork;
590
591 work = &pfvf->refill_wrk[cq->cq_idx];
592 dwork = &work->pool_refill_work;
593 /* Schedule a task if no other task is running */
594 if (!cq->refill_task_sched) {
595 work->napi = napi;
596 cq->refill_task_sched = true;
597 schedule_delayed_work(dwork,
598 msecs_to_jiffies(100));
599 }
600 } else {
601 /* Re-enable interrupts */
602 otx2_write64(pfvf,
603 NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx),
604 BIT_ULL(0));
605 }
606 }
607 return workdone;
608 }
609 EXPORT_SYMBOL(otx2_napi_handler);
610
otx2_sqe_flush(void * dev,struct otx2_snd_queue * sq,int size,int qidx)611 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
612 int size, int qidx)
613 {
614 u64 status;
615
616 /* Packet data stores should finish before SQE is flushed to HW */
617 dma_wmb();
618
619 do {
620 memcpy(sq->lmt_addr, sq->sqe_base, size);
621 status = otx2_lmt_flush(sq->io_addr);
622 } while (status == 0);
623
624 sq->head++;
625 sq->head &= (sq->sqe_cnt - 1);
626 }
627
628 #define MAX_SEGS_PER_SG 3
629 /* Add SQE scatter/gather subdescriptor structure */
otx2_sqe_add_sg(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int num_segs,int * offset)630 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
631 struct sk_buff *skb, int num_segs, int *offset)
632 {
633 struct nix_sqe_sg_s *sg = NULL;
634 u64 dma_addr, *iova = NULL;
635 u16 *sg_lens = NULL;
636 int seg, len;
637
638 sq->sg[sq->head].num_segs = 0;
639
640 for (seg = 0; seg < num_segs; seg++) {
641 if ((seg % MAX_SEGS_PER_SG) == 0) {
642 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
643 sg->ld_type = NIX_SEND_LDTYPE_LDD;
644 sg->subdc = NIX_SUBDC_SG;
645 sg->segs = 0;
646 sg_lens = (void *)sg;
647 iova = (void *)sg + sizeof(*sg);
648 /* Next subdc always starts at a 16byte boundary.
649 * So if sg->segs is whether 2 or 3, offset += 16bytes.
650 */
651 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
652 *offset += sizeof(*sg) + (3 * sizeof(u64));
653 else
654 *offset += sizeof(*sg) + sizeof(u64);
655 }
656 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
657 if (dma_mapping_error(pfvf->dev, dma_addr))
658 return false;
659
660 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len;
661 sg->segs++;
662 *iova++ = dma_addr;
663
664 /* Save DMA mapping info for later unmapping */
665 sq->sg[sq->head].dma_addr[seg] = dma_addr;
666 sq->sg[sq->head].size[seg] = len;
667 sq->sg[sq->head].num_segs++;
668 }
669
670 sq->sg[sq->head].skb = (u64)skb;
671 return true;
672 }
673
674 /* Add SQE extended header subdescriptor */
otx2_sqe_add_ext(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int * offset)675 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
676 struct sk_buff *skb, int *offset)
677 {
678 struct nix_sqe_ext_s *ext;
679
680 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset);
681 ext->subdc = NIX_SUBDC_EXT;
682 if (skb_shinfo(skb)->gso_size) {
683 ext->lso = 1;
684 ext->lso_sb = skb_tcp_all_headers(skb);
685 ext->lso_mps = skb_shinfo(skb)->gso_size;
686
687 /* Only TSOv4 and TSOv6 GSO offloads are supported */
688 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
689 ext->lso_format = pfvf->hw.lso_tsov4_idx;
690
691 /* HW adds payload size to 'ip_hdr->tot_len' while
692 * sending TSO segment, hence set payload length
693 * in IP header of the packet to just header length.
694 */
695 ip_hdr(skb)->tot_len =
696 htons(ext->lso_sb - skb_network_offset(skb));
697 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
698 ext->lso_format = pfvf->hw.lso_tsov6_idx;
699 ipv6_hdr(skb)->payload_len = htons(tcp_hdrlen(skb));
700 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
701 __be16 l3_proto = vlan_get_protocol(skb);
702 struct udphdr *udph = udp_hdr(skb);
703 __be16 iplen;
704
705 ext->lso_sb = skb_transport_offset(skb) +
706 sizeof(struct udphdr);
707
708 /* HW adds payload size to length fields in IP and
709 * UDP headers while segmentation, hence adjust the
710 * lengths to just header sizes.
711 */
712 iplen = htons(ext->lso_sb - skb_network_offset(skb));
713 if (l3_proto == htons(ETH_P_IP)) {
714 ip_hdr(skb)->tot_len = iplen;
715 ext->lso_format = pfvf->hw.lso_udpv4_idx;
716 } else {
717 ipv6_hdr(skb)->payload_len = iplen;
718 ext->lso_format = pfvf->hw.lso_udpv6_idx;
719 }
720
721 udph->len = htons(sizeof(struct udphdr));
722 }
723 } else if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
724 ext->tstmp = 1;
725 }
726
727 #define OTX2_VLAN_PTR_OFFSET (ETH_HLEN - ETH_TLEN)
728 if (skb_vlan_tag_present(skb)) {
729 if (skb->vlan_proto == htons(ETH_P_8021Q)) {
730 ext->vlan1_ins_ena = 1;
731 ext->vlan1_ins_ptr = OTX2_VLAN_PTR_OFFSET;
732 ext->vlan1_ins_tci = skb_vlan_tag_get(skb);
733 } else if (skb->vlan_proto == htons(ETH_P_8021AD)) {
734 ext->vlan0_ins_ena = 1;
735 ext->vlan0_ins_ptr = OTX2_VLAN_PTR_OFFSET;
736 ext->vlan0_ins_tci = skb_vlan_tag_get(skb);
737 }
738 }
739
740 *offset += sizeof(*ext);
741 }
742
otx2_sqe_add_mem(struct otx2_snd_queue * sq,int * offset,int alg,u64 iova,int ptp_offset,u64 base_ns,bool udp_csum_crt)743 static void otx2_sqe_add_mem(struct otx2_snd_queue *sq, int *offset,
744 int alg, u64 iova, int ptp_offset,
745 u64 base_ns, bool udp_csum_crt)
746 {
747 struct nix_sqe_mem_s *mem;
748
749 mem = (struct nix_sqe_mem_s *)(sq->sqe_base + *offset);
750 mem->subdc = NIX_SUBDC_MEM;
751 mem->alg = alg;
752 mem->wmem = 1; /* wait for the memory operation */
753 mem->addr = iova;
754
755 if (ptp_offset) {
756 mem->start_offset = ptp_offset;
757 mem->udp_csum_crt = !!udp_csum_crt;
758 mem->base_ns = base_ns;
759 mem->step_type = 1;
760 }
761
762 *offset += sizeof(*mem);
763 }
764
765 /* Add SQE header subdescriptor structure */
otx2_sqe_add_hdr(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct nix_sqe_hdr_s * sqe_hdr,struct sk_buff * skb,u16 qidx)766 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
767 struct nix_sqe_hdr_s *sqe_hdr,
768 struct sk_buff *skb, u16 qidx)
769 {
770 int proto = 0;
771
772 /* Check if SQE was framed before, if yes then no need to
773 * set these constants again and again.
774 */
775 if (!sqe_hdr->total) {
776 /* Don't free Tx buffers to Aura */
777 sqe_hdr->df = 1;
778 sqe_hdr->aura = sq->aura_id;
779 /* Post a CQE Tx after pkt transmission */
780 sqe_hdr->pnc = 1;
781 sqe_hdr->sq = (qidx >= pfvf->hw.tx_queues) ?
782 qidx + pfvf->hw.xdp_queues : qidx;
783 }
784 sqe_hdr->total = skb->len;
785 /* Set SQE identifier which will be used later for freeing SKB */
786 sqe_hdr->sqe_id = sq->head;
787
788 /* Offload TCP/UDP checksum to HW */
789 if (skb->ip_summed == CHECKSUM_PARTIAL) {
790 sqe_hdr->ol3ptr = skb_network_offset(skb);
791 sqe_hdr->ol4ptr = skb_transport_offset(skb);
792 /* get vlan protocol Ethertype */
793 if (eth_type_vlan(skb->protocol))
794 skb->protocol = vlan_get_protocol(skb);
795
796 if (skb->protocol == htons(ETH_P_IP)) {
797 proto = ip_hdr(skb)->protocol;
798 /* In case of TSO, HW needs this to be explicitly set.
799 * So set this always, instead of adding a check.
800 */
801 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM;
802 } else if (skb->protocol == htons(ETH_P_IPV6)) {
803 proto = ipv6_hdr(skb)->nexthdr;
804 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP6;
805 }
806
807 if (proto == IPPROTO_TCP)
808 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM;
809 else if (proto == IPPROTO_UDP)
810 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM;
811 }
812 }
813
otx2_dma_map_tso_skb(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int sqe,int hdr_len)814 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf,
815 struct otx2_snd_queue *sq,
816 struct sk_buff *skb, int sqe, int hdr_len)
817 {
818 int num_segs = skb_shinfo(skb)->nr_frags + 1;
819 struct sg_list *sg = &sq->sg[sqe];
820 u64 dma_addr;
821 int seg, len;
822
823 sg->num_segs = 0;
824
825 /* Get payload length at skb->data */
826 len = skb_headlen(skb) - hdr_len;
827
828 for (seg = 0; seg < num_segs; seg++) {
829 /* Skip skb->data, if there is no payload */
830 if (!seg && !len)
831 continue;
832 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
833 if (dma_mapping_error(pfvf->dev, dma_addr))
834 goto unmap;
835
836 /* Save DMA mapping info for later unmapping */
837 sg->dma_addr[sg->num_segs] = dma_addr;
838 sg->size[sg->num_segs] = len;
839 sg->num_segs++;
840 }
841 return 0;
842 unmap:
843 otx2_dma_unmap_skb_frags(pfvf, sg);
844 return -EINVAL;
845 }
846
otx2_tso_frag_dma_addr(struct otx2_snd_queue * sq,struct sk_buff * skb,int seg,u64 seg_addr,int hdr_len,int sqe)847 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq,
848 struct sk_buff *skb, int seg,
849 u64 seg_addr, int hdr_len, int sqe)
850 {
851 struct sg_list *sg = &sq->sg[sqe];
852 const skb_frag_t *frag;
853 int offset;
854
855 if (seg < 0)
856 return sg->dma_addr[0] + (seg_addr - (u64)skb->data);
857
858 frag = &skb_shinfo(skb)->frags[seg];
859 offset = seg_addr - (u64)skb_frag_address(frag);
860 if (skb_headlen(skb) - hdr_len)
861 seg++;
862 return sg->dma_addr[seg] + offset;
863 }
864
otx2_sqe_tso_add_sg(struct otx2_snd_queue * sq,struct sg_list * list,int * offset)865 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq,
866 struct sg_list *list, int *offset)
867 {
868 struct nix_sqe_sg_s *sg = NULL;
869 u16 *sg_lens = NULL;
870 u64 *iova = NULL;
871 int seg;
872
873 /* Add SG descriptors with buffer addresses */
874 for (seg = 0; seg < list->num_segs; seg++) {
875 if ((seg % MAX_SEGS_PER_SG) == 0) {
876 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
877 sg->ld_type = NIX_SEND_LDTYPE_LDD;
878 sg->subdc = NIX_SUBDC_SG;
879 sg->segs = 0;
880 sg_lens = (void *)sg;
881 iova = (void *)sg + sizeof(*sg);
882 /* Next subdc always starts at a 16byte boundary.
883 * So if sg->segs is whether 2 or 3, offset += 16bytes.
884 */
885 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
886 *offset += sizeof(*sg) + (3 * sizeof(u64));
887 else
888 *offset += sizeof(*sg) + sizeof(u64);
889 }
890 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg];
891 *iova++ = list->dma_addr[seg];
892 sg->segs++;
893 }
894 }
895
otx2_sq_append_tso(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)896 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
897 struct sk_buff *skb, u16 qidx)
898 {
899 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx);
900 int hdr_len, tcp_data, seg_len, pkt_len, offset;
901 struct nix_sqe_hdr_s *sqe_hdr;
902 int first_sqe = sq->head;
903 struct sg_list list;
904 struct tso_t tso;
905
906 hdr_len = tso_start(skb, &tso);
907
908 /* Map SKB's fragments to DMA.
909 * It's done here to avoid mapping for every TSO segment's packet.
910 */
911 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) {
912 dev_kfree_skb_any(skb);
913 return;
914 }
915
916 netdev_tx_sent_queue(txq, skb->len);
917
918 tcp_data = skb->len - hdr_len;
919 while (tcp_data > 0) {
920 char *hdr;
921
922 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data);
923 tcp_data -= seg_len;
924
925 /* Set SQE's SEND_HDR */
926 memset(sq->sqe_base, 0, sq->sqe_size);
927 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
928 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
929 offset = sizeof(*sqe_hdr);
930
931 /* Add TSO segment's pkt header */
932 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE);
933 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0);
934 list.dma_addr[0] =
935 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE);
936 list.size[0] = hdr_len;
937 list.num_segs = 1;
938
939 /* Add TSO segment's payload data fragments */
940 pkt_len = hdr_len;
941 while (seg_len > 0) {
942 int size;
943
944 size = min_t(int, tso.size, seg_len);
945
946 list.size[list.num_segs] = size;
947 list.dma_addr[list.num_segs] =
948 otx2_tso_frag_dma_addr(sq, skb,
949 tso.next_frag_idx - 1,
950 (u64)tso.data, hdr_len,
951 first_sqe);
952 list.num_segs++;
953 pkt_len += size;
954 seg_len -= size;
955 tso_build_data(skb, &tso, size);
956 }
957 sqe_hdr->total = pkt_len;
958 otx2_sqe_tso_add_sg(sq, &list, &offset);
959
960 /* DMA mappings and skb needs to be freed only after last
961 * TSO segment is transmitted out. So set 'PNC' only for
962 * last segment. Also point last segment's sqe_id to first
963 * segment's SQE index where skb address and DMA mappings
964 * are saved.
965 */
966 if (!tcp_data) {
967 sqe_hdr->pnc = 1;
968 sqe_hdr->sqe_id = first_sqe;
969 sq->sg[first_sqe].skb = (u64)skb;
970 } else {
971 sqe_hdr->pnc = 0;
972 }
973
974 sqe_hdr->sizem1 = (offset / 16) - 1;
975
976 /* Flush SQE to HW */
977 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
978 }
979 }
980
is_hw_tso_supported(struct otx2_nic * pfvf,struct sk_buff * skb)981 static bool is_hw_tso_supported(struct otx2_nic *pfvf,
982 struct sk_buff *skb)
983 {
984 int payload_len, last_seg_size;
985
986 if (test_bit(HW_TSO, &pfvf->hw.cap_flag))
987 return true;
988
989 /* On 96xx A0, HW TSO not supported */
990 if (!is_96xx_B0(pfvf->pdev))
991 return false;
992
993 /* HW has an issue due to which when the payload of the last LSO
994 * segment is shorter than 16 bytes, some header fields may not
995 * be correctly modified, hence don't offload such TSO segments.
996 */
997
998 payload_len = skb->len - skb_tcp_all_headers(skb);
999 last_seg_size = payload_len % skb_shinfo(skb)->gso_size;
1000 if (last_seg_size && last_seg_size < 16)
1001 return false;
1002
1003 return true;
1004 }
1005
otx2_get_sqe_count(struct otx2_nic * pfvf,struct sk_buff * skb)1006 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb)
1007 {
1008 if (!skb_shinfo(skb)->gso_size)
1009 return 1;
1010
1011 /* HW TSO */
1012 if (is_hw_tso_supported(pfvf, skb))
1013 return 1;
1014
1015 /* SW TSO */
1016 return skb_shinfo(skb)->gso_segs;
1017 }
1018
otx2_validate_network_transport(struct sk_buff * skb)1019 static bool otx2_validate_network_transport(struct sk_buff *skb)
1020 {
1021 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) ||
1022 (ipv6_hdr(skb)->nexthdr == IPPROTO_UDP)) {
1023 struct udphdr *udph = udp_hdr(skb);
1024
1025 if (udph->source == htons(PTP_PORT) &&
1026 udph->dest == htons(PTP_PORT))
1027 return true;
1028 }
1029
1030 return false;
1031 }
1032
otx2_ptp_is_sync(struct sk_buff * skb,int * offset,bool * udp_csum_crt)1033 static bool otx2_ptp_is_sync(struct sk_buff *skb, int *offset, bool *udp_csum_crt)
1034 {
1035 struct ethhdr *eth = (struct ethhdr *)(skb->data);
1036 u16 nix_offload_hlen = 0, inner_vhlen = 0;
1037 bool udp_hdr_present = false, is_sync;
1038 u8 *data = skb->data, *msgtype;
1039 __be16 proto = eth->h_proto;
1040 int network_depth = 0;
1041
1042 /* NIX is programmed to offload outer VLAN header
1043 * in case of single vlan protocol field holds Network header ETH_IP/V6
1044 * in case of stacked vlan protocol field holds Inner vlan (8100)
1045 */
1046 if (skb->dev->features & NETIF_F_HW_VLAN_CTAG_TX &&
1047 skb->dev->features & NETIF_F_HW_VLAN_STAG_TX) {
1048 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
1049 /* Get vlan protocol */
1050 proto = __vlan_get_protocol(skb, eth->h_proto, NULL);
1051 /* SKB APIs like skb_transport_offset does not include
1052 * offloaded vlan header length. Need to explicitly add
1053 * the length
1054 */
1055 nix_offload_hlen = VLAN_HLEN;
1056 inner_vhlen = VLAN_HLEN;
1057 } else if (skb->vlan_proto == htons(ETH_P_8021Q)) {
1058 nix_offload_hlen = VLAN_HLEN;
1059 }
1060 } else if (eth_type_vlan(eth->h_proto)) {
1061 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
1062 }
1063
1064 switch (ntohs(proto)) {
1065 case ETH_P_1588:
1066 if (network_depth)
1067 *offset = network_depth;
1068 else
1069 *offset = ETH_HLEN + nix_offload_hlen +
1070 inner_vhlen;
1071 break;
1072 case ETH_P_IP:
1073 case ETH_P_IPV6:
1074 if (!otx2_validate_network_transport(skb))
1075 return false;
1076
1077 *offset = nix_offload_hlen + skb_transport_offset(skb) +
1078 sizeof(struct udphdr);
1079 udp_hdr_present = true;
1080
1081 }
1082
1083 msgtype = data + *offset;
1084 /* Check PTP messageId is SYNC or not */
1085 is_sync = !(*msgtype & 0xf);
1086 if (is_sync)
1087 *udp_csum_crt = udp_hdr_present;
1088 else
1089 *offset = 0;
1090
1091 return is_sync;
1092 }
1093
otx2_set_txtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,struct otx2_snd_queue * sq,int * offset)1094 static void otx2_set_txtstamp(struct otx2_nic *pfvf, struct sk_buff *skb,
1095 struct otx2_snd_queue *sq, int *offset)
1096 {
1097 struct ethhdr *eth = (struct ethhdr *)(skb->data);
1098 struct ptpv2_tstamp *origin_tstamp;
1099 bool udp_csum_crt = false;
1100 unsigned int udphoff;
1101 struct timespec64 ts;
1102 int ptp_offset = 0;
1103 __wsum skb_csum;
1104 u64 iova;
1105
1106 if (unlikely(!skb_shinfo(skb)->gso_size &&
1107 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) {
1108 if (unlikely(pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC &&
1109 otx2_ptp_is_sync(skb, &ptp_offset, &udp_csum_crt))) {
1110 origin_tstamp = (struct ptpv2_tstamp *)
1111 ((u8 *)skb->data + ptp_offset +
1112 PTP_SYNC_SEC_OFFSET);
1113 ts = ns_to_timespec64(pfvf->ptp->tstamp);
1114 origin_tstamp->seconds_msb = htons((ts.tv_sec >> 32) & 0xffff);
1115 origin_tstamp->seconds_lsb = htonl(ts.tv_sec & 0xffffffff);
1116 origin_tstamp->nanoseconds = htonl(ts.tv_nsec);
1117 /* Point to correction field in PTP packet */
1118 ptp_offset += 8;
1119
1120 /* When user disables hw checksum, stack calculates the csum,
1121 * but it does not cover ptp timestamp which is added later.
1122 * Recalculate the checksum manually considering the timestamp.
1123 */
1124 if (udp_csum_crt) {
1125 struct udphdr *uh = udp_hdr(skb);
1126
1127 if (skb->ip_summed != CHECKSUM_PARTIAL && uh->check != 0) {
1128 udphoff = skb_transport_offset(skb);
1129 uh->check = 0;
1130 skb_csum = skb_checksum(skb, udphoff, skb->len - udphoff,
1131 0);
1132 if (ntohs(eth->h_proto) == ETH_P_IPV6)
1133 uh->check = csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1134 &ipv6_hdr(skb)->daddr,
1135 skb->len - udphoff,
1136 ipv6_hdr(skb)->nexthdr,
1137 skb_csum);
1138 else
1139 uh->check = csum_tcpudp_magic(ip_hdr(skb)->saddr,
1140 ip_hdr(skb)->daddr,
1141 skb->len - udphoff,
1142 IPPROTO_UDP,
1143 skb_csum);
1144 }
1145 }
1146 } else {
1147 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1148 }
1149 iova = sq->timestamps->iova + (sq->head * sizeof(u64));
1150 otx2_sqe_add_mem(sq, offset, NIX_SENDMEMALG_E_SETTSTMP, iova,
1151 ptp_offset, pfvf->ptp->base_ns, udp_csum_crt);
1152 } else {
1153 skb_tx_timestamp(skb);
1154 }
1155 }
1156
otx2_sq_append_skb(void * dev,struct netdev_queue * txq,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)1157 bool otx2_sq_append_skb(void *dev, struct netdev_queue *txq,
1158 struct otx2_snd_queue *sq,
1159 struct sk_buff *skb, u16 qidx)
1160 {
1161 int offset, num_segs, free_desc;
1162 struct nix_sqe_hdr_s *sqe_hdr;
1163 struct otx2_nic *pfvf = dev;
1164
1165 /* Check if there is enough room between producer
1166 * and consumer index.
1167 */
1168 free_desc = (sq->cons_head - sq->head - 1 + sq->sqe_cnt) & (sq->sqe_cnt - 1);
1169 if (free_desc < sq->sqe_thresh)
1170 return false;
1171
1172 if (free_desc < otx2_get_sqe_count(pfvf, skb))
1173 return false;
1174
1175 num_segs = skb_shinfo(skb)->nr_frags + 1;
1176
1177 /* If SKB doesn't fit in a single SQE, linearize it.
1178 * TODO: Consider adding JUMP descriptor instead.
1179 */
1180 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) {
1181 if (__skb_linearize(skb)) {
1182 dev_kfree_skb_any(skb);
1183 return true;
1184 }
1185 num_segs = skb_shinfo(skb)->nr_frags + 1;
1186 }
1187
1188 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) {
1189 /* Insert vlan tag before giving pkt to tso */
1190 if (skb_vlan_tag_present(skb)) {
1191 skb = __vlan_hwaccel_push_inside(skb);
1192 if (!skb)
1193 return true;
1194 }
1195 otx2_sq_append_tso(pfvf, sq, skb, qidx);
1196 return true;
1197 }
1198
1199 /* Set SQE's SEND_HDR.
1200 * Do not clear the first 64bit as it contains constant info.
1201 */
1202 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8);
1203 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
1204 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
1205 offset = sizeof(*sqe_hdr);
1206
1207 /* Add extended header if needed */
1208 otx2_sqe_add_ext(pfvf, sq, skb, &offset);
1209
1210 /* Add SG subdesc with data frags */
1211 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) {
1212 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]);
1213 return false;
1214 }
1215
1216 otx2_set_txtstamp(pfvf, skb, sq, &offset);
1217
1218 sqe_hdr->sizem1 = (offset / 16) - 1;
1219
1220 netdev_tx_sent_queue(txq, skb->len);
1221
1222 /* Flush SQE to HW */
1223 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
1224
1225 return true;
1226 }
1227 EXPORT_SYMBOL(otx2_sq_append_skb);
1228
otx2_cleanup_rx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,int qidx)1229 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx)
1230 {
1231 struct nix_cqe_rx_s *cqe;
1232 struct otx2_pool *pool;
1233 int processed_cqe = 0;
1234 u16 pool_id;
1235 u64 iova;
1236
1237 if (pfvf->xdp_prog)
1238 xdp_rxq_info_unreg(&cq->xdp_rxq);
1239
1240 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
1241 return;
1242
1243 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
1244 pool = &pfvf->qset.pool[pool_id];
1245
1246 while (cq->pend_cqe) {
1247 cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq);
1248 processed_cqe++;
1249 cq->pend_cqe--;
1250
1251 if (!cqe)
1252 continue;
1253 if (cqe->sg.segs > 1) {
1254 otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx);
1255 continue;
1256 }
1257 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM;
1258
1259 otx2_free_bufs(pfvf, pool, iova, pfvf->rbsize);
1260 }
1261
1262 /* Free CQEs to HW */
1263 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
1264 ((u64)cq->cq_idx << 32) | processed_cqe);
1265 }
1266
otx2_cleanup_tx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)1267 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq)
1268 {
1269 int tx_pkts = 0, tx_bytes = 0;
1270 struct sk_buff *skb = NULL;
1271 struct otx2_snd_queue *sq;
1272 struct nix_cqe_tx_s *cqe;
1273 struct netdev_queue *txq;
1274 int processed_cqe = 0;
1275 struct sg_list *sg;
1276 int qidx;
1277
1278 qidx = cq->cq_idx - pfvf->hw.rx_queues;
1279 sq = &pfvf->qset.sq[qidx];
1280
1281 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
1282 return;
1283
1284 while (cq->pend_cqe) {
1285 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
1286 processed_cqe++;
1287 cq->pend_cqe--;
1288
1289 if (!cqe)
1290 continue;
1291 sg = &sq->sg[cqe->comp.sqe_id];
1292 skb = (struct sk_buff *)sg->skb;
1293 if (skb) {
1294 tx_bytes += skb->len;
1295 tx_pkts++;
1296 otx2_dma_unmap_skb_frags(pfvf, sg);
1297 dev_kfree_skb_any(skb);
1298 sg->skb = (u64)NULL;
1299 }
1300 }
1301
1302 if (likely(tx_pkts)) {
1303 if (qidx >= pfvf->hw.tx_queues)
1304 qidx -= pfvf->hw.xdp_queues;
1305 txq = netdev_get_tx_queue(pfvf->netdev, qidx);
1306 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
1307 }
1308 /* Free CQEs to HW */
1309 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
1310 ((u64)cq->cq_idx << 32) | processed_cqe);
1311 }
1312
otx2_rxtx_enable(struct otx2_nic * pfvf,bool enable)1313 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable)
1314 {
1315 struct msg_req *msg;
1316 int err;
1317
1318 mutex_lock(&pfvf->mbox.lock);
1319 if (enable)
1320 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox);
1321 else
1322 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox);
1323
1324 if (!msg) {
1325 mutex_unlock(&pfvf->mbox.lock);
1326 return -ENOMEM;
1327 }
1328
1329 err = otx2_sync_mbox_msg(&pfvf->mbox);
1330 mutex_unlock(&pfvf->mbox.lock);
1331 return err;
1332 }
1333
otx2_free_pending_sqe(struct otx2_nic * pfvf)1334 void otx2_free_pending_sqe(struct otx2_nic *pfvf)
1335 {
1336 int tx_pkts = 0, tx_bytes = 0;
1337 struct sk_buff *skb = NULL;
1338 struct otx2_snd_queue *sq;
1339 struct netdev_queue *txq;
1340 struct sg_list *sg;
1341 int sq_idx, sqe;
1342
1343 for (sq_idx = 0; sq_idx < pfvf->hw.tx_queues; sq_idx++) {
1344 sq = &pfvf->qset.sq[sq_idx];
1345 for (sqe = 0; sqe < sq->sqe_cnt; sqe++) {
1346 sg = &sq->sg[sqe];
1347 skb = (struct sk_buff *)sg->skb;
1348 if (skb) {
1349 tx_bytes += skb->len;
1350 tx_pkts++;
1351 otx2_dma_unmap_skb_frags(pfvf, sg);
1352 dev_kfree_skb_any(skb);
1353 sg->skb = (u64)NULL;
1354 }
1355 }
1356
1357 if (!tx_pkts)
1358 continue;
1359 txq = netdev_get_tx_queue(pfvf->netdev, sq_idx);
1360 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
1361 tx_pkts = 0;
1362 tx_bytes = 0;
1363 }
1364 }
1365
otx2_xdp_sqe_add_sg(struct otx2_snd_queue * sq,u64 dma_addr,int len,int * offset)1366 static void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, u64 dma_addr,
1367 int len, int *offset)
1368 {
1369 struct nix_sqe_sg_s *sg = NULL;
1370 u64 *iova = NULL;
1371
1372 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
1373 sg->ld_type = NIX_SEND_LDTYPE_LDD;
1374 sg->subdc = NIX_SUBDC_SG;
1375 sg->segs = 1;
1376 sg->seg1_size = len;
1377 iova = (void *)sg + sizeof(*sg);
1378 *iova = dma_addr;
1379 *offset += sizeof(*sg) + sizeof(u64);
1380
1381 sq->sg[sq->head].dma_addr[0] = dma_addr;
1382 sq->sg[sq->head].size[0] = len;
1383 sq->sg[sq->head].num_segs = 1;
1384 }
1385
otx2_xdp_sq_append_pkt(struct otx2_nic * pfvf,u64 iova,int len,u16 qidx)1386 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx)
1387 {
1388 struct nix_sqe_hdr_s *sqe_hdr;
1389 struct otx2_snd_queue *sq;
1390 int offset, free_sqe;
1391
1392 sq = &pfvf->qset.sq[qidx];
1393 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb;
1394 if (free_sqe < sq->sqe_thresh)
1395 return false;
1396
1397 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8);
1398
1399 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
1400
1401 if (!sqe_hdr->total) {
1402 sqe_hdr->aura = sq->aura_id;
1403 sqe_hdr->df = 1;
1404 sqe_hdr->sq = qidx;
1405 sqe_hdr->pnc = 1;
1406 }
1407 sqe_hdr->total = len;
1408 sqe_hdr->sqe_id = sq->head;
1409
1410 offset = sizeof(*sqe_hdr);
1411
1412 otx2_xdp_sqe_add_sg(sq, iova, len, &offset);
1413 sqe_hdr->sizem1 = (offset / 16) - 1;
1414 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
1415
1416 return true;
1417 }
1418
otx2_xdp_rcv_pkt_handler(struct otx2_nic * pfvf,struct bpf_prog * prog,struct nix_cqe_rx_s * cqe,struct otx2_cq_queue * cq,bool * need_xdp_flush)1419 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf,
1420 struct bpf_prog *prog,
1421 struct nix_cqe_rx_s *cqe,
1422 struct otx2_cq_queue *cq,
1423 bool *need_xdp_flush)
1424 {
1425 unsigned char *hard_start;
1426 int qidx = cq->cq_idx;
1427 struct xdp_buff xdp;
1428 struct page *page;
1429 u64 iova, pa;
1430 u32 act;
1431 int err;
1432
1433 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM;
1434 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1435 page = virt_to_page(phys_to_virt(pa));
1436
1437 xdp_init_buff(&xdp, pfvf->rbsize, &cq->xdp_rxq);
1438
1439 hard_start = (unsigned char *)phys_to_virt(pa);
1440 xdp_prepare_buff(&xdp, hard_start, OTX2_HEAD_ROOM,
1441 cqe->sg.seg_size, false);
1442
1443 act = bpf_prog_run_xdp(prog, &xdp);
1444
1445 switch (act) {
1446 case XDP_PASS:
1447 break;
1448 case XDP_TX:
1449 qidx += pfvf->hw.tx_queues;
1450 cq->pool_ptrs++;
1451 return otx2_xdp_sq_append_pkt(pfvf, iova,
1452 cqe->sg.seg_size, qidx);
1453 case XDP_REDIRECT:
1454 cq->pool_ptrs++;
1455 err = xdp_do_redirect(pfvf->netdev, &xdp, prog);
1456
1457 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize,
1458 DMA_FROM_DEVICE);
1459 if (!err) {
1460 *need_xdp_flush = true;
1461 return true;
1462 }
1463 put_page(page);
1464 break;
1465 default:
1466 bpf_warn_invalid_xdp_action(pfvf->netdev, prog, act);
1467 break;
1468 case XDP_ABORTED:
1469 trace_xdp_exception(pfvf->netdev, prog, act);
1470 break;
1471 case XDP_DROP:
1472 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize,
1473 DMA_FROM_DEVICE);
1474 put_page(page);
1475 cq->pool_ptrs++;
1476 return true;
1477 }
1478 return false;
1479 }
1480