1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * HWMON driver for MCP998X/33 and MCP998XD/33D Multichannel Automotive
4 * Temperature Monitor Family
5 *
6 * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries
7 *
8 * Author: Victor Duicu <victor.duicu@microchip.com>
9 *
10 * Datasheet can be found here:
11 * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP998X-Family-Data-Sheet-DS20006827.pdf
12 */
13
14 #include <linux/array_size.h>
15 #include <linux/bitfield.h>
16 #include <linux/bitops.h>
17 #include <linux/bits.h>
18 #include <linux/byteorder/generic.h>
19 #include <linux/delay.h>
20 #include <linux/device/devres.h>
21 #include <linux/device.h>
22 #include <linux/dev_printk.h>
23 #include <linux/err.h>
24 #include <linux/hwmon.h>
25 #include <linux/i2c.h>
26 #include <linux/math.h>
27 #include <linux/minmax.h>
28 #include <linux/property.h>
29 #include <linux/regmap.h>
30 #include <linux/time64.h>
31 #include <linux/util_macros.h>
32
33 /* MCP9982 Registers */
34 #define MCP9982_HIGH_BYTE_ADDR(index) (2 * (index))
35 #define MCP9982_ONE_SHOT_ADDR 0x0A
36 #define MCP9982_INTERNAL_HIGH_LIMIT_ADDR 0x0B
37 #define MCP9982_INTERNAL_LOW_LIMIT_ADDR 0x0C
38 #define MCP9982_EXT_HIGH_LIMIT_ADDR(index) (4 * ((index) - 1) + 0x0D)
39 #define MCP9982_EXT_LOW_LIMIT_ADDR(index) (4 * ((index) - 1) + 0x0F)
40 #define MCP9982_THERM_LIMIT_ADDR(index) ((index) + 0x1D)
41 #define MCP9982_CFG_ADDR 0x22
42 #define MCP9982_CONV_ADDR 0x24
43 #define MCP9982_HYS_ADDR 0x25
44 #define MCP9982_CONSEC_ALRT_ADDR 0x26
45 #define MCP9982_ALRT_CFG_ADDR 0x27
46 #define MCP9982_RUNNING_AVG_ADDR 0x28
47 #define MCP9982_HOTTEST_CFG_ADDR 0x29
48 #define MCP9982_STATUS_ADDR 0x2A
49 #define MCP9982_EXT_FAULT_STATUS_ADDR 0x2B
50 #define MCP9982_HIGH_LIMIT_STATUS_ADDR 0x2C
51 #define MCP9982_LOW_LIMIT_STATUS_ADDR 0x2D
52 #define MCP9982_THERM_LIMIT_STATUS_ADDR 0x2E
53 #define MCP9982_HOTTEST_HIGH_BYTE_ADDR 0x2F
54 #define MCP9982_HOTTEST_LOW_BYTE_ADDR 0x30
55 #define MCP9982_HOTTEST_STATUS_ADDR 0x31
56 #define MCP9982_THERM_SHTDWN_CFG_ADDR 0x32
57 #define MCP9982_HRDW_THERM_SHTDWN_LIMIT_ADDR 0x33
58 #define MCP9982_EXT_BETA_CFG_ADDR(index) ((index) + 0x33)
59 #define MCP9982_EXT_IDEAL_ADDR(index) ((index) + 0x35)
60
61 /* MCP9982 Bits */
62 #define MCP9982_CFG_MSKAL BIT(7)
63 #define MCP9982_CFG_RS BIT(6)
64 #define MCP9982_CFG_ATTHM BIT(5)
65 #define MCP9982_CFG_RECD12 BIT(4)
66 #define MCP9982_CFG_RECD34 BIT(3)
67 #define MCP9982_CFG_RANGE BIT(2)
68 #define MCP9982_CFG_DA_ENA BIT(1)
69 #define MCP9982_CFG_APDD BIT(0)
70
71 #define MCP9982_STATUS_BUSY BIT(5)
72
73 /* Constants and default values */
74 #define MCP9982_MAX_NUM_CHANNELS 5
75 #define MCP9982_BETA_AUTODETECT 16
76 #define MCP9982_IDEALITY_DEFAULT 18
77 #define MCP9982_OFFSET 64
78 #define MCP9982_DEFAULT_CONSEC_ALRT_VAL 112
79 #define MCP9982_DEFAULT_HYS_VAL 10
80 #define MCP9982_DEFAULT_CONV_VAL 6
81 #define MCP9982_WAKE_UP_TIME_US 125000
82 #define MCP9982_WAKE_UP_TIME_MAX_US 130000
83 #define MCP9982_HIGH_LIMIT_DEFAULT 85000
84 #define MCP9982_LOW_LIMIT_DEFAULT 0
85
86 static const struct hwmon_channel_info * const mcp9985_info[] = {
87 HWMON_CHANNEL_INFO(temp,
88 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN |
89 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM |
90 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
91 HWMON_T_CRIT_HYST,
92 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN |
93 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM |
94 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
95 HWMON_T_CRIT_HYST | HWMON_T_FAULT,
96 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN |
97 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM |
98 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
99 HWMON_T_CRIT_HYST | HWMON_T_FAULT,
100 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN |
101 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM |
102 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
103 HWMON_T_CRIT_HYST | HWMON_T_FAULT,
104 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN |
105 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM |
106 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
107 HWMON_T_CRIT_HYST | HWMON_T_FAULT),
108 HWMON_CHANNEL_INFO(chip,
109 HWMON_C_UPDATE_INTERVAL),
110 NULL
111 };
112
113 /**
114 * struct mcp9982_features - features of a mcp9982 instance
115 * @name: chip's name
116 * @phys_channels: number of physical channels supported by the chip
117 * @hw_thermal_shutdown: presence of hardware thermal shutdown circuitry
118 * @allow_apdd: whether the chip supports enabling APDD
119 * @has_recd34: whether the chip has the channels that are affected by recd34
120 */
121 struct mcp9982_features {
122 const char *name;
123 u8 phys_channels;
124 bool hw_thermal_shutdown;
125 bool allow_apdd;
126 bool has_recd34;
127 };
128
129 static const struct mcp9982_features mcp9933_chip_config = {
130 .name = "mcp9933",
131 .phys_channels = 3,
132 .hw_thermal_shutdown = false,
133 .allow_apdd = true,
134 .has_recd34 = false,
135 };
136
137 static const struct mcp9982_features mcp9933d_chip_config = {
138 .name = "mcp9933d",
139 .phys_channels = 3,
140 .hw_thermal_shutdown = true,
141 .allow_apdd = true,
142 .has_recd34 = false,
143 };
144
145 static const struct mcp9982_features mcp9982_chip_config = {
146 .name = "mcp9982",
147 .phys_channels = 2,
148 .hw_thermal_shutdown = false,
149 .allow_apdd = false,
150 .has_recd34 = false,
151 };
152
153 static const struct mcp9982_features mcp9982d_chip_config = {
154 .name = "mcp9982d",
155 .phys_channels = 2,
156 .hw_thermal_shutdown = true,
157 .allow_apdd = false,
158 .has_recd34 = false,
159 };
160
161 static const struct mcp9982_features mcp9983_chip_config = {
162 .name = "mcp9983",
163 .phys_channels = 3,
164 .hw_thermal_shutdown = false,
165 .allow_apdd = false,
166 .has_recd34 = true,
167 };
168
169 static const struct mcp9982_features mcp9983d_chip_config = {
170 .name = "mcp9983d",
171 .phys_channels = 3,
172 .hw_thermal_shutdown = true,
173 .allow_apdd = false,
174 .has_recd34 = true,
175 };
176
177 static const struct mcp9982_features mcp9984_chip_config = {
178 .name = "mcp9984",
179 .phys_channels = 4,
180 .hw_thermal_shutdown = false,
181 .allow_apdd = true,
182 .has_recd34 = true,
183 };
184
185 static const struct mcp9982_features mcp9984d_chip_config = {
186 .name = "mcp9984d",
187 .phys_channels = 4,
188 .hw_thermal_shutdown = true,
189 .allow_apdd = true,
190 .has_recd34 = true,
191 };
192
193 static const struct mcp9982_features mcp9985_chip_config = {
194 .name = "mcp9985",
195 .phys_channels = 5,
196 .hw_thermal_shutdown = false,
197 .allow_apdd = true,
198 .has_recd34 = true,
199 };
200
201 static const struct mcp9982_features mcp9985d_chip_config = {
202 .name = "mcp9985d",
203 .phys_channels = 5,
204 .hw_thermal_shutdown = true,
205 .allow_apdd = true,
206 .has_recd34 = true,
207 };
208
209 static const unsigned int mcp9982_update_interval[11] = {
210 16000, 8000, 4000, 2000, 1000, 500, 250, 125, 64, 32, 16
211 };
212
213 /* MCP9982 regmap configuration */
214 static const struct regmap_range mcp9982_regmap_wr_ranges[] = {
215 regmap_reg_range(MCP9982_ONE_SHOT_ADDR, MCP9982_CFG_ADDR),
216 regmap_reg_range(MCP9982_CONV_ADDR, MCP9982_HOTTEST_CFG_ADDR),
217 regmap_reg_range(MCP9982_THERM_SHTDWN_CFG_ADDR, MCP9982_THERM_SHTDWN_CFG_ADDR),
218 regmap_reg_range(MCP9982_EXT_BETA_CFG_ADDR(1), MCP9982_EXT_IDEAL_ADDR(4)),
219 };
220
221 static const struct regmap_access_table mcp9982_regmap_wr_table = {
222 .yes_ranges = mcp9982_regmap_wr_ranges,
223 .n_yes_ranges = ARRAY_SIZE(mcp9982_regmap_wr_ranges),
224 };
225
226 static const struct regmap_range mcp9982_regmap_rd_ranges[] = {
227 regmap_reg_range(MCP9982_HIGH_BYTE_ADDR(0), MCP9982_CFG_ADDR),
228 regmap_reg_range(MCP9982_CONV_ADDR, MCP9982_EXT_IDEAL_ADDR(4)),
229 };
230
231 static const struct regmap_access_table mcp9982_regmap_rd_table = {
232 .yes_ranges = mcp9982_regmap_rd_ranges,
233 .n_yes_ranges = ARRAY_SIZE(mcp9982_regmap_rd_ranges),
234 };
235
mcp9982_is_volatile_reg(struct device * dev,unsigned int reg)236 static bool mcp9982_is_volatile_reg(struct device *dev, unsigned int reg)
237 {
238 switch (reg) {
239 case MCP9982_ONE_SHOT_ADDR:
240 case MCP9982_INTERNAL_HIGH_LIMIT_ADDR:
241 case MCP9982_INTERNAL_LOW_LIMIT_ADDR:
242 case MCP9982_EXT_LOW_LIMIT_ADDR(1):
243 case MCP9982_EXT_LOW_LIMIT_ADDR(1) + 1:
244 case MCP9982_EXT_LOW_LIMIT_ADDR(2):
245 case MCP9982_EXT_LOW_LIMIT_ADDR(2) + 1:
246 case MCP9982_EXT_LOW_LIMIT_ADDR(3):
247 case MCP9982_EXT_LOW_LIMIT_ADDR(3) + 1:
248 case MCP9982_EXT_LOW_LIMIT_ADDR(4):
249 case MCP9982_EXT_LOW_LIMIT_ADDR(4) + 1:
250 case MCP9982_EXT_HIGH_LIMIT_ADDR(1):
251 case MCP9982_EXT_HIGH_LIMIT_ADDR(1) + 1:
252 case MCP9982_EXT_HIGH_LIMIT_ADDR(2):
253 case MCP9982_EXT_HIGH_LIMIT_ADDR(2) + 1:
254 case MCP9982_EXT_HIGH_LIMIT_ADDR(3):
255 case MCP9982_EXT_HIGH_LIMIT_ADDR(3) + 1:
256 case MCP9982_EXT_HIGH_LIMIT_ADDR(4):
257 case MCP9982_EXT_HIGH_LIMIT_ADDR(4) + 1:
258 case MCP9982_THERM_LIMIT_ADDR(0):
259 case MCP9982_THERM_LIMIT_ADDR(1):
260 case MCP9982_THERM_LIMIT_ADDR(2):
261 case MCP9982_THERM_LIMIT_ADDR(3):
262 case MCP9982_THERM_LIMIT_ADDR(4):
263 case MCP9982_CFG_ADDR:
264 case MCP9982_CONV_ADDR:
265 case MCP9982_HYS_ADDR:
266 case MCP9982_CONSEC_ALRT_ADDR:
267 case MCP9982_ALRT_CFG_ADDR:
268 case MCP9982_RUNNING_AVG_ADDR:
269 case MCP9982_HOTTEST_CFG_ADDR:
270 case MCP9982_THERM_SHTDWN_CFG_ADDR:
271 return false;
272 default:
273 return true;
274 }
275 }
276
277 static const struct regmap_config mcp9982_regmap_config = {
278 .reg_bits = 8,
279 .val_bits = 8,
280 .rd_table = &mcp9982_regmap_rd_table,
281 .wr_table = &mcp9982_regmap_wr_table,
282 .volatile_reg = mcp9982_is_volatile_reg,
283 .max_register = MCP9982_EXT_IDEAL_ADDR(4),
284 .cache_type = REGCACHE_MAPLE,
285 };
286
287 /**
288 * struct mcp9982_priv - information about chip parameters
289 * @regmap: device register map
290 * @chip: pointer to structure holding chip features
291 * @labels: labels of the channels
292 * @interval_idx: index representing the current update interval
293 * @enabled_channel_mask: mask containing which channels should be enabled
294 * @num_channels: number of active physical channels
295 * @recd34_enable: state of Resistance Error Correction(REC) on channels 3 and 4
296 * @recd12_enable: state of Resistance Error Correction(REC) on channels 1 and 2
297 * @apdd_enable: state of anti-parallel diode mode
298 * @run_state: chip is in Run state, otherwise is in Standby state
299 */
300 struct mcp9982_priv {
301 struct regmap *regmap;
302 const struct mcp9982_features *chip;
303 const char *labels[MCP9982_MAX_NUM_CHANNELS];
304 unsigned int interval_idx;
305 unsigned long enabled_channel_mask;
306 u8 num_channels;
307 bool recd34_enable;
308 bool recd12_enable;
309 bool apdd_enable;
310 bool run_state;
311 };
312
mcp9982_read_limit(struct mcp9982_priv * priv,u8 address,long * val)313 static int mcp9982_read_limit(struct mcp9982_priv *priv, u8 address, long *val)
314 {
315 unsigned int limit, reg_high, reg_low;
316 int ret;
317
318 switch (address) {
319 case MCP9982_INTERNAL_HIGH_LIMIT_ADDR:
320 case MCP9982_INTERNAL_LOW_LIMIT_ADDR:
321 case MCP9982_THERM_LIMIT_ADDR(0):
322 case MCP9982_THERM_LIMIT_ADDR(1):
323 case MCP9982_THERM_LIMIT_ADDR(2):
324 case MCP9982_THERM_LIMIT_ADDR(3):
325 case MCP9982_THERM_LIMIT_ADDR(4):
326 ret = regmap_read(priv->regmap, address, &limit);
327 if (ret)
328 return ret;
329
330 *val = ((int)limit - MCP9982_OFFSET) * 1000;
331
332 return 0;
333 case MCP9982_EXT_HIGH_LIMIT_ADDR(1):
334 case MCP9982_EXT_HIGH_LIMIT_ADDR(2):
335 case MCP9982_EXT_HIGH_LIMIT_ADDR(3):
336 case MCP9982_EXT_HIGH_LIMIT_ADDR(4):
337 case MCP9982_EXT_LOW_LIMIT_ADDR(1):
338 case MCP9982_EXT_LOW_LIMIT_ADDR(2):
339 case MCP9982_EXT_LOW_LIMIT_ADDR(3):
340 case MCP9982_EXT_LOW_LIMIT_ADDR(4):
341 /*
342 * In order to keep consistency with reading temperature memory region we will use
343 * single byte I2C read.
344 */
345 ret = regmap_read(priv->regmap, address, ®_high);
346 if (ret)
347 return ret;
348
349 ret = regmap_read(priv->regmap, address + 1, ®_low);
350 if (ret)
351 return ret;
352
353 *val = ((reg_high << 8) + reg_low) >> 5;
354 *val = (*val - (MCP9982_OFFSET << 3)) * 125;
355
356 return 0;
357 default:
358 return -EINVAL;
359 }
360 }
361
mcp9982_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)362 static int mcp9982_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
363 long *val)
364 {
365 struct mcp9982_priv *priv = dev_get_drvdata(dev);
366 unsigned int reg_high, reg_low, hyst, reg_status;
367 int ret;
368 u8 addr;
369
370 /*
371 * In Standby State the conversion cycle must be initated manually in
372 * order to read fresh temperature values, the status of the alarms and
373 * fault information.
374 */
375 if (!priv->run_state) {
376 switch (type) {
377 case hwmon_temp:
378 switch (attr) {
379 case hwmon_temp_input:
380 case hwmon_temp_max_alarm:
381 case hwmon_temp_min_alarm:
382 case hwmon_temp_crit_alarm:
383 case hwmon_temp_fault:
384 ret = regmap_write(priv->regmap, MCP9982_ONE_SHOT_ADDR, 1);
385 if (ret)
386 return ret;
387 /*
388 * When the device is in Standby mode, 125 ms need
389 * to pass from writing in One Shot register before
390 * the conversion cycle begins.
391 */
392 usleep_range(MCP9982_WAKE_UP_TIME_US, MCP9982_WAKE_UP_TIME_MAX_US);
393 ret = regmap_read_poll_timeout
394 (priv->regmap, MCP9982_STATUS_ADDR,
395 reg_status, !(reg_status & MCP9982_STATUS_BUSY),
396 MCP9982_WAKE_UP_TIME_US,
397 MCP9982_WAKE_UP_TIME_US * 10);
398 if (ret)
399 return ret;
400 break;
401 }
402 break;
403 default:
404 break;
405 }
406 }
407
408 switch (type) {
409 /*
410 * Because the ALERT/THERM pin is set in Therm(Comparator) mode,
411 * the external diode fault status, high limit status and low
412 * limit status registers do not clear the bits after reading.
413 */
414 case hwmon_temp:
415 switch (attr) {
416 case hwmon_temp_input:
417 /*
418 * The only areas of memory that support SMBus block read are 80h->89h
419 * (temperature memory block) and 90h->97h(status memory block).
420 * In this context the read operation uses SMBus protocol and the first
421 * value returned will be the number of addresses that can be read.
422 * Temperature memory block is 10 bytes long and status memory block is 8
423 * bytes long.
424 *
425 * Depending on the read instruction used, the chip behaves differently:
426 * - regmap_bulk_read() when applied to the temperature memory block
427 * (80h->89h), the chip replies with SMBus block read, including count,
428 * additionally to the high and the low bytes. This function cannot be
429 * applied on the memory region 00h->09h(memory area which does not support
430 * block reads, returns wrong data) unless use_single_read is set in
431 * regmap_config.
432 *
433 * - regmap_multi_reg_read() when applied to the 00h->09h area uses I2C
434 * and returns only the high and low temperature bytes. When applied to
435 * the temperature memory block (80h->89h) returns the count till the end of
436 * the temperature memory block(aka SMBus count).
437 *
438 * - i2c_smbus_read_block_data() is not supported by all drivers.
439 *
440 * In order to keep consistency with reading limit memory region we will
441 * use single byte I2C read.
442 *
443 * Low register is latched when high temperature register is read.
444 */
445 ret = regmap_read(priv->regmap, MCP9982_HIGH_BYTE_ADDR(channel), ®_high);
446 if (ret)
447 return ret;
448
449 ret = regmap_read(priv->regmap, MCP9982_HIGH_BYTE_ADDR(channel) + 1,
450 ®_low);
451 if (ret)
452 return ret;
453
454 *val = ((reg_high << 8) + reg_low) >> 5;
455 *val = (*val - (MCP9982_OFFSET << 3)) * 125;
456
457 return 0;
458 case hwmon_temp_max:
459 if (channel)
460 addr = MCP9982_EXT_HIGH_LIMIT_ADDR(channel);
461 else
462 addr = MCP9982_INTERNAL_HIGH_LIMIT_ADDR;
463
464 return mcp9982_read_limit(priv, addr, val);
465 case hwmon_temp_max_alarm:
466 *val = regmap_test_bits(priv->regmap, MCP9982_HIGH_LIMIT_STATUS_ADDR,
467 BIT(channel));
468 if (*val < 0)
469 return *val;
470
471 return 0;
472 case hwmon_temp_max_hyst:
473 if (channel)
474 addr = MCP9982_EXT_HIGH_LIMIT_ADDR(channel);
475 else
476 addr = MCP9982_INTERNAL_HIGH_LIMIT_ADDR;
477 ret = mcp9982_read_limit(priv, addr, val);
478 if (ret)
479 return ret;
480
481 ret = regmap_read(priv->regmap, MCP9982_HYS_ADDR, &hyst);
482 if (ret)
483 return ret;
484
485 *val -= hyst * 1000;
486
487 return 0;
488 case hwmon_temp_min:
489 if (channel)
490 addr = MCP9982_EXT_LOW_LIMIT_ADDR(channel);
491 else
492 addr = MCP9982_INTERNAL_LOW_LIMIT_ADDR;
493
494 return mcp9982_read_limit(priv, addr, val);
495 case hwmon_temp_min_alarm:
496 *val = regmap_test_bits(priv->regmap, MCP9982_LOW_LIMIT_STATUS_ADDR,
497 BIT(channel));
498 if (*val < 0)
499 return *val;
500
501 return 0;
502 case hwmon_temp_crit:
503 return mcp9982_read_limit(priv, MCP9982_THERM_LIMIT_ADDR(channel), val);
504 case hwmon_temp_crit_alarm:
505 *val = regmap_test_bits(priv->regmap, MCP9982_THERM_LIMIT_STATUS_ADDR,
506 BIT(channel));
507 if (*val < 0)
508 return *val;
509
510 return 0;
511 case hwmon_temp_crit_hyst:
512 ret = mcp9982_read_limit(priv, MCP9982_THERM_LIMIT_ADDR(channel), val);
513 if (ret)
514 return ret;
515
516 ret = regmap_read(priv->regmap, MCP9982_HYS_ADDR, &hyst);
517 if (ret)
518 return ret;
519
520 *val -= hyst * 1000;
521
522 return 0;
523 case hwmon_temp_fault:
524 *val = regmap_test_bits(priv->regmap, MCP9982_EXT_FAULT_STATUS_ADDR,
525 BIT(channel));
526 if (*val < 0)
527 return *val;
528
529 return 0;
530 default:
531 return -EINVAL;
532 }
533 case hwmon_chip:
534 switch (attr) {
535 case hwmon_chip_update_interval:
536 *val = mcp9982_update_interval[priv->interval_idx];
537 return 0;
538 default:
539 return -EINVAL;
540 }
541 default:
542 return -EINVAL;
543 }
544 }
545
mcp9982_read_label(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)546 static int mcp9982_read_label(struct device *dev, enum hwmon_sensor_types type, u32 attr,
547 int channel, const char **str)
548 {
549 struct mcp9982_priv *priv = dev_get_drvdata(dev);
550
551 switch (type) {
552 case hwmon_temp:
553 switch (attr) {
554 case hwmon_temp_label:
555 *str = priv->labels[channel];
556 return 0;
557 default:
558 return -EOPNOTSUPP;
559 }
560 default:
561 return -EOPNOTSUPP;
562 }
563 }
564
mcp9982_write_limit(struct mcp9982_priv * priv,u8 address,long val)565 static int mcp9982_write_limit(struct mcp9982_priv *priv, u8 address, long val)
566 {
567 int ret;
568 unsigned int regh, regl;
569
570 switch (address) {
571 case MCP9982_INTERNAL_HIGH_LIMIT_ADDR:
572 case MCP9982_INTERNAL_LOW_LIMIT_ADDR:
573 case MCP9982_THERM_LIMIT_ADDR(0):
574 case MCP9982_THERM_LIMIT_ADDR(1):
575 case MCP9982_THERM_LIMIT_ADDR(2):
576 case MCP9982_THERM_LIMIT_ADDR(3):
577 case MCP9982_THERM_LIMIT_ADDR(4):
578 regh = DIV_ROUND_CLOSEST(val, 1000);
579 regh = clamp_val(regh, 0, 255);
580
581 return regmap_write(priv->regmap, address, regh);
582 case MCP9982_EXT_HIGH_LIMIT_ADDR(1):
583 case MCP9982_EXT_HIGH_LIMIT_ADDR(2):
584 case MCP9982_EXT_HIGH_LIMIT_ADDR(3):
585 case MCP9982_EXT_HIGH_LIMIT_ADDR(4):
586 case MCP9982_EXT_LOW_LIMIT_ADDR(1):
587 case MCP9982_EXT_LOW_LIMIT_ADDR(2):
588 case MCP9982_EXT_LOW_LIMIT_ADDR(3):
589 case MCP9982_EXT_LOW_LIMIT_ADDR(4):
590 val = DIV_ROUND_CLOSEST(val, 125);
591 regh = (val >> 3) & 0xff;
592 regl = (val & 0x07) << 5;
593 /* Block writing is not supported by the chip. */
594 ret = regmap_write(priv->regmap, address, regh);
595 if (ret)
596 return ret;
597
598 return regmap_write(priv->regmap, address + 1, regl);
599 default:
600 return -EINVAL;
601 }
602 }
603
mcp9982_write_hyst(struct mcp9982_priv * priv,int channel,long val)604 static int mcp9982_write_hyst(struct mcp9982_priv *priv, int channel, long val)
605 {
606 int hyst, ret;
607 int limit;
608
609 val = DIV_ROUND_CLOSEST(val, 1000);
610 val = clamp_val(val, 0, 255);
611
612 /* Therm register is 8 bits and so it keeps only the integer part of the temperature. */
613 ret = regmap_read(priv->regmap, MCP9982_THERM_LIMIT_ADDR(channel), &limit);
614 if (ret)
615 return ret;
616
617 hyst = clamp_val(limit - val, 0, 255);
618
619 return regmap_write(priv->regmap, MCP9982_HYS_ADDR, hyst);
620 }
621
mcp9982_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)622 static int mcp9982_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
623 long val)
624 {
625 struct mcp9982_priv *priv = dev_get_drvdata(dev);
626 unsigned int idx;
627 u8 addr;
628
629 switch (type) {
630 case hwmon_chip:
631 switch (attr) {
632 case hwmon_chip_update_interval:
633
634 /*
635 * For MCP998XD and MCP9933D update interval
636 * can't be longer than 1 second.
637 */
638 if (priv->chip->hw_thermal_shutdown)
639 val = clamp_val(val, 0, 1000);
640
641 idx = find_closest_descending(val, mcp9982_update_interval,
642 ARRAY_SIZE(mcp9982_update_interval));
643 priv->interval_idx = idx;
644
645 return regmap_write(priv->regmap, MCP9982_CONV_ADDR, idx);
646 default:
647 return -EINVAL;
648 }
649 case hwmon_temp:
650 val = clamp_val(val, -64000, 191875);
651 val = val + (MCP9982_OFFSET * 1000);
652 switch (attr) {
653 case hwmon_temp_max:
654 if (channel)
655 addr = MCP9982_EXT_HIGH_LIMIT_ADDR(channel);
656 else
657 addr = MCP9982_INTERNAL_HIGH_LIMIT_ADDR;
658
659 return mcp9982_write_limit(priv, addr, val);
660 case hwmon_temp_min:
661 if (channel)
662 addr = MCP9982_EXT_LOW_LIMIT_ADDR(channel);
663 else
664 addr = MCP9982_INTERNAL_LOW_LIMIT_ADDR;
665
666 return mcp9982_write_limit(priv, addr, val);
667 case hwmon_temp_crit:
668 return mcp9982_write_limit(priv, MCP9982_THERM_LIMIT_ADDR(channel), val);
669 case hwmon_temp_crit_hyst:
670 return mcp9982_write_hyst(priv, channel, val);
671 default:
672 return -EINVAL;
673 }
674 default:
675 return -EINVAL;
676 }
677 }
678
mcp9982_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)679 static umode_t mcp9982_is_visible(const void *_data, enum hwmon_sensor_types type, u32 attr,
680 int channel)
681 {
682 const struct mcp9982_priv *priv = _data;
683
684 if (!test_bit(channel, &priv->enabled_channel_mask))
685 return 0;
686
687 switch (type) {
688 case hwmon_temp:
689 switch (attr) {
690 case hwmon_temp_label:
691 if (priv->labels[channel])
692 return 0444;
693 else
694 return 0;
695 case hwmon_temp_input:
696 case hwmon_temp_min_alarm:
697 case hwmon_temp_max_alarm:
698 case hwmon_temp_max_hyst:
699 case hwmon_temp_crit_alarm:
700 case hwmon_temp_fault:
701 return 0444;
702 case hwmon_temp_min:
703 case hwmon_temp_max:
704 case hwmon_temp_crit:
705 case hwmon_temp_crit_hyst:
706 return 0644;
707 default:
708 return 0;
709 }
710 case hwmon_chip:
711 switch (attr) {
712 case hwmon_chip_update_interval:
713 return 0644;
714 default:
715 return 0;
716 }
717 default:
718 return 0;
719 }
720 }
721
722 static const struct hwmon_ops mcp9982_hwmon_ops = {
723 .is_visible = mcp9982_is_visible,
724 .read = mcp9982_read,
725 .read_string = mcp9982_read_label,
726 .write = mcp9982_write,
727 };
728
mcp9982_init(struct device * dev,struct mcp9982_priv * priv)729 static int mcp9982_init(struct device *dev, struct mcp9982_priv *priv)
730 {
731 long high_limit, low_limit;
732 unsigned int i;
733 int ret;
734 u8 val;
735
736 /* Chips 82/83 and 82D/83D do not support anti-parallel diode mode. */
737 if (!priv->chip->allow_apdd && priv->apdd_enable == 1)
738 return dev_err_probe(dev, -EINVAL, "Incorrect setting of APDD.\n");
739
740 /* Chips with "D" work only in Run state. */
741 if (priv->chip->hw_thermal_shutdown && !priv->run_state)
742 return dev_err_probe(dev, -EINVAL, "Incorrect setting of Power State.\n");
743
744 /* All chips with "D" in the name must have RECD12 enabled. */
745 if (priv->chip->hw_thermal_shutdown && !priv->recd12_enable)
746 return dev_err_probe(dev, -EINVAL, "Incorrect setting of RECD12.\n");
747 /* Chips 83D/84D/85D must have RECD34 enabled. */
748 if (priv->chip->hw_thermal_shutdown)
749 if ((priv->chip->has_recd34 && !priv->recd34_enable))
750 return dev_err_probe(dev, -EINVAL, "Incorrect setting of RECD34.\n");
751
752 /*
753 * Set default values in registers.
754 * APDD, RECD12 and RECD34 are active on 0.
755 */
756 val = FIELD_PREP(MCP9982_CFG_MSKAL, 1) |
757 FIELD_PREP(MCP9982_CFG_RS, !priv->run_state) |
758 FIELD_PREP(MCP9982_CFG_ATTHM, 1) |
759 FIELD_PREP(MCP9982_CFG_RECD12, !priv->recd12_enable) |
760 FIELD_PREP(MCP9982_CFG_RECD34, !priv->recd34_enable) |
761 FIELD_PREP(MCP9982_CFG_RANGE, 1) | FIELD_PREP(MCP9982_CFG_DA_ENA, 0) |
762 FIELD_PREP(MCP9982_CFG_APDD, !priv->apdd_enable);
763
764 ret = regmap_write(priv->regmap, MCP9982_CFG_ADDR, val);
765 if (ret)
766 return ret;
767
768 /*
769 * Read initial value from register.
770 * The convert register utilises only 4 out of 8 bits.
771 * Numerical values 0->10 set their respective update intervals,
772 * while numerical values 11->15 default to 1 second.
773 */
774 ret = regmap_read(priv->regmap, MCP9982_CONV_ADDR, &priv->interval_idx);
775 if (ret)
776 return ret;
777 if (priv->interval_idx >= 11)
778 priv->interval_idx = 4;
779
780 ret = regmap_write(priv->regmap, MCP9982_HYS_ADDR, MCP9982_DEFAULT_HYS_VAL);
781 if (ret)
782 return ret;
783
784 ret = regmap_write(priv->regmap, MCP9982_CONSEC_ALRT_ADDR, MCP9982_DEFAULT_CONSEC_ALRT_VAL);
785 if (ret)
786 return ret;
787
788 ret = regmap_write(priv->regmap, MCP9982_ALRT_CFG_ADDR, 0);
789 if (ret)
790 return ret;
791
792 ret = regmap_write(priv->regmap, MCP9982_RUNNING_AVG_ADDR, 0);
793 if (ret)
794 return ret;
795
796 ret = regmap_write(priv->regmap, MCP9982_HOTTEST_CFG_ADDR, 0);
797 if (ret)
798 return ret;
799
800 /*
801 * Only external channels 1 and 2 support beta compensation.
802 * Set beta auto-detection.
803 */
804 for (i = 1; i < 3; i++)
805 if (test_bit(i, &priv->enabled_channel_mask)) {
806 ret = regmap_write(priv->regmap, MCP9982_EXT_BETA_CFG_ADDR(i),
807 MCP9982_BETA_AUTODETECT);
808 if (ret)
809 return ret;
810 }
811
812 high_limit = MCP9982_HIGH_LIMIT_DEFAULT + (MCP9982_OFFSET * 1000);
813 low_limit = MCP9982_LOW_LIMIT_DEFAULT + (MCP9982_OFFSET * 1000);
814
815 /* Set default values for internal channel limits. */
816 if (test_bit(0, &priv->enabled_channel_mask)) {
817 ret = mcp9982_write_limit(priv, MCP9982_INTERNAL_HIGH_LIMIT_ADDR, high_limit);
818 if (ret)
819 return ret;
820
821 ret = mcp9982_write_limit(priv, MCP9982_INTERNAL_LOW_LIMIT_ADDR, low_limit);
822 if (ret)
823 return ret;
824
825 ret = mcp9982_write_limit(priv, MCP9982_THERM_LIMIT_ADDR(0), high_limit);
826 if (ret)
827 return ret;
828 }
829
830 /* Set ideality factor and limits to default for external channels. */
831 for (i = 1; i < MCP9982_MAX_NUM_CHANNELS; i++)
832 if (test_bit(i, &priv->enabled_channel_mask)) {
833 ret = regmap_write(priv->regmap, MCP9982_EXT_IDEAL_ADDR(i),
834 MCP9982_IDEALITY_DEFAULT);
835 if (ret)
836 return ret;
837
838 ret = mcp9982_write_limit(priv, MCP9982_EXT_HIGH_LIMIT_ADDR(i), high_limit);
839 if (ret)
840 return ret;
841
842 ret = mcp9982_write_limit(priv, MCP9982_EXT_LOW_LIMIT_ADDR(i), low_limit);
843 if (ret)
844 return ret;
845
846 ret = mcp9982_write_limit(priv, MCP9982_THERM_LIMIT_ADDR(i), high_limit);
847 if (ret)
848 return ret;
849 }
850
851 return 0;
852 }
853
mcp9982_parse_fw_config(struct device * dev,int device_nr_channels)854 static int mcp9982_parse_fw_config(struct device *dev, int device_nr_channels)
855 {
856 struct mcp9982_priv *priv = dev_get_drvdata(dev);
857 unsigned int reg_nr;
858 int ret;
859
860 /* Initialise internal channel( which is always present ). */
861 priv->labels[0] = "internal diode";
862 priv->enabled_channel_mask = 1;
863
864 /* Default values to work on systems without devicetree or firmware nodes. */
865 if (!dev_fwnode(dev)) {
866 priv->num_channels = device_nr_channels;
867 priv->enabled_channel_mask = BIT(priv->num_channels) - 1;
868 priv->apdd_enable = false;
869 priv->recd12_enable = true;
870 priv->recd34_enable = true;
871 priv->run_state = true;
872 return 0;
873 }
874
875 priv->apdd_enable =
876 device_property_read_bool(dev, "microchip,enable-anti-parallel");
877
878 priv->recd12_enable =
879 device_property_read_bool(dev, "microchip,parasitic-res-on-channel1-2");
880
881 priv->recd34_enable =
882 device_property_read_bool(dev, "microchip,parasitic-res-on-channel3-4");
883
884 priv->run_state =
885 device_property_read_bool(dev, "microchip,power-state");
886
887 priv->num_channels = device_get_child_node_count(dev) + 1;
888
889 if (priv->num_channels > device_nr_channels)
890 return dev_err_probe(dev, -EINVAL,
891 "More channels than the chip supports.\n");
892
893 /* Read information about the external channels. */
894 device_for_each_named_child_node_scoped(dev, child, "channel") {
895 reg_nr = 0;
896 ret = fwnode_property_read_u32(child, "reg", ®_nr);
897 if (ret || !reg_nr || reg_nr >= device_nr_channels)
898 return dev_err_probe(dev, -EINVAL,
899 "Channel reg is incorrectly set.\n");
900
901 fwnode_property_read_string(child, "label", &priv->labels[reg_nr]);
902 set_bit(reg_nr, &priv->enabled_channel_mask);
903 }
904
905 return 0;
906 }
907
908 static const struct hwmon_chip_info mcp998x_chip_info = {
909 .ops = &mcp9982_hwmon_ops,
910 .info = mcp9985_info,
911 };
912
mcp9982_probe(struct i2c_client * client)913 static int mcp9982_probe(struct i2c_client *client)
914 {
915 const struct mcp9982_features *chip;
916 struct device *dev = &client->dev;
917 struct mcp9982_priv *priv;
918 struct device *hwmon_dev;
919 int ret;
920
921 priv = devm_kzalloc(dev, sizeof(struct mcp9982_priv), GFP_KERNEL);
922 if (!priv)
923 return -ENOMEM;
924
925 priv->regmap = devm_regmap_init_i2c(client, &mcp9982_regmap_config);
926
927 if (IS_ERR(priv->regmap))
928 return dev_err_probe(dev, PTR_ERR(priv->regmap),
929 "Cannot initialize register map.\n");
930
931 dev_set_drvdata(dev, priv);
932
933 chip = i2c_get_match_data(client);
934 if (!chip)
935 return -EINVAL;
936 priv->chip = chip;
937
938 ret = mcp9982_parse_fw_config(dev, chip->phys_channels);
939 if (ret)
940 return ret;
941
942 ret = mcp9982_init(dev, priv);
943 if (ret)
944 return ret;
945
946 hwmon_dev = devm_hwmon_device_register_with_info(dev, chip->name, priv,
947 &mcp998x_chip_info, NULL);
948
949 return PTR_ERR_OR_ZERO(hwmon_dev);
950 }
951
952 static const struct i2c_device_id mcp9982_id[] = {
953 { .name = "mcp9933", .driver_data = (kernel_ulong_t)&mcp9933_chip_config },
954 { .name = "mcp9933d", .driver_data = (kernel_ulong_t)&mcp9933d_chip_config },
955 { .name = "mcp9982", .driver_data = (kernel_ulong_t)&mcp9982_chip_config },
956 { .name = "mcp9982d", .driver_data = (kernel_ulong_t)&mcp9982d_chip_config },
957 { .name = "mcp9983", .driver_data = (kernel_ulong_t)&mcp9983_chip_config },
958 { .name = "mcp9983d", .driver_data = (kernel_ulong_t)&mcp9983d_chip_config },
959 { .name = "mcp9984", .driver_data = (kernel_ulong_t)&mcp9984_chip_config },
960 { .name = "mcp9984d", .driver_data = (kernel_ulong_t)&mcp9984d_chip_config },
961 { .name = "mcp9985", .driver_data = (kernel_ulong_t)&mcp9985_chip_config },
962 { .name = "mcp9985d", .driver_data = (kernel_ulong_t)&mcp9985d_chip_config },
963 { }
964 };
965 MODULE_DEVICE_TABLE(i2c, mcp9982_id);
966
967 static const struct of_device_id mcp9982_of_match[] = {
968 {
969 .compatible = "microchip,mcp9933",
970 .data = &mcp9933_chip_config,
971 }, {
972 .compatible = "microchip,mcp9933d",
973 .data = &mcp9933d_chip_config,
974 }, {
975 .compatible = "microchip,mcp9982",
976 .data = &mcp9982_chip_config,
977 }, {
978 .compatible = "microchip,mcp9982d",
979 .data = &mcp9982d_chip_config,
980 }, {
981 .compatible = "microchip,mcp9983",
982 .data = &mcp9983_chip_config,
983 }, {
984 .compatible = "microchip,mcp9983d",
985 .data = &mcp9983d_chip_config,
986 }, {
987 .compatible = "microchip,mcp9984",
988 .data = &mcp9984_chip_config,
989 }, {
990 .compatible = "microchip,mcp9984d",
991 .data = &mcp9984d_chip_config,
992 }, {
993 .compatible = "microchip,mcp9985",
994 .data = &mcp9985_chip_config,
995 }, {
996 .compatible = "microchip,mcp9985d",
997 .data = &mcp9985d_chip_config,
998 },
999 { }
1000 };
1001 MODULE_DEVICE_TABLE(of, mcp9982_of_match);
1002
1003 static struct i2c_driver mcp9982_driver = {
1004 .driver = {
1005 .name = "mcp9982",
1006 .of_match_table = mcp9982_of_match,
1007 },
1008 .probe = mcp9982_probe,
1009 .id_table = mcp9982_id,
1010 };
1011 module_i2c_driver(mcp9982_driver);
1012
1013 MODULE_AUTHOR("Victor Duicu <victor.duicu@microchip.com>");
1014 MODULE_DESCRIPTION("MCP998X/33 and MCP998XD/33D Multichannel Automotive Temperature Monitor Driver");
1015 MODULE_LICENSE("GPL");
1016