1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADIS16480 and similar IMUs driver
4 *
5 * Copyright 2012 Analog Devices Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/bitfield.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/math.h>
13 #include <linux/device.h>
14 #include <linux/kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/module.h>
17 #include <linux/lcm.h>
18 #include <linux/property.h>
19 #include <linux/swab.h>
20 #include <linux/crc32.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/imu/adis.h>
25 #include <linux/iio/trigger_consumer.h>
26
27 #include <linux/debugfs.h>
28
29 #define ADIS16480_PAGE_SIZE 0x80
30
31 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg))
32
33 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */
34 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06)
35 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08)
36 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A)
37 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C)
38 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E)
39 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10)
40 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14)
41 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18)
42 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C)
43 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20)
44 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24)
45 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28)
46 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A)
47 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C)
48 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E)
49 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40)
50 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44)
51 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48)
52 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C)
53 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50)
54 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54)
55 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E)
56
57 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04)
58 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06)
59 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08)
60 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A)
61 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C)
62 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E)
63 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10)
64 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14)
65 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18)
66 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C)
67 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20)
68 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24)
69 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28)
70 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A)
71 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C)
72 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40)
73 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C)
74
75 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02)
76 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06)
77 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08)
78 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A)
79 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C)
80 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10)
81 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16)
82 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18)
83 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20)
84 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22)
85 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24)
86 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28)
87 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A)
88 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C)
89 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E)
90 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30)
91 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32)
92 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34)
93 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36)
94 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38)
95 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A)
96 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78)
97 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A)
98 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C)
99
100 /*
101 * External clock scaling in PPS mode.
102 * Available only for ADIS1649x devices
103 */
104 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10)
105 #define ADIS16495_REG_BURST_CMD ADIS16480_REG(0x00, 0x7C)
106 #define ADIS16495_GYRO_ACCEL_BURST_ID 0xA5A5
107 #define ADIS16545_DELTA_ANG_VEL_BURST_ID 0xC3C3
108 /* total number of segments in burst */
109 #define ADIS16495_BURST_MAX_DATA 20
110
111 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20)
112
113 /* Each filter coefficient bank spans two pages */
114 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \
115 ADIS16480_REG((page) + 1, (x) - 60 + 8))
116 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x))
117 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x))
118 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x))
119 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x))
120
121 /* ADIS16480_REG_FNCTIO_CTRL */
122 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0)
123 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x)
124 #define ADIS16480_DRDY_POL_MSK BIT(2)
125 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x)
126 #define ADIS16480_DRDY_EN_MSK BIT(3)
127 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x)
128 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4)
129 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x)
130 #define ADIS16480_SYNC_EN_MSK BIT(7)
131 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x)
132 #define ADIS16480_SYNC_MODE_MSK BIT(8)
133 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x)
134
135 #define ADIS16545_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0)
136 #define ADIS16545_BURST_DATA_SEL_1_CHN_MASK GENMASK(16, 11)
137 #define ADIS16545_BURST_DATA_SEL_MASK BIT(8)
138
139 struct adis16480_chip_info {
140 unsigned int num_channels;
141 const struct iio_chan_spec *channels;
142 unsigned int gyro_max_val;
143 unsigned int gyro_max_scale;
144 unsigned int accel_max_val;
145 unsigned int accel_max_scale;
146 unsigned int temp_scale;
147 unsigned int deltang_max_val;
148 unsigned int deltvel_max_val;
149 unsigned int int_clk;
150 unsigned int max_dec_rate;
151 const unsigned int *filter_freqs;
152 bool has_pps_clk_mode;
153 bool has_sleep_cnt;
154 bool has_burst_delta_data;
155 const struct adis_data adis_data;
156 };
157
158 enum adis16480_int_pin {
159 ADIS16480_PIN_DIO1,
160 ADIS16480_PIN_DIO2,
161 ADIS16480_PIN_DIO3,
162 ADIS16480_PIN_DIO4
163 };
164
165 enum adis16480_clock_mode {
166 ADIS16480_CLK_SYNC,
167 ADIS16480_CLK_PPS,
168 ADIS16480_CLK_INT
169 };
170
171 struct adis16480 {
172 const struct adis16480_chip_info *chip_info;
173
174 struct adis adis;
175 struct clk *ext_clk;
176 enum adis16480_clock_mode clk_mode;
177 unsigned int clk_freq;
178 u16 burst_id;
179 /* Alignment needed for the timestamp */
180 __be16 data[ADIS16495_BURST_MAX_DATA] __aligned(8);
181 };
182
183 static const char * const adis16480_int_pin_names[4] = {
184 [ADIS16480_PIN_DIO1] = "DIO1",
185 [ADIS16480_PIN_DIO2] = "DIO2",
186 [ADIS16480_PIN_DIO3] = "DIO3",
187 [ADIS16480_PIN_DIO4] = "DIO4",
188 };
189
190 static bool low_rate_allow;
191 module_param(low_rate_allow, bool, 0444);
192 MODULE_PARM_DESC(low_rate_allow,
193 "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)");
194
adis16480_show_firmware_revision(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)195 static ssize_t adis16480_show_firmware_revision(struct file *file,
196 char __user *userbuf, size_t count, loff_t *ppos)
197 {
198 struct adis16480 *adis16480 = file->private_data;
199 char buf[7];
200 size_t len;
201 u16 rev;
202 int ret;
203
204 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev);
205 if (ret)
206 return ret;
207
208 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
209
210 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
211 }
212
213 static const struct file_operations adis16480_firmware_revision_fops = {
214 .open = simple_open,
215 .read = adis16480_show_firmware_revision,
216 .llseek = default_llseek,
217 .owner = THIS_MODULE,
218 };
219
adis16480_show_firmware_date(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)220 static ssize_t adis16480_show_firmware_date(struct file *file,
221 char __user *userbuf, size_t count, loff_t *ppos)
222 {
223 struct adis16480 *adis16480 = file->private_data;
224 u16 md, year;
225 char buf[12];
226 size_t len;
227 int ret;
228
229 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year);
230 if (ret)
231 return ret;
232
233 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md);
234 if (ret)
235 return ret;
236
237 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n",
238 md >> 8, md & 0xff, year);
239
240 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
241 }
242
243 static const struct file_operations adis16480_firmware_date_fops = {
244 .open = simple_open,
245 .read = adis16480_show_firmware_date,
246 .llseek = default_llseek,
247 .owner = THIS_MODULE,
248 };
249
adis16480_show_serial_number(void * arg,u64 * val)250 static int adis16480_show_serial_number(void *arg, u64 *val)
251 {
252 struct adis16480 *adis16480 = arg;
253 u16 serial;
254 int ret;
255
256 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM,
257 &serial);
258 if (ret)
259 return ret;
260
261 *val = serial;
262
263 return 0;
264 }
265 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops,
266 adis16480_show_serial_number, NULL, "0x%.4llx\n");
267
adis16480_show_product_id(void * arg,u64 * val)268 static int adis16480_show_product_id(void *arg, u64 *val)
269 {
270 struct adis16480 *adis16480 = arg;
271 u16 prod_id;
272 int ret;
273
274 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID,
275 &prod_id);
276 if (ret)
277 return ret;
278
279 *val = prod_id;
280
281 return 0;
282 }
283 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops,
284 adis16480_show_product_id, NULL, "%llu\n");
285
adis16480_show_flash_count(void * arg,u64 * val)286 static int adis16480_show_flash_count(void *arg, u64 *val)
287 {
288 struct adis16480 *adis16480 = arg;
289 u32 flash_count;
290 int ret;
291
292 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT,
293 &flash_count);
294 if (ret)
295 return ret;
296
297 *val = flash_count;
298
299 return 0;
300 }
301 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops,
302 adis16480_show_flash_count, NULL, "%lld\n");
303
adis16480_debugfs_init(struct iio_dev * indio_dev)304 static void adis16480_debugfs_init(struct iio_dev *indio_dev)
305 {
306 struct adis16480 *adis16480 = iio_priv(indio_dev);
307 struct dentry *d = iio_get_debugfs_dentry(indio_dev);
308
309 if (!IS_ENABLED(CONFIG_DEBUG_FS))
310 return;
311
312 debugfs_create_file_unsafe("firmware_revision", 0400,
313 d, adis16480, &adis16480_firmware_revision_fops);
314 debugfs_create_file_unsafe("firmware_date", 0400,
315 d, adis16480, &adis16480_firmware_date_fops);
316 debugfs_create_file_unsafe("serial_number", 0400,
317 d, adis16480, &adis16480_serial_number_fops);
318 debugfs_create_file_unsafe("product_id", 0400,
319 d, adis16480, &adis16480_product_id_fops);
320 debugfs_create_file_unsafe("flash_count", 0400,
321 d, adis16480, &adis16480_flash_count_fops);
322 }
323
adis16480_set_freq(struct iio_dev * indio_dev,int val,int val2)324 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2)
325 {
326 struct adis16480 *st = iio_priv(indio_dev);
327 unsigned int t, sample_rate = st->clk_freq;
328 int ret;
329
330 if (val < 0 || val2 < 0)
331 return -EINVAL;
332
333 t = val * 1000 + val2 / 1000;
334 if (t == 0)
335 return -EINVAL;
336
337 adis_dev_auto_lock(&st->adis);
338 /*
339 * When using PPS mode, the input clock needs to be scaled so that we have an IMU
340 * sample rate between (optimally) 4000 and 4250. After this, we can use the
341 * decimation filter to lower the sampling rate in order to get what the user wants.
342 * Optimally, the user sample rate is a multiple of both the IMU sample rate and
343 * the input clock. Hence, calculating the sync_scale dynamically gives us better
344 * chances of achieving a perfect/integer value for DEC_RATE. The math here is:
345 * 1. lcm of the input clock and the desired output rate.
346 * 2. get the highest multiple of the previous result lower than the adis max rate.
347 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE
348 * and DEC_RATE (to get the user output rate)
349 */
350 if (st->clk_mode == ADIS16480_CLK_PPS) {
351 unsigned long scaled_rate = lcm(st->clk_freq, t);
352 int sync_scale;
353
354 /*
355 * If lcm is bigger than the IMU maximum sampling rate there's no perfect
356 * solution. In this case, we get the highest multiple of the input clock
357 * lower than the IMU max sample rate.
358 */
359 if (scaled_rate > st->chip_info->int_clk)
360 scaled_rate = st->chip_info->int_clk / st->clk_freq * st->clk_freq;
361 else
362 scaled_rate = st->chip_info->int_clk / scaled_rate * scaled_rate;
363
364 /*
365 * This is not an hard requirement but it's not advised to run the IMU
366 * with a sample rate lower than 4000Hz due to possible undersampling
367 * issues. However, there are users that might really want to take the risk.
368 * Hence, we provide a module parameter for them. If set, we allow sample
369 * rates lower than 4KHz. By default, we won't allow this and we just roundup
370 * the rate to the next multiple of the input clock bigger than 4KHz. This
371 * is done like this as in some cases (when DEC_RATE is 0) might give
372 * us the closest value to the one desired by the user...
373 */
374 if (scaled_rate < 4000000 && !low_rate_allow)
375 scaled_rate = roundup(4000000, st->clk_freq);
376
377 sync_scale = scaled_rate / st->clk_freq;
378 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale);
379 if (ret)
380 return ret;
381
382 sample_rate = scaled_rate;
383 }
384
385 t = DIV_ROUND_CLOSEST(sample_rate, t);
386 if (t)
387 t--;
388
389 if (t > st->chip_info->max_dec_rate)
390 t = st->chip_info->max_dec_rate;
391
392 return __adis_write_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, t);
393 }
394
adis16480_get_freq(struct iio_dev * indio_dev,int * val,int * val2)395 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2)
396 {
397 struct adis16480 *st = iio_priv(indio_dev);
398 uint16_t t;
399 int ret;
400 unsigned int freq, sample_rate = st->clk_freq;
401
402 adis_dev_auto_lock(&st->adis);
403
404 if (st->clk_mode == ADIS16480_CLK_PPS) {
405 u16 sync_scale;
406
407 ret = __adis_read_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, &sync_scale);
408 if (ret)
409 return ret;
410
411 sample_rate = st->clk_freq * sync_scale;
412 }
413
414 ret = __adis_read_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, &t);
415 if (ret)
416 return ret;
417
418 freq = DIV_ROUND_CLOSEST(sample_rate, (t + 1));
419
420 *val = freq / 1000;
421 *val2 = (freq % 1000) * 1000;
422
423 return IIO_VAL_INT_PLUS_MICRO;
424 }
425
426 enum {
427 ADIS16480_SCAN_GYRO_X,
428 ADIS16480_SCAN_GYRO_Y,
429 ADIS16480_SCAN_GYRO_Z,
430 ADIS16480_SCAN_ACCEL_X,
431 ADIS16480_SCAN_ACCEL_Y,
432 ADIS16480_SCAN_ACCEL_Z,
433 ADIS16480_SCAN_MAGN_X,
434 ADIS16480_SCAN_MAGN_Y,
435 ADIS16480_SCAN_MAGN_Z,
436 ADIS16480_SCAN_BARO,
437 ADIS16480_SCAN_TEMP,
438 ADIS16480_SCAN_DELTANG_X,
439 ADIS16480_SCAN_DELTANG_Y,
440 ADIS16480_SCAN_DELTANG_Z,
441 ADIS16480_SCAN_DELTVEL_X,
442 ADIS16480_SCAN_DELTVEL_Y,
443 ADIS16480_SCAN_DELTVEL_Z,
444 };
445
446 static const unsigned int adis16480_calibbias_regs[] = {
447 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS,
448 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS,
449 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS,
450 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS,
451 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS,
452 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS,
453 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON,
454 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON,
455 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON,
456 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS,
457 };
458
459 static const unsigned int adis16480_calibscale_regs[] = {
460 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE,
461 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE,
462 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE,
463 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE,
464 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE,
465 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE,
466 };
467
adis16480_set_calibbias(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int bias)468 static int adis16480_set_calibbias(struct iio_dev *indio_dev,
469 const struct iio_chan_spec *chan, int bias)
470 {
471 unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
472 struct adis16480 *st = iio_priv(indio_dev);
473
474 switch (chan->type) {
475 case IIO_MAGN:
476 case IIO_PRESSURE:
477 if (bias < -0x8000 || bias >= 0x8000)
478 return -EINVAL;
479 return adis_write_reg_16(&st->adis, reg, bias);
480 case IIO_ANGL_VEL:
481 case IIO_ACCEL:
482 return adis_write_reg_32(&st->adis, reg, bias);
483 default:
484 break;
485 }
486
487 return -EINVAL;
488 }
489
adis16480_get_calibbias(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * bias)490 static int adis16480_get_calibbias(struct iio_dev *indio_dev,
491 const struct iio_chan_spec *chan, int *bias)
492 {
493 unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
494 struct adis16480 *st = iio_priv(indio_dev);
495 uint16_t val16;
496 uint32_t val32;
497 int ret;
498
499 switch (chan->type) {
500 case IIO_MAGN:
501 case IIO_PRESSURE:
502 ret = adis_read_reg_16(&st->adis, reg, &val16);
503 if (ret == 0)
504 *bias = sign_extend32(val16, 15);
505 break;
506 case IIO_ANGL_VEL:
507 case IIO_ACCEL:
508 ret = adis_read_reg_32(&st->adis, reg, &val32);
509 if (ret == 0)
510 *bias = sign_extend32(val32, 31);
511 break;
512 default:
513 ret = -EINVAL;
514 }
515
516 if (ret)
517 return ret;
518
519 return IIO_VAL_INT;
520 }
521
adis16480_set_calibscale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int scale)522 static int adis16480_set_calibscale(struct iio_dev *indio_dev,
523 const struct iio_chan_spec *chan, int scale)
524 {
525 unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
526 struct adis16480 *st = iio_priv(indio_dev);
527
528 if (scale < -0x8000 || scale >= 0x8000)
529 return -EINVAL;
530
531 return adis_write_reg_16(&st->adis, reg, scale);
532 }
533
adis16480_get_calibscale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * scale)534 static int adis16480_get_calibscale(struct iio_dev *indio_dev,
535 const struct iio_chan_spec *chan, int *scale)
536 {
537 unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
538 struct adis16480 *st = iio_priv(indio_dev);
539 uint16_t val16;
540 int ret;
541
542 ret = adis_read_reg_16(&st->adis, reg, &val16);
543 if (ret)
544 return ret;
545
546 *scale = sign_extend32(val16, 15);
547 return IIO_VAL_INT;
548 }
549
550 static const unsigned int adis16480_def_filter_freqs[] = {
551 310,
552 55,
553 275,
554 63,
555 };
556
557 static const unsigned int adis16495_def_filter_freqs[] = {
558 300,
559 100,
560 300,
561 100,
562 };
563
564 static const unsigned int ad16480_filter_data[][2] = {
565 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 },
566 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 },
567 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 },
568 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 },
569 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 },
570 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 },
571 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 },
572 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 },
573 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 },
574 };
575
adis16480_get_filter_freq(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * freq)576 static int adis16480_get_filter_freq(struct iio_dev *indio_dev,
577 const struct iio_chan_spec *chan, int *freq)
578 {
579 struct adis16480 *st = iio_priv(indio_dev);
580 unsigned int enable_mask, offset, reg;
581 uint16_t val;
582 int ret;
583
584 reg = ad16480_filter_data[chan->scan_index][0];
585 offset = ad16480_filter_data[chan->scan_index][1];
586 enable_mask = BIT(offset + 2);
587
588 ret = adis_read_reg_16(&st->adis, reg, &val);
589 if (ret)
590 return ret;
591
592 if (!(val & enable_mask))
593 *freq = 0;
594 else
595 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3];
596
597 return IIO_VAL_INT;
598 }
599
adis16480_set_filter_freq(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int freq)600 static int adis16480_set_filter_freq(struct iio_dev *indio_dev,
601 const struct iio_chan_spec *chan, unsigned int freq)
602 {
603 struct adis16480 *st = iio_priv(indio_dev);
604 unsigned int enable_mask, offset, reg;
605 unsigned int diff, best_diff;
606 unsigned int i, best_freq;
607 uint16_t val;
608 int ret;
609
610 reg = ad16480_filter_data[chan->scan_index][0];
611 offset = ad16480_filter_data[chan->scan_index][1];
612 enable_mask = BIT(offset + 2);
613
614 adis_dev_auto_lock(&st->adis);
615
616 ret = __adis_read_reg_16(&st->adis, reg, &val);
617 if (ret)
618 return ret;
619
620 if (freq == 0) {
621 val &= ~enable_mask;
622 } else {
623 best_freq = 0;
624 best_diff = st->chip_info->filter_freqs[0];
625 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) {
626 if (st->chip_info->filter_freqs[i] >= freq) {
627 diff = st->chip_info->filter_freqs[i] - freq;
628 if (diff < best_diff) {
629 best_diff = diff;
630 best_freq = i;
631 }
632 }
633 }
634
635 val &= ~(0x3 << offset);
636 val |= best_freq << offset;
637 val |= enable_mask;
638 }
639
640 return __adis_write_reg_16(&st->adis, reg, val);
641 }
642
adis16480_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)643 static int adis16480_read_raw(struct iio_dev *indio_dev,
644 const struct iio_chan_spec *chan, int *val, int *val2, long info)
645 {
646 struct adis16480 *st = iio_priv(indio_dev);
647 unsigned int temp;
648
649 switch (info) {
650 case IIO_CHAN_INFO_RAW:
651 return adis_single_conversion(indio_dev, chan, 0, val);
652 case IIO_CHAN_INFO_SCALE:
653 switch (chan->type) {
654 case IIO_ANGL_VEL:
655 *val = st->chip_info->gyro_max_scale;
656 *val2 = st->chip_info->gyro_max_val;
657 return IIO_VAL_FRACTIONAL;
658 case IIO_ACCEL:
659 *val = st->chip_info->accel_max_scale;
660 *val2 = st->chip_info->accel_max_val;
661 return IIO_VAL_FRACTIONAL;
662 case IIO_MAGN:
663 *val = 0;
664 *val2 = 100; /* 0.0001 gauss */
665 return IIO_VAL_INT_PLUS_MICRO;
666 case IIO_TEMP:
667 /*
668 * +85 degrees Celsius = temp_max_scale
669 * +25 degrees Celsius = 0
670 * LSB, 25 degrees Celsius = 60 / temp_max_scale
671 */
672 *val = st->chip_info->temp_scale / 1000;
673 *val2 = (st->chip_info->temp_scale % 1000) * 1000;
674 return IIO_VAL_INT_PLUS_MICRO;
675 case IIO_PRESSURE:
676 /*
677 * max scale is 1310 mbar
678 * max raw value is 32767 shifted for 32bits
679 */
680 *val = 131; /* 1310mbar = 131 kPa */
681 *val2 = 32767 << 16;
682 return IIO_VAL_FRACTIONAL;
683 case IIO_DELTA_ANGL:
684 *val = st->chip_info->deltang_max_val;
685 *val2 = 31;
686 return IIO_VAL_FRACTIONAL_LOG2;
687 case IIO_DELTA_VELOCITY:
688 *val = st->chip_info->deltvel_max_val;
689 *val2 = 31;
690 return IIO_VAL_FRACTIONAL_LOG2;
691 default:
692 return -EINVAL;
693 }
694 case IIO_CHAN_INFO_OFFSET:
695 /* Only the temperature channel has a offset */
696 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */
697 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale);
698 return IIO_VAL_INT;
699 case IIO_CHAN_INFO_CALIBBIAS:
700 return adis16480_get_calibbias(indio_dev, chan, val);
701 case IIO_CHAN_INFO_CALIBSCALE:
702 return adis16480_get_calibscale(indio_dev, chan, val);
703 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
704 return adis16480_get_filter_freq(indio_dev, chan, val);
705 case IIO_CHAN_INFO_SAMP_FREQ:
706 return adis16480_get_freq(indio_dev, val, val2);
707 default:
708 return -EINVAL;
709 }
710 }
711
adis16480_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long info)712 static int adis16480_write_raw(struct iio_dev *indio_dev,
713 const struct iio_chan_spec *chan, int val, int val2, long info)
714 {
715 switch (info) {
716 case IIO_CHAN_INFO_CALIBBIAS:
717 return adis16480_set_calibbias(indio_dev, chan, val);
718 case IIO_CHAN_INFO_CALIBSCALE:
719 return adis16480_set_calibscale(indio_dev, chan, val);
720 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
721 return adis16480_set_filter_freq(indio_dev, chan, val);
722 case IIO_CHAN_INFO_SAMP_FREQ:
723 return adis16480_set_freq(indio_dev, val, val2);
724
725 default:
726 return -EINVAL;
727 }
728 }
729
730 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \
731 { \
732 .type = (_type), \
733 .modified = 1, \
734 .channel2 = (_mod), \
735 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
736 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
737 _info_sep, \
738 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
739 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
740 .address = (_address), \
741 .scan_index = (_si), \
742 .scan_type = { \
743 .sign = 's', \
744 .realbits = (_bits), \
745 .storagebits = (_bits), \
746 .endianness = IIO_BE, \
747 }, \
748 }
749
750 #define ADIS16480_GYRO_CHANNEL(_mod) \
751 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
752 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \
753 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
754 BIT(IIO_CHAN_INFO_CALIBSCALE), \
755 32)
756
757 #define ADIS16480_ACCEL_CHANNEL(_mod) \
758 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \
759 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \
760 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
761 BIT(IIO_CHAN_INFO_CALIBSCALE), \
762 32)
763
764 #define ADIS16480_DELTANG_CHANNEL(_mod) \
765 ADIS16480_MOD_CHANNEL(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
766 ADIS16480_REG_ ## _mod ## _DELTAANG_OUT, ADIS16480_SCAN_DELTANG_ ## _mod, \
767 0, 32)
768
769 #define ADIS16480_DELTANG_CHANNEL_NO_SCAN(_mod) \
770 ADIS16480_MOD_CHANNEL(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
771 ADIS16480_REG_ ## _mod ## _DELTAANG_OUT, -1, 0, 32)
772
773 #define ADIS16480_DELTVEL_CHANNEL(_mod) \
774 ADIS16480_MOD_CHANNEL(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
775 ADIS16480_REG_ ## _mod ## _DELTAVEL_OUT, ADIS16480_SCAN_DELTVEL_ ## _mod, \
776 0, 32)
777
778 #define ADIS16480_DELTVEL_CHANNEL_NO_SCAN(_mod) \
779 ADIS16480_MOD_CHANNEL(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
780 ADIS16480_REG_ ## _mod ## _DELTAVEL_OUT, -1, 0, 32)
781
782 #define ADIS16480_MAGN_CHANNEL(_mod) \
783 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \
784 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \
785 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
786 16)
787
788 #define ADIS16480_PRESSURE_CHANNEL() \
789 { \
790 .type = IIO_PRESSURE, \
791 .indexed = 1, \
792 .channel = 0, \
793 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
794 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
795 BIT(IIO_CHAN_INFO_SCALE), \
796 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
797 .address = ADIS16480_REG_BAROM_OUT, \
798 .scan_index = ADIS16480_SCAN_BARO, \
799 .scan_type = { \
800 .sign = 's', \
801 .realbits = 32, \
802 .storagebits = 32, \
803 .endianness = IIO_BE, \
804 }, \
805 }
806
807 #define ADIS16480_TEMP_CHANNEL() { \
808 .type = IIO_TEMP, \
809 .indexed = 1, \
810 .channel = 0, \
811 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
812 BIT(IIO_CHAN_INFO_SCALE) | \
813 BIT(IIO_CHAN_INFO_OFFSET), \
814 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
815 .address = ADIS16480_REG_TEMP_OUT, \
816 .scan_index = ADIS16480_SCAN_TEMP, \
817 .scan_type = { \
818 .sign = 's', \
819 .realbits = 16, \
820 .storagebits = 16, \
821 .endianness = IIO_BE, \
822 }, \
823 }
824
825 static const struct iio_chan_spec adis16480_channels[] = {
826 ADIS16480_GYRO_CHANNEL(X),
827 ADIS16480_GYRO_CHANNEL(Y),
828 ADIS16480_GYRO_CHANNEL(Z),
829 ADIS16480_ACCEL_CHANNEL(X),
830 ADIS16480_ACCEL_CHANNEL(Y),
831 ADIS16480_ACCEL_CHANNEL(Z),
832 ADIS16480_MAGN_CHANNEL(X),
833 ADIS16480_MAGN_CHANNEL(Y),
834 ADIS16480_MAGN_CHANNEL(Z),
835 ADIS16480_PRESSURE_CHANNEL(),
836 ADIS16480_TEMP_CHANNEL(),
837 IIO_CHAN_SOFT_TIMESTAMP(11),
838 ADIS16480_DELTANG_CHANNEL_NO_SCAN(X),
839 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y),
840 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z),
841 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X),
842 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y),
843 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z),
844 };
845
846 static const struct iio_chan_spec adis16485_channels[] = {
847 ADIS16480_GYRO_CHANNEL(X),
848 ADIS16480_GYRO_CHANNEL(Y),
849 ADIS16480_GYRO_CHANNEL(Z),
850 ADIS16480_ACCEL_CHANNEL(X),
851 ADIS16480_ACCEL_CHANNEL(Y),
852 ADIS16480_ACCEL_CHANNEL(Z),
853 ADIS16480_TEMP_CHANNEL(),
854 IIO_CHAN_SOFT_TIMESTAMP(7),
855 ADIS16480_DELTANG_CHANNEL_NO_SCAN(X),
856 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y),
857 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z),
858 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X),
859 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y),
860 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z),
861 };
862
863 static const struct iio_chan_spec adis16545_channels[] = {
864 ADIS16480_GYRO_CHANNEL(X),
865 ADIS16480_GYRO_CHANNEL(Y),
866 ADIS16480_GYRO_CHANNEL(Z),
867 ADIS16480_ACCEL_CHANNEL(X),
868 ADIS16480_ACCEL_CHANNEL(Y),
869 ADIS16480_ACCEL_CHANNEL(Z),
870 ADIS16480_TEMP_CHANNEL(),
871 ADIS16480_DELTANG_CHANNEL(X),
872 ADIS16480_DELTANG_CHANNEL(Y),
873 ADIS16480_DELTANG_CHANNEL(Z),
874 ADIS16480_DELTVEL_CHANNEL(X),
875 ADIS16480_DELTVEL_CHANNEL(Y),
876 ADIS16480_DELTVEL_CHANNEL(Z),
877 IIO_CHAN_SOFT_TIMESTAMP(17),
878 };
879
880 static const struct iio_chan_spec adis16489_channels[] = {
881 ADIS16480_GYRO_CHANNEL(X),
882 ADIS16480_GYRO_CHANNEL(Y),
883 ADIS16480_GYRO_CHANNEL(Z),
884 ADIS16480_ACCEL_CHANNEL(X),
885 ADIS16480_ACCEL_CHANNEL(Y),
886 ADIS16480_ACCEL_CHANNEL(Z),
887 ADIS16480_PRESSURE_CHANNEL(),
888 ADIS16480_TEMP_CHANNEL(),
889 IIO_CHAN_SOFT_TIMESTAMP(8),
890 ADIS16480_DELTANG_CHANNEL_NO_SCAN(X),
891 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y),
892 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z),
893 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X),
894 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y),
895 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z),
896 };
897
898 enum adis16480_variant {
899 ADIS16375,
900 ADIS16480,
901 ADIS16485,
902 ADIS16486,
903 ADIS16487,
904 ADIS16488,
905 ADIS16489,
906 ADIS16490,
907 ADIS16495_1,
908 ADIS16495_2,
909 ADIS16495_3,
910 ADIS16497_1,
911 ADIS16497_2,
912 ADIS16497_3,
913 ADIS16545_1,
914 ADIS16545_2,
915 ADIS16545_3,
916 ADIS16547_1,
917 ADIS16547_2,
918 ADIS16547_3
919 };
920
921 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0
922 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1
923 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2
924 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3
925 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4
926 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5
927 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8
928 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9
929 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10
930 #define ADIS16480_DIAG_STAT_BARO_FAIL 11
931
932 static const char * const adis16480_status_error_msgs[] = {
933 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure",
934 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure",
935 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure",
936 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure",
937 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure",
938 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure",
939 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure",
940 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure",
941 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure",
942 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure",
943 };
944
945 static int adis16480_enable_irq(struct adis *adis, bool enable);
946
947 #define ADIS16480_DATA(_prod_id, _timeouts, _burst_len, _burst_max_speed) \
948 { \
949 .diag_stat_reg = ADIS16480_REG_DIAG_STS, \
950 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \
951 .prod_id_reg = ADIS16480_REG_PROD_ID, \
952 .prod_id = (_prod_id), \
953 .has_paging = true, \
954 .read_delay = 5, \
955 .write_delay = 5, \
956 .self_test_mask = BIT(1), \
957 .self_test_reg = ADIS16480_REG_GLOB_CMD, \
958 .status_error_msgs = adis16480_status_error_msgs, \
959 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | \
960 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | \
961 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | \
962 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | \
963 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | \
964 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | \
965 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | \
966 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | \
967 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | \
968 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \
969 .enable_irq = adis16480_enable_irq, \
970 .timeouts = (_timeouts), \
971 .burst_reg_cmd = ADIS16495_REG_BURST_CMD, \
972 .burst_len = (_burst_len), \
973 .burst_max_speed_hz = _burst_max_speed \
974 }
975
976 static const struct adis_timeout adis16485_timeouts = {
977 .reset_ms = 560,
978 .sw_reset_ms = 120,
979 .self_test_ms = 12,
980 };
981
982 static const struct adis_timeout adis16480_timeouts = {
983 .reset_ms = 560,
984 .sw_reset_ms = 560,
985 .self_test_ms = 12,
986 };
987
988 static const struct adis_timeout adis16495_timeouts = {
989 .reset_ms = 170,
990 .sw_reset_ms = 130,
991 .self_test_ms = 40,
992 };
993
994 static const struct adis_timeout adis16495_1_timeouts = {
995 .reset_ms = 250,
996 .sw_reset_ms = 210,
997 .self_test_ms = 20,
998 };
999
1000 static const struct adis_timeout adis16545_timeouts = {
1001 .reset_ms = 315,
1002 .sw_reset_ms = 270,
1003 .self_test_ms = 35,
1004 };
1005
1006 static const struct adis16480_chip_info adis16480_chip_info[] = {
1007 [ADIS16375] = {
1008 .channels = adis16485_channels,
1009 .num_channels = ARRAY_SIZE(adis16485_channels),
1010 /*
1011 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which
1012 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since
1013 * it gives better approximation. However, in this case we
1014 * cannot do it since it would not fit in a 32bit variable.
1015 */
1016 .gyro_max_val = 22887 << 16,
1017 .gyro_max_scale = IIO_DEGREE_TO_RAD(300),
1018 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16),
1019 .accel_max_scale = 18,
1020 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1021 .deltang_max_val = IIO_DEGREE_TO_RAD(180),
1022 .deltvel_max_val = 100,
1023 .int_clk = 2460000,
1024 .max_dec_rate = 2048,
1025 .has_sleep_cnt = true,
1026 .filter_freqs = adis16480_def_filter_freqs,
1027 .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts, 0, 0),
1028 },
1029 [ADIS16480] = {
1030 .channels = adis16480_channels,
1031 .num_channels = ARRAY_SIZE(adis16480_channels),
1032 .gyro_max_val = 22500 << 16,
1033 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1034 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16),
1035 .accel_max_scale = 10,
1036 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1037 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1038 .deltvel_max_val = 200,
1039 .int_clk = 2460000,
1040 .max_dec_rate = 2048,
1041 .has_sleep_cnt = true,
1042 .filter_freqs = adis16480_def_filter_freqs,
1043 .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts, 0, 0),
1044 },
1045 [ADIS16485] = {
1046 .channels = adis16485_channels,
1047 .num_channels = ARRAY_SIZE(adis16485_channels),
1048 .gyro_max_val = 22500 << 16,
1049 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1050 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
1051 .accel_max_scale = 5,
1052 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1053 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1054 .deltvel_max_val = 50,
1055 .int_clk = 2460000,
1056 .max_dec_rate = 2048,
1057 .has_sleep_cnt = true,
1058 .filter_freqs = adis16480_def_filter_freqs,
1059 .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts, 0, 0),
1060 },
1061 [ADIS16486] = {
1062 .channels = adis16485_channels,
1063 .num_channels = ARRAY_SIZE(adis16485_channels),
1064 .gyro_max_val = 22500 << 16,
1065 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1066 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
1067 .accel_max_scale = 18,
1068 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1069 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1070 .deltvel_max_val = 200,
1071 .int_clk = 2460000,
1072 .max_dec_rate = 2048,
1073 .has_sleep_cnt = true,
1074 .filter_freqs = adis16480_def_filter_freqs,
1075 .adis_data = ADIS16480_DATA(16486, &adis16480_timeouts, 0, 0),
1076 },
1077 [ADIS16487] = {
1078 .channels = adis16485_channels,
1079 .num_channels = ARRAY_SIZE(adis16485_channels),
1080 .gyro_max_val = 22500 << 16,
1081 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1082 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
1083 .accel_max_scale = 5,
1084 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1085 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1086 .deltvel_max_val = 50,
1087 .int_clk = 2460000,
1088 .max_dec_rate = 2048,
1089 .has_sleep_cnt = true,
1090 .filter_freqs = adis16480_def_filter_freqs,
1091 .adis_data = ADIS16480_DATA(16487, &adis16485_timeouts, 0, 0),
1092 },
1093 [ADIS16488] = {
1094 .channels = adis16480_channels,
1095 .num_channels = ARRAY_SIZE(adis16480_channels),
1096 .gyro_max_val = 22500 << 16,
1097 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1098 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16),
1099 .accel_max_scale = 18,
1100 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1101 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1102 .deltvel_max_val = 200,
1103 .int_clk = 2460000,
1104 .max_dec_rate = 2048,
1105 .has_sleep_cnt = true,
1106 .filter_freqs = adis16480_def_filter_freqs,
1107 .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts, 0, 0),
1108 },
1109 [ADIS16489] = {
1110 .channels = adis16489_channels,
1111 .num_channels = ARRAY_SIZE(adis16489_channels),
1112 .gyro_max_val = 22500 << 16,
1113 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1114 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
1115 .accel_max_scale = 18,
1116 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1117 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1118 .deltvel_max_val = 200,
1119 .int_clk = 2460000,
1120 .max_dec_rate = 2048,
1121 .has_sleep_cnt = true,
1122 .filter_freqs = adis16480_def_filter_freqs,
1123 .adis_data = ADIS16480_DATA(16489, &adis16480_timeouts, 0, 0),
1124 },
1125 [ADIS16490] = {
1126 .channels = adis16485_channels,
1127 .num_channels = ARRAY_SIZE(adis16485_channels),
1128 .gyro_max_val = 20000 << 16,
1129 .gyro_max_scale = IIO_DEGREE_TO_RAD(100),
1130 .accel_max_val = IIO_M_S_2_TO_G(16000 << 16),
1131 .accel_max_scale = 8,
1132 .temp_scale = 14285, /* 14.285 milli degree Celsius */
1133 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1134 .deltvel_max_val = 200,
1135 .int_clk = 4250000,
1136 .max_dec_rate = 4250,
1137 .filter_freqs = adis16495_def_filter_freqs,
1138 .has_pps_clk_mode = true,
1139 .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts, 0, 0),
1140 },
1141 [ADIS16495_1] = {
1142 .channels = adis16485_channels,
1143 .num_channels = ARRAY_SIZE(adis16485_channels),
1144 .gyro_max_val = 20000 << 16,
1145 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1146 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1147 .accel_max_scale = 8,
1148 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1149 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1150 .deltvel_max_val = 100,
1151 .int_clk = 4250000,
1152 .max_dec_rate = 4250,
1153 .filter_freqs = adis16495_def_filter_freqs,
1154 .has_pps_clk_mode = true,
1155 /* 20 elements of 16bits */
1156 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1157 ADIS16495_BURST_MAX_DATA * 2,
1158 6000000),
1159 },
1160 [ADIS16495_2] = {
1161 .channels = adis16485_channels,
1162 .num_channels = ARRAY_SIZE(adis16485_channels),
1163 .gyro_max_val = 18000 << 16,
1164 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1165 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1166 .accel_max_scale = 8,
1167 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1168 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1169 .deltvel_max_val = 100,
1170 .int_clk = 4250000,
1171 .max_dec_rate = 4250,
1172 .filter_freqs = adis16495_def_filter_freqs,
1173 .has_pps_clk_mode = true,
1174 /* 20 elements of 16bits */
1175 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1176 ADIS16495_BURST_MAX_DATA * 2,
1177 6000000),
1178 },
1179 [ADIS16495_3] = {
1180 .channels = adis16485_channels,
1181 .num_channels = ARRAY_SIZE(adis16485_channels),
1182 .gyro_max_val = 20000 << 16,
1183 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1184 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1185 .accel_max_scale = 8,
1186 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1187 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1188 .deltvel_max_val = 100,
1189 .int_clk = 4250000,
1190 .max_dec_rate = 4250,
1191 .filter_freqs = adis16495_def_filter_freqs,
1192 .has_pps_clk_mode = true,
1193 /* 20 elements of 16bits */
1194 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1195 ADIS16495_BURST_MAX_DATA * 2,
1196 6000000),
1197 },
1198 [ADIS16497_1] = {
1199 .channels = adis16485_channels,
1200 .num_channels = ARRAY_SIZE(adis16485_channels),
1201 .gyro_max_val = 20000 << 16,
1202 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1203 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1204 .accel_max_scale = 40,
1205 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1206 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1207 .deltvel_max_val = 400,
1208 .int_clk = 4250000,
1209 .max_dec_rate = 4250,
1210 .filter_freqs = adis16495_def_filter_freqs,
1211 .has_pps_clk_mode = true,
1212 /* 20 elements of 16bits */
1213 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1214 ADIS16495_BURST_MAX_DATA * 2,
1215 6000000),
1216 },
1217 [ADIS16497_2] = {
1218 .channels = adis16485_channels,
1219 .num_channels = ARRAY_SIZE(adis16485_channels),
1220 .gyro_max_val = 18000 << 16,
1221 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1222 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1223 .accel_max_scale = 40,
1224 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1225 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1226 .deltvel_max_val = 400,
1227 .int_clk = 4250000,
1228 .max_dec_rate = 4250,
1229 .filter_freqs = adis16495_def_filter_freqs,
1230 .has_pps_clk_mode = true,
1231 /* 20 elements of 16bits */
1232 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1233 ADIS16495_BURST_MAX_DATA * 2,
1234 6000000),
1235 },
1236 [ADIS16497_3] = {
1237 .channels = adis16485_channels,
1238 .num_channels = ARRAY_SIZE(adis16485_channels),
1239 .gyro_max_val = 20000 << 16,
1240 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1241 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1242 .accel_max_scale = 40,
1243 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1244 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1245 .deltvel_max_val = 400,
1246 .int_clk = 4250000,
1247 .max_dec_rate = 4250,
1248 .filter_freqs = adis16495_def_filter_freqs,
1249 .has_pps_clk_mode = true,
1250 /* 20 elements of 16bits */
1251 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1252 ADIS16495_BURST_MAX_DATA * 2,
1253 6000000),
1254 },
1255 [ADIS16545_1] = {
1256 .channels = adis16545_channels,
1257 .num_channels = ARRAY_SIZE(adis16545_channels),
1258 .gyro_max_val = 20000 << 16,
1259 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1260 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1261 .accel_max_scale = 8,
1262 .temp_scale = 7000, /* 7 milli degree Celsius */
1263 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1264 .deltvel_max_val = 100,
1265 .int_clk = 4250000,
1266 .max_dec_rate = 4250,
1267 .filter_freqs = adis16495_def_filter_freqs,
1268 .has_pps_clk_mode = true,
1269 .has_burst_delta_data = true,
1270 /* 20 elements of 16bits */
1271 .adis_data = ADIS16480_DATA(16545, &adis16545_timeouts,
1272 ADIS16495_BURST_MAX_DATA * 2,
1273 6500000),
1274 },
1275 [ADIS16545_2] = {
1276 .channels = adis16545_channels,
1277 .num_channels = ARRAY_SIZE(adis16545_channels),
1278 .gyro_max_val = 18000 << 16,
1279 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1280 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1281 .accel_max_scale = 8,
1282 .temp_scale = 7000, /* 7 milli degree Celsius */
1283 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1284 .deltvel_max_val = 100,
1285 .int_clk = 4250000,
1286 .max_dec_rate = 4250,
1287 .filter_freqs = adis16495_def_filter_freqs,
1288 .has_pps_clk_mode = true,
1289 .has_burst_delta_data = true,
1290 /* 20 elements of 16bits */
1291 .adis_data = ADIS16480_DATA(16545, &adis16545_timeouts,
1292 ADIS16495_BURST_MAX_DATA * 2,
1293 6500000),
1294 },
1295 [ADIS16545_3] = {
1296 .channels = adis16545_channels,
1297 .num_channels = ARRAY_SIZE(adis16545_channels),
1298 .gyro_max_val = 20000 << 16,
1299 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1300 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1301 .accel_max_scale = 8,
1302 .temp_scale = 7000, /* 7 milli degree Celsius */
1303 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1304 .deltvel_max_val = 100,
1305 .int_clk = 4250000,
1306 .max_dec_rate = 4250,
1307 .filter_freqs = adis16495_def_filter_freqs,
1308 .has_pps_clk_mode = true,
1309 .has_burst_delta_data = true,
1310 /* 20 elements of 16bits */
1311 .adis_data = ADIS16480_DATA(16545, &adis16545_timeouts,
1312 ADIS16495_BURST_MAX_DATA * 2,
1313 6500000),
1314 },
1315 [ADIS16547_1] = {
1316 .channels = adis16545_channels,
1317 .num_channels = ARRAY_SIZE(adis16545_channels),
1318 .gyro_max_val = 20000 << 16,
1319 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1320 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1321 .accel_max_scale = 40,
1322 .temp_scale = 7000, /* 7 milli degree Celsius */
1323 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1324 .deltvel_max_val = 400,
1325 .int_clk = 4250000,
1326 .max_dec_rate = 4250,
1327 .filter_freqs = adis16495_def_filter_freqs,
1328 .has_pps_clk_mode = true,
1329 .has_burst_delta_data = true,
1330 /* 20 elements of 16bits */
1331 .adis_data = ADIS16480_DATA(16547, &adis16545_timeouts,
1332 ADIS16495_BURST_MAX_DATA * 2,
1333 6500000),
1334 },
1335 [ADIS16547_2] = {
1336 .channels = adis16545_channels,
1337 .num_channels = ARRAY_SIZE(adis16545_channels),
1338 .gyro_max_val = 18000 << 16,
1339 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1340 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1341 .accel_max_scale = 40,
1342 .temp_scale = 7000, /* 7 milli degree Celsius */
1343 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1344 .deltvel_max_val = 400,
1345 .int_clk = 4250000,
1346 .max_dec_rate = 4250,
1347 .filter_freqs = adis16495_def_filter_freqs,
1348 .has_pps_clk_mode = true,
1349 .has_burst_delta_data = true,
1350 /* 20 elements of 16bits */
1351 .adis_data = ADIS16480_DATA(16547, &adis16545_timeouts,
1352 ADIS16495_BURST_MAX_DATA * 2,
1353 6500000),
1354 },
1355 [ADIS16547_3] = {
1356 .channels = adis16545_channels,
1357 .num_channels = ARRAY_SIZE(adis16545_channels),
1358 .gyro_max_val = 20000 << 16,
1359 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1360 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1361 .accel_max_scale = 40,
1362 .temp_scale = 7000, /* 7 milli degree Celsius */
1363 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1364 .deltvel_max_val = 400,
1365 .int_clk = 4250000,
1366 .max_dec_rate = 4250,
1367 .filter_freqs = adis16495_def_filter_freqs,
1368 .has_pps_clk_mode = true,
1369 .has_burst_delta_data = true,
1370 /* 20 elements of 16bits */
1371 .adis_data = ADIS16480_DATA(16547, &adis16545_timeouts,
1372 ADIS16495_BURST_MAX_DATA * 2,
1373 6500000),
1374 },
1375 };
1376
adis16480_validate_crc(const u16 * buf,const u8 n_elem,const u32 crc)1377 static bool adis16480_validate_crc(const u16 *buf, const u8 n_elem, const u32 crc)
1378 {
1379 u32 crc_calc;
1380 u16 crc_buf[15];
1381 int j;
1382
1383 for (j = 0; j < n_elem; j++)
1384 crc_buf[j] = swab16(buf[j]);
1385
1386 crc_calc = crc32(~0, crc_buf, n_elem * 2);
1387 crc_calc ^= ~0;
1388
1389 return (crc == crc_calc);
1390 }
1391
adis16480_trigger_handler(int irq,void * p)1392 static irqreturn_t adis16480_trigger_handler(int irq, void *p)
1393 {
1394 struct iio_poll_func *pf = p;
1395 struct iio_dev *indio_dev = pf->indio_dev;
1396 struct adis16480 *st = iio_priv(indio_dev);
1397 struct adis *adis = &st->adis;
1398 struct device *dev = &adis->spi->dev;
1399 int ret, bit, offset, i = 0, buff_offset = 0;
1400 __be16 *buffer;
1401 u32 crc;
1402 bool valid;
1403
1404 adis_dev_auto_scoped_lock(adis) {
1405 if (adis->current_page != 0) {
1406 adis->tx[0] = ADIS_WRITE_REG(ADIS_REG_PAGE_ID);
1407 adis->tx[1] = 0;
1408 ret = spi_write(adis->spi, adis->tx, 2);
1409 if (ret) {
1410 dev_err(dev, "Failed to change device page: %d\n", ret);
1411 goto irq_done;
1412 }
1413
1414 adis->current_page = 0;
1415 }
1416
1417 ret = spi_sync(adis->spi, &adis->msg);
1418 if (ret) {
1419 dev_err(dev, "Failed to read data: %d\n", ret);
1420 goto irq_done;
1421 }
1422 }
1423
1424 /*
1425 * After making the burst request, the response can have one or two
1426 * 16-bit responses containing the BURST_ID depending on the sclk. If
1427 * clk > 3.6MHz, then we will have two BURST_ID in a row. If clk < 3MHZ,
1428 * we have only one. To manage that variation, we use the transition from the
1429 * BURST_ID to the SYS_E_FLAG register, which will not be equal to 0xA5A5/0xC3C3.
1430 * If we not find this variation in the first 4 segments, then the data should
1431 * not be valid.
1432 */
1433 buffer = adis->buffer;
1434 for (offset = 0; offset < 4; offset++) {
1435 u16 curr = be16_to_cpu(buffer[offset]);
1436 u16 next = be16_to_cpu(buffer[offset + 1]);
1437
1438 if (curr == st->burst_id && next != st->burst_id) {
1439 offset++;
1440 break;
1441 }
1442 }
1443
1444 if (offset == 4) {
1445 dev_err(dev, "Invalid burst data\n");
1446 goto irq_done;
1447 }
1448
1449 crc = be16_to_cpu(buffer[offset + 16]) << 16 | be16_to_cpu(buffer[offset + 15]);
1450 valid = adis16480_validate_crc((u16 *)&buffer[offset], 15, crc);
1451 if (!valid) {
1452 dev_err(dev, "Invalid crc\n");
1453 goto irq_done;
1454 }
1455
1456 iio_for_each_active_channel(indio_dev, bit) {
1457 /*
1458 * When burst mode is used, temperature is the first data
1459 * channel in the sequence, but the temperature scan index
1460 * is 10.
1461 */
1462 switch (bit) {
1463 case ADIS16480_SCAN_TEMP:
1464 st->data[i++] = buffer[offset + 1];
1465 /*
1466 * The temperature channel has 16-bit storage size.
1467 * We need to perform the padding to have the buffer
1468 * elements naturally aligned in case there are any
1469 * 32-bit storage size channels enabled which are added
1470 * in the buffer after the temperature data. In case
1471 * there is no data being added after the temperature
1472 * data, the padding is harmless.
1473 */
1474 st->data[i++] = 0;
1475 break;
1476 case ADIS16480_SCAN_DELTANG_X ... ADIS16480_SCAN_DELTVEL_Z:
1477 buff_offset = ADIS16480_SCAN_DELTANG_X;
1478 fallthrough;
1479 case ADIS16480_SCAN_GYRO_X ... ADIS16480_SCAN_ACCEL_Z:
1480 /* The lower register data is sequenced first */
1481 st->data[i++] = buffer[2 * (bit - buff_offset) + offset + 3];
1482 st->data[i++] = buffer[2 * (bit - buff_offset) + offset + 2];
1483 break;
1484 }
1485 }
1486
1487 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
1488 irq_done:
1489 iio_trigger_notify_done(indio_dev->trig);
1490
1491 return IRQ_HANDLED;
1492 }
1493
1494 static const unsigned long adis16545_channel_masks[] = {
1495 ADIS16545_BURST_DATA_SEL_0_CHN_MASK | BIT(ADIS16480_SCAN_TEMP) | BIT(17),
1496 ADIS16545_BURST_DATA_SEL_1_CHN_MASK | BIT(ADIS16480_SCAN_TEMP) | BIT(17),
1497 0,
1498 };
1499
adis16480_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1500 static int adis16480_update_scan_mode(struct iio_dev *indio_dev,
1501 const unsigned long *scan_mask)
1502 {
1503 u16 en;
1504 int ret;
1505 struct adis16480 *st = iio_priv(indio_dev);
1506
1507 if (st->chip_info->has_burst_delta_data) {
1508 if (*scan_mask & ADIS16545_BURST_DATA_SEL_0_CHN_MASK) {
1509 en = FIELD_PREP(ADIS16545_BURST_DATA_SEL_MASK, 0);
1510 st->burst_id = ADIS16495_GYRO_ACCEL_BURST_ID;
1511 } else {
1512 en = FIELD_PREP(ADIS16545_BURST_DATA_SEL_MASK, 1);
1513 st->burst_id = ADIS16545_DELTA_ANG_VEL_BURST_ID;
1514 }
1515
1516 ret = __adis_update_bits(&st->adis, ADIS16480_REG_CONFIG,
1517 ADIS16545_BURST_DATA_SEL_MASK, en);
1518 if (ret)
1519 return ret;
1520 }
1521
1522 return adis_update_scan_mode(indio_dev, scan_mask);
1523 }
1524
1525 static const struct iio_info adis16480_info = {
1526 .read_raw = &adis16480_read_raw,
1527 .write_raw = &adis16480_write_raw,
1528 .update_scan_mode = &adis16480_update_scan_mode,
1529 .debugfs_reg_access = adis_debugfs_reg_access,
1530 };
1531
adis16480_stop_device(struct iio_dev * indio_dev)1532 static int adis16480_stop_device(struct iio_dev *indio_dev)
1533 {
1534 struct adis16480 *st = iio_priv(indio_dev);
1535 struct device *dev = &st->adis.spi->dev;
1536 int ret;
1537
1538 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9));
1539 if (ret)
1540 dev_err(dev, "Could not power down device: %d\n", ret);
1541
1542 return ret;
1543 }
1544
adis16480_enable_irq(struct adis * adis,bool enable)1545 static int adis16480_enable_irq(struct adis *adis, bool enable)
1546 {
1547 uint16_t val;
1548 int ret;
1549
1550 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1551 if (ret)
1552 return ret;
1553
1554 val &= ~ADIS16480_DRDY_EN_MSK;
1555 val |= ADIS16480_DRDY_EN(enable);
1556
1557 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val);
1558 }
1559
adis16480_config_irq_pin(struct adis16480 * st)1560 static int adis16480_config_irq_pin(struct adis16480 *st)
1561 {
1562 struct device *dev = &st->adis.spi->dev;
1563 struct fwnode_handle *fwnode = dev_fwnode(dev);
1564 enum adis16480_int_pin pin;
1565 unsigned int irq_type;
1566 uint16_t val;
1567 int i, irq = 0;
1568
1569 /* Disable data ready since the default after reset is on */
1570 val = ADIS16480_DRDY_EN(0);
1571
1572 /*
1573 * Get the interrupt from the devicetre by reading the interrupt-names
1574 * property. If it is not specified, use DIO1 pin as default.
1575 * According to the datasheet, the factory default assigns DIO2 as data
1576 * ready signal. However, in the previous versions of the driver, DIO1
1577 * pin was used. So, we should leave it as is since some devices might
1578 * be expecting the interrupt on the wrong physical pin.
1579 */
1580 pin = ADIS16480_PIN_DIO1;
1581 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1582 irq = fwnode_irq_get_byname(fwnode, adis16480_int_pin_names[i]);
1583 if (irq > 0) {
1584 pin = i;
1585 break;
1586 }
1587 }
1588
1589 val |= ADIS16480_DRDY_SEL(pin);
1590
1591 /*
1592 * Get the interrupt line behaviour. The data ready polarity can be
1593 * configured as positive or negative, corresponding to
1594 * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively.
1595 */
1596 irq_type = irq_get_trigger_type(st->adis.spi->irq);
1597 if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */
1598 val |= ADIS16480_DRDY_POL(1);
1599 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
1600 val |= ADIS16480_DRDY_POL(0);
1601 } else {
1602 dev_err(dev, "Invalid interrupt type 0x%x specified\n", irq_type);
1603 return -EINVAL;
1604 }
1605 /* Write the data ready configuration to the FNCTIO_CTRL register */
1606 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1607 }
1608
adis16480_fw_get_ext_clk_pin(struct adis16480 * st)1609 static int adis16480_fw_get_ext_clk_pin(struct adis16480 *st)
1610 {
1611 struct device *dev = &st->adis.spi->dev;
1612 const char *ext_clk_pin;
1613 enum adis16480_int_pin pin;
1614 int i;
1615
1616 pin = ADIS16480_PIN_DIO2;
1617 if (device_property_read_string(dev, "adi,ext-clk-pin", &ext_clk_pin))
1618 goto clk_input_not_found;
1619
1620 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1621 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0)
1622 return i;
1623 }
1624
1625 clk_input_not_found:
1626 dev_info(dev, "clk input line not specified, using DIO2\n");
1627 return pin;
1628 }
1629
adis16480_ext_clk_config(struct adis16480 * st,bool enable)1630 static int adis16480_ext_clk_config(struct adis16480 *st, bool enable)
1631 {
1632 struct device *dev = &st->adis.spi->dev;
1633 unsigned int mode, mask;
1634 enum adis16480_int_pin pin;
1635 uint16_t val;
1636 int ret;
1637
1638 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1639 if (ret)
1640 return ret;
1641
1642 pin = adis16480_fw_get_ext_clk_pin(st);
1643 /*
1644 * Each DIOx pin supports only one function at a time. When a single pin
1645 * has two assignments, the enable bit for a lower priority function
1646 * automatically resets to zero (disabling the lower priority function).
1647 */
1648 if (pin == ADIS16480_DRDY_SEL(val))
1649 dev_warn(dev, "DIO%x pin supports only one function at a time\n", pin + 1);
1650
1651 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin);
1652 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK;
1653 /* Only ADIS1649x devices support pps ext clock mode */
1654 if (st->chip_info->has_pps_clk_mode) {
1655 mode |= ADIS16480_SYNC_MODE(st->clk_mode);
1656 mask |= ADIS16480_SYNC_MODE_MSK;
1657 }
1658
1659 val &= ~mask;
1660 val |= mode;
1661
1662 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1663 if (ret)
1664 return ret;
1665
1666 return clk_prepare_enable(st->ext_clk);
1667 }
1668
adis16480_get_ext_clocks(struct adis16480 * st)1669 static int adis16480_get_ext_clocks(struct adis16480 *st)
1670 {
1671 struct device *dev = &st->adis.spi->dev;
1672
1673 st->ext_clk = devm_clk_get_optional(dev, "sync");
1674 if (IS_ERR(st->ext_clk))
1675 return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n");
1676 if (st->ext_clk) {
1677 st->clk_mode = ADIS16480_CLK_SYNC;
1678 return 0;
1679 }
1680
1681 if (st->chip_info->has_pps_clk_mode) {
1682 st->ext_clk = devm_clk_get_optional(dev, "pps");
1683 if (IS_ERR(st->ext_clk))
1684 return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n");
1685 if (st->ext_clk) {
1686 st->clk_mode = ADIS16480_CLK_PPS;
1687 return 0;
1688 }
1689 }
1690
1691 st->clk_mode = ADIS16480_CLK_INT;
1692 return 0;
1693 }
1694
adis16480_stop(void * data)1695 static void adis16480_stop(void *data)
1696 {
1697 adis16480_stop_device(data);
1698 }
1699
adis16480_clk_disable(void * data)1700 static void adis16480_clk_disable(void *data)
1701 {
1702 clk_disable_unprepare(data);
1703 }
1704
adis16480_probe(struct spi_device * spi)1705 static int adis16480_probe(struct spi_device *spi)
1706 {
1707 const struct spi_device_id *id = spi_get_device_id(spi);
1708 const struct adis_data *adis16480_data;
1709 irq_handler_t trigger_handler = NULL;
1710 struct device *dev = &spi->dev;
1711 struct iio_dev *indio_dev;
1712 struct adis16480 *st;
1713 int ret;
1714
1715 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1716 if (indio_dev == NULL)
1717 return -ENOMEM;
1718
1719 st = iio_priv(indio_dev);
1720
1721 st->chip_info = &adis16480_chip_info[id->driver_data];
1722 indio_dev->name = spi_get_device_id(spi)->name;
1723 indio_dev->channels = st->chip_info->channels;
1724 indio_dev->num_channels = st->chip_info->num_channels;
1725 if (st->chip_info->has_burst_delta_data)
1726 indio_dev->available_scan_masks = adis16545_channel_masks;
1727 indio_dev->info = &adis16480_info;
1728 indio_dev->modes = INDIO_DIRECT_MODE;
1729
1730 adis16480_data = &st->chip_info->adis_data;
1731
1732 ret = adis_init(&st->adis, indio_dev, spi, adis16480_data);
1733 if (ret)
1734 return ret;
1735
1736 ret = __adis_initial_startup(&st->adis);
1737 if (ret)
1738 return ret;
1739
1740 /*
1741 * By default, use burst id for gyroscope and accelerometer data.
1742 * This is the only option for devices which do not offer delta angle
1743 * and delta velocity burst readings.
1744 */
1745 st->burst_id = ADIS16495_GYRO_ACCEL_BURST_ID;
1746
1747 if (st->chip_info->has_sleep_cnt) {
1748 ret = devm_add_action_or_reset(dev, adis16480_stop, indio_dev);
1749 if (ret)
1750 return ret;
1751 }
1752
1753 ret = adis16480_config_irq_pin(st);
1754 if (ret)
1755 return ret;
1756
1757 ret = adis16480_get_ext_clocks(st);
1758 if (ret)
1759 return ret;
1760
1761 if (st->ext_clk) {
1762 ret = adis16480_ext_clk_config(st, true);
1763 if (ret)
1764 return ret;
1765
1766 ret = devm_add_action_or_reset(dev, adis16480_clk_disable, st->ext_clk);
1767 if (ret)
1768 return ret;
1769
1770 st->clk_freq = clk_get_rate(st->ext_clk);
1771 st->clk_freq *= 1000; /* micro */
1772 if (st->clk_mode == ADIS16480_CLK_PPS) {
1773 u16 sync_scale;
1774
1775 /*
1776 * In PPS mode, the IMU sample rate is the clk_freq * sync_scale. Hence,
1777 * default the IMU sample rate to the highest multiple of the input clock
1778 * lower than the IMU max sample rate. The internal sample rate is the
1779 * max...
1780 */
1781 sync_scale = st->chip_info->int_clk / st->clk_freq;
1782 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale);
1783 if (ret)
1784 return ret;
1785 }
1786 } else {
1787 st->clk_freq = st->chip_info->int_clk;
1788 }
1789
1790 /* Only use our trigger handler if burst mode is supported */
1791 if (adis16480_data->burst_len)
1792 trigger_handler = adis16480_trigger_handler;
1793
1794 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
1795 trigger_handler);
1796 if (ret)
1797 return ret;
1798
1799 ret = devm_iio_device_register(dev, indio_dev);
1800 if (ret)
1801 return ret;
1802
1803 adis16480_debugfs_init(indio_dev);
1804
1805 return 0;
1806 }
1807
1808 static const struct spi_device_id adis16480_ids[] = {
1809 { .name = "adis16375", .driver_data = ADIS16375 },
1810 { .name = "adis16480", .driver_data = ADIS16480 },
1811 { .name = "adis16485", .driver_data = ADIS16485 },
1812 { .name = "adis16486", .driver_data = ADIS16486 },
1813 { .name = "adis16487", .driver_data = ADIS16487 },
1814 { .name = "adis16488", .driver_data = ADIS16488 },
1815 { .name = "adis16489", .driver_data = ADIS16489 },
1816 { .name = "adis16490", .driver_data = ADIS16490 },
1817 { .name = "adis16495-1", .driver_data = ADIS16495_1 },
1818 { .name = "adis16495-2", .driver_data = ADIS16495_2 },
1819 { .name = "adis16495-3", .driver_data = ADIS16495_3 },
1820 { .name = "adis16497-1", .driver_data = ADIS16497_1 },
1821 { .name = "adis16497-2", .driver_data = ADIS16497_2 },
1822 { .name = "adis16497-3", .driver_data = ADIS16497_3 },
1823 { .name = "adis16545-1", .driver_data = ADIS16545_1 },
1824 { .name = "adis16545-2", .driver_data = ADIS16545_2 },
1825 { .name = "adis16545-3", .driver_data = ADIS16545_3 },
1826 { .name = "adis16547-1", .driver_data = ADIS16547_1 },
1827 { .name = "adis16547-2", .driver_data = ADIS16547_2 },
1828 { .name = "adis16547-3", .driver_data = ADIS16547_3 },
1829 { }
1830 };
1831 MODULE_DEVICE_TABLE(spi, adis16480_ids);
1832
1833 static const struct of_device_id adis16480_of_match[] = {
1834 { .compatible = "adi,adis16375" },
1835 { .compatible = "adi,adis16480" },
1836 { .compatible = "adi,adis16485" },
1837 { .compatible = "adi,adis16486" },
1838 { .compatible = "adi,adis16487" },
1839 { .compatible = "adi,adis16488" },
1840 { .compatible = "adi,adis16489" },
1841 { .compatible = "adi,adis16490" },
1842 { .compatible = "adi,adis16495-1" },
1843 { .compatible = "adi,adis16495-2" },
1844 { .compatible = "adi,adis16495-3" },
1845 { .compatible = "adi,adis16497-1" },
1846 { .compatible = "adi,adis16497-2" },
1847 { .compatible = "adi,adis16497-3" },
1848 { .compatible = "adi,adis16545-1" },
1849 { .compatible = "adi,adis16545-2" },
1850 { .compatible = "adi,adis16545-3" },
1851 { .compatible = "adi,adis16547-1" },
1852 { .compatible = "adi,adis16547-2" },
1853 { .compatible = "adi,adis16547-3" },
1854 { }
1855 };
1856 MODULE_DEVICE_TABLE(of, adis16480_of_match);
1857
1858 static struct spi_driver adis16480_driver = {
1859 .driver = {
1860 .name = "adis16480",
1861 .of_match_table = adis16480_of_match,
1862 },
1863 .id_table = adis16480_ids,
1864 .probe = adis16480_probe,
1865 };
1866 module_spi_driver(adis16480_driver);
1867
1868 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1869 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver");
1870 MODULE_LICENSE("GPL v2");
1871 MODULE_IMPORT_NS("IIO_ADISLIB");
1872