1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2024 NXP. 4 * NXP PF9453 pmic driver 5 */ 6 7 #include <linux/bits.h> 8 #include <linux/err.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/driver.h> 18 #include <linux/regulator/machine.h> 19 #include <linux/regulator/of_regulator.h> 20 21 struct pf9453_dvs_config { 22 unsigned int run_reg; /* dvs0 */ 23 unsigned int run_mask; 24 unsigned int standby_reg; /* dvs1 */ 25 unsigned int standby_mask; 26 }; 27 28 struct pf9453_regulator_desc { 29 struct regulator_desc desc; 30 const struct pf9453_dvs_config dvs; 31 }; 32 33 struct pf9453 { 34 struct device *dev; 35 struct regmap *regmap; 36 struct gpio_desc *sd_vsel_gpio; 37 int irq; 38 }; 39 40 enum { 41 PF9453_BUCK1 = 0, 42 PF9453_BUCK2, 43 PF9453_BUCK3, 44 PF9453_BUCK4, 45 PF9453_LDO1, 46 PF9453_LDO2, 47 PF9453_LDOSNVS, 48 PF9453_REGULATOR_CNT 49 }; 50 51 enum { 52 PF9453_DVS_LEVEL_RUN = 0, 53 PF9453_DVS_LEVEL_STANDBY, 54 PF9453_DVS_LEVEL_DPSTANDBY, 55 PF9453_DVS_LEVEL_MAX 56 }; 57 58 #define PF9453_BUCK1_VOLTAGE_NUM 0x80 59 #define PF9453_BUCK2_VOLTAGE_NUM 0x80 60 #define PF9453_BUCK3_VOLTAGE_NUM 0x80 61 #define PF9453_BUCK4_VOLTAGE_NUM 0x80 62 63 #define PF9453_LDO1_VOLTAGE_NUM 0x65 64 #define PF9453_LDO2_VOLTAGE_NUM 0x3b 65 #define PF9453_LDOSNVS_VOLTAGE_NUM 0x59 66 67 enum { 68 PF9453_REG_DEV_ID = 0x01, 69 PF9453_REG_INT1 = 0x02, 70 PF9453_REG_INT1_MASK = 0x03, 71 PF9453_REG_INT1_STATUS = 0x04, 72 PF9453_REG_VRFLT1_INT = 0x05, 73 PF9453_REG_VRFLT1_MASK = 0x06, 74 PF9453_REG_PWRON_STAT = 0x07, 75 PF9453_REG_RESET_CTRL = 0x08, 76 PF9453_REG_SW_RST = 0x09, 77 PF9453_REG_PWR_CTRL = 0x0a, 78 PF9453_REG_CONFIG1 = 0x0b, 79 PF9453_REG_CONFIG2 = 0x0c, 80 PF9453_REG_32K_CONFIG = 0x0d, 81 PF9453_REG_BUCK1CTRL = 0x10, 82 PF9453_REG_BUCK1OUT = 0x11, 83 PF9453_REG_BUCK2CTRL = 0x14, 84 PF9453_REG_BUCK2OUT = 0x15, 85 PF9453_REG_BUCK2OUT_STBY = 0x1d, 86 PF9453_REG_BUCK2OUT_MAX_LIMIT = 0x1f, 87 PF9453_REG_BUCK2OUT_MIN_LIMIT = 0x20, 88 PF9453_REG_BUCK3CTRL = 0x21, 89 PF9453_REG_BUCK3OUT = 0x22, 90 PF9453_REG_BUCK4CTRL = 0x2e, 91 PF9453_REG_BUCK4OUT = 0x2f, 92 PF9453_REG_LDO1OUT_L = 0x36, 93 PF9453_REG_LDO1CFG = 0x37, 94 PF9453_REG_LDO1OUT_H = 0x38, 95 PF9453_REG_LDOSNVS_CFG1 = 0x39, 96 PF9453_REG_LDOSNVS_CFG2 = 0x3a, 97 PF9453_REG_LDO2CFG = 0x3b, 98 PF9453_REG_LDO2OUT = 0x3c, 99 PF9453_REG_BUCK_POK = 0x3d, 100 PF9453_REG_LSW_CTRL1 = 0x40, 101 PF9453_REG_LSW_CTRL2 = 0x41, 102 PF9453_REG_LOCK = 0x4e, 103 PF9453_MAX_REG 104 }; 105 106 #define PF9453_UNLOCK_KEY 0x5c 107 #define PF9453_LOCK_KEY 0x0 108 109 /* PF9453 BUCK ENMODE bits */ 110 #define BUCK_ENMODE_OFF 0x00 111 #define BUCK_ENMODE_ONREQ 0x01 112 #define BUCK_ENMODE_ONREQ_STBY 0x02 113 #define BUCK_ENMODE_ONREQ_STBY_DPSTBY 0x03 114 115 /* PF9453 BUCK ENMODE bits */ 116 #define LDO_ENMODE_OFF 0x00 117 #define LDO_ENMODE_ONREQ 0x01 118 #define LDO_ENMODE_ONREQ_STBY 0x02 119 #define LDO_ENMODE_ONREQ_STBY_DPSTBY 0x03 120 121 /* PF9453_REG_BUCK1_CTRL bits */ 122 #define BUCK1_AD 0x08 123 #define BUCK1_FPWM 0x04 124 #define BUCK1_ENMODE_MASK GENMASK(1, 0) 125 126 /* PF9453_REG_BUCK2_CTRL bits */ 127 #define BUCK2_RAMP_MASK GENMASK(7, 6) 128 #define BUCK2_RAMP_25MV 0x0 129 #define BUCK2_RAMP_12P5MV 0x1 130 #define BUCK2_RAMP_6P25MV 0x2 131 #define BUCK2_RAMP_3P125MV 0x3 132 #define BUCK2_AD 0x08 133 #define BUCK2_FPWM 0x04 134 #define BUCK2_ENMODE_MASK GENMASK(1, 0) 135 136 /* PF9453_REG_BUCK3_CTRL bits */ 137 #define BUCK3_AD 0x08 138 #define BUCK3_FPWM 0x04 139 #define BUCK3_ENMODE_MASK GENMASK(1, 0) 140 141 /* PF9453_REG_BUCK4_CTRL bits */ 142 #define BUCK4_AD 0x08 143 #define BUCK4_FPWM 0x04 144 #define BUCK4_ENMODE_MASK GENMASK(1, 0) 145 146 /* PF9453_REG_BUCK123_PRESET_EN bit */ 147 #define BUCK123_PRESET_EN 0x80 148 149 /* PF9453_BUCK1OUT bits */ 150 #define BUCK1OUT_MASK GENMASK(6, 0) 151 152 /* PF9453_BUCK2OUT bits */ 153 #define BUCK2OUT_MASK GENMASK(6, 0) 154 #define BUCK2OUT_STBY_MASK GENMASK(6, 0) 155 156 /* PF9453_REG_BUCK3OUT bits */ 157 #define BUCK3OUT_MASK GENMASK(6, 0) 158 159 /* PF9453_REG_BUCK4OUT bits */ 160 #define BUCK4OUT_MASK GENMASK(6, 0) 161 162 /* PF9453_REG_LDO1_VOLT bits */ 163 #define LDO1_EN_MASK GENMASK(1, 0) 164 #define LDO1OUT_MASK GENMASK(6, 0) 165 166 /* PF9453_REG_LDO2_VOLT bits */ 167 #define LDO2_EN_MASK GENMASK(1, 0) 168 #define LDO2OUT_MASK GENMASK(6, 0) 169 170 /* PF9453_REG_LDOSNVS_VOLT bits */ 171 #define LDOSNVS_EN_MASK GENMASK(0, 0) 172 #define LDOSNVSCFG1_MASK GENMASK(6, 0) 173 174 /* PF9453_REG_IRQ bits */ 175 #define IRQ_RSVD 0x80 176 #define IRQ_RSTB 0x40 177 #define IRQ_ONKEY 0x20 178 #define IRQ_RESETKEY 0x10 179 #define IRQ_VR_FLT1 0x08 180 #define IRQ_LOWVSYS 0x04 181 #define IRQ_THERM_100 0x02 182 #define IRQ_THERM_80 0x01 183 184 /* PF9453_REG_RESET_CTRL bits */ 185 #define WDOG_B_CFG_MASK GENMASK(7, 6) 186 #define WDOG_B_CFG_NONE 0x00 187 #define WDOG_B_CFG_WARM 0x40 188 #define WDOG_B_CFG_COLD 0x80 189 190 static const struct regmap_range pf9453_status_range = { 191 .range_min = PF9453_REG_INT1, 192 .range_max = PF9453_REG_PWRON_STAT, 193 }; 194 195 static const struct regmap_access_table pf9453_volatile_regs = { 196 .yes_ranges = &pf9453_status_range, 197 .n_yes_ranges = 1, 198 }; 199 200 static const struct regmap_config pf9453_regmap_config = { 201 .reg_bits = 8, 202 .val_bits = 8, 203 .volatile_table = &pf9453_volatile_regs, 204 .max_register = PF9453_MAX_REG - 1, 205 .cache_type = REGCACHE_MAPLE, 206 }; 207 208 /* 209 * BUCK2 210 * BUCK2RAM[1:0] BUCK2 DVS ramp rate setting 211 * 00: 25mV/1usec 212 * 01: 25mV/2usec 213 * 10: 25mV/4usec 214 * 11: 25mV/8usec 215 */ 216 static const unsigned int pf9453_dvs_buck_ramp_table[] = { 217 25000, 12500, 6250, 3125 218 }; 219 220 static bool is_reg_protect(uint reg) 221 { 222 switch (reg) { 223 case PF9453_REG_BUCK1OUT: 224 case PF9453_REG_BUCK2OUT: 225 case PF9453_REG_BUCK3OUT: 226 case PF9453_REG_BUCK4OUT: 227 case PF9453_REG_LDO1OUT_L: 228 case PF9453_REG_LDO1OUT_H: 229 case PF9453_REG_LDO2OUT: 230 case PF9453_REG_LDOSNVS_CFG1: 231 case PF9453_REG_BUCK2OUT_MAX_LIMIT: 232 case PF9453_REG_BUCK2OUT_MIN_LIMIT: 233 return true; 234 default: 235 return false; 236 } 237 } 238 239 static int pf9453_pmic_write(struct pf9453 *pf9453, unsigned int reg, u8 mask, unsigned int val) 240 { 241 int ret = -EINVAL; 242 u8 data, key; 243 u32 rxBuf; 244 245 /* If not updating entire register, perform a read-mod-write */ 246 data = val; 247 key = PF9453_UNLOCK_KEY; 248 249 if (mask != 0xffU) { 250 /* Read data */ 251 ret = regmap_read(pf9453->regmap, reg, &rxBuf); 252 if (ret) { 253 dev_err(pf9453->dev, "Read reg=%0x error!\n", reg); 254 return ret; 255 } 256 data = (val & mask) | (rxBuf & (~mask)); 257 } 258 259 if (reg < PF9453_MAX_REG) { 260 if (is_reg_protect(reg)) { 261 ret = regmap_raw_write(pf9453->regmap, PF9453_REG_LOCK, &key, 1U); 262 if (ret) { 263 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 264 return ret; 265 } 266 267 ret = regmap_raw_write(pf9453->regmap, reg, &data, 1U); 268 if (ret) { 269 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 270 return ret; 271 } 272 273 key = PF9453_LOCK_KEY; 274 ret = regmap_raw_write(pf9453->regmap, PF9453_REG_LOCK, &key, 1U); 275 if (ret) { 276 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 277 return ret; 278 } 279 } else { 280 ret = regmap_raw_write(pf9453->regmap, reg, &data, 1U); 281 if (ret) { 282 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 283 return ret; 284 } 285 } 286 } 287 288 return ret; 289 } 290 291 /** 292 * pf9453_regulator_enable_regmap - enable regulator for regmap users 293 * 294 * @rdev: regulator to operate on 295 * 296 * Regulators that use regmap for their register I/O can set the 297 * enable_reg and enable_mask fields in their descriptor and then use 298 * this as their enable() operation, saving some code. 299 * 300 * Return: %0 on success, or negative errno. 301 */ 302 static int pf9453_regulator_enable_regmap(struct regulator_dev *rdev) 303 { 304 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 305 unsigned int val; 306 307 if (rdev->desc->enable_is_inverted) { 308 val = rdev->desc->disable_val; 309 } else { 310 val = rdev->desc->enable_val; 311 if (!val) 312 val = rdev->desc->enable_mask; 313 } 314 315 return pf9453_pmic_write(pf9453, rdev->desc->enable_reg, rdev->desc->enable_mask, val); 316 } 317 318 /** 319 * pf9453_regulator_disable_regmap - disable regulator for regmap users 320 * 321 * @rdev: regulator to operate on 322 * 323 * Regulators that use regmap for their register I/O can set the 324 * enable_reg and enable_mask fields in their descriptor and then use 325 * this as their disable() operation, saving some code. 326 * 327 * Return: %0 on success, or negative errno. 328 */ 329 static int pf9453_regulator_disable_regmap(struct regulator_dev *rdev) 330 { 331 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 332 unsigned int val; 333 334 if (rdev->desc->enable_is_inverted) { 335 val = rdev->desc->enable_val; 336 if (!val) 337 val = rdev->desc->enable_mask; 338 } else { 339 val = rdev->desc->disable_val; 340 } 341 342 return pf9453_pmic_write(pf9453, rdev->desc->enable_reg, rdev->desc->enable_mask, val); 343 } 344 345 /** 346 * pf9453_regulator_set_voltage_sel_regmap - set voltage for regmap users 347 * 348 * @rdev: regulator to operate on 349 * @sel: Selector to set 350 * 351 * Regulators that use regmap for their register I/O can set the 352 * vsel_reg and vsel_mask fields in their descriptor and then use this 353 * as their set_voltage_vsel operation, saving some code. 354 * 355 * Return: %0 on success, or negative errno. 356 */ 357 static int pf9453_regulator_set_voltage_sel_regmap(struct regulator_dev *rdev, unsigned int sel) 358 { 359 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 360 int ret; 361 362 sel <<= ffs(rdev->desc->vsel_mask) - 1; 363 ret = pf9453_pmic_write(pf9453, rdev->desc->vsel_reg, rdev->desc->vsel_mask, sel); 364 if (ret) 365 return ret; 366 367 if (rdev->desc->apply_bit) 368 ret = pf9453_pmic_write(pf9453, rdev->desc->apply_reg, 369 rdev->desc->apply_bit, rdev->desc->apply_bit); 370 return ret; 371 } 372 373 static int find_closest_bigger(unsigned int target, const unsigned int *table, 374 unsigned int num_sel, unsigned int *sel) 375 { 376 unsigned int s, tmp, max, maxsel = 0; 377 bool found = false; 378 379 max = table[0]; 380 381 for (s = 0; s < num_sel; s++) { 382 if (table[s] > max) { 383 max = table[s]; 384 maxsel = s; 385 } 386 if (table[s] >= target) { 387 if (!found || table[s] - target < tmp - target) { 388 tmp = table[s]; 389 *sel = s; 390 found = true; 391 if (tmp == target) 392 break; 393 } 394 } 395 } 396 397 if (!found) { 398 *sel = maxsel; 399 return -EINVAL; 400 } 401 402 return 0; 403 } 404 405 /** 406 * pf9453_regulator_set_ramp_delay_regmap - set ramp delay for regmap users 407 * 408 * @rdev: regulator to operate on 409 * @ramp_delay: desired ramp delay value in microseconds 410 * 411 * Regulators that use regmap for their register I/O can set the ramp_reg 412 * and ramp_mask fields in their descriptor and then use this as their 413 * set_ramp_delay operation, saving some code. 414 * 415 * Return: %0 on success, or negative errno. 416 */ 417 static int pf9453_regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay) 418 { 419 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 420 unsigned int sel; 421 int ret; 422 423 if (WARN_ON(!rdev->desc->n_ramp_values || !rdev->desc->ramp_delay_table)) 424 return -EINVAL; 425 426 ret = find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table, 427 rdev->desc->n_ramp_values, &sel); 428 429 if (ret) { 430 dev_warn(rdev_get_dev(rdev), 431 "Can't set ramp-delay %u, setting %u\n", ramp_delay, 432 rdev->desc->ramp_delay_table[sel]); 433 } 434 435 sel <<= ffs(rdev->desc->ramp_mask) - 1; 436 437 return pf9453_pmic_write(pf9453, rdev->desc->ramp_reg, 438 rdev->desc->ramp_mask, sel); 439 } 440 441 static const struct regulator_ops pf9453_dvs_buck_regulator_ops = { 442 .enable = pf9453_regulator_enable_regmap, 443 .disable = pf9453_regulator_disable_regmap, 444 .is_enabled = regulator_is_enabled_regmap, 445 .list_voltage = regulator_list_voltage_linear_range, 446 .set_voltage_sel = pf9453_regulator_set_voltage_sel_regmap, 447 .get_voltage_sel = regulator_get_voltage_sel_regmap, 448 .set_voltage_time_sel = regulator_set_voltage_time_sel, 449 .set_ramp_delay = pf9453_regulator_set_ramp_delay_regmap, 450 }; 451 452 static const struct regulator_ops pf9453_buck_regulator_ops = { 453 .enable = pf9453_regulator_enable_regmap, 454 .disable = pf9453_regulator_disable_regmap, 455 .is_enabled = regulator_is_enabled_regmap, 456 .list_voltage = regulator_list_voltage_linear_range, 457 .set_voltage_sel = pf9453_regulator_set_voltage_sel_regmap, 458 .get_voltage_sel = regulator_get_voltage_sel_regmap, 459 .set_voltage_time_sel = regulator_set_voltage_time_sel, 460 }; 461 462 static const struct regulator_ops pf9453_ldo_regulator_ops = { 463 .enable = pf9453_regulator_enable_regmap, 464 .disable = pf9453_regulator_disable_regmap, 465 .is_enabled = regulator_is_enabled_regmap, 466 .list_voltage = regulator_list_voltage_linear_range, 467 .set_voltage_sel = pf9453_regulator_set_voltage_sel_regmap, 468 .get_voltage_sel = regulator_get_voltage_sel_regmap, 469 }; 470 471 /* 472 * BUCK1/3/4 473 * 0.60 to 3.775V (25mV step) 474 */ 475 static const struct linear_range pf9453_buck134_volts[] = { 476 REGULATOR_LINEAR_RANGE(600000, 0x00, 0x7F, 25000), 477 }; 478 479 /* 480 * BUCK2 481 * 0.60 to 2.1875V (12.5mV step) 482 */ 483 static const struct linear_range pf9453_buck2_volts[] = { 484 REGULATOR_LINEAR_RANGE(600000, 0x00, 0x7F, 12500), 485 }; 486 487 /* 488 * LDO1 489 * 0.8 to 3.3V (25mV step) 490 */ 491 static const struct linear_range pf9453_ldo1_volts[] = { 492 REGULATOR_LINEAR_RANGE(800000, 0x00, 0x64, 25000), 493 }; 494 495 /* 496 * LDO2 497 * 0.5 to 1.95V (25mV step) 498 */ 499 static const struct linear_range pf9453_ldo2_volts[] = { 500 REGULATOR_LINEAR_RANGE(500000, 0x00, 0x3A, 25000), 501 }; 502 503 /* 504 * LDOSNVS 505 * 1.2 to 3.4V (25mV step) 506 */ 507 static const struct linear_range pf9453_ldosnvs_volts[] = { 508 REGULATOR_LINEAR_RANGE(1200000, 0x00, 0x58, 25000), 509 }; 510 511 static int buck_set_dvs(const struct regulator_desc *desc, 512 struct device_node *np, struct pf9453 *pf9453, 513 char *prop, unsigned int reg, unsigned int mask) 514 { 515 int ret, i; 516 u32 uv; 517 518 ret = of_property_read_u32(np, prop, &uv); 519 if (ret == -EINVAL) 520 return 0; 521 else if (ret) 522 return ret; 523 524 for (i = 0; i < desc->n_voltages; i++) { 525 ret = regulator_desc_list_voltage_linear_range(desc, i); 526 if (ret < 0) 527 continue; 528 if (ret == uv) { 529 i <<= ffs(desc->vsel_mask) - 1; 530 ret = pf9453_pmic_write(pf9453, reg, mask, i); 531 break; 532 } 533 } 534 535 return ret; 536 } 537 538 static int pf9453_set_dvs_levels(struct device_node *np, const struct regulator_desc *desc, 539 struct regulator_config *cfg) 540 { 541 const struct pf9453_regulator_desc *data = container_of_const(desc, 542 struct pf9453_regulator_desc, 543 desc); 544 struct pf9453 *pf9453 = dev_get_drvdata(cfg->dev); 545 const struct pf9453_dvs_config *dvs = &data->dvs; 546 unsigned int reg, mask; 547 int i, ret = 0; 548 char *prop; 549 550 for (i = 0; i < PF9453_DVS_LEVEL_MAX; i++) { 551 switch (i) { 552 case PF9453_DVS_LEVEL_RUN: 553 prop = "nxp,dvs-run-voltage"; 554 reg = dvs->run_reg; 555 mask = dvs->run_mask; 556 break; 557 case PF9453_DVS_LEVEL_DPSTANDBY: 558 case PF9453_DVS_LEVEL_STANDBY: 559 prop = "nxp,dvs-standby-voltage"; 560 reg = dvs->standby_reg; 561 mask = dvs->standby_mask; 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 ret = buck_set_dvs(desc, np, pf9453, prop, reg, mask); 568 if (ret) 569 break; 570 } 571 572 return ret; 573 } 574 575 static const struct pf9453_regulator_desc pf9453_regulators[] = { 576 { 577 .desc = { 578 .name = "buck1", 579 .of_match = of_match_ptr("BUCK1"), 580 .regulators_node = of_match_ptr("regulators"), 581 .id = PF9453_BUCK1, 582 .ops = &pf9453_buck_regulator_ops, 583 .type = REGULATOR_VOLTAGE, 584 .n_voltages = PF9453_BUCK1_VOLTAGE_NUM, 585 .linear_ranges = pf9453_buck134_volts, 586 .n_linear_ranges = ARRAY_SIZE(pf9453_buck134_volts), 587 .vsel_reg = PF9453_REG_BUCK1OUT, 588 .vsel_mask = BUCK1OUT_MASK, 589 .enable_reg = PF9453_REG_BUCK1CTRL, 590 .enable_mask = BUCK1_ENMODE_MASK, 591 .enable_val = BUCK_ENMODE_ONREQ, 592 .owner = THIS_MODULE, 593 }, 594 }, 595 { 596 .desc = { 597 .name = "buck2", 598 .of_match = of_match_ptr("BUCK2"), 599 .regulators_node = of_match_ptr("regulators"), 600 .id = PF9453_BUCK2, 601 .ops = &pf9453_dvs_buck_regulator_ops, 602 .type = REGULATOR_VOLTAGE, 603 .n_voltages = PF9453_BUCK2_VOLTAGE_NUM, 604 .linear_ranges = pf9453_buck2_volts, 605 .n_linear_ranges = ARRAY_SIZE(pf9453_buck2_volts), 606 .vsel_reg = PF9453_REG_BUCK2OUT, 607 .vsel_mask = BUCK2OUT_MASK, 608 .enable_reg = PF9453_REG_BUCK2CTRL, 609 .enable_mask = BUCK2_ENMODE_MASK, 610 .enable_val = BUCK_ENMODE_ONREQ, 611 .ramp_reg = PF9453_REG_BUCK2CTRL, 612 .ramp_mask = BUCK2_RAMP_MASK, 613 .ramp_delay_table = pf9453_dvs_buck_ramp_table, 614 .n_ramp_values = ARRAY_SIZE(pf9453_dvs_buck_ramp_table), 615 .owner = THIS_MODULE, 616 .of_parse_cb = pf9453_set_dvs_levels, 617 }, 618 .dvs = { 619 .run_reg = PF9453_REG_BUCK2OUT, 620 .run_mask = BUCK2OUT_MASK, 621 .standby_reg = PF9453_REG_BUCK2OUT_STBY, 622 .standby_mask = BUCK2OUT_STBY_MASK, 623 }, 624 }, 625 { 626 .desc = { 627 .name = "buck3", 628 .of_match = of_match_ptr("BUCK3"), 629 .regulators_node = of_match_ptr("regulators"), 630 .id = PF9453_BUCK3, 631 .ops = &pf9453_buck_regulator_ops, 632 .type = REGULATOR_VOLTAGE, 633 .n_voltages = PF9453_BUCK3_VOLTAGE_NUM, 634 .linear_ranges = pf9453_buck134_volts, 635 .n_linear_ranges = ARRAY_SIZE(pf9453_buck134_volts), 636 .vsel_reg = PF9453_REG_BUCK3OUT, 637 .vsel_mask = BUCK3OUT_MASK, 638 .enable_reg = PF9453_REG_BUCK3CTRL, 639 .enable_mask = BUCK3_ENMODE_MASK, 640 .enable_val = BUCK_ENMODE_ONREQ, 641 .owner = THIS_MODULE, 642 }, 643 }, 644 { 645 .desc = { 646 .name = "buck4", 647 .of_match = of_match_ptr("BUCK4"), 648 .regulators_node = of_match_ptr("regulators"), 649 .id = PF9453_BUCK4, 650 .ops = &pf9453_buck_regulator_ops, 651 .type = REGULATOR_VOLTAGE, 652 .n_voltages = PF9453_BUCK4_VOLTAGE_NUM, 653 .linear_ranges = pf9453_buck134_volts, 654 .n_linear_ranges = ARRAY_SIZE(pf9453_buck134_volts), 655 .vsel_reg = PF9453_REG_BUCK4OUT, 656 .vsel_mask = BUCK4OUT_MASK, 657 .enable_reg = PF9453_REG_BUCK4CTRL, 658 .enable_mask = BUCK4_ENMODE_MASK, 659 .enable_val = BUCK_ENMODE_ONREQ, 660 .owner = THIS_MODULE, 661 }, 662 }, 663 { 664 .desc = { 665 .name = "ldo1", 666 .of_match = of_match_ptr("LDO1"), 667 .regulators_node = of_match_ptr("regulators"), 668 .id = PF9453_LDO1, 669 .ops = &pf9453_ldo_regulator_ops, 670 .type = REGULATOR_VOLTAGE, 671 .n_voltages = PF9453_LDO1_VOLTAGE_NUM, 672 .linear_ranges = pf9453_ldo1_volts, 673 .n_linear_ranges = ARRAY_SIZE(pf9453_ldo1_volts), 674 .vsel_reg = PF9453_REG_LDO1OUT_H, 675 .vsel_mask = LDO1OUT_MASK, 676 .enable_reg = PF9453_REG_LDO1CFG, 677 .enable_mask = LDO1_EN_MASK, 678 .enable_val = LDO_ENMODE_ONREQ, 679 .owner = THIS_MODULE, 680 }, 681 }, 682 { 683 .desc = { 684 .name = "ldo2", 685 .of_match = of_match_ptr("LDO2"), 686 .regulators_node = of_match_ptr("regulators"), 687 .id = PF9453_LDO2, 688 .ops = &pf9453_ldo_regulator_ops, 689 .type = REGULATOR_VOLTAGE, 690 .n_voltages = PF9453_LDO2_VOLTAGE_NUM, 691 .linear_ranges = pf9453_ldo2_volts, 692 .n_linear_ranges = ARRAY_SIZE(pf9453_ldo2_volts), 693 .vsel_reg = PF9453_REG_LDO2OUT, 694 .vsel_mask = LDO2OUT_MASK, 695 .enable_reg = PF9453_REG_LDO2CFG, 696 .enable_mask = LDO2_EN_MASK, 697 .enable_val = LDO_ENMODE_ONREQ, 698 .owner = THIS_MODULE, 699 }, 700 }, 701 { 702 .desc = { 703 .name = "ldosnvs", 704 .of_match = of_match_ptr("LDO-SNVS"), 705 .regulators_node = of_match_ptr("regulators"), 706 .id = PF9453_LDOSNVS, 707 .ops = &pf9453_ldo_regulator_ops, 708 .type = REGULATOR_VOLTAGE, 709 .n_voltages = PF9453_LDOSNVS_VOLTAGE_NUM, 710 .linear_ranges = pf9453_ldosnvs_volts, 711 .n_linear_ranges = ARRAY_SIZE(pf9453_ldosnvs_volts), 712 .vsel_reg = PF9453_REG_LDOSNVS_CFG1, 713 .vsel_mask = LDOSNVSCFG1_MASK, 714 .enable_reg = PF9453_REG_LDOSNVS_CFG2, 715 .enable_mask = LDOSNVS_EN_MASK, 716 .owner = THIS_MODULE, 717 }, 718 }, 719 { } 720 }; 721 722 static irqreturn_t pf9453_irq_handler(int irq, void *data) 723 { 724 struct pf9453 *pf9453 = data; 725 struct regmap *regmap = pf9453->regmap; 726 unsigned int status; 727 int ret; 728 729 ret = regmap_read(regmap, PF9453_REG_INT1, &status); 730 if (ret < 0) { 731 dev_err(pf9453->dev, "Failed to read INT1(%d)\n", ret); 732 return IRQ_NONE; 733 } 734 735 if (status & IRQ_RSTB) 736 dev_warn(pf9453->dev, "IRQ_RSTB interrupt.\n"); 737 738 if (status & IRQ_ONKEY) 739 dev_warn(pf9453->dev, "IRQ_ONKEY interrupt.\n"); 740 741 if (status & IRQ_VR_FLT1) 742 dev_warn(pf9453->dev, "VRFLT1 interrupt.\n"); 743 744 if (status & IRQ_RESETKEY) 745 dev_warn(pf9453->dev, "IRQ_RESETKEY interrupt.\n"); 746 747 if (status & IRQ_LOWVSYS) 748 dev_warn(pf9453->dev, "LOWVSYS interrupt.\n"); 749 750 if (status & IRQ_THERM_100) 751 dev_warn(pf9453->dev, "IRQ_THERM_100 interrupt.\n"); 752 753 if (status & IRQ_THERM_80) 754 dev_warn(pf9453->dev, "IRQ_THERM_80 interrupt.\n"); 755 756 return IRQ_HANDLED; 757 } 758 759 static int pf9453_i2c_probe(struct i2c_client *i2c) 760 { 761 const struct pf9453_regulator_desc *regulator_desc = of_device_get_match_data(&i2c->dev); 762 struct regulator_config config = { }; 763 unsigned int reset_ctrl; 764 unsigned int device_id; 765 struct pf9453 *pf9453; 766 int ret; 767 768 if (!i2c->irq) 769 return dev_err_probe(&i2c->dev, -EINVAL, "No IRQ configured?\n"); 770 771 pf9453 = devm_kzalloc(&i2c->dev, sizeof(struct pf9453), GFP_KERNEL); 772 if (!pf9453) 773 return -ENOMEM; 774 775 pf9453->regmap = devm_regmap_init_i2c(i2c, &pf9453_regmap_config); 776 if (IS_ERR(pf9453->regmap)) 777 return dev_err_probe(&i2c->dev, PTR_ERR(pf9453->regmap), 778 "regmap initialization failed\n"); 779 780 pf9453->irq = i2c->irq; 781 pf9453->dev = &i2c->dev; 782 783 dev_set_drvdata(&i2c->dev, pf9453); 784 785 ret = regmap_read(pf9453->regmap, PF9453_REG_DEV_ID, &device_id); 786 if (ret) 787 return dev_err_probe(&i2c->dev, ret, "Read device id error\n"); 788 789 /* Check your board and dts for match the right pmic */ 790 if ((device_id >> 4) != 0xb) 791 return dev_err_probe(&i2c->dev, -EINVAL, "Device id(%x) mismatched\n", 792 device_id >> 4); 793 794 while (regulator_desc->desc.name) { 795 const struct regulator_desc *desc; 796 struct regulator_dev *rdev; 797 798 desc = ®ulator_desc->desc; 799 800 config.regmap = pf9453->regmap; 801 config.dev = pf9453->dev; 802 803 rdev = devm_regulator_register(pf9453->dev, desc, &config); 804 if (IS_ERR(rdev)) 805 return dev_err_probe(pf9453->dev, PTR_ERR(rdev), 806 "Failed to register regulator(%s)\n", desc->name); 807 808 regulator_desc++; 809 } 810 811 ret = devm_request_threaded_irq(pf9453->dev, pf9453->irq, NULL, pf9453_irq_handler, 812 (IRQF_TRIGGER_FALLING | IRQF_ONESHOT), 813 "pf9453-irq", pf9453); 814 if (ret) 815 return dev_err_probe(pf9453->dev, ret, "Failed to request IRQ: %d\n", pf9453->irq); 816 817 /* Unmask all interrupt except PWRON/WDOG/RSVD */ 818 ret = pf9453_pmic_write(pf9453, PF9453_REG_INT1_MASK, 819 IRQ_ONKEY | IRQ_RESETKEY | IRQ_RSTB | IRQ_VR_FLT1 820 | IRQ_LOWVSYS | IRQ_THERM_100 | IRQ_THERM_80, IRQ_RSVD); 821 if (ret) 822 return dev_err_probe(&i2c->dev, ret, "Unmask irq error\n"); 823 824 if (of_property_read_bool(i2c->dev.of_node, "nxp,wdog_b-warm-reset")) 825 reset_ctrl = WDOG_B_CFG_WARM; 826 else 827 reset_ctrl = WDOG_B_CFG_COLD; 828 829 /* Set reset behavior on assertion of WDOG_B signal */ 830 ret = pf9453_pmic_write(pf9453, PF9453_REG_RESET_CTRL, WDOG_B_CFG_MASK, reset_ctrl); 831 if (ret) 832 return dev_err_probe(&i2c->dev, ret, "Failed to set WDOG_B reset behavior\n"); 833 834 /* 835 * The driver uses the LDO1OUT_H register to control the LDO1 regulator. 836 * This is only valid if the SD_VSEL input of the PMIC is high. Let's 837 * check if the pin is available as GPIO and set it to high. 838 */ 839 pf9453->sd_vsel_gpio = gpiod_get_optional(pf9453->dev, "sd-vsel", GPIOD_OUT_HIGH); 840 841 if (IS_ERR(pf9453->sd_vsel_gpio)) 842 return dev_err_probe(&i2c->dev, PTR_ERR(pf9453->sd_vsel_gpio), 843 "Failed to get SD_VSEL GPIO\n"); 844 845 return 0; 846 } 847 848 static const struct of_device_id pf9453_of_match[] = { 849 { 850 .compatible = "nxp,pf9453", 851 .data = pf9453_regulators, 852 }, 853 { } 854 }; 855 MODULE_DEVICE_TABLE(of, pf9453_of_match); 856 857 static struct i2c_driver pf9453_i2c_driver = { 858 .driver = { 859 .name = "nxp-pf9453", 860 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 861 .of_match_table = pf9453_of_match, 862 }, 863 .probe = pf9453_i2c_probe, 864 }; 865 866 module_i2c_driver(pf9453_i2c_driver); 867 868 MODULE_AUTHOR("Joy Zou <joy.zou@nxp.com>"); 869 MODULE_DESCRIPTION("NXP PF9453 Power Management IC driver"); 870 MODULE_LICENSE("GPL"); 871