1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Invensense, Inc.
4 */
5
6 #include <linux/module.h>
7 #include <linux/slab.h>
8 #include <linux/i2c.h>
9 #include <linux/err.h>
10 #include <linux/delay.h>
11 #include <linux/sysfs.h>
12 #include <linux/jiffies.h>
13 #include <linux/irq.h>
14 #include <linux/interrupt.h>
15 #include <linux/acpi.h>
16 #include <linux/platform_device.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/math64.h>
19 #include <linux/minmax.h>
20 #include <linux/pm.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23
24 #include <linux/iio/common/inv_sensors_timestamp.h>
25 #include <linux/iio/iio.h>
26
27 #include "inv_mpu_iio.h"
28 #include "inv_mpu_magn.h"
29
30 /*
31 * this is the gyro scale translated from dynamic range plus/minus
32 * {250, 500, 1000, 2000} to rad/s
33 */
34 static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
35
36 /*
37 * this is the accel scale translated from dynamic range plus/minus
38 * {2, 4, 8, 16} to m/s^2
39 */
40 static const int accel_scale[] = {598, 1196, 2392, 4785};
41
42 static const struct inv_mpu6050_reg_map reg_set_icm20602 = {
43 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
44 .lpf = INV_MPU6050_REG_CONFIG,
45 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
46 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
47 .fifo_en = INV_MPU6050_REG_FIFO_EN,
48 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
49 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
50 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
51 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
52 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
53 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
54 .temperature = INV_MPU6050_REG_TEMPERATURE,
55 .int_enable = INV_MPU6050_REG_INT_ENABLE,
56 .int_status = INV_MPU6050_REG_INT_STATUS,
57 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
58 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
59 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
60 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
61 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
62 .i2c_if = INV_ICM20602_REG_I2C_IF,
63 };
64
65 static const struct inv_mpu6050_reg_map reg_set_6500 = {
66 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
67 .lpf = INV_MPU6050_REG_CONFIG,
68 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
69 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
70 .fifo_en = INV_MPU6050_REG_FIFO_EN,
71 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
72 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
73 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
74 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
75 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
76 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
77 .temperature = INV_MPU6050_REG_TEMPERATURE,
78 .int_enable = INV_MPU6050_REG_INT_ENABLE,
79 .int_status = INV_MPU6050_REG_INT_STATUS,
80 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
81 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
82 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
83 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
84 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
85 .i2c_if = 0,
86 };
87
88 static const struct inv_mpu6050_reg_map reg_set_6050 = {
89 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
90 .lpf = INV_MPU6050_REG_CONFIG,
91 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
92 .fifo_en = INV_MPU6050_REG_FIFO_EN,
93 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
94 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
95 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
96 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
97 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
98 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
99 .temperature = INV_MPU6050_REG_TEMPERATURE,
100 .int_enable = INV_MPU6050_REG_INT_ENABLE,
101 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
102 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
103 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
104 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
105 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
106 .i2c_if = 0,
107 };
108
109 static const struct inv_mpu6050_chip_config chip_config_6050 = {
110 .clk = INV_CLK_INTERNAL,
111 .fsr = INV_MPU6050_FSR_2000DPS,
112 .lpf = INV_MPU6050_FILTER_20HZ,
113 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
114 .gyro_en = true,
115 .accl_en = true,
116 .temp_en = true,
117 .magn_en = false,
118 .gyro_fifo_enable = false,
119 .accl_fifo_enable = false,
120 .temp_fifo_enable = false,
121 .magn_fifo_enable = false,
122 .accl_fs = INV_MPU6050_FS_02G,
123 .user_ctrl = 0,
124 };
125
126 static const struct inv_mpu6050_chip_config chip_config_6500 = {
127 .clk = INV_CLK_PLL,
128 .fsr = INV_MPU6050_FSR_2000DPS,
129 .lpf = INV_MPU6050_FILTER_20HZ,
130 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
131 .gyro_en = true,
132 .accl_en = true,
133 .temp_en = true,
134 .magn_en = false,
135 .gyro_fifo_enable = false,
136 .accl_fifo_enable = false,
137 .temp_fifo_enable = false,
138 .magn_fifo_enable = false,
139 .accl_fs = INV_MPU6050_FS_02G,
140 .user_ctrl = 0,
141 };
142
143 /* Indexed by enum inv_devices */
144 static const struct inv_mpu6050_hw hw_info[] = {
145 {
146 .whoami = INV_MPU6050_WHOAMI_VALUE,
147 .name = "MPU6050",
148 .reg = ®_set_6050,
149 .config = &chip_config_6050,
150 .fifo_size = 1024,
151 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
152 .startup_time = {INV_MPU6050_GYRO_STARTUP_TIME, INV_MPU6050_ACCEL_STARTUP_TIME},
153 },
154 {
155 .whoami = INV_MPU6500_WHOAMI_VALUE,
156 .name = "MPU6500",
157 .reg = ®_set_6500,
158 .config = &chip_config_6500,
159 .fifo_size = 512,
160 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
161 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
162 },
163 {
164 .whoami = INV_MPU6515_WHOAMI_VALUE,
165 .name = "MPU6515",
166 .reg = ®_set_6500,
167 .config = &chip_config_6500,
168 .fifo_size = 512,
169 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
170 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
171 },
172 {
173 .whoami = INV_MPU6880_WHOAMI_VALUE,
174 .name = "MPU6880",
175 .reg = ®_set_6500,
176 .config = &chip_config_6500,
177 .fifo_size = 4096,
178 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
179 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
180 },
181 {
182 .whoami = INV_MPU6000_WHOAMI_VALUE,
183 .name = "MPU6000",
184 .reg = ®_set_6050,
185 .config = &chip_config_6050,
186 .fifo_size = 1024,
187 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
188 .startup_time = {INV_MPU6050_GYRO_STARTUP_TIME, INV_MPU6050_ACCEL_STARTUP_TIME},
189 },
190 {
191 .whoami = INV_MPU9150_WHOAMI_VALUE,
192 .name = "MPU9150",
193 .reg = ®_set_6050,
194 .config = &chip_config_6050,
195 .fifo_size = 1024,
196 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
197 .startup_time = {INV_MPU6050_GYRO_STARTUP_TIME, INV_MPU6050_ACCEL_STARTUP_TIME},
198 },
199 {
200 .whoami = INV_MPU9250_WHOAMI_VALUE,
201 .name = "MPU9250",
202 .reg = ®_set_6500,
203 .config = &chip_config_6500,
204 .fifo_size = 512,
205 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
206 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
207 },
208 {
209 .whoami = INV_MPU9255_WHOAMI_VALUE,
210 .name = "MPU9255",
211 .reg = ®_set_6500,
212 .config = &chip_config_6500,
213 .fifo_size = 512,
214 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
215 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
216 },
217 {
218 .whoami = INV_ICM20608_WHOAMI_VALUE,
219 .name = "ICM20608",
220 .reg = ®_set_6500,
221 .config = &chip_config_6500,
222 .fifo_size = 512,
223 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
224 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
225 },
226 {
227 .whoami = INV_ICM20608D_WHOAMI_VALUE,
228 .name = "ICM20608D",
229 .reg = ®_set_6500,
230 .config = &chip_config_6500,
231 .fifo_size = 512,
232 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
233 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
234 },
235 {
236 .whoami = INV_ICM20609_WHOAMI_VALUE,
237 .name = "ICM20609",
238 .reg = ®_set_6500,
239 .config = &chip_config_6500,
240 .fifo_size = 4 * 1024,
241 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
242 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
243 },
244 {
245 .whoami = INV_ICM20689_WHOAMI_VALUE,
246 .name = "ICM20689",
247 .reg = ®_set_6500,
248 .config = &chip_config_6500,
249 .fifo_size = 4 * 1024,
250 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
251 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
252 },
253 {
254 .whoami = INV_ICM20600_WHOAMI_VALUE,
255 .name = "ICM20600",
256 .reg = ®_set_icm20602,
257 .config = &chip_config_6500,
258 .fifo_size = 1008,
259 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
260 .startup_time = {INV_ICM20602_GYRO_STARTUP_TIME, INV_ICM20602_ACCEL_STARTUP_TIME},
261 },
262 {
263 .whoami = INV_ICM20602_WHOAMI_VALUE,
264 .name = "ICM20602",
265 .reg = ®_set_icm20602,
266 .config = &chip_config_6500,
267 .fifo_size = 1008,
268 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
269 .startup_time = {INV_ICM20602_GYRO_STARTUP_TIME, INV_ICM20602_ACCEL_STARTUP_TIME},
270 },
271 {
272 .whoami = INV_ICM20690_WHOAMI_VALUE,
273 .name = "ICM20690",
274 .reg = ®_set_6500,
275 .config = &chip_config_6500,
276 .fifo_size = 1024,
277 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
278 .startup_time = {INV_ICM20690_GYRO_STARTUP_TIME, INV_ICM20690_ACCEL_STARTUP_TIME},
279 },
280 { .whoami = INV_IAM20380_WHOAMI_VALUE,
281 .name = "IAM20380",
282 .reg = ®_set_6500,
283 .config = &chip_config_6500,
284 .fifo_size = 512,
285 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
286 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
287 },
288 {
289 .whoami = INV_IAM20680_WHOAMI_VALUE,
290 .name = "IAM20680",
291 .reg = ®_set_6500,
292 .config = &chip_config_6500,
293 .fifo_size = 512,
294 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
295 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
296 },
297 {
298 .whoami = INV_IAM20680HP_WHOAMI_VALUE,
299 .name = "IAM20680HP",
300 .reg = ®_set_6500,
301 .config = &chip_config_6500,
302 .fifo_size = 4 * 1024,
303 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
304 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
305 },
306 {
307 .whoami = INV_IAM20680HT_WHOAMI_VALUE,
308 .name = "IAM20680HT",
309 .reg = ®_set_6500,
310 .config = &chip_config_6500,
311 .fifo_size = 4 * 1024,
312 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
313 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
314 },
315 };
316
inv_mpu6050_pwr_mgmt_1_write(struct inv_mpu6050_state * st,bool sleep,bool cycle,int clock,int temp_dis)317 static int inv_mpu6050_pwr_mgmt_1_write(struct inv_mpu6050_state *st, bool sleep,
318 bool cycle, int clock, int temp_dis)
319 {
320 u8 val;
321
322 if (clock < 0)
323 clock = st->chip_config.clk;
324 if (temp_dis < 0)
325 temp_dis = !st->chip_config.temp_en;
326
327 val = clock & INV_MPU6050_BIT_CLK_MASK;
328 if (temp_dis)
329 val |= INV_MPU6050_BIT_TEMP_DIS;
330 if (sleep)
331 val |= INV_MPU6050_BIT_SLEEP;
332 if (cycle)
333 val |= INV_MPU6050_BIT_CYCLE;
334
335 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_1: 0x%x\n", val);
336 return regmap_write(st->map, st->reg->pwr_mgmt_1, val);
337 }
338
inv_mpu6050_clock_switch(struct inv_mpu6050_state * st,unsigned int clock)339 static int inv_mpu6050_clock_switch(struct inv_mpu6050_state *st,
340 unsigned int clock)
341 {
342 int ret;
343
344 switch (st->chip_type) {
345 case INV_MPU6050:
346 case INV_MPU6000:
347 case INV_MPU9150:
348 /* old chips: switch clock manually */
349 ret = inv_mpu6050_pwr_mgmt_1_write(st, false, false, clock, -1);
350 if (ret)
351 return ret;
352 st->chip_config.clk = clock;
353 break;
354 default:
355 /* automatic clock switching, nothing to do */
356 break;
357 }
358
359 return 0;
360 }
361
inv_mpu6050_switch_engine(struct inv_mpu6050_state * st,bool en,unsigned int mask)362 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
363 unsigned int mask)
364 {
365 unsigned int sleep, val;
366 u8 pwr_mgmt2, user_ctrl;
367 int ret;
368
369 /* delete useless requests */
370 if (mask & INV_MPU6050_SENSOR_ACCL && en == st->chip_config.accl_en)
371 mask &= ~INV_MPU6050_SENSOR_ACCL;
372 if (mask & INV_MPU6050_SENSOR_GYRO && en == st->chip_config.gyro_en)
373 mask &= ~INV_MPU6050_SENSOR_GYRO;
374 if (mask & INV_MPU6050_SENSOR_TEMP && en == st->chip_config.temp_en)
375 mask &= ~INV_MPU6050_SENSOR_TEMP;
376 if (mask & INV_MPU6050_SENSOR_MAGN && en == st->chip_config.magn_en)
377 mask &= ~INV_MPU6050_SENSOR_MAGN;
378 if (mask & INV_MPU6050_SENSOR_WOM && en == st->chip_config.wom_en)
379 mask &= ~INV_MPU6050_SENSOR_WOM;
380
381 /* force accel on if WoM is on and not going off */
382 if (!en && (mask & INV_MPU6050_SENSOR_ACCL) && st->chip_config.wom_en &&
383 !(mask & INV_MPU6050_SENSOR_WOM))
384 mask &= ~INV_MPU6050_SENSOR_ACCL;
385
386 if (mask == 0)
387 return 0;
388
389 /* turn on/off temperature sensor */
390 if (mask & INV_MPU6050_SENSOR_TEMP) {
391 ret = inv_mpu6050_pwr_mgmt_1_write(st, false, false, -1, !en);
392 if (ret)
393 return ret;
394 st->chip_config.temp_en = en;
395 }
396
397 /* update user_crtl for driving magnetometer */
398 if (mask & INV_MPU6050_SENSOR_MAGN) {
399 user_ctrl = st->chip_config.user_ctrl;
400 if (en)
401 user_ctrl |= INV_MPU6050_BIT_I2C_MST_EN;
402 else
403 user_ctrl &= ~INV_MPU6050_BIT_I2C_MST_EN;
404 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl);
405 if (ret)
406 return ret;
407 st->chip_config.user_ctrl = user_ctrl;
408 st->chip_config.magn_en = en;
409 }
410
411 /* manage accel & gyro engines */
412 if (mask & (INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO)) {
413 /* compute power management 2 current value */
414 pwr_mgmt2 = 0;
415 if (!st->chip_config.accl_en)
416 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
417 if (!st->chip_config.gyro_en)
418 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
419
420 /* update to new requested value */
421 if (mask & INV_MPU6050_SENSOR_ACCL) {
422 if (en)
423 pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_ACCL_STBY;
424 else
425 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
426 }
427 if (mask & INV_MPU6050_SENSOR_GYRO) {
428 if (en)
429 pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_GYRO_STBY;
430 else
431 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
432 }
433
434 /* switch clock to internal when turning gyro off */
435 if (mask & INV_MPU6050_SENSOR_GYRO && !en) {
436 ret = inv_mpu6050_clock_switch(st, INV_CLK_INTERNAL);
437 if (ret)
438 return ret;
439 }
440
441 /* update sensors engine */
442 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_2: 0x%x\n",
443 pwr_mgmt2);
444 ret = regmap_write(st->map, st->reg->pwr_mgmt_2, pwr_mgmt2);
445 if (ret)
446 return ret;
447 if (mask & INV_MPU6050_SENSOR_ACCL)
448 st->chip_config.accl_en = en;
449 if (mask & INV_MPU6050_SENSOR_GYRO)
450 st->chip_config.gyro_en = en;
451
452 /* compute required time to have sensors stabilized */
453 sleep = 0;
454 if (en) {
455 if (mask & INV_MPU6050_SENSOR_ACCL) {
456 if (sleep < st->hw->startup_time.accel)
457 sleep = st->hw->startup_time.accel;
458 }
459 if (mask & INV_MPU6050_SENSOR_GYRO) {
460 if (sleep < st->hw->startup_time.gyro)
461 sleep = st->hw->startup_time.gyro;
462 }
463 } else {
464 if (mask & INV_MPU6050_SENSOR_GYRO) {
465 if (sleep < INV_MPU6050_GYRO_DOWN_TIME)
466 sleep = INV_MPU6050_GYRO_DOWN_TIME;
467 }
468 }
469 if (sleep)
470 msleep(sleep);
471
472 /* switch clock to PLL when turning gyro on */
473 if (mask & INV_MPU6050_SENSOR_GYRO && en) {
474 ret = inv_mpu6050_clock_switch(st, INV_CLK_PLL);
475 if (ret)
476 return ret;
477 }
478 }
479
480 /* enable/disable accel intelligence control */
481 if (mask & INV_MPU6050_SENSOR_WOM) {
482 val = en ? INV_MPU6500_BIT_ACCEL_INTEL_EN |
483 INV_MPU6500_BIT_ACCEL_INTEL_MODE : 0;
484 ret = regmap_write(st->map, INV_MPU6500_REG_ACCEL_INTEL_CTRL, val);
485 if (ret)
486 return ret;
487 st->chip_config.wom_en = en;
488 }
489
490 return 0;
491 }
492
inv_mpu6050_set_power_itg(struct inv_mpu6050_state * st,bool power_on)493 static int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st,
494 bool power_on)
495 {
496 int result;
497
498 result = inv_mpu6050_pwr_mgmt_1_write(st, !power_on, false, -1, -1);
499 if (result)
500 return result;
501
502 if (power_on)
503 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
504 INV_MPU6050_REG_UP_TIME_MAX);
505
506 return 0;
507 }
508
inv_mpu6050_set_gyro_fsr(struct inv_mpu6050_state * st,enum inv_mpu6050_fsr_e val)509 static int inv_mpu6050_set_gyro_fsr(struct inv_mpu6050_state *st,
510 enum inv_mpu6050_fsr_e val)
511 {
512 unsigned int gyro_shift;
513 u8 data;
514
515 switch (st->chip_type) {
516 case INV_ICM20690:
517 gyro_shift = INV_ICM20690_GYRO_CONFIG_FSR_SHIFT;
518 break;
519 default:
520 gyro_shift = INV_MPU6050_GYRO_CONFIG_FSR_SHIFT;
521 break;
522 }
523
524 data = val << gyro_shift;
525 return regmap_write(st->map, st->reg->gyro_config, data);
526 }
527
inv_mpu6050_set_accel_lpf_regs(struct inv_mpu6050_state * st,enum inv_mpu6050_filter_e val)528 static int inv_mpu6050_set_accel_lpf_regs(struct inv_mpu6050_state *st,
529 enum inv_mpu6050_filter_e val)
530 {
531 switch (st->chip_type) {
532 case INV_MPU6050:
533 case INV_MPU6000:
534 case INV_MPU9150:
535 /* old chips, nothing to do */
536 return 0;
537 case INV_ICM20689:
538 case INV_ICM20690:
539 case INV_IAM20680HT:
540 case INV_IAM20680HP:
541 /* set FIFO size to maximum value */
542 val |= INV_ICM20689_BITS_FIFO_SIZE_MAX;
543 break;
544 default:
545 break;
546 }
547
548 return regmap_write(st->map, st->reg->accel_lpf, val);
549 }
550
551 /*
552 * inv_mpu6050_set_lpf_regs() - set low pass filter registers, chip dependent
553 *
554 * MPU60xx/MPU9150 use only 1 register for accelerometer + gyroscope
555 * MPU6500 and above have a dedicated register for accelerometer
556 */
inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state * st,enum inv_mpu6050_filter_e val)557 static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
558 enum inv_mpu6050_filter_e val)
559 {
560 int result;
561
562 result = regmap_write(st->map, st->reg->lpf, val);
563 if (result)
564 return result;
565
566 /* set accel lpf */
567 return inv_mpu6050_set_accel_lpf_regs(st, val);
568 }
569
570 /*
571 * inv_mpu6050_init_config() - Initialize hardware, disable FIFO.
572 *
573 * Initial configuration:
574 * FSR: ± 2000DPS
575 * DLPF: 20Hz
576 * FIFO rate: 50Hz
577 * Clock source: Gyro PLL
578 */
inv_mpu6050_init_config(struct iio_dev * indio_dev)579 static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
580 {
581 int result;
582 u8 d;
583 struct inv_mpu6050_state *st = iio_priv(indio_dev);
584 struct inv_sensors_timestamp_chip timestamp;
585
586 result = inv_mpu6050_set_gyro_fsr(st, st->chip_config.fsr);
587 if (result)
588 return result;
589
590 result = inv_mpu6050_set_lpf_regs(st, st->chip_config.lpf);
591 if (result)
592 return result;
593
594 d = st->chip_config.divider;
595 result = regmap_write(st->map, st->reg->sample_rate_div, d);
596 if (result)
597 return result;
598
599 d = (st->chip_config.accl_fs << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
600 result = regmap_write(st->map, st->reg->accl_config, d);
601 if (result)
602 return result;
603
604 result = regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask);
605 if (result)
606 return result;
607
608 /* clock jitter is +/- 2% */
609 timestamp.clock_period = NSEC_PER_SEC / INV_MPU6050_INTERNAL_FREQ_HZ;
610 timestamp.jitter = 20;
611 timestamp.init_period =
612 NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
613 inv_sensors_timestamp_init(&st->timestamp, ×tamp);
614
615 /* magn chip init, noop if not present in the chip */
616 result = inv_mpu_magn_probe(st);
617 if (result)
618 return result;
619
620 return 0;
621 }
622
inv_mpu6050_sensor_set(struct inv_mpu6050_state * st,int reg,int axis,int val)623 static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
624 int axis, int val)
625 {
626 int ind;
627 __be16 d = cpu_to_be16(val);
628
629 ind = (axis - IIO_MOD_X) * 2;
630
631 return regmap_bulk_write(st->map, reg + ind, &d, sizeof(d));
632 }
633
inv_mpu6050_sensor_show(struct inv_mpu6050_state * st,int reg,int axis,int * val)634 static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
635 int axis, int *val)
636 {
637 int ind, result;
638 __be16 d;
639
640 ind = (axis - IIO_MOD_X) * 2;
641 result = regmap_bulk_read(st->map, reg + ind, &d, sizeof(d));
642 if (result)
643 return result;
644 *val = (short)be16_to_cpup(&d);
645
646 return IIO_VAL_INT;
647 }
648
inv_mpu6050_read_channel_data(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)649 static int inv_mpu6050_read_channel_data(struct iio_dev *indio_dev,
650 struct iio_chan_spec const *chan,
651 int *val)
652 {
653 struct inv_mpu6050_state *st = iio_priv(indio_dev);
654 struct device *pdev = regmap_get_device(st->map);
655 unsigned int freq_hz, period_us, min_sleep_us, max_sleep_us;
656 int result;
657 int ret;
658
659 /* compute sample period */
660 freq_hz = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
661 period_us = 1000000 / freq_hz;
662
663 result = pm_runtime_resume_and_get(pdev);
664 if (result)
665 return result;
666
667 switch (chan->type) {
668 case IIO_ANGL_VEL:
669 if (!st->chip_config.gyro_en) {
670 result = inv_mpu6050_switch_engine(st, true,
671 INV_MPU6050_SENSOR_GYRO);
672 if (result)
673 goto error_power_off;
674 /* need to wait 2 periods to have first valid sample */
675 min_sleep_us = 2 * period_us;
676 max_sleep_us = 2 * (period_us + period_us / 2);
677 usleep_range(min_sleep_us, max_sleep_us);
678 }
679 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
680 chan->channel2, val);
681 break;
682 case IIO_ACCEL:
683 if (!st->chip_config.accl_en) {
684 result = inv_mpu6050_switch_engine(st, true,
685 INV_MPU6050_SENSOR_ACCL);
686 if (result)
687 goto error_power_off;
688 /* wait 1 period for first sample availability */
689 min_sleep_us = period_us;
690 max_sleep_us = period_us + period_us / 2;
691 usleep_range(min_sleep_us, max_sleep_us);
692 }
693 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
694 chan->channel2, val);
695 break;
696 case IIO_TEMP:
697 /* temperature sensor work only with accel and/or gyro */
698 if (!st->chip_config.accl_en && !st->chip_config.gyro_en) {
699 result = -EBUSY;
700 goto error_power_off;
701 }
702 if (!st->chip_config.temp_en) {
703 result = inv_mpu6050_switch_engine(st, true,
704 INV_MPU6050_SENSOR_TEMP);
705 if (result)
706 goto error_power_off;
707 /* wait 1 period for first sample availability */
708 min_sleep_us = period_us;
709 max_sleep_us = period_us + period_us / 2;
710 usleep_range(min_sleep_us, max_sleep_us);
711 }
712 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
713 IIO_MOD_X, val);
714 break;
715 case IIO_MAGN:
716 if (!st->chip_config.magn_en) {
717 result = inv_mpu6050_switch_engine(st, true,
718 INV_MPU6050_SENSOR_MAGN);
719 if (result)
720 goto error_power_off;
721 /* frequency is limited for magnetometer */
722 if (freq_hz > INV_MPU_MAGN_FREQ_HZ_MAX) {
723 freq_hz = INV_MPU_MAGN_FREQ_HZ_MAX;
724 period_us = 1000000 / freq_hz;
725 }
726 /* need to wait 2 periods to have first valid sample */
727 min_sleep_us = 2 * period_us;
728 max_sleep_us = 2 * (period_us + period_us / 2);
729 usleep_range(min_sleep_us, max_sleep_us);
730 }
731 ret = inv_mpu_magn_read(st, chan->channel2, val);
732 break;
733 default:
734 ret = -EINVAL;
735 break;
736 }
737
738 pm_runtime_mark_last_busy(pdev);
739 pm_runtime_put_autosuspend(pdev);
740
741 return ret;
742
743 error_power_off:
744 pm_runtime_put_autosuspend(pdev);
745 return result;
746 }
747
748 static int
inv_mpu6050_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)749 inv_mpu6050_read_raw(struct iio_dev *indio_dev,
750 struct iio_chan_spec const *chan,
751 int *val, int *val2, long mask)
752 {
753 struct inv_mpu6050_state *st = iio_priv(indio_dev);
754 int ret = 0;
755
756 switch (mask) {
757 case IIO_CHAN_INFO_RAW:
758 ret = iio_device_claim_direct_mode(indio_dev);
759 if (ret)
760 return ret;
761 mutex_lock(&st->lock);
762 ret = inv_mpu6050_read_channel_data(indio_dev, chan, val);
763 mutex_unlock(&st->lock);
764 iio_device_release_direct_mode(indio_dev);
765 return ret;
766 case IIO_CHAN_INFO_SCALE:
767 switch (chan->type) {
768 case IIO_ANGL_VEL:
769 mutex_lock(&st->lock);
770 *val = 0;
771 *val2 = gyro_scale_6050[st->chip_config.fsr];
772 mutex_unlock(&st->lock);
773
774 return IIO_VAL_INT_PLUS_NANO;
775 case IIO_ACCEL:
776 mutex_lock(&st->lock);
777 *val = 0;
778 *val2 = accel_scale[st->chip_config.accl_fs];
779 mutex_unlock(&st->lock);
780
781 return IIO_VAL_INT_PLUS_MICRO;
782 case IIO_TEMP:
783 *val = st->hw->temp.scale / 1000000;
784 *val2 = st->hw->temp.scale % 1000000;
785 return IIO_VAL_INT_PLUS_MICRO;
786 case IIO_MAGN:
787 return inv_mpu_magn_get_scale(st, chan, val, val2);
788 default:
789 return -EINVAL;
790 }
791 case IIO_CHAN_INFO_OFFSET:
792 switch (chan->type) {
793 case IIO_TEMP:
794 *val = st->hw->temp.offset;
795 return IIO_VAL_INT;
796 default:
797 return -EINVAL;
798 }
799 case IIO_CHAN_INFO_CALIBBIAS:
800 switch (chan->type) {
801 case IIO_ANGL_VEL:
802 mutex_lock(&st->lock);
803 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
804 chan->channel2, val);
805 mutex_unlock(&st->lock);
806 return ret;
807 case IIO_ACCEL:
808 mutex_lock(&st->lock);
809 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
810 chan->channel2, val);
811 mutex_unlock(&st->lock);
812 return ret;
813
814 default:
815 return -EINVAL;
816 }
817 default:
818 return -EINVAL;
819 }
820 }
821
inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state * st,int val,int val2)822 static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val,
823 int val2)
824 {
825 int result, i;
826
827 if (val != 0)
828 return -EINVAL;
829
830 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
831 if (gyro_scale_6050[i] == val2) {
832 result = inv_mpu6050_set_gyro_fsr(st, i);
833 if (result)
834 return result;
835
836 st->chip_config.fsr = i;
837 return 0;
838 }
839 }
840
841 return -EINVAL;
842 }
843
inv_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)844 static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
845 struct iio_chan_spec const *chan, long mask)
846 {
847 switch (mask) {
848 case IIO_CHAN_INFO_SCALE:
849 switch (chan->type) {
850 case IIO_ANGL_VEL:
851 return IIO_VAL_INT_PLUS_NANO;
852 default:
853 return IIO_VAL_INT_PLUS_MICRO;
854 }
855 default:
856 return IIO_VAL_INT_PLUS_MICRO;
857 }
858
859 return -EINVAL;
860 }
861
inv_mpu6050_write_accel_scale(struct inv_mpu6050_state * st,int val,int val2)862 static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val,
863 int val2)
864 {
865 int result, i;
866 u8 d;
867
868 if (val != 0)
869 return -EINVAL;
870
871 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
872 if (accel_scale[i] == val2) {
873 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
874 result = regmap_write(st->map, st->reg->accl_config, d);
875 if (result)
876 return result;
877
878 st->chip_config.accl_fs = i;
879 return 0;
880 }
881 }
882
883 return -EINVAL;
884 }
885
inv_mpu6050_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)886 static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
887 struct iio_chan_spec const *chan,
888 int val, int val2, long mask)
889 {
890 struct inv_mpu6050_state *st = iio_priv(indio_dev);
891 struct device *pdev = regmap_get_device(st->map);
892 int result;
893
894 /*
895 * we should only update scale when the chip is disabled, i.e.
896 * not running
897 */
898 result = iio_device_claim_direct_mode(indio_dev);
899 if (result)
900 return result;
901
902 mutex_lock(&st->lock);
903 result = pm_runtime_resume_and_get(pdev);
904 if (result)
905 goto error_write_raw_unlock;
906
907 switch (mask) {
908 case IIO_CHAN_INFO_SCALE:
909 switch (chan->type) {
910 case IIO_ANGL_VEL:
911 result = inv_mpu6050_write_gyro_scale(st, val, val2);
912 break;
913 case IIO_ACCEL:
914 result = inv_mpu6050_write_accel_scale(st, val, val2);
915 break;
916 default:
917 result = -EINVAL;
918 break;
919 }
920 break;
921 case IIO_CHAN_INFO_CALIBBIAS:
922 switch (chan->type) {
923 case IIO_ANGL_VEL:
924 result = inv_mpu6050_sensor_set(st,
925 st->reg->gyro_offset,
926 chan->channel2, val);
927 break;
928 case IIO_ACCEL:
929 result = inv_mpu6050_sensor_set(st,
930 st->reg->accl_offset,
931 chan->channel2, val);
932 break;
933 default:
934 result = -EINVAL;
935 break;
936 }
937 break;
938 default:
939 result = -EINVAL;
940 break;
941 }
942
943 pm_runtime_mark_last_busy(pdev);
944 pm_runtime_put_autosuspend(pdev);
945 error_write_raw_unlock:
946 mutex_unlock(&st->lock);
947 iio_device_release_direct_mode(indio_dev);
948
949 return result;
950 }
951
inv_mpu6050_convert_wom_to_roc(unsigned int threshold,unsigned int freq_div)952 static u64 inv_mpu6050_convert_wom_to_roc(unsigned int threshold, unsigned int freq_div)
953 {
954 /* 4mg per LSB converted in m/s² in micro (1000000) */
955 const unsigned int convert = 4U * 9807U;
956 u64 value;
957
958 value = threshold * convert;
959
960 /* compute the differential by multiplying by the frequency */
961 return div_u64(value * INV_MPU6050_INTERNAL_FREQ_HZ, freq_div);
962 }
963
inv_mpu6050_convert_roc_to_wom(u64 roc,unsigned int freq_div)964 static unsigned int inv_mpu6050_convert_roc_to_wom(u64 roc, unsigned int freq_div)
965 {
966 /* 4mg per LSB converted in m/s² in micro (1000000) */
967 const unsigned int convert = 4U * 9807U;
968 u64 value;
969
970 /* return 0 only if roc is 0 */
971 if (roc == 0)
972 return 0;
973
974 value = div_u64(roc * freq_div, convert * INV_MPU6050_INTERNAL_FREQ_HZ);
975
976 /* limit value to 8 bits and prevent 0 */
977 return min(255, max(1, value));
978 }
979
inv_mpu6050_set_wom_int(struct inv_mpu6050_state * st,bool on)980 static int inv_mpu6050_set_wom_int(struct inv_mpu6050_state *st, bool on)
981 {
982 unsigned int reg_val, val;
983
984 switch (st->chip_type) {
985 case INV_MPU6050:
986 case INV_MPU6500:
987 case INV_MPU6515:
988 case INV_MPU6880:
989 case INV_MPU6000:
990 case INV_MPU9150:
991 case INV_MPU9250:
992 case INV_MPU9255:
993 reg_val = INV_MPU6500_BIT_WOM_INT_EN;
994 break;
995 default:
996 reg_val = INV_ICM20608_BIT_WOM_INT_EN;
997 break;
998 }
999
1000 val = on ? reg_val : 0;
1001
1002 return regmap_update_bits(st->map, st->reg->int_enable, reg_val, val);
1003 }
1004
inv_mpu6050_set_wom_threshold(struct inv_mpu6050_state * st,u64 value,unsigned int freq_div)1005 static int inv_mpu6050_set_wom_threshold(struct inv_mpu6050_state *st, u64 value,
1006 unsigned int freq_div)
1007 {
1008 unsigned int threshold;
1009 int result;
1010
1011 /* convert roc to wom threshold and convert back to handle clipping */
1012 threshold = inv_mpu6050_convert_roc_to_wom(value, freq_div);
1013 value = inv_mpu6050_convert_wom_to_roc(threshold, freq_div);
1014
1015 dev_dbg(regmap_get_device(st->map), "wom_threshold: 0x%x\n", threshold);
1016
1017 switch (st->chip_type) {
1018 case INV_ICM20609:
1019 case INV_ICM20689:
1020 case INV_ICM20600:
1021 case INV_ICM20602:
1022 case INV_ICM20690:
1023 st->data[0] = threshold;
1024 st->data[1] = threshold;
1025 st->data[2] = threshold;
1026 result = regmap_bulk_write(st->map, INV_ICM20609_REG_ACCEL_WOM_X_THR,
1027 st->data, 3);
1028 break;
1029 default:
1030 result = regmap_write(st->map, INV_MPU6500_REG_WOM_THRESHOLD, threshold);
1031 break;
1032 }
1033 if (result)
1034 return result;
1035
1036 st->chip_config.roc_threshold = value;
1037
1038 return 0;
1039 }
1040
inv_mpu6050_set_lp_odr(struct inv_mpu6050_state * st,unsigned int freq_div,unsigned int * lp_div)1041 static int inv_mpu6050_set_lp_odr(struct inv_mpu6050_state *st, unsigned int freq_div,
1042 unsigned int *lp_div)
1043 {
1044 static const unsigned int freq_dividers[] = {2, 4, 8, 16, 32, 64, 128, 256};
1045 static const unsigned int reg_values[] = {
1046 INV_MPU6050_LPOSC_500HZ, INV_MPU6050_LPOSC_250HZ,
1047 INV_MPU6050_LPOSC_125HZ, INV_MPU6050_LPOSC_62HZ,
1048 INV_MPU6050_LPOSC_31HZ, INV_MPU6050_LPOSC_16HZ,
1049 INV_MPU6050_LPOSC_8HZ, INV_MPU6050_LPOSC_4HZ,
1050 };
1051 unsigned int val, i;
1052
1053 switch (st->chip_type) {
1054 case INV_ICM20609:
1055 case INV_ICM20689:
1056 case INV_ICM20600:
1057 case INV_ICM20602:
1058 case INV_ICM20690:
1059 /* nothing to do */
1060 *lp_div = INV_MPU6050_FREQ_DIVIDER(st);
1061 return 0;
1062 default:
1063 break;
1064 }
1065
1066 /* found the nearest superior frequency divider */
1067 i = ARRAY_SIZE(reg_values) - 1;
1068 val = reg_values[i];
1069 *lp_div = freq_dividers[i];
1070 for (i = 0; i < ARRAY_SIZE(freq_dividers); ++i) {
1071 if (freq_div <= freq_dividers[i]) {
1072 val = reg_values[i];
1073 *lp_div = freq_dividers[i];
1074 break;
1075 }
1076 }
1077
1078 dev_dbg(regmap_get_device(st->map), "lp_odr: 0x%x\n", val);
1079 return regmap_write(st->map, INV_MPU6500_REG_LP_ODR, val);
1080 }
1081
inv_mpu6050_set_wom_lp(struct inv_mpu6050_state * st,bool on)1082 static int inv_mpu6050_set_wom_lp(struct inv_mpu6050_state *st, bool on)
1083 {
1084 unsigned int lp_div;
1085 int result;
1086
1087 if (on) {
1088 /* set low power ODR */
1089 result = inv_mpu6050_set_lp_odr(st, INV_MPU6050_FREQ_DIVIDER(st), &lp_div);
1090 if (result)
1091 return result;
1092 /* disable accel low pass filter */
1093 result = inv_mpu6050_set_accel_lpf_regs(st, INV_MPU6050_FILTER_NOLPF);
1094 if (result)
1095 return result;
1096 /* update wom threshold with new low-power frequency divider */
1097 result = inv_mpu6050_set_wom_threshold(st, st->chip_config.roc_threshold, lp_div);
1098 if (result)
1099 return result;
1100 /* set cycle mode */
1101 result = inv_mpu6050_pwr_mgmt_1_write(st, false, true, -1, -1);
1102 } else {
1103 /* disable cycle mode */
1104 result = inv_mpu6050_pwr_mgmt_1_write(st, false, false, -1, -1);
1105 if (result)
1106 return result;
1107 /* restore wom threshold */
1108 result = inv_mpu6050_set_wom_threshold(st, st->chip_config.roc_threshold,
1109 INV_MPU6050_FREQ_DIVIDER(st));
1110 if (result)
1111 return result;
1112 /* restore accel low pass filter */
1113 result = inv_mpu6050_set_accel_lpf_regs(st, st->chip_config.lpf);
1114 }
1115
1116 return result;
1117 }
1118
inv_mpu6050_enable_wom(struct inv_mpu6050_state * st,bool en)1119 static int inv_mpu6050_enable_wom(struct inv_mpu6050_state *st, bool en)
1120 {
1121 struct device *pdev = regmap_get_device(st->map);
1122 unsigned int mask;
1123 int result;
1124
1125 if (en) {
1126 result = pm_runtime_resume_and_get(pdev);
1127 if (result)
1128 return result;
1129
1130 mask = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_WOM;
1131 result = inv_mpu6050_switch_engine(st, true, mask);
1132 if (result)
1133 goto error_suspend;
1134
1135 result = inv_mpu6050_set_wom_int(st, true);
1136 if (result)
1137 goto error_suspend;
1138 } else {
1139 result = inv_mpu6050_set_wom_int(st, false);
1140 if (result)
1141 dev_err(pdev, "error %d disabling WoM interrupt bit", result);
1142
1143 /* disable only WoM and let accel be disabled by autosuspend */
1144 result = inv_mpu6050_switch_engine(st, false, INV_MPU6050_SENSOR_WOM);
1145 if (result) {
1146 dev_err(pdev, "error %d disabling WoM force off", result);
1147 /* force WoM off */
1148 st->chip_config.wom_en = false;
1149 }
1150
1151 pm_runtime_mark_last_busy(pdev);
1152 pm_runtime_put_autosuspend(pdev);
1153 }
1154
1155 return result;
1156
1157 error_suspend:
1158 pm_runtime_mark_last_busy(pdev);
1159 pm_runtime_put_autosuspend(pdev);
1160 return result;
1161 }
1162
inv_mpu6050_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1163 static int inv_mpu6050_read_event_config(struct iio_dev *indio_dev,
1164 const struct iio_chan_spec *chan,
1165 enum iio_event_type type,
1166 enum iio_event_direction dir)
1167 {
1168 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1169
1170 /* support only WoM (accel roc rising) event */
1171 if (chan->type != IIO_ACCEL || type != IIO_EV_TYPE_ROC ||
1172 dir != IIO_EV_DIR_RISING)
1173 return -EINVAL;
1174
1175 guard(mutex)(&st->lock);
1176
1177 return st->chip_config.wom_en ? 1 : 0;
1178 }
1179
inv_mpu6050_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1180 static int inv_mpu6050_write_event_config(struct iio_dev *indio_dev,
1181 const struct iio_chan_spec *chan,
1182 enum iio_event_type type,
1183 enum iio_event_direction dir,
1184 bool state)
1185 {
1186 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1187
1188 /* support only WoM (accel roc rising) event */
1189 if (chan->type != IIO_ACCEL || type != IIO_EV_TYPE_ROC ||
1190 dir != IIO_EV_DIR_RISING)
1191 return -EINVAL;
1192
1193 guard(mutex)(&st->lock);
1194
1195 if (st->chip_config.wom_en == state)
1196 return 0;
1197
1198 return inv_mpu6050_enable_wom(st, state);
1199 }
1200
inv_mpu6050_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1201 static int inv_mpu6050_read_event_value(struct iio_dev *indio_dev,
1202 const struct iio_chan_spec *chan,
1203 enum iio_event_type type,
1204 enum iio_event_direction dir,
1205 enum iio_event_info info,
1206 int *val, int *val2)
1207 {
1208 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1209 u32 rem;
1210
1211 /* support only WoM (accel roc rising) event value */
1212 if (chan->type != IIO_ACCEL || type != IIO_EV_TYPE_ROC ||
1213 dir != IIO_EV_DIR_RISING || info != IIO_EV_INFO_VALUE)
1214 return -EINVAL;
1215
1216 guard(mutex)(&st->lock);
1217
1218 /* return value in micro */
1219 *val = div_u64_rem(st->chip_config.roc_threshold, 1000000U, &rem);
1220 *val2 = rem;
1221
1222 return IIO_VAL_INT_PLUS_MICRO;
1223 }
1224
inv_mpu6050_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1225 static int inv_mpu6050_write_event_value(struct iio_dev *indio_dev,
1226 const struct iio_chan_spec *chan,
1227 enum iio_event_type type,
1228 enum iio_event_direction dir,
1229 enum iio_event_info info,
1230 int val, int val2)
1231 {
1232 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1233 struct device *pdev = regmap_get_device(st->map);
1234 u64 value;
1235 int result;
1236
1237 /* support only WoM (accel roc rising) event value */
1238 if (chan->type != IIO_ACCEL || type != IIO_EV_TYPE_ROC ||
1239 dir != IIO_EV_DIR_RISING || info != IIO_EV_INFO_VALUE)
1240 return -EINVAL;
1241
1242 if (val < 0 || val2 < 0)
1243 return -EINVAL;
1244
1245 guard(mutex)(&st->lock);
1246
1247 result = pm_runtime_resume_and_get(pdev);
1248 if (result)
1249 return result;
1250
1251 value = (u64)val * 1000000ULL + (u64)val2;
1252 result = inv_mpu6050_set_wom_threshold(st, value, INV_MPU6050_FREQ_DIVIDER(st));
1253
1254 pm_runtime_mark_last_busy(pdev);
1255 pm_runtime_put_autosuspend(pdev);
1256
1257 return result;
1258 }
1259
1260 /*
1261 * inv_mpu6050_set_lpf() - set low pass filer based on fifo rate.
1262 *
1263 * Based on the Nyquist principle, the bandwidth of the low
1264 * pass filter must not exceed the signal sampling rate divided
1265 * by 2, or there would be aliasing.
1266 * This function basically search for the correct low pass
1267 * parameters based on the fifo rate, e.g, sampling frequency.
1268 *
1269 * lpf is set automatically when setting sampling rate to avoid any aliases.
1270 */
inv_mpu6050_set_lpf(struct inv_mpu6050_state * st,int rate)1271 static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
1272 {
1273 static const int hz[] = {400, 200, 90, 40, 20, 10};
1274 static const int d[] = {
1275 INV_MPU6050_FILTER_200HZ, INV_MPU6050_FILTER_100HZ,
1276 INV_MPU6050_FILTER_45HZ, INV_MPU6050_FILTER_20HZ,
1277 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ
1278 };
1279 int i, result;
1280 u8 data;
1281
1282 data = INV_MPU6050_FILTER_5HZ;
1283 for (i = 0; i < ARRAY_SIZE(hz); ++i) {
1284 if (rate >= hz[i]) {
1285 data = d[i];
1286 break;
1287 }
1288 }
1289 result = inv_mpu6050_set_lpf_regs(st, data);
1290 if (result)
1291 return result;
1292 st->chip_config.lpf = data;
1293
1294 return 0;
1295 }
1296
1297 /*
1298 * inv_mpu6050_fifo_rate_store() - Set fifo rate.
1299 */
1300 static ssize_t
inv_mpu6050_fifo_rate_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1301 inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
1302 const char *buf, size_t count)
1303 {
1304 int fifo_rate;
1305 u32 fifo_period;
1306 bool fifo_on;
1307 u8 d;
1308 int result;
1309 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1310 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1311 struct device *pdev = regmap_get_device(st->map);
1312
1313 if (kstrtoint(buf, 10, &fifo_rate))
1314 return -EINVAL;
1315 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
1316 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
1317 return -EINVAL;
1318
1319 /* compute the chip sample rate divider */
1320 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate);
1321 /* compute back the fifo rate to handle truncation cases */
1322 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(d);
1323 fifo_period = NSEC_PER_SEC / fifo_rate;
1324
1325 mutex_lock(&st->lock);
1326 if (d == st->chip_config.divider) {
1327 result = 0;
1328 goto fifo_rate_fail_unlock;
1329 }
1330
1331 fifo_on = st->chip_config.accl_fifo_enable ||
1332 st->chip_config.gyro_fifo_enable ||
1333 st->chip_config.magn_fifo_enable;
1334 result = inv_sensors_timestamp_update_odr(&st->timestamp, fifo_period, fifo_on);
1335 if (result)
1336 goto fifo_rate_fail_unlock;
1337
1338 result = pm_runtime_resume_and_get(pdev);
1339 if (result)
1340 goto fifo_rate_fail_unlock;
1341
1342 result = regmap_write(st->map, st->reg->sample_rate_div, d);
1343 if (result)
1344 goto fifo_rate_fail_power_off;
1345 st->chip_config.divider = d;
1346
1347 result = inv_mpu6050_set_lpf(st, fifo_rate);
1348 if (result)
1349 goto fifo_rate_fail_power_off;
1350
1351 /* update rate for magn, noop if not present in chip */
1352 result = inv_mpu_magn_set_rate(st, fifo_rate);
1353 if (result)
1354 goto fifo_rate_fail_power_off;
1355
1356 /* update wom threshold since roc is dependent on sampling frequency */
1357 result = inv_mpu6050_set_wom_threshold(st, st->chip_config.roc_threshold,
1358 INV_MPU6050_FREQ_DIVIDER(st));
1359 if (result)
1360 goto fifo_rate_fail_power_off;
1361
1362 pm_runtime_mark_last_busy(pdev);
1363 fifo_rate_fail_power_off:
1364 pm_runtime_put_autosuspend(pdev);
1365 fifo_rate_fail_unlock:
1366 mutex_unlock(&st->lock);
1367 if (result)
1368 return result;
1369
1370 return count;
1371 }
1372
1373 /*
1374 * inv_fifo_rate_show() - Get the current sampling rate.
1375 */
1376 static ssize_t
inv_fifo_rate_show(struct device * dev,struct device_attribute * attr,char * buf)1377 inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
1378 char *buf)
1379 {
1380 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
1381 unsigned fifo_rate;
1382
1383 mutex_lock(&st->lock);
1384 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
1385 mutex_unlock(&st->lock);
1386
1387 return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate);
1388 }
1389
1390 /*
1391 * inv_attr_show() - calling this function will show current
1392 * parameters.
1393 *
1394 * Deprecated in favor of IIO mounting matrix API.
1395 *
1396 * See inv_get_mount_matrix()
1397 */
inv_attr_show(struct device * dev,struct device_attribute * attr,char * buf)1398 static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
1399 char *buf)
1400 {
1401 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
1402 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
1403 s8 *m;
1404
1405 switch (this_attr->address) {
1406 /*
1407 * In MPU6050, the two matrix are the same because gyro and accel
1408 * are integrated in one chip
1409 */
1410 case ATTR_GYRO_MATRIX:
1411 case ATTR_ACCL_MATRIX:
1412 m = st->plat_data.orientation;
1413
1414 return scnprintf(buf, PAGE_SIZE,
1415 "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
1416 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
1417 default:
1418 return -EINVAL;
1419 }
1420 }
1421
1422 /**
1423 * inv_mpu6050_validate_trigger() - validate_trigger callback for invensense
1424 * MPU6050 device.
1425 * @indio_dev: The IIO device
1426 * @trig: The new trigger
1427 *
1428 * Returns: 0 if the 'trig' matches the trigger registered by the MPU6050
1429 * device, -EINVAL otherwise.
1430 */
inv_mpu6050_validate_trigger(struct iio_dev * indio_dev,struct iio_trigger * trig)1431 static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
1432 struct iio_trigger *trig)
1433 {
1434 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1435
1436 if (st->trig != trig)
1437 return -EINVAL;
1438
1439 return 0;
1440 }
1441
1442 static const struct iio_mount_matrix *
inv_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)1443 inv_get_mount_matrix(const struct iio_dev *indio_dev,
1444 const struct iio_chan_spec *chan)
1445 {
1446 struct inv_mpu6050_state *data = iio_priv(indio_dev);
1447 const struct iio_mount_matrix *matrix;
1448
1449 if (chan->type == IIO_MAGN)
1450 matrix = &data->magn_orient;
1451 else
1452 matrix = &data->orientation;
1453
1454 return matrix;
1455 }
1456
1457 static const struct iio_chan_spec_ext_info inv_ext_info[] = {
1458 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
1459 { }
1460 };
1461
1462 static const struct iio_event_spec inv_wom_events[] = {
1463 {
1464 .type = IIO_EV_TYPE_ROC,
1465 .dir = IIO_EV_DIR_RISING,
1466 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
1467 BIT(IIO_EV_INFO_VALUE),
1468 },
1469 };
1470
1471 #define INV_MPU6050_CHAN(_type, _channel2, _index) \
1472 { \
1473 .type = _type, \
1474 .modified = 1, \
1475 .channel2 = _channel2, \
1476 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1477 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1478 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1479 .scan_index = _index, \
1480 .scan_type = { \
1481 .sign = 's', \
1482 .realbits = 16, \
1483 .storagebits = 16, \
1484 .shift = 0, \
1485 .endianness = IIO_BE, \
1486 }, \
1487 .ext_info = inv_ext_info, \
1488 }
1489
1490 #define INV_MPU6050_TEMP_CHAN(_index) \
1491 { \
1492 .type = IIO_TEMP, \
1493 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1494 | BIT(IIO_CHAN_INFO_OFFSET) \
1495 | BIT(IIO_CHAN_INFO_SCALE), \
1496 .scan_index = _index, \
1497 .scan_type = { \
1498 .sign = 's', \
1499 .realbits = 16, \
1500 .storagebits = 16, \
1501 .shift = 0, \
1502 .endianness = IIO_BE, \
1503 }, \
1504 }
1505
1506 #define INV_MPU6050_EVENT_CHAN(_type, _channel2, _events, _events_nb) \
1507 { \
1508 .type = _type, \
1509 .modified = 1, \
1510 .channel2 = _channel2, \
1511 .event_spec = _events, \
1512 .num_event_specs = _events_nb, \
1513 .scan_index = -1, \
1514 }
1515
1516 static const struct iio_chan_spec inv_mpu6050_channels[] = {
1517 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
1518
1519 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1520
1521 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1522 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1523 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1524
1525 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1526 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1527 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1528 };
1529
1530 static const struct iio_chan_spec inv_iam20380_channels[] = {
1531 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
1532
1533 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1534 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1535 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1536 };
1537
1538 static const struct iio_chan_spec inv_mpu6500_channels[] = {
1539 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
1540
1541 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1542
1543 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1544 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1545 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1546
1547 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1548 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1549 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1550
1551 INV_MPU6050_EVENT_CHAN(IIO_ACCEL, IIO_MOD_X_OR_Y_OR_Z,
1552 inv_wom_events, ARRAY_SIZE(inv_wom_events)),
1553 };
1554
1555 #define INV_MPU6050_SCAN_MASK_3AXIS_ACCEL \
1556 (BIT(INV_MPU6050_SCAN_ACCL_X) \
1557 | BIT(INV_MPU6050_SCAN_ACCL_Y) \
1558 | BIT(INV_MPU6050_SCAN_ACCL_Z))
1559
1560 #define INV_MPU6050_SCAN_MASK_3AXIS_GYRO \
1561 (BIT(INV_MPU6050_SCAN_GYRO_X) \
1562 | BIT(INV_MPU6050_SCAN_GYRO_Y) \
1563 | BIT(INV_MPU6050_SCAN_GYRO_Z))
1564
1565 #define INV_MPU6050_SCAN_MASK_TEMP (BIT(INV_MPU6050_SCAN_TEMP))
1566
1567 static const unsigned long inv_mpu_scan_masks[] = {
1568 /* 3-axis accel */
1569 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1570 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1571 /* 3-axis gyro */
1572 INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1573 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1574 /* 6-axis accel + gyro */
1575 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1576 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1577 | INV_MPU6050_SCAN_MASK_TEMP,
1578 0,
1579 };
1580
1581 #define INV_MPU9X50_MAGN_CHAN(_chan2, _bits, _index) \
1582 { \
1583 .type = IIO_MAGN, \
1584 .modified = 1, \
1585 .channel2 = _chan2, \
1586 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \
1587 BIT(IIO_CHAN_INFO_RAW), \
1588 .scan_index = _index, \
1589 .scan_type = { \
1590 .sign = 's', \
1591 .realbits = _bits, \
1592 .storagebits = 16, \
1593 .shift = 0, \
1594 .endianness = IIO_BE, \
1595 }, \
1596 .ext_info = inv_ext_info, \
1597 }
1598
1599 static const struct iio_chan_spec inv_mpu9150_channels[] = {
1600 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1601
1602 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1603
1604 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1605 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1606 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1607
1608 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1609 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1610 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1611
1612 /* Magnetometer resolution is 13 bits */
1613 INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 13, INV_MPU9X50_SCAN_MAGN_X),
1614 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 13, INV_MPU9X50_SCAN_MAGN_Y),
1615 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 13, INV_MPU9X50_SCAN_MAGN_Z),
1616 };
1617
1618 static const struct iio_chan_spec inv_mpu9250_channels[] = {
1619 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1620
1621 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1622
1623 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1624 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1625 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1626
1627 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1628 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1629 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1630
1631 /* Magnetometer resolution is 16 bits */
1632 INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 16, INV_MPU9X50_SCAN_MAGN_X),
1633 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 16, INV_MPU9X50_SCAN_MAGN_Y),
1634 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 16, INV_MPU9X50_SCAN_MAGN_Z),
1635 };
1636
1637 #define INV_MPU9X50_SCAN_MASK_3AXIS_MAGN \
1638 (BIT(INV_MPU9X50_SCAN_MAGN_X) \
1639 | BIT(INV_MPU9X50_SCAN_MAGN_Y) \
1640 | BIT(INV_MPU9X50_SCAN_MAGN_Z))
1641
1642 static const unsigned long inv_iam20380_scan_masks[] = {
1643 INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1644 };
1645
1646 static const unsigned long inv_mpu9x50_scan_masks[] = {
1647 /* 3-axis accel */
1648 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1649 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1650 /* 3-axis gyro */
1651 INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1652 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1653 /* 3-axis magn */
1654 INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1655 INV_MPU9X50_SCAN_MASK_3AXIS_MAGN | INV_MPU6050_SCAN_MASK_TEMP,
1656 /* 6-axis accel + gyro */
1657 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1658 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1659 | INV_MPU6050_SCAN_MASK_TEMP,
1660 /* 6-axis accel + magn */
1661 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1662 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1663 | INV_MPU6050_SCAN_MASK_TEMP,
1664 /* 6-axis gyro + magn */
1665 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1666 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1667 | INV_MPU6050_SCAN_MASK_TEMP,
1668 /* 9-axis accel + gyro + magn */
1669 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1670 | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1671 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1672 | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1673 | INV_MPU6050_SCAN_MASK_TEMP,
1674 0,
1675 };
1676
1677 static const unsigned long inv_icm20602_scan_masks[] = {
1678 /* 3-axis accel + temp (mandatory) */
1679 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1680 /* 3-axis gyro + temp (mandatory) */
1681 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1682 /* 6-axis accel + gyro + temp (mandatory) */
1683 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1684 | INV_MPU6050_SCAN_MASK_TEMP,
1685 0,
1686 };
1687
1688 /*
1689 * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and
1690 * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the
1691 * low-pass filter. Specifically, each of these sampling rates are about twice
1692 * the bandwidth of a corresponding low-pass filter, which should eliminate
1693 * aliasing following the Nyquist principle. By picking a frequency different
1694 * from these, the user risks aliasing effects.
1695 */
1696 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
1697 static IIO_CONST_ATTR(in_anglvel_scale_available,
1698 "0.000133090 0.000266181 0.000532362 0.001064724");
1699 static IIO_CONST_ATTR(in_accel_scale_available,
1700 "0.000598 0.001196 0.002392 0.004785");
1701 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
1702 inv_mpu6050_fifo_rate_store);
1703
1704 /* Deprecated: kept for userspace backward compatibility. */
1705 static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
1706 ATTR_GYRO_MATRIX);
1707 static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
1708 ATTR_ACCL_MATRIX);
1709
1710 static struct attribute *inv_attributes[] = {
1711 &iio_dev_attr_in_gyro_matrix.dev_attr.attr, /* deprecated */
1712 &iio_dev_attr_in_accel_matrix.dev_attr.attr, /* deprecated */
1713 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1714 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1715 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
1716 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
1717 NULL,
1718 };
1719
1720 static const struct attribute_group inv_attribute_group = {
1721 .attrs = inv_attributes
1722 };
1723
inv_mpu6050_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1724 static int inv_mpu6050_reg_access(struct iio_dev *indio_dev,
1725 unsigned int reg,
1726 unsigned int writeval,
1727 unsigned int *readval)
1728 {
1729 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1730 int ret;
1731
1732 mutex_lock(&st->lock);
1733 if (readval)
1734 ret = regmap_read(st->map, reg, readval);
1735 else
1736 ret = regmap_write(st->map, reg, writeval);
1737 mutex_unlock(&st->lock);
1738
1739 return ret;
1740 }
1741
1742 static const struct iio_info mpu_info = {
1743 .read_raw = &inv_mpu6050_read_raw,
1744 .write_raw = &inv_mpu6050_write_raw,
1745 .write_raw_get_fmt = &inv_write_raw_get_fmt,
1746 .attrs = &inv_attribute_group,
1747 .read_event_config = inv_mpu6050_read_event_config,
1748 .write_event_config = inv_mpu6050_write_event_config,
1749 .read_event_value = inv_mpu6050_read_event_value,
1750 .write_event_value = inv_mpu6050_write_event_value,
1751 .validate_trigger = inv_mpu6050_validate_trigger,
1752 .debugfs_reg_access = &inv_mpu6050_reg_access,
1753 };
1754
1755 /*
1756 * inv_check_and_setup_chip() - check and setup chip.
1757 */
inv_check_and_setup_chip(struct inv_mpu6050_state * st)1758 static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
1759 {
1760 int result;
1761 unsigned int regval, mask;
1762 int i;
1763
1764 st->hw = &hw_info[st->chip_type];
1765 st->reg = hw_info[st->chip_type].reg;
1766 memcpy(&st->chip_config, hw_info[st->chip_type].config,
1767 sizeof(st->chip_config));
1768 st->data = devm_kzalloc(regmap_get_device(st->map), st->hw->fifo_size, GFP_KERNEL);
1769 if (st->data == NULL)
1770 return -ENOMEM;
1771
1772 /* check chip self-identification */
1773 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
1774 if (result)
1775 return result;
1776 if (regval != st->hw->whoami) {
1777 /* check whoami against all possible values */
1778 for (i = 0; i < INV_NUM_PARTS; ++i) {
1779 if (regval == hw_info[i].whoami) {
1780 dev_warn(regmap_get_device(st->map),
1781 "whoami mismatch got 0x%02x (%s) expected 0x%02x (%s)\n",
1782 regval, hw_info[i].name,
1783 st->hw->whoami, st->hw->name);
1784 break;
1785 }
1786 }
1787 if (i >= INV_NUM_PARTS) {
1788 dev_err(regmap_get_device(st->map),
1789 "invalid whoami 0x%02x expected 0x%02x (%s)\n",
1790 regval, st->hw->whoami, st->hw->name);
1791 return -ENODEV;
1792 }
1793 }
1794
1795 /* reset to make sure previous state are not there */
1796 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
1797 INV_MPU6050_BIT_H_RESET);
1798 if (result)
1799 return result;
1800 msleep(INV_MPU6050_POWER_UP_TIME);
1801 switch (st->chip_type) {
1802 case INV_MPU6000:
1803 case INV_MPU6500:
1804 case INV_MPU6515:
1805 case INV_MPU6880:
1806 case INV_MPU9250:
1807 case INV_MPU9255:
1808 /* reset signal path (required for spi connection) */
1809 regval = INV_MPU6050_BIT_TEMP_RST | INV_MPU6050_BIT_ACCEL_RST |
1810 INV_MPU6050_BIT_GYRO_RST;
1811 result = regmap_write(st->map, INV_MPU6050_REG_SIGNAL_PATH_RESET,
1812 regval);
1813 if (result)
1814 return result;
1815 msleep(INV_MPU6050_POWER_UP_TIME);
1816 break;
1817 default:
1818 break;
1819 }
1820
1821 /*
1822 * Turn power on. After reset, the sleep bit could be on
1823 * or off depending on the OTP settings. Turning power on
1824 * make it in a definite state as well as making the hardware
1825 * state align with the software state
1826 */
1827 result = inv_mpu6050_set_power_itg(st, true);
1828 if (result)
1829 return result;
1830 mask = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
1831 INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN;
1832 result = inv_mpu6050_switch_engine(st, false, mask);
1833 if (result)
1834 goto error_power_off;
1835
1836 return 0;
1837
1838 error_power_off:
1839 inv_mpu6050_set_power_itg(st, false);
1840 return result;
1841 }
1842
inv_mpu_core_enable_regulator_vddio(struct inv_mpu6050_state * st)1843 static int inv_mpu_core_enable_regulator_vddio(struct inv_mpu6050_state *st)
1844 {
1845 int result;
1846
1847 result = regulator_enable(st->vddio_supply);
1848 if (result) {
1849 dev_err(regmap_get_device(st->map),
1850 "Failed to enable vddio regulator: %d\n", result);
1851 } else {
1852 /* Give the device a little bit of time to start up. */
1853 usleep_range(3000, 5000);
1854 }
1855
1856 return result;
1857 }
1858
inv_mpu_core_disable_regulator_vddio(struct inv_mpu6050_state * st)1859 static int inv_mpu_core_disable_regulator_vddio(struct inv_mpu6050_state *st)
1860 {
1861 int result;
1862
1863 result = regulator_disable(st->vddio_supply);
1864 if (result)
1865 dev_err(regmap_get_device(st->map),
1866 "Failed to disable vddio regulator: %d\n", result);
1867
1868 return result;
1869 }
1870
inv_mpu_core_disable_regulator_action(void * _data)1871 static void inv_mpu_core_disable_regulator_action(void *_data)
1872 {
1873 struct inv_mpu6050_state *st = _data;
1874 int result;
1875
1876 result = regulator_disable(st->vdd_supply);
1877 if (result)
1878 dev_err(regmap_get_device(st->map),
1879 "Failed to disable vdd regulator: %d\n", result);
1880
1881 inv_mpu_core_disable_regulator_vddio(st);
1882 }
1883
inv_mpu_pm_disable(void * data)1884 static void inv_mpu_pm_disable(void *data)
1885 {
1886 struct device *dev = data;
1887
1888 pm_runtime_disable(dev);
1889 }
1890
inv_mpu_core_probe(struct regmap * regmap,int irq,const char * name,int (* inv_mpu_bus_setup)(struct iio_dev *),int chip_type)1891 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
1892 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
1893 {
1894 struct inv_mpu6050_state *st;
1895 struct iio_dev *indio_dev;
1896 struct inv_mpu6050_platform_data *pdata;
1897 struct device *dev = regmap_get_device(regmap);
1898 int result;
1899 int irq_type;
1900
1901 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1902 if (!indio_dev)
1903 return -ENOMEM;
1904
1905 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
1906 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
1907 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
1908 chip_type, name);
1909 return -ENODEV;
1910 }
1911 st = iio_priv(indio_dev);
1912 mutex_init(&st->lock);
1913 st->chip_type = chip_type;
1914 st->irq = irq;
1915 st->map = regmap;
1916
1917 st->level_shifter = device_property_read_bool(dev,
1918 "invensense,level-shifter");
1919 pdata = dev_get_platdata(dev);
1920 if (!pdata) {
1921 result = iio_read_mount_matrix(dev, &st->orientation);
1922 if (result) {
1923 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
1924 result);
1925 return result;
1926 }
1927 } else {
1928 st->plat_data = *pdata;
1929 }
1930
1931 if (irq > 0) {
1932 irq_type = irq_get_trigger_type(irq);
1933 if (!irq_type)
1934 irq_type = IRQF_TRIGGER_RISING;
1935 } else {
1936 /* Doesn't really matter, use the default */
1937 irq_type = IRQF_TRIGGER_RISING;
1938 }
1939
1940 if (irq_type & IRQF_TRIGGER_RISING) // rising or both-edge
1941 st->irq_mask = INV_MPU6050_ACTIVE_HIGH;
1942 else if (irq_type == IRQF_TRIGGER_FALLING)
1943 st->irq_mask = INV_MPU6050_ACTIVE_LOW;
1944 else if (irq_type == IRQF_TRIGGER_HIGH)
1945 st->irq_mask = INV_MPU6050_ACTIVE_HIGH |
1946 INV_MPU6050_LATCH_INT_EN;
1947 else if (irq_type == IRQF_TRIGGER_LOW)
1948 st->irq_mask = INV_MPU6050_ACTIVE_LOW |
1949 INV_MPU6050_LATCH_INT_EN;
1950 else {
1951 dev_err(dev, "Invalid interrupt type 0x%x specified\n",
1952 irq_type);
1953 return -EINVAL;
1954 }
1955 device_set_wakeup_capable(dev, true);
1956
1957 st->vdd_supply = devm_regulator_get(dev, "vdd");
1958 if (IS_ERR(st->vdd_supply))
1959 return dev_err_probe(dev, PTR_ERR(st->vdd_supply),
1960 "Failed to get vdd regulator\n");
1961
1962 st->vddio_supply = devm_regulator_get(dev, "vddio");
1963 if (IS_ERR(st->vddio_supply))
1964 return dev_err_probe(dev, PTR_ERR(st->vddio_supply),
1965 "Failed to get vddio regulator\n");
1966
1967 result = regulator_enable(st->vdd_supply);
1968 if (result) {
1969 dev_err(dev, "Failed to enable vdd regulator: %d\n", result);
1970 return result;
1971 }
1972 msleep(INV_MPU6050_POWER_UP_TIME);
1973
1974 result = inv_mpu_core_enable_regulator_vddio(st);
1975 if (result) {
1976 regulator_disable(st->vdd_supply);
1977 return result;
1978 }
1979
1980 result = devm_add_action_or_reset(dev, inv_mpu_core_disable_regulator_action,
1981 st);
1982 if (result) {
1983 dev_err(dev, "Failed to setup regulator cleanup action %d\n",
1984 result);
1985 return result;
1986 }
1987
1988 /* fill magnetometer orientation */
1989 result = inv_mpu_magn_set_orient(st);
1990 if (result)
1991 return result;
1992
1993 /* power is turned on inside check chip type*/
1994 result = inv_check_and_setup_chip(st);
1995 if (result)
1996 return result;
1997
1998 result = inv_mpu6050_init_config(indio_dev);
1999 if (result) {
2000 dev_err(dev, "Could not initialize device.\n");
2001 goto error_power_off;
2002 }
2003
2004 dev_set_drvdata(dev, indio_dev);
2005 /* name will be NULL when enumerated via ACPI */
2006 if (name)
2007 indio_dev->name = name;
2008 else
2009 indio_dev->name = dev_name(dev);
2010
2011 /* requires parent device set in indio_dev */
2012 if (inv_mpu_bus_setup) {
2013 result = inv_mpu_bus_setup(indio_dev);
2014 if (result)
2015 goto error_power_off;
2016 }
2017
2018 /* chip init is done, turning on runtime power management */
2019 result = pm_runtime_set_active(dev);
2020 if (result)
2021 goto error_power_off;
2022 pm_runtime_get_noresume(dev);
2023 pm_runtime_enable(dev);
2024 pm_runtime_set_autosuspend_delay(dev, INV_MPU6050_SUSPEND_DELAY_MS);
2025 pm_runtime_use_autosuspend(dev);
2026 pm_runtime_put(dev);
2027 result = devm_add_action_or_reset(dev, inv_mpu_pm_disable, dev);
2028 if (result)
2029 return result;
2030
2031 switch (chip_type) {
2032 case INV_MPU6000:
2033 case INV_MPU6050:
2034 indio_dev->channels = inv_mpu6050_channels;
2035 indio_dev->num_channels = ARRAY_SIZE(inv_mpu6050_channels);
2036 indio_dev->available_scan_masks = inv_mpu_scan_masks;
2037 break;
2038 case INV_MPU9150:
2039 indio_dev->channels = inv_mpu9150_channels;
2040 indio_dev->num_channels = ARRAY_SIZE(inv_mpu9150_channels);
2041 indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
2042 break;
2043 case INV_MPU9250:
2044 case INV_MPU9255:
2045 indio_dev->channels = inv_mpu9250_channels;
2046 indio_dev->num_channels = ARRAY_SIZE(inv_mpu9250_channels);
2047 indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
2048 break;
2049 case INV_IAM20380:
2050 indio_dev->channels = inv_iam20380_channels;
2051 indio_dev->num_channels = ARRAY_SIZE(inv_iam20380_channels);
2052 indio_dev->available_scan_masks = inv_iam20380_scan_masks;
2053 break;
2054 case INV_ICM20600:
2055 case INV_ICM20602:
2056 indio_dev->channels = inv_mpu6500_channels;
2057 indio_dev->num_channels = ARRAY_SIZE(inv_mpu6500_channels);
2058 indio_dev->available_scan_masks = inv_icm20602_scan_masks;
2059 break;
2060 default:
2061 indio_dev->channels = inv_mpu6500_channels;
2062 indio_dev->num_channels = ARRAY_SIZE(inv_mpu6500_channels);
2063 indio_dev->available_scan_masks = inv_mpu_scan_masks;
2064 break;
2065 }
2066 /*
2067 * Use magnetometer inside the chip only if there is no i2c
2068 * auxiliary device in use. Otherwise Going back to 6-axis only.
2069 */
2070 if (st->magn_disabled) {
2071 switch (chip_type) {
2072 case INV_MPU9150:
2073 indio_dev->channels = inv_mpu6050_channels;
2074 indio_dev->num_channels = ARRAY_SIZE(inv_mpu6050_channels);
2075 indio_dev->available_scan_masks = inv_mpu_scan_masks;
2076 break;
2077 default:
2078 indio_dev->channels = inv_mpu6500_channels;
2079 indio_dev->num_channels = ARRAY_SIZE(inv_mpu6500_channels);
2080 indio_dev->available_scan_masks = inv_mpu_scan_masks;
2081 break;
2082 }
2083 }
2084
2085 indio_dev->info = &mpu_info;
2086
2087 if (irq > 0) {
2088 /*
2089 * The driver currently only supports buffered capture with its
2090 * own trigger. So no IRQ, no trigger, no buffer
2091 */
2092 result = devm_iio_triggered_buffer_setup(dev, indio_dev,
2093 iio_pollfunc_store_time,
2094 inv_mpu6050_read_fifo,
2095 NULL);
2096 if (result) {
2097 dev_err(dev, "configure buffer fail %d\n", result);
2098 return result;
2099 }
2100
2101 result = inv_mpu6050_probe_trigger(indio_dev, irq_type);
2102 if (result) {
2103 dev_err(dev, "trigger probe fail %d\n", result);
2104 return result;
2105 }
2106 }
2107
2108 result = devm_iio_device_register(dev, indio_dev);
2109 if (result) {
2110 dev_err(dev, "IIO register fail %d\n", result);
2111 return result;
2112 }
2113
2114 return 0;
2115
2116 error_power_off:
2117 inv_mpu6050_set_power_itg(st, false);
2118 return result;
2119 }
2120 EXPORT_SYMBOL_NS_GPL(inv_mpu_core_probe, "IIO_MPU6050");
2121
inv_mpu_resume(struct device * dev)2122 static int inv_mpu_resume(struct device *dev)
2123 {
2124 struct iio_dev *indio_dev = dev_get_drvdata(dev);
2125 struct inv_mpu6050_state *st = iio_priv(indio_dev);
2126 bool wakeup;
2127 int result;
2128
2129 guard(mutex)(&st->lock);
2130
2131 wakeup = device_may_wakeup(dev) && st->chip_config.wom_en;
2132
2133 if (wakeup) {
2134 enable_irq(st->irq);
2135 disable_irq_wake(st->irq);
2136 result = inv_mpu6050_set_wom_lp(st, false);
2137 if (result)
2138 return result;
2139 } else {
2140 result = inv_mpu_core_enable_regulator_vddio(st);
2141 if (result)
2142 return result;
2143 result = inv_mpu6050_set_power_itg(st, true);
2144 if (result)
2145 return result;
2146 }
2147
2148 pm_runtime_disable(dev);
2149 pm_runtime_set_active(dev);
2150 pm_runtime_enable(dev);
2151
2152 result = inv_mpu6050_switch_engine(st, true, st->suspended_sensors);
2153 if (result)
2154 return result;
2155
2156 if (st->chip_config.wom_en && !wakeup) {
2157 result = inv_mpu6050_set_wom_int(st, true);
2158 if (result)
2159 return result;
2160 }
2161
2162 if (iio_buffer_enabled(indio_dev))
2163 result = inv_mpu6050_prepare_fifo(st, true);
2164
2165 return result;
2166 }
2167
inv_mpu_suspend(struct device * dev)2168 static int inv_mpu_suspend(struct device *dev)
2169 {
2170 struct iio_dev *indio_dev = dev_get_drvdata(dev);
2171 struct inv_mpu6050_state *st = iio_priv(indio_dev);
2172 bool wakeup;
2173 int result;
2174
2175 guard(mutex)(&st->lock);
2176
2177 st->suspended_sensors = 0;
2178 if (pm_runtime_suspended(dev))
2179 return 0;
2180
2181 if (iio_buffer_enabled(indio_dev)) {
2182 result = inv_mpu6050_prepare_fifo(st, false);
2183 if (result)
2184 return result;
2185 }
2186
2187 wakeup = device_may_wakeup(dev) && st->chip_config.wom_en;
2188
2189 if (st->chip_config.wom_en && !wakeup) {
2190 result = inv_mpu6050_set_wom_int(st, false);
2191 if (result)
2192 return result;
2193 }
2194
2195 if (st->chip_config.accl_en && !wakeup)
2196 st->suspended_sensors |= INV_MPU6050_SENSOR_ACCL;
2197 if (st->chip_config.gyro_en)
2198 st->suspended_sensors |= INV_MPU6050_SENSOR_GYRO;
2199 if (st->chip_config.temp_en)
2200 st->suspended_sensors |= INV_MPU6050_SENSOR_TEMP;
2201 if (st->chip_config.magn_en)
2202 st->suspended_sensors |= INV_MPU6050_SENSOR_MAGN;
2203 if (st->chip_config.wom_en && !wakeup)
2204 st->suspended_sensors |= INV_MPU6050_SENSOR_WOM;
2205 result = inv_mpu6050_switch_engine(st, false, st->suspended_sensors);
2206 if (result)
2207 return result;
2208
2209 if (wakeup) {
2210 result = inv_mpu6050_set_wom_lp(st, true);
2211 if (result)
2212 return result;
2213 enable_irq_wake(st->irq);
2214 disable_irq(st->irq);
2215 } else {
2216 result = inv_mpu6050_set_power_itg(st, false);
2217 if (result)
2218 return result;
2219 inv_mpu_core_disable_regulator_vddio(st);
2220 }
2221
2222 return 0;
2223 }
2224
inv_mpu_runtime_suspend(struct device * dev)2225 static int inv_mpu_runtime_suspend(struct device *dev)
2226 {
2227 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
2228 unsigned int sensors;
2229 int ret;
2230
2231 mutex_lock(&st->lock);
2232
2233 sensors = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
2234 INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN |
2235 INV_MPU6050_SENSOR_WOM;
2236 ret = inv_mpu6050_switch_engine(st, false, sensors);
2237 if (ret)
2238 goto out_unlock;
2239
2240 ret = inv_mpu6050_set_power_itg(st, false);
2241 if (ret)
2242 goto out_unlock;
2243
2244 inv_mpu_core_disable_regulator_vddio(st);
2245
2246 out_unlock:
2247 mutex_unlock(&st->lock);
2248 return ret;
2249 }
2250
inv_mpu_runtime_resume(struct device * dev)2251 static int inv_mpu_runtime_resume(struct device *dev)
2252 {
2253 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
2254 int ret;
2255
2256 ret = inv_mpu_core_enable_regulator_vddio(st);
2257 if (ret)
2258 return ret;
2259
2260 return inv_mpu6050_set_power_itg(st, true);
2261 }
2262
2263 EXPORT_NS_GPL_DEV_PM_OPS(inv_mpu_pmops, IIO_MPU6050) = {
2264 SYSTEM_SLEEP_PM_OPS(inv_mpu_suspend, inv_mpu_resume)
2265 RUNTIME_PM_OPS(inv_mpu_runtime_suspend, inv_mpu_runtime_resume, NULL)
2266 };
2267
2268 MODULE_AUTHOR("Invensense Corporation");
2269 MODULE_DESCRIPTION("Invensense device MPU6050 driver");
2270 MODULE_LICENSE("GPL");
2271 MODULE_IMPORT_NS("IIO_INV_SENSORS_TIMESTAMP");
2272