1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/T2H Pin Control and GPIO driver core 4 * 5 * Based on drivers/pinctrl/renesas/pinctrl-rzg2l.c 6 * 7 * Copyright (C) 2025 Renesas Electronics Corporation. 8 */ 9 10 #include <linux/array_size.h> 11 #include <linux/bitfield.h> 12 #include <linux/bitops.h> 13 #include <linux/bits.h> 14 #include <linux/cleanup.h> 15 #include <linux/clk.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/io.h> 18 #include <linux/ioport.h> 19 #include <linux/module.h> 20 #include <linux/mutex.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/spinlock.h> 26 #include <linux/types.h> 27 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinctrl.h> 32 #include <linux/pinctrl/pinmux.h> 33 34 #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> 35 36 #include "../core.h" 37 #include "../pinconf.h" 38 #include "../pinmux.h" 39 40 #define DRV_NAME "pinctrl-rzt2h" 41 42 #define P(m) (0x001 * (m)) 43 #define PM(m) (0x200 + 2 * (m)) 44 #define PMC(m) (0x400 + (m)) 45 #define PFC(m) (0x600 + 8 * (m)) 46 #define PIN(m) (0x800 + (m)) 47 #define DRCTL(n) (0xa00 + 8 * (n)) 48 #define RSELP(m) (0xc00 + (m)) 49 50 #define PM_MASK GENMASK(1, 0) 51 #define PM_PIN_MASK(pin) (PM_MASK << ((pin) * 2)) 52 #define PM_INPUT BIT(0) 53 #define PM_OUTPUT BIT(1) 54 55 #define PFC_MASK GENMASK_ULL(5, 0) 56 #define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8)) 57 #define PFC_FUNC_INTERRUPT 0 58 59 #define DRCTL_DRV_PIN_MASK(pin) (GENMASK_ULL(1, 0) << ((pin) * 8)) 60 #define DRCTL_PUD_PIN_MASK(pin) (GENMASK_ULL(3, 2) << ((pin) * 8)) 61 #define DRCTL_SMT_PIN_MASK(pin) (BIT_ULL(4) << ((pin) * 8)) 62 #define DRCTL_SR_PIN_MASK(pin) (BIT_ULL(5) << ((pin) * 8)) 63 64 #define DRCTL_PUD_NONE 0 65 #define DRCTL_PUD_PULL_UP 1 66 #define DRCTL_PUD_PULL_DOWN 2 67 68 /* 69 * Use 16 lower bits [15:0] for pin identifier 70 * Use 8 higher bits [23:16] for pin mux function 71 */ 72 #define MUX_PIN_ID_MASK GENMASK(15, 0) 73 #define MUX_FUNC_MASK GENMASK(23, 16) 74 75 #define RZT2H_PIN_ID_TO_PORT(id) ((id) / RZT2H_PINS_PER_PORT) 76 #define RZT2H_PIN_ID_TO_PIN(id) ((id) % RZT2H_PINS_PER_PORT) 77 78 #define RZT2H_MAX_SAFETY_PORTS 12 79 80 #define RZT2H_INTERRUPTS_START 16 81 #define RZT2H_INTERRUPTS_NUM 17 82 83 struct rzt2h_pinctrl_data { 84 unsigned int n_port_pins; 85 const u8 *port_pin_configs; 86 unsigned int n_ports; 87 }; 88 89 struct rzt2h_pinctrl { 90 struct pinctrl_dev *pctl; 91 struct pinctrl_desc desc; 92 struct pinctrl_pin_desc *pins; 93 const struct rzt2h_pinctrl_data *data; 94 void __iomem *base0, *base1; 95 struct device *dev; 96 struct gpio_chip gpio_chip; 97 struct pinctrl_gpio_range gpio_range; 98 DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM); 99 raw_spinlock_t lock; /* lock read/write registers */ 100 struct mutex mutex; /* serialize adding groups and functions */ 101 bool safety_port_enabled; 102 atomic_t wakeup_path; 103 }; 104 105 static const unsigned int rzt2h_drive_strength_ua[] = { 2500, 5000, 9000, 11800 }; 106 107 #define RZT2H_GET_BASE(pctrl, port) \ 108 ((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1) 109 110 #define RZT2H_PINCTRL_REG_ACCESS(size, type) \ 111 static inline void rzt2h_pinctrl_write##size(struct rzt2h_pinctrl *pctrl, u8 port, \ 112 type val, unsigned int offset) \ 113 { \ 114 write##size(val, RZT2H_GET_BASE(pctrl, port) + offset); \ 115 } \ 116 static inline type rzt2h_pinctrl_read##size(struct rzt2h_pinctrl *pctrl, u8 port, \ 117 unsigned int offset) \ 118 { \ 119 return read##size(RZT2H_GET_BASE(pctrl, port) + offset); \ 120 } 121 122 RZT2H_PINCTRL_REG_ACCESS(b, u8) 123 RZT2H_PINCTRL_REG_ACCESS(w, u16) 124 RZT2H_PINCTRL_REG_ACCESS(q, u64) 125 126 static int rzt2h_drive_strength_ua_to_idx(unsigned int ua) 127 { 128 unsigned int i; 129 130 for (i = 0; i < ARRAY_SIZE(rzt2h_drive_strength_ua); i++) { 131 if (rzt2h_drive_strength_ua[i] == ua) 132 return i; 133 } 134 135 return -EINVAL; 136 } 137 138 static int rzt2h_drive_strength_idx_to_ua(unsigned int idx) 139 { 140 if (idx >= ARRAY_SIZE(rzt2h_drive_strength_ua)) 141 return -EINVAL; 142 143 return rzt2h_drive_strength_ua[idx]; 144 } 145 146 static void rzt2h_pinctrl_drctl_rmwq(struct rzt2h_pinctrl *pctrl, 147 u32 port, u64 mask, u64 val) 148 { 149 u32 offset = DRCTL(port); 150 u64 drctl; 151 152 guard(raw_spinlock_irqsave)(&pctrl->lock); 153 drctl = rzt2h_pinctrl_readq(pctrl, port, offset) & ~mask; 154 rzt2h_pinctrl_writeq(pctrl, port, drctl | val, offset); 155 } 156 157 static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset) 158 { 159 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 160 u8 pin = RZT2H_PIN_ID_TO_PIN(offset); 161 u8 pincfg; 162 163 if (offset >= pctrl->data->n_port_pins || port >= pctrl->data->n_ports) 164 return -EINVAL; 165 166 if (!pctrl->safety_port_enabled && port <= RZT2H_MAX_SAFETY_PORTS) 167 return -EINVAL; 168 169 pincfg = pctrl->data->port_pin_configs[port]; 170 return (pincfg & BIT(pin)) ? 0 : -EINVAL; 171 } 172 173 static void rzt2h_pinctrl_set_gpio_en(struct rzt2h_pinctrl *pctrl, 174 u8 port, u8 pin, bool en) 175 { 176 u8 reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 177 178 if (en) 179 reg &= ~BIT(pin); 180 else 181 reg |= BIT(pin); 182 183 rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port)); 184 } 185 186 static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, 187 u8 port, u8 pin, u8 func) 188 { 189 u64 reg64; 190 u16 reg16; 191 192 guard(raw_spinlock_irqsave)(&pctrl->lock); 193 194 reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); 195 /* Check if pin is already configured to the desired function */ 196 if ((rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(pin)) && 197 field_get(PFC_PIN_MASK(pin), reg64) == func) 198 return; 199 200 /* Set pin to 'Non-use (Hi-Z input protection)' */ 201 reg16 = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 202 reg16 &= ~PM_PIN_MASK(pin); 203 rzt2h_pinctrl_writew(pctrl, port, reg16, PM(port)); 204 205 /* Temporarily switch to GPIO mode with PMC register */ 206 rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true); 207 208 /* Select Pin function mode with PFC register */ 209 reg64 &= ~PFC_PIN_MASK(pin); 210 rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port)); 211 212 /* Switch to Peripheral pin function with PMC register */ 213 rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); 214 } 215 216 static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev, 217 unsigned int func_selector, 218 unsigned int group_selector) 219 { 220 struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 221 const struct function_desc *func; 222 struct group_desc *group; 223 const unsigned int *pins; 224 unsigned int i; 225 u8 *psel_val; 226 int ret; 227 228 func = pinmux_generic_get_function(pctldev, func_selector); 229 if (!func) 230 return -EINVAL; 231 232 group = pinctrl_generic_get_group(pctldev, group_selector); 233 if (!group) 234 return -EINVAL; 235 236 psel_val = func->data; 237 pins = group->grp.pins; 238 239 for (i = 0; i < group->grp.npins; i++) { 240 dev_dbg(pctrl->dev, "port:%u pin:%u PSEL:%u\n", 241 RZT2H_PIN_ID_TO_PORT(pins[i]), RZT2H_PIN_ID_TO_PIN(pins[i]), 242 psel_val[i]); 243 ret = rzt2h_validate_pin(pctrl, pins[i]); 244 if (ret) 245 return ret; 246 247 rzt2h_pinctrl_set_pfc_mode(pctrl, RZT2H_PIN_ID_TO_PORT(pins[i]), 248 RZT2H_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 249 } 250 251 return 0; 252 } 253 254 static int rzt2h_map_add_config(struct pinctrl_map *map, 255 const char *group_or_pin, 256 enum pinctrl_map_type type, 257 unsigned long *configs, 258 unsigned int num_configs) 259 { 260 unsigned long *cfgs; 261 262 cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL); 263 if (!cfgs) 264 return -ENOMEM; 265 266 map->type = type; 267 map->data.configs.group_or_pin = group_or_pin; 268 map->data.configs.configs = cfgs; 269 map->data.configs.num_configs = num_configs; 270 271 return 0; 272 } 273 274 static int rzt2h_dt_subnode_to_map(struct pinctrl_dev *pctldev, 275 struct device_node *np, 276 struct device_node *parent, 277 struct pinctrl_map **map, 278 unsigned int *num_maps, 279 unsigned int *index) 280 { 281 struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 282 struct pinctrl_map *maps = *map; 283 unsigned int nmaps = *num_maps; 284 unsigned long *configs = NULL; 285 unsigned int num_pinmux = 0; 286 unsigned int idx = *index; 287 unsigned int num_pins, i; 288 unsigned int num_configs; 289 struct property *pinmux; 290 struct property *prop; 291 int ret, gsel, fsel; 292 const char **pin_fn; 293 unsigned int *pins; 294 const char *name; 295 const char *pin; 296 u8 *psel_val; 297 298 pinmux = of_find_property(np, "pinmux", NULL); 299 if (pinmux) 300 num_pinmux = pinmux->length / sizeof(u32); 301 302 ret = of_property_count_strings(np, "pins"); 303 if (ret == -EINVAL) { 304 num_pins = 0; 305 } else if (ret < 0) { 306 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 307 return ret; 308 } else { 309 num_pins = ret; 310 } 311 312 if (!num_pinmux && !num_pins) 313 return 0; 314 315 if (num_pinmux && num_pins) { 316 dev_err(pctrl->dev, 317 "DT node must contain either a pinmux or pins and not both\n"); 318 return -EINVAL; 319 } 320 321 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); 322 if (ret < 0) 323 return ret; 324 325 if (num_pins && !num_configs) { 326 dev_err(pctrl->dev, "DT node must contain a config\n"); 327 ret = -ENODEV; 328 goto done; 329 } 330 331 if (num_pinmux) { 332 nmaps += 1; 333 if (num_configs) 334 nmaps += 1; 335 } 336 337 if (num_pins) 338 nmaps += num_pins; 339 340 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 341 if (!maps) { 342 ret = -ENOMEM; 343 goto done; 344 } 345 346 *map = maps; 347 *num_maps = nmaps; 348 if (num_pins) { 349 of_property_for_each_string(np, "pins", prop, pin) { 350 ret = rzt2h_map_add_config(&maps[idx], pin, 351 PIN_MAP_TYPE_CONFIGS_PIN, 352 configs, num_configs); 353 if (ret < 0) 354 goto done; 355 356 idx++; 357 } 358 ret = 0; 359 goto done; 360 } 361 362 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 363 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 364 GFP_KERNEL); 365 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 366 if (!pins || !psel_val || !pin_fn) { 367 ret = -ENOMEM; 368 goto done; 369 } 370 371 /* Collect pin locations and mux settings from DT properties */ 372 for (i = 0; i < num_pinmux; ++i) { 373 u32 value; 374 375 ret = of_property_read_u32_index(np, "pinmux", i, &value); 376 if (ret) 377 goto done; 378 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); 379 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); 380 } 381 382 if (parent) { 383 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 384 parent, np); 385 if (!name) { 386 ret = -ENOMEM; 387 goto done; 388 } 389 } else { 390 name = np->name; 391 } 392 393 if (num_configs) { 394 ret = rzt2h_map_add_config(&maps[idx], name, 395 PIN_MAP_TYPE_CONFIGS_GROUP, 396 configs, num_configs); 397 if (ret < 0) 398 goto done; 399 400 idx++; 401 } 402 403 scoped_guard(mutex, &pctrl->mutex) { 404 /* Register a single pin group listing all the pins we read from DT */ 405 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 406 if (gsel < 0) { 407 ret = gsel; 408 goto done; 409 } 410 411 /* 412 * Register a single group function where the 'data' is an array PSEL 413 * register values read from DT. 414 */ 415 pin_fn[0] = name; 416 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 417 if (fsel < 0) { 418 ret = fsel; 419 goto remove_group; 420 } 421 } 422 423 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 424 maps[idx].data.mux.group = name; 425 maps[idx].data.mux.function = name; 426 idx++; 427 428 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 429 ret = 0; 430 goto done; 431 432 remove_group: 433 pinctrl_generic_remove_group(pctldev, gsel); 434 done: 435 *index = idx; 436 kfree(configs); 437 return ret; 438 } 439 440 static void rzt2h_dt_free_map(struct pinctrl_dev *pctldev, 441 struct pinctrl_map *map, 442 unsigned int num_maps) 443 { 444 unsigned int i; 445 446 if (!map) 447 return; 448 449 for (i = 0; i < num_maps; ++i) { 450 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 451 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 452 kfree(map[i].data.configs.configs); 453 } 454 kfree(map); 455 } 456 457 static int rzt2h_dt_node_to_map(struct pinctrl_dev *pctldev, 458 struct device_node *np, 459 struct pinctrl_map **map, 460 unsigned int *num_maps) 461 { 462 struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 463 unsigned int index; 464 int ret; 465 466 *map = NULL; 467 *num_maps = 0; 468 index = 0; 469 470 for_each_child_of_node_scoped(np, child) { 471 ret = rzt2h_dt_subnode_to_map(pctldev, child, np, map, 472 num_maps, &index); 473 if (ret < 0) 474 goto done; 475 } 476 477 if (*num_maps == 0) { 478 ret = rzt2h_dt_subnode_to_map(pctldev, np, NULL, map, 479 num_maps, &index); 480 if (ret < 0) 481 goto done; 482 } 483 484 if (*num_maps) 485 return 0; 486 487 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 488 ret = -EINVAL; 489 490 done: 491 rzt2h_dt_free_map(pctldev, *map, *num_maps); 492 return ret; 493 } 494 495 static int rzt2h_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 496 unsigned int pin, 497 unsigned long *config) 498 { 499 struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 500 u32 port, param = pinconf_to_config_param(*config); 501 unsigned int arg; 502 u8 port_pin; 503 u64 drctl; 504 int ret; 505 506 ret = rzt2h_validate_pin(pctrl, pin); 507 if (ret) 508 return ret; 509 510 port = RZT2H_PIN_ID_TO_PORT(pin); 511 port_pin = RZT2H_PIN_ID_TO_PIN(pin); 512 513 switch (param) { 514 case PIN_CONFIG_SLEW_RATE: 515 drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); 516 arg = field_get(DRCTL_SR_PIN_MASK(port_pin), drctl); 517 break; 518 519 case PIN_CONFIG_BIAS_DISABLE: 520 case PIN_CONFIG_BIAS_PULL_UP: 521 case PIN_CONFIG_BIAS_PULL_DOWN: 522 drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); 523 arg = field_get(DRCTL_PUD_PIN_MASK(port_pin), drctl); 524 /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ 525 switch (arg) { 526 case DRCTL_PUD_NONE: 527 if (param != PIN_CONFIG_BIAS_DISABLE) 528 return -EINVAL; 529 break; 530 case DRCTL_PUD_PULL_UP: 531 if (param != PIN_CONFIG_BIAS_PULL_UP) 532 return -EINVAL; 533 arg = 1; 534 break; 535 case DRCTL_PUD_PULL_DOWN: 536 if (param != PIN_CONFIG_BIAS_PULL_DOWN) 537 return -EINVAL; 538 arg = 1; 539 break; 540 default: 541 return -EINVAL; 542 } 543 break; 544 545 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 546 drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); 547 arg = field_get(DRCTL_SMT_PIN_MASK(port_pin), drctl); 548 if (!arg) 549 return -EINVAL; 550 break; 551 552 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 553 int idx_drv; 554 555 drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); 556 arg = field_get(DRCTL_DRV_PIN_MASK(port_pin), drctl); 557 idx_drv = rzt2h_drive_strength_idx_to_ua(arg); 558 if (idx_drv < 0) 559 return idx_drv; 560 arg = idx_drv; 561 break; 562 } 563 564 default: 565 return -ENOTSUPP; 566 } 567 568 *config = pinconf_to_config_packed(param, arg); 569 return 0; 570 } 571 572 static int rzt2h_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 573 unsigned int pin, 574 unsigned long *configs, 575 unsigned int num_configs) 576 { 577 struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 578 unsigned int i; 579 u8 port_pin; 580 int ret; 581 582 ret = rzt2h_validate_pin(pctrl, pin); 583 if (ret) 584 return ret; 585 586 port_pin = RZT2H_PIN_ID_TO_PIN(pin); 587 588 for (i = 0; i < num_configs; i++) { 589 u32 arg = pinconf_to_config_argument(configs[i]); 590 u32 param = pinconf_to_config_param(configs[i]); 591 u64 mask, val; 592 593 switch (param) { 594 case PIN_CONFIG_SLEW_RATE: 595 mask = DRCTL_SR_PIN_MASK(port_pin); 596 val = field_prep(mask, !!arg); 597 break; 598 599 case PIN_CONFIG_BIAS_DISABLE: 600 case PIN_CONFIG_BIAS_PULL_UP: 601 case PIN_CONFIG_BIAS_PULL_DOWN: { 602 u32 bias; 603 604 switch (param) { 605 case PIN_CONFIG_BIAS_DISABLE: 606 bias = DRCTL_PUD_NONE; 607 break; 608 case PIN_CONFIG_BIAS_PULL_UP: 609 bias = DRCTL_PUD_PULL_UP; 610 break; 611 case PIN_CONFIG_BIAS_PULL_DOWN: 612 bias = DRCTL_PUD_PULL_DOWN; 613 break; 614 } 615 616 mask = DRCTL_PUD_PIN_MASK(port_pin); 617 val = field_prep(mask, bias); 618 break; 619 } 620 621 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 622 mask = DRCTL_SMT_PIN_MASK(port_pin); 623 val = field_prep(mask, !!arg); 624 break; 625 626 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 627 int drv_idx; 628 629 drv_idx = rzt2h_drive_strength_ua_to_idx(arg); 630 if (drv_idx < 0) 631 return drv_idx; 632 633 mask = DRCTL_DRV_PIN_MASK(port_pin); 634 val = field_prep(mask, drv_idx); 635 break; 636 } 637 638 default: 639 return -ENOTSUPP; 640 } 641 642 rzt2h_pinctrl_drctl_rmwq(pctrl, RZT2H_PIN_ID_TO_PORT(pin), mask, val); 643 } 644 645 return 0; 646 } 647 648 static int rzt2h_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 649 unsigned int group, 650 unsigned long *config) 651 { 652 unsigned long prev_config = 0; 653 const unsigned int *pins; 654 unsigned int i, npins; 655 int ret; 656 657 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 658 if (ret) 659 return ret; 660 661 for (i = 0; i < npins; i++) { 662 ret = rzt2h_pinctrl_pinconf_get(pctldev, pins[i], config); 663 if (ret) 664 return ret; 665 666 /* Check config matches previous pins */ 667 if (i && prev_config != *config) 668 return -ENOTSUPP; 669 670 prev_config = *config; 671 } 672 673 return 0; 674 } 675 676 static int rzt2h_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 677 unsigned int group, 678 unsigned long *configs, 679 unsigned int num_configs) 680 { 681 const unsigned int *pins; 682 unsigned int i, npins; 683 int ret; 684 685 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 686 if (ret) 687 return ret; 688 689 for (i = 0; i < npins; i++) { 690 ret = rzt2h_pinctrl_pinconf_set(pctldev, pins[i], configs, 691 num_configs); 692 if (ret) 693 return ret; 694 } 695 696 return 0; 697 } 698 699 static const struct pinctrl_ops rzt2h_pinctrl_pctlops = { 700 .get_groups_count = pinctrl_generic_get_group_count, 701 .get_group_name = pinctrl_generic_get_group_name, 702 .get_group_pins = pinctrl_generic_get_group_pins, 703 .dt_node_to_map = rzt2h_dt_node_to_map, 704 .dt_free_map = rzt2h_dt_free_map, 705 }; 706 707 static const struct pinmux_ops rzt2h_pinctrl_pmxops = { 708 .get_functions_count = pinmux_generic_get_function_count, 709 .get_function_name = pinmux_generic_get_function_name, 710 .get_function_groups = pinmux_generic_get_function_groups, 711 .set_mux = rzt2h_pinctrl_set_mux, 712 .strict = true, 713 }; 714 715 static const struct pinconf_ops rzt2h_pinctrl_confops = { 716 .is_generic = true, 717 .pin_config_get = rzt2h_pinctrl_pinconf_get, 718 .pin_config_set = rzt2h_pinctrl_pinconf_set, 719 .pin_config_group_set = rzt2h_pinctrl_pinconf_group_set, 720 .pin_config_group_get = rzt2h_pinctrl_pinconf_group_get, 721 .pin_config_config_dbg_show = pinconf_generic_dump_config, 722 }; 723 724 static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset) 725 { 726 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 727 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 728 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 729 int ret; 730 731 ret = rzt2h_validate_pin(pctrl, offset); 732 if (ret) 733 return ret; 734 735 ret = pinctrl_gpio_request(chip, offset); 736 if (ret) 737 return ret; 738 739 guard(raw_spinlock_irqsave)(&pctrl->lock); 740 741 /* Select GPIO mode in PMC Register */ 742 rzt2h_pinctrl_set_gpio_en(pctrl, port, bit, true); 743 744 return 0; 745 } 746 747 static void rzt2h_gpio_set_direction(struct rzt2h_pinctrl *pctrl, u32 port, 748 u8 bit, bool output) 749 { 750 u16 reg; 751 752 guard(raw_spinlock_irqsave)(&pctrl->lock); 753 754 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 755 reg &= ~PM_PIN_MASK(bit); 756 757 reg |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 758 rzt2h_pinctrl_writew(pctrl, port, reg, PM(port)); 759 } 760 761 static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 762 { 763 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 764 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 765 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 766 u64 reg64; 767 u16 reg; 768 int ret; 769 770 ret = rzt2h_validate_pin(pctrl, offset); 771 if (ret) 772 return ret; 773 774 guard(raw_spinlock_irqsave)(&pctrl->lock); 775 776 if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) { 777 /* 778 * When a GPIO is being requested as an IRQ, the pinctrl 779 * framework expects to be able to read the GPIO's direction. 780 * IRQ function is separate from GPIO, and enabling it takes the 781 * pin out of GPIO mode. 782 * At this point, .child_to_parent_hwirq() has already been 783 * called to enable the IRQ function. 784 * Default to input direction for IRQ function. 785 */ 786 reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); 787 reg64 = (reg64 >> (bit * 8)) & PFC_MASK; 788 if (reg64 == PFC_FUNC_INTERRUPT) 789 return GPIO_LINE_DIRECTION_IN; 790 791 return -EINVAL; 792 } 793 794 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 795 reg = (reg >> (bit * 2)) & PM_MASK; 796 if (reg & PM_OUTPUT) 797 return GPIO_LINE_DIRECTION_OUT; 798 if (reg & PM_INPUT) 799 return GPIO_LINE_DIRECTION_IN; 800 801 return -EINVAL; 802 } 803 804 static int rzt2h_gpio_set(struct gpio_chip *chip, unsigned int offset, 805 int value) 806 { 807 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 808 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 809 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 810 u8 reg; 811 812 guard(raw_spinlock_irqsave)(&pctrl->lock); 813 814 reg = rzt2h_pinctrl_readb(pctrl, port, P(port)); 815 if (value) 816 rzt2h_pinctrl_writeb(pctrl, port, reg | BIT(bit), P(port)); 817 else 818 rzt2h_pinctrl_writeb(pctrl, port, reg & ~BIT(bit), P(port)); 819 820 return 0; 821 } 822 823 static int rzt2h_gpio_get(struct gpio_chip *chip, unsigned int offset) 824 { 825 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 826 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 827 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 828 u16 reg; 829 830 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 831 reg = (reg >> (bit * 2)) & PM_MASK; 832 if (reg & PM_INPUT) 833 return !!(rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit)); 834 if (reg & PM_OUTPUT) 835 return !!(rzt2h_pinctrl_readb(pctrl, port, P(port)) & BIT(bit)); 836 837 return -EINVAL; 838 } 839 840 static int rzt2h_gpio_direction_input(struct gpio_chip *chip, 841 unsigned int offset) 842 { 843 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 844 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 845 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 846 847 rzt2h_gpio_set_direction(pctrl, port, bit, false); 848 849 return 0; 850 } 851 852 static int rzt2h_gpio_direction_output(struct gpio_chip *chip, 853 unsigned int offset, int value) 854 { 855 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 856 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 857 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 858 859 rzt2h_gpio_set(chip, offset, value); 860 rzt2h_gpio_set_direction(pctrl, port, bit, true); 861 862 return 0; 863 } 864 865 static void rzt2h_gpio_free(struct gpio_chip *chip, unsigned int offset) 866 { 867 pinctrl_gpio_free(chip, offset); 868 869 /* 870 * Set the GPIO as an input to ensure that the next GPIO request won't 871 * drive the GPIO pin as an output. 872 */ 873 rzt2h_gpio_direction_input(chip, offset); 874 } 875 876 static const char * const rzt2h_gpio_names[] = { 877 "P00_0", "P00_1", "P00_2", "P00_3", "P00_4", "P00_5", "P00_6", "P00_7", 878 "P01_0", "P01_1", "P01_2", "P01_3", "P01_4", "P01_5", "P01_6", "P01_7", 879 "P02_0", "P02_1", "P02_2", "P02_3", "P02_4", "P02_5", "P02_6", "P02_7", 880 "P03_0", "P03_1", "P03_2", "P03_3", "P03_4", "P03_5", "P03_6", "P03_7", 881 "P04_0", "P04_1", "P04_2", "P04_3", "P04_4", "P04_5", "P04_6", "P04_7", 882 "P05_0", "P05_1", "P05_2", "P05_3", "P05_4", "P05_5", "P05_6", "P05_7", 883 "P06_0", "P06_1", "P06_2", "P06_3", "P06_4", "P06_5", "P06_6", "P06_7", 884 "P07_0", "P07_1", "P07_2", "P07_3", "P07_4", "P07_5", "P07_6", "P07_7", 885 "P08_0", "P08_1", "P08_2", "P08_3", "P08_4", "P08_5", "P08_6", "P08_7", 886 "P09_0", "P09_1", "P09_2", "P09_3", "P09_4", "P09_5", "P09_6", "P09_7", 887 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 888 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 889 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 890 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 891 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 892 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 893 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 894 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 895 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 896 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 897 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 898 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 899 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 900 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 901 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 902 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 903 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 904 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 905 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 906 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 907 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 908 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 909 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 910 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 911 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 912 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 913 }; 914 915 /* 916 * Interrupts 0-15 are for INTCPUn, which are not exposed externally. 917 * Interrupts 16-31 are for IRQn. SEI is 32. 918 * This table matches the information found in User Manual's Section 919 * 17.5, Multiplexed Pin Configurations, Tables 17.5 to 17.40, on the 920 * Interrupt rows. 921 * RZ/N2H has the same GPIO to IRQ mapping, except for the pins which 922 * are not present. 923 */ 924 static const u8 rzt2h_gpio_irq_map[] = { 925 32, 16, 17, 18, 19, 0, 20, 21, 926 22, 0, 0, 0, 0, 0, 0, 0, 927 23, 24, 25, 26, 27, 0, 0, 0, 928 0, 0, 28, 29, 30, 31, 0, 0, 929 0, 0, 0, 0, 0, 32, 16, 17, 930 18, 19, 20, 21, 22, 0, 0, 0, 931 0, 0, 24, 25, 26, 27, 0, 28, 932 29, 30, 31, 0, 0, 0, 0, 0, 933 0, 0, 0, 0, 0, 24, 32, 16, 934 0, 0, 0, 0, 0, 0, 0, 0, 935 20, 23, 17, 18, 19, 0, 16, 25, 936 29, 20, 21, 22, 23, 0, 0, 0, 937 0, 0, 0, 0, 17, 0, 0, 18, 938 0, 0, 19, 0, 0, 20, 0, 30, 939 21, 0, 0, 22, 0, 0, 24, 25, 940 0, 0, 0, 0, 0, 16, 17, 0, 941 18, 0, 0, 26, 27, 0, 0, 0, 942 28, 29, 30, 31, 0, 0, 0, 0, 943 23, 31, 32, 16, 17, 18, 19, 20, 944 0, 0, 0, 0, 0, 0, 0, 0, 945 0, 0, 0, 0, 0, 0, 0, 0, 946 0, 0, 0, 0, 0, 0, 0, 0, 947 27, 0, 0, 21, 22, 23, 24, 25, 948 26, 0, 0, 0, 0, 0, 0, 0, 949 27, 28, 29, 30, 31, 0, 0, 0, 950 0, 0, 0, 0, 0, 0, 0, 0, 951 0, 0, 0, 0, 0, 28, 32, 16, 952 17, 18, 19, 0, 0, 0, 0, 20, 953 21, 22, 23, 0, 0, 0, 0, 0, 954 0, 0, 0, 0, 24, 25, 0, 0, 955 0, 0, 26, 27, 0, 0, 0, 30, 956 0, 29, 0, 0, 0, 0, 0, 0, 957 0, 0, 0, 0, 0, 0, 0, 0, 958 0, 0, 0, 28, 29, 30, 31, 0, 959 0, 0, 0, 0, 0, 0, 0, 30, 960 0, 0, 0, 0, 0, 0, 0, 0, 961 }; 962 963 static void rzt2h_gpio_irq_disable(struct irq_data *d) 964 { 965 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 966 unsigned int hwirq = irqd_to_hwirq(d); 967 968 irq_chip_disable_parent(d); 969 gpiochip_disable_irq(gc, hwirq); 970 } 971 972 static void rzt2h_gpio_irq_enable(struct irq_data *d) 973 { 974 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 975 unsigned int hwirq = irqd_to_hwirq(d); 976 977 gpiochip_enable_irq(gc, hwirq); 978 irq_chip_enable_parent(d); 979 } 980 981 static int rzt2h_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 982 { 983 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 984 struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip); 985 int ret; 986 987 ret = irq_chip_set_wake_parent(d, on); 988 if (ret) 989 return ret; 990 991 /* 992 * If any of the IRQs are in use, put the entire pin controller on the 993 * device wakeup path. 994 */ 995 if (on) 996 atomic_inc(&pctrl->wakeup_path); 997 else 998 atomic_dec(&pctrl->wakeup_path); 999 1000 return 0; 1001 } 1002 1003 static const struct irq_chip rzt2h_gpio_irqchip = { 1004 .name = "rzt2h-gpio", 1005 .irq_disable = rzt2h_gpio_irq_disable, 1006 .irq_enable = rzt2h_gpio_irq_enable, 1007 .irq_mask = irq_chip_mask_parent, 1008 .irq_unmask = irq_chip_unmask_parent, 1009 .irq_set_type = irq_chip_set_type_parent, 1010 .irq_set_wake = rzt2h_gpio_irq_set_wake, 1011 .irq_eoi = irq_chip_eoi_parent, 1012 .irq_set_affinity = irq_chip_set_affinity_parent, 1013 .flags = IRQCHIP_IMMUTABLE, 1014 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1015 }; 1016 1017 static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 1018 unsigned int child, 1019 unsigned int child_type, 1020 unsigned int *parent, 1021 unsigned int *parent_type) 1022 { 1023 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc); 1024 u8 port = RZT2H_PIN_ID_TO_PORT(child); 1025 u8 pin = RZT2H_PIN_ID_TO_PIN(child); 1026 u8 parent_irq; 1027 1028 parent_irq = rzt2h_gpio_irq_map[child]; 1029 if (parent_irq < RZT2H_INTERRUPTS_START) 1030 return -EINVAL; 1031 1032 if (test_and_set_bit(parent_irq - RZT2H_INTERRUPTS_START, 1033 pctrl->used_irqs)) 1034 return -EBUSY; 1035 1036 rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT); 1037 1038 *parent = parent_irq; 1039 *parent_type = child_type; 1040 1041 return 0; 1042 } 1043 1044 static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1045 unsigned int nr_irqs) 1046 { 1047 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 1048 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1049 struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip); 1050 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1051 u8 port = RZT2H_PIN_ID_TO_PORT(hwirq); 1052 u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq); 1053 1054 if (test_and_clear_bit(hwirq - RZT2H_INTERRUPTS_START, pctrl->used_irqs)) 1055 rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); 1056 1057 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1058 } 1059 1060 static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc, 1061 unsigned long *valid_mask, 1062 unsigned int ngpios) 1063 { 1064 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc); 1065 unsigned int offset; 1066 1067 for (offset = 0; offset < ngpios; offset++) { 1068 if (!rzt2h_gpio_irq_map[offset] || rzt2h_validate_pin(pctrl, offset)) 1069 clear_bit(offset, valid_mask); 1070 } 1071 } 1072 1073 static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) 1074 { 1075 struct pinctrl_gpio_range *range = &pctrl->gpio_range; 1076 struct gpio_chip *chip = &pctrl->gpio_chip; 1077 struct device_node *np = pctrl->dev->of_node; 1078 struct irq_domain *parent_domain; 1079 struct device *dev = pctrl->dev; 1080 struct of_phandle_args of_args; 1081 struct device_node *parent_np; 1082 struct gpio_irq_chip *girq; 1083 int ret; 1084 1085 parent_np = of_irq_find_parent(np); 1086 if (!parent_np) 1087 return -ENXIO; 1088 1089 parent_domain = irq_find_host(parent_np); 1090 of_node_put(parent_np); 1091 if (!parent_domain) 1092 return -EPROBE_DEFER; 1093 1094 ret = of_parse_phandle_with_fixed_args(dev->of_node, "gpio-ranges", 3, 0, &of_args); 1095 if (ret) 1096 return dev_err_probe(dev, ret, "Unable to parse gpio-ranges\n"); 1097 1098 of_node_put(of_args.np); 1099 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 1100 of_args.args[2] != pctrl->data->n_port_pins) 1101 return dev_err_probe(dev, -EINVAL, 1102 "gpio-ranges does not match selected SOC\n"); 1103 1104 chip->base = -1; 1105 chip->parent = dev; 1106 chip->owner = THIS_MODULE; 1107 chip->ngpio = of_args.args[2]; 1108 chip->names = rzt2h_gpio_names; 1109 chip->request = rzt2h_gpio_request; 1110 chip->free = rzt2h_gpio_free; 1111 chip->get_direction = rzt2h_gpio_get_direction; 1112 chip->direction_input = rzt2h_gpio_direction_input; 1113 chip->direction_output = rzt2h_gpio_direction_output; 1114 chip->get = rzt2h_gpio_get; 1115 chip->set = rzt2h_gpio_set; 1116 chip->label = dev_name(dev); 1117 1118 if (of_property_present(np, "interrupt-controller")) { 1119 girq = &chip->irq; 1120 gpio_irq_chip_set_chip(girq, &rzt2h_gpio_irqchip); 1121 girq->fwnode = dev_fwnode(pctrl->dev); 1122 girq->parent_domain = parent_domain; 1123 girq->child_to_parent_hwirq = rzt2h_gpio_child_to_parent_hwirq; 1124 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; 1125 girq->child_irq_domain_ops.free = rzt2h_gpio_irq_domain_free; 1126 girq->init_valid_mask = rzt2h_gpio_init_irq_valid_mask; 1127 } 1128 1129 range->id = 0; 1130 range->pin_base = 0; 1131 range->base = 0; 1132 range->npins = chip->ngpio; 1133 range->name = chip->label; 1134 range->gc = chip; 1135 1136 ret = devm_gpiochip_add_data(dev, chip, pctrl); 1137 if (ret) 1138 return dev_err_probe(dev, ret, "gpiochip registration failed\n"); 1139 1140 return ret; 1141 } 1142 1143 static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl) 1144 { 1145 struct pinctrl_desc *desc = &pctrl->desc; 1146 struct device *dev = pctrl->dev; 1147 struct pinctrl_pin_desc *pins; 1148 unsigned int i; 1149 int ret; 1150 1151 desc->name = DRV_NAME; 1152 desc->npins = pctrl->data->n_port_pins; 1153 desc->pctlops = &rzt2h_pinctrl_pctlops; 1154 desc->pmxops = &rzt2h_pinctrl_pmxops; 1155 desc->confops = &rzt2h_pinctrl_confops; 1156 desc->owner = THIS_MODULE; 1157 1158 pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL); 1159 if (!pins) 1160 return -ENOMEM; 1161 1162 pctrl->pins = pins; 1163 desc->pins = pins; 1164 1165 for (i = 0; i < pctrl->data->n_port_pins; i++) { 1166 pins[i].number = i; 1167 pins[i].name = rzt2h_gpio_names[i]; 1168 } 1169 1170 ret = devm_pinctrl_register_and_init(dev, desc, pctrl, &pctrl->pctl); 1171 if (ret) 1172 return dev_err_probe(dev, ret, "pinctrl registration failed\n"); 1173 1174 ret = pinctrl_enable(pctrl->pctl); 1175 if (ret) 1176 return dev_err_probe(dev, ret, "pinctrl enable failed\n"); 1177 1178 return rzt2h_gpio_register(pctrl); 1179 } 1180 1181 static int rzt2h_pinctrl_cfg_regions(struct platform_device *pdev, 1182 struct rzt2h_pinctrl *pctrl) 1183 { 1184 struct resource *res; 1185 1186 pctrl->base0 = devm_platform_ioremap_resource_byname(pdev, "nsr"); 1187 if (IS_ERR(pctrl->base0)) 1188 return PTR_ERR(pctrl->base0); 1189 1190 /* 1191 * Open-coded instead of using devm_platform_ioremap_resource_byname() 1192 * because the "srs" region is optional. 1193 */ 1194 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "srs"); 1195 if (res) { 1196 u8 port; 1197 1198 pctrl->base1 = devm_ioremap_resource(&pdev->dev, res); 1199 if (IS_ERR(pctrl->base1)) 1200 return PTR_ERR(pctrl->base1); 1201 1202 pctrl->safety_port_enabled = true; 1203 1204 /* Configure to select safety region 0x812c0xxx */ 1205 for (port = 0; port <= RZT2H_MAX_SAFETY_PORTS; port++) 1206 writeb(0x0, pctrl->base1 + RSELP(port)); 1207 } 1208 1209 return 0; 1210 } 1211 1212 static int rzt2h_pinctrl_probe(struct platform_device *pdev) 1213 { 1214 struct device *dev = &pdev->dev; 1215 struct rzt2h_pinctrl *pctrl; 1216 int ret; 1217 1218 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1219 if (!pctrl) 1220 return -ENOMEM; 1221 1222 pctrl->dev = dev; 1223 pctrl->data = of_device_get_match_data(dev); 1224 1225 ret = rzt2h_pinctrl_cfg_regions(pdev, pctrl); 1226 if (ret) 1227 return ret; 1228 1229 raw_spin_lock_init(&pctrl->lock); 1230 mutex_init(&pctrl->mutex); 1231 platform_set_drvdata(pdev, pctrl); 1232 1233 return rzt2h_pinctrl_register(pctrl); 1234 } 1235 1236 static const u8 r9a09g077_gpio_configs[] = { 1237 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 1238 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 1239 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 1240 }; 1241 1242 static const u8 r9a09g087_gpio_configs[] = { 1243 0x1f, 0xff, 0xff, 0x1f, 0x00, 0xfe, 0xff, 0x00, 0x7e, 0xf0, 0xff, 0x01, 1244 0xff, 0xff, 0xff, 0x00, 0xe0, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x01, 1245 0xe0, 0xff, 0xff, 0x7f, 0x00, 0xfe, 0xff, 0x7f, 0x00, 0xfc, 0x7f, 1246 }; 1247 1248 static struct rzt2h_pinctrl_data r9a09g077_data = { 1249 .n_port_pins = ARRAY_SIZE(r9a09g077_gpio_configs) * RZT2H_PINS_PER_PORT, 1250 .port_pin_configs = r9a09g077_gpio_configs, 1251 .n_ports = ARRAY_SIZE(r9a09g077_gpio_configs), 1252 }; 1253 1254 static struct rzt2h_pinctrl_data r9a09g087_data = { 1255 .n_port_pins = ARRAY_SIZE(r9a09g087_gpio_configs) * RZT2H_PINS_PER_PORT, 1256 .port_pin_configs = r9a09g087_gpio_configs, 1257 .n_ports = ARRAY_SIZE(r9a09g087_gpio_configs), 1258 }; 1259 1260 static const struct of_device_id rzt2h_pinctrl_of_table[] = { 1261 { 1262 .compatible = "renesas,r9a09g077-pinctrl", 1263 .data = &r9a09g077_data, 1264 }, 1265 { 1266 .compatible = "renesas,r9a09g087-pinctrl", 1267 .data = &r9a09g087_data, 1268 }, 1269 { /* sentinel */ } 1270 }; 1271 1272 static int rzt2h_pinctrl_suspend_noirq(struct device *dev) 1273 { 1274 struct rzt2h_pinctrl *pctrl = dev_get_drvdata(dev); 1275 1276 if (atomic_read(&pctrl->wakeup_path)) 1277 device_set_wakeup_path(dev); 1278 1279 return 0; 1280 } 1281 1282 static const struct dev_pm_ops rzt2h_pinctrl_pm_ops = { 1283 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzt2h_pinctrl_suspend_noirq, NULL) 1284 }; 1285 1286 static struct platform_driver rzt2h_pinctrl_driver = { 1287 .driver = { 1288 .name = DRV_NAME, 1289 .of_match_table = of_match_ptr(rzt2h_pinctrl_of_table), 1290 .pm = pm_sleep_ptr(&rzt2h_pinctrl_pm_ops), 1291 .suppress_bind_attrs = true, 1292 }, 1293 .probe = rzt2h_pinctrl_probe, 1294 }; 1295 1296 static int __init rzt2h_pinctrl_init(void) 1297 { 1298 return platform_driver_register(&rzt2h_pinctrl_driver); 1299 } 1300 core_initcall(rzt2h_pinctrl_init); 1301 1302 MODULE_LICENSE("GPL"); 1303 MODULE_AUTHOR("Thierry Bultel <thierry.bultel.yh@bp.renesas.com>"); 1304 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 1305 MODULE_DESCRIPTION("Pin and gpio controller driver for the RZ/T2H family"); 1306