| /linux/include/linux/soc/pxa/ |
| H A D | cpu.h | 59 #define __cpu_is_pxa210(id) \ argument
65 #define __cpu_is_pxa250(id) \ argument
71 #define __cpu_is_pxa255(id) \ argument
77 #define __cpu_is_pxa25x(id) \ argument
83 #define __cpu_is_pxa210(id) (0) argument
84 #define __cpu_is_pxa250(id) (0) argument
85 #define __cpu_is_pxa255(id) (0) argument
86 #define __cpu_is_pxa25x(id) (0) argument
90 #define __cpu_is_pxa27x(id) \ argument
96 #define __cpu_is_pxa27x(id) (0) argument
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| /linux/tools/power/x86/intel-speed-select/ |
| H A D | isst-core.c | 64 int isst_is_punit_valid(struct isst_id *id) in isst_is_punit_valid()
107 int isst_read_pm_config(struct isst_id *id, int *cp_state, int *cp_cap) in isst_read_pm_config()
113 int isst_get_ctdp_levels(struct isst_id *id, struct isst_pkg_ctdp *pkg_dev) in isst_get_ctdp_levels()
119 int isst_get_ctdp_control(struct isst_id *id, int config_index, in isst_get_ctdp_control()
126 int isst_get_tdp_info(struct isst_id *id, int config_index, in isst_get_tdp_info()
133 int isst_get_pwr_info(struct isst_id *id, int config_index, in isst_get_pwr_info()
140 int isst_get_coremask_info(struct isst_id *id, int config_index, in isst_get_coremask_info()
147 int isst_get_get_trl_from_msr(struct isst_id *id, int *trl) in isst_get_get_trl_from_msr()
168 int isst_get_get_trl(struct isst_id *id, int level, int avx_level, int *trl) in isst_get_get_trl()
174 int isst_get_get_trls(struct isst_id *id, int level, struct isst_pkg_ctdp_level_info *ctdp_level) in isst_get_get_trls()
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| H A D | isst-core-tpmi.c | 115 static int tpmi_is_punit_valid(struct isst_id *id) in tpmi_is_punit_valid()
134 static int tpmi_read_pm_config(struct isst_id *id, int *cp_state, int *cp_cap) in tpmi_read_pm_config()
152 int tpmi_get_config_levels(struct isst_id *id, struct isst_pkg_ctdp *pkg_dev) in tpmi_get_config_levels()
174 static int tpmi_get_ctdp_control(struct isst_id *id, int config_index, in tpmi_get_ctdp_control()
227 static int tpmi_get_tdp_info(struct isst_id *id, int config_index, in tpmi_get_tdp_info()
276 static int tpmi_get_pwr_info(struct isst_id *id, int config_index, in tpmi_get_pwr_info()
291 int tpmi_get_coremask_info(struct isst_id *id, int config_index, in tpmi_get_coremask_info()
317 static int tpmi_get_get_trls(struct isst_id *id, int config_index, in tpmi_get_get_trls()
344 static int tpmi_get_get_trl(struct isst_id *id, int config_index, int level, in tpmi_get_get_trl()
361 static int tpmi_get_trl_bucket_info(struct isst_id *id, int config_index, in tpmi_get_trl_bucket_info()
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| H A D | isst-core-mbox.c | 64 static int mbox_is_punit_valid(struct isst_id *id) in mbox_is_punit_valid()
219 static int mbox_read_pm_config(struct isst_id *id, int *cp_state, int *cp_cap) in mbox_read_pm_config()
237 static int mbox_get_config_levels(struct isst_id *id, struct isst_pkg_ctdp *pkg_dev) in mbox_get_config_levels()
264 static int mbox_get_ctdp_control(struct isst_id *id, int config_index, in mbox_get_ctdp_control()
299 static void _get_uncore_p0_p1_info(struct isst_id *id, int config_index, in _get_uncore_p0_p1_info()
345 static int _set_uncore_min_max(struct isst_id *id, int max, int freq) in _set_uncore_min_max()
373 static void mbox_adjust_uncore_freq(struct isst_id *id, int config_index, in mbox_adjust_uncore_freq()
384 static void _get_p1_info(struct isst_id *id, int config_index, in _get_p1_info()
408 static void _get_uncore_mem_freq(struct isst_id *id, int config_index, in _get_uncore_mem_freq()
441 static int mbox_get_tdp_info(struct isst_id *id, int config_index, in mbox_get_tdp_info()
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| /linux/drivers/clk/rockchip/ |
| H A D | rst-rv1126b.c | 13 #define TOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x0 * 4 + reg * 16 + bit) argument
15 #define BUSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + reg * 16 + bit) argument
17 #define PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + reg * 16 + bit) argument
19 #define CORECRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000 * 4 + reg * 16 + bit) argument
21 #define PMUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x40000 * 4 + reg * 16 + bit) argument
23 #define PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x50000 * 4 + reg * 16 + bit) argument
25 #define DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x60000 * 4 + reg * 16 + bit) argument
27 #define SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x68000 * 4 + reg * 16 + bit) argument
29 #define VICRU_RESET_OFFSET(id, reg, bit) [id] = (0x70000 * 4 + reg * 16 + bit) argument
31 #define VEPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x80000 * 4 + reg * 16 + bit) argument
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| /linux/sound/soc/tegra/ |
| H A D | tegra186_asrc.c | 23 #define ASRC_STREAM_SOURCE_SELECT(id) \ argument
26 #define ASRC_STREAM_REG(reg, id) ((reg) + ((id) * TEGRA186_ASRC_STREAM_STRIDE)) argument
28 #define ASRC_STREAM_REG_DEFAULTS(id) \ argument
70 tegra186_asrc_lock_stream(struct tegra186_asrc * asrc,unsigned int id) tegra186_asrc_lock_stream() argument
91 int id; tegra186_asrc_runtime_resume() local
167 int ret, id = dai->id; tegra186_asrc_in_hw_params() local
190 int ret, id = dai->id - 7; tegra186_asrc_out_hw_params() local
246 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_get_ratio_source() local
260 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_put_ratio_source() local
280 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_get_ratio_int() local
298 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_put_ratio_int() local
328 unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_get_ratio_frac() local
346 unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_put_ratio_frac() local
376 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_get_hwcomp_disable() local
390 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_put_hwcomp_disable() local
408 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_get_input_threshold() local
422 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_put_input_threshold() local
441 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_get_output_threshold() local
455 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; tegra186_asrc_put_output_threshold() local
472 unsigned int id = tegra186_asrc_widget_event() local
490 IN_DAI(id) global() argument
516 OUT_DAI(id) global() argument
608 ASRC_STREAM_ROUTE(id,sname) global() argument
617 ASRC_ROUTE(id) global() argument
643 ASRC_SOURCE_DECL(name,id) global() argument
[all...] |
| /linux/drivers/media/platform/samsung/s3c-camif/ |
| H A D | camif-regs.h | 65 #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id)) argument
71 #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) argument
73 #define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4) argument
75 #define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4) argument
78 #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) argument
98 #define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs))) argument
111 #define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs))) argument
114 #define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs))) argument
117 #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) argument
147 #define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs))) argument
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| /linux/drivers/reset/ |
| H A D | reset-uniphier.c | 15 unsigned int id; member
157 #define UNIPHIER_MIO_RESET_SD(id, ch) \ argument
160 #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \ argument
163 #define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \ argument
166 #define UNIPHIER_MIO_RESET_USB2(id, ch) \ argument
169 #define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \ argument
172 #define UNIPHIER_MIO_RESET_DMAC(id) \ argument
201 #define UNIPHIER_PERI_RESET_UART(id, ch) \ argument
204 #define UNIPHIER_PERI_RESET_I2C(id, ch) \ argument
207 #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 120 #define SR_ARR(reg_name, id)\ argument
123 #define SR_ARR_INIT(reg_name, id, value)\ argument
126 #define SRI(reg_name, block, id)\ argument
130 #define SRI_ARR(reg_name, block, id)\ argument
134 #define SR_ARR_I2C(reg_name, id) \ argument
137 #define SRI_ARR_I2C(reg_name, block, id)\ argument
141 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
145 #define SRI2(reg_name, block, id)\ argument
148 #define SRI2_ARR(reg_name, block, id)\ argument
152 #define SRIR(var_name, reg_name, block, id)\ argument
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| /linux/drivers/gpu/host1x/hw/ |
| H A D | hw_host1x02_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| H A D | hw_host1x01_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| H A D | hw_host1x05_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| H A D | hw_host1x04_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| /linux/fs/smb/server/mgmt/ |
| H A D | user_session.c | 29 int id; member
87 unsigned long id; in show_proc_session() local
205 unsigned long id; in show_proc_sessions() local
319 int method, id; in ksmbd_session_rpc_open() local
358 void ksmbd_session_rpc_close(struct ksmbd_session *sess, int id) in ksmbd_session_rpc_close()
369 int ksmbd_session_rpc_method(struct ksmbd_session *sess, int id) in ksmbd_session_rpc_method()
399 struct ksmbd_session *__session_lookup(unsigned long long id) in __session_lookup()
414 unsigned long id; in ksmbd_expire_session() local
460 unsigned long id; in ksmbd_sessions_deregister() local
503 unsigned long long id) in is_ksmbd_session_in_connection()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 120 #define SR_ARR(reg_name, id) \ argument
123 #define SR_ARR_INIT(reg_name, id, value) \ argument
126 #define SRI(reg_name, block, id)\ argument
130 #define SRI_ARR(reg_name, block, id)\ argument
134 #define SR_ARR_I2C(reg_name, id) \ argument
137 #define SRI_ARR_I2C(reg_name, block, id)\ argument
141 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
145 #define SRI2(reg_name, block, id)\ argument
149 #define SRI2_ARR(reg_name, block, id)\ argument
153 #define SRIR(var_name, reg_name, block, id)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 135 #define SR_ARR(reg_name, id) \ argument
138 #define SR_ARR_INIT(reg_name, id, value) \ argument
141 #define SRI(reg_name, block, id)\ argument
145 #define SRI_ARR(reg_name, block, id)\ argument
149 #define SR_ARR_I2C(reg_name, id) \ argument
152 #define SRI_ARR_I2C(reg_name, block, id)\ argument
156 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
160 #define SRI2(reg_name, block, id)\ argument
164 #define SRI2_ARR(reg_name, block, id)\ argument
168 #define SRIR(var_name, reg_name, block, id)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 115 #define SR_ARR(reg_name, id) \ argument
118 #define SR_ARR_INIT(reg_name, id, value) \ argument
121 #define SRI(reg_name, block, id)\ argument
125 #define SRI_ARR(reg_name, block, id)\ argument
129 #define SR_ARR_I2C(reg_name, id) \ argument
132 #define SRI_ARR_I2C(reg_name, block, id)\ argument
136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
140 #define SRI2(reg_name, block, id)\ argument
144 #define SRI2_ARR(reg_name, block, id)\ argument
148 #define SRIR(var_name, reg_name, block, id)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 102 #define SR_ARR(reg_name, id)\ argument
105 #define SR_ARR_INIT(reg_name, id, value)\ argument
108 #define SRI(reg_name, block, id)\ argument
112 #define SRI_ARR(reg_name, block, id)\ argument
119 #define SRI_ARR_US(reg_name, block, id)\ argument
122 #define SR_ARR_I2C(reg_name, id) \ argument
125 #define SRI_ARR_I2C(reg_name, block, id)\ argument
129 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
133 #define SRI2(reg_name, block, id)\ argument
136 #define SRI2_ARR(reg_name, block, id)\ argument
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| /linux/include/linux/ |
| H A D | reset.h | 25 const char *id; member
157 const char *id, int index, enum reset_control_flags flags) in __of_reset_control_get()
165 struct device *dev, const char *id, in __reset_control_get()
218 struct device *dev, const char *id, in __devm_reset_control_get()
285 __must_check reset_control_get_exclusive(struct device *dev, const char *id) in reset_control_get_exclusive()
323 const char *id) in reset_control_get_exclusive_released()
394 struct device *dev, const char *id) in reset_control_get_shared()
428 struct device *dev, const char *id) in reset_control_get_optional_exclusive()
465 struct device *dev, const char *id) in reset_control_get_optional_shared()
501 struct device_node *node, const char *id) in of_reset_control_get_exclusive()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/ |
| H A D | gpio_service.c | 131 enum gpio_id id = 0; in dal_gpio_service_create_irq() local
147 enum gpio_id id = 0; in dal_gpio_service_create_generic_mux() local
178 enum gpio_id id, in dal_gpio_get_generic_pin_info()
239 enum gpio_id id, in is_pin_busy()
250 enum gpio_id id, in set_pin_busy()
261 enum gpio_id id, in set_pin_free()
272 enum gpio_id id, in dal_gpio_service_lock()
286 enum gpio_id id, in dal_gpio_service_unlock()
302 enum gpio_id id = gpio->id; in dal_gpio_service_open() local
386 enum gpio_id id = dal_gpio_get_id(irq); in dal_irq_get_source() local
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 181 #define SRI(reg_name, block, id)\ argument
184 #define SRI2(reg_name, block, id)\ argument
187 #define SRII(reg_name, block, id)\ argument
191 #define DCCG_SRII(reg_name, block, id)\ argument
195 #define VUPDATE_SRII(reg_name, block, id)\ argument
199 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
203 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
206 #define SRII_MPC_RMU(reg_name, block, id)\ argument
222 #define vmid_regs(id)\ argument
276 #define vpg_regs(id)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 185 #define SRI(reg_name, block, id)\ argument
188 #define SRI2(reg_name, block, id)\ argument
191 #define SRII(reg_name, block, id)\ argument
195 #define DCCG_SRII(reg_name, block, id)\ argument
199 #define VUPDATE_SRII(reg_name, block, id)\ argument
203 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
207 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
210 #define SRII_MPC_RMU(reg_name, block, id)\ argument
226 #define vmid_regs(id)\ argument
280 #define vpg_regs(id)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 152 #define SRI(reg_name, block, id)\ argument
156 #define SRI2(reg_name, block, id)\ argument
160 #define SRIR(var_name, reg_name, block, id)\ argument
164 #define SRII(reg_name, block, id)\ argument
168 #define SRII_MPC_RMU(reg_name, block, id)\ argument
172 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
176 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
179 #define DCCG_SRII(reg_name, block, id)\ argument
183 #define VUPDATE_SRII(reg_name, block, id)\ argument
224 #define abm_regs(id)\ argument
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| /linux/drivers/net/ethernet/intel/fm10k/ |
| H A D | fm10k_tlv.h | 62 unsigned int id; member
67 #define FM10K_TLV_ATTR_NULL_STRING(id, len) { id, FM10K_TLV_NULL_STRING, len } argument
68 #define FM10K_TLV_ATTR_MAC_ADDR(id) { id, FM10K_TLV_MAC_ADDR, 6 } argument
69 #define FM10K_TLV_ATTR_BOOL(id) { id, FM10K_TLV_BOOL, 0 } argument
70 #define FM10K_TLV_ATTR_U8(id) { id, FM10K_TLV_UNSIGNED, 1 } argument
71 #define FM10K_TLV_ATTR_U16(id) { id, FM10K_TLV_UNSIGNED, 2 } argument
72 #define FM10K_TLV_ATTR_U32(id) { id, FM10K_TLV_UNSIGNED, 4 } argument
73 #define FM10K_TLV_ATTR_U64(id) { id, FM10K_TLV_UNSIGNED, 8 } argument
74 #define FM10K_TLV_ATTR_S8(id) { id, FM10K_TLV_SIGNED, 1 } argument
75 #define FM10K_TLV_ATTR_S16(id) { id, FM10K_TLV_SIGNED, 2 } argument
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| /linux/drivers/i2c/busses/ |
| H A D | i2c-cadence.c | 243 static void cdns_i2c_init(struct cdns_i2c *id) in cdns_i2c_init()
302 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) in cdns_i2c_clear_bus_hold()
309 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) in cdns_is_holdquirk()
316 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) in cdns_i2c_set_mode()
359 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) in cdns_i2c_slave_rcv_data()
380 static void cdns_i2c_slave_send_data(struct cdns_i2c *id) in cdns_i2c_slave_send_data()
407 struct cdns_i2c *id = ptr; in cdns_i2c_slave_isr() local
468 struct cdns_i2c *id = ptr; in cdns_i2c_master_isr() local
621 struct cdns_i2c *id = ptr; in cdns_i2c_isr() local
629 static bool cdns_i2c_error_check(struct cdns_i2c *id) in cdns_i2c_error_check()
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