1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2021, Intel Corporation. */
3
4 #include <linux/delay.h>
5 #include <linux/iopoll.h>
6 #include "ice_common.h"
7 #include "ice_ptp_hw.h"
8 #include "ice_ptp_consts.h"
9 #include "ice_cgu_regs.h"
10
11 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = {
12 DPLL_PIN_FREQUENCY_1PPS,
13 DPLL_PIN_FREQUENCY_10MHZ,
14 };
15
16 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = {
17 DPLL_PIN_FREQUENCY_1PPS,
18 };
19
20 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = {
21 DPLL_PIN_FREQUENCY_10MHZ,
22 };
23
24 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
31 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
32 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
33 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
34 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
36 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
37 };
38
39 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, },
47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, },
48 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
49 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
50 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
51 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
53 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
54 };
55
56 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {
57 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
58 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
59 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
60 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
61 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
62 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
63 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
64 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
65 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
66 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
67 };
68
69 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {
70 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
71 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
72 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
73 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
74 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
75 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
76 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
77 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
78 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
79 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
80 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
81 };
82
83 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {
84 { "NONE", SI_REF0P, 0, 0 },
85 { "NONE", SI_REF0N, 0, 0 },
86 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 },
87 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 },
88 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT,
89 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
90 { "NONE", SI_REF2N, 0, 0 },
91 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT,
92 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
93 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT,
94 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
95 };
96
97 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = {
98 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
99 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
100 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
101 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
102 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
103 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
104 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
105 };
106
107 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = {
108 { "NONE", ZL_REF0P, 0, 0 },
109 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT,
110 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
111 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 },
112 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 },
113 { "NONE", ZL_REF2P, 0, 0 },
114 { "NONE", ZL_REF2N, 0, 0 },
115 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT,
116 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
117 { "NONE", ZL_REF3N, 0, 0 },
118 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT,
119 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
120 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 },
121 };
122
123 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = {
124 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
125 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
126 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
127 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
128 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
129 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
130 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
131 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
132 { "NONE", ZL_OUT5, 0, 0 },
133 };
134
135 /* Low level functions for interacting with and managing the device clock used
136 * for the Precision Time Protocol.
137 *
138 * The ice hardware represents the current time using three registers:
139 *
140 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R
141 * +---------------+ +---------------+ +---------------+
142 * | 32 bits | | 32 bits | | 32 bits |
143 * +---------------+ +---------------+ +---------------+
144 *
145 * The registers are incremented every clock tick using a 40bit increment
146 * value defined over two registers:
147 *
148 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L
149 * +---------------+ +---------------+
150 * | 8 bit s | | 32 bits |
151 * +---------------+ +---------------+
152 *
153 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L
154 * registers every clock source tick. Depending on the specific device
155 * configuration, the clock source frequency could be one of a number of
156 * values.
157 *
158 * For E810 devices, the increment frequency is 812.5 MHz
159 *
160 * For E822 devices the clock can be derived from different sources, and the
161 * increment has an effective frequency of one of the following:
162 * - 823.4375 MHz
163 * - 783.36 MHz
164 * - 796.875 MHz
165 * - 816 MHz
166 * - 830.078125 MHz
167 * - 783.36 MHz
168 *
169 * The hardware captures timestamps in the PHY for incoming packets, and for
170 * outgoing packets on request. To support this, the PHY maintains a timer
171 * that matches the lower 64 bits of the global source timer.
172 *
173 * In order to ensure that the PHY timers and the source timer are equivalent,
174 * shadow registers are used to prepare the desired initial values. A special
175 * sync command is issued to trigger copying from the shadow registers into
176 * the appropriate source and PHY registers simultaneously.
177 *
178 * The driver supports devices which have different PHYs with subtly different
179 * mechanisms to program and control the timers. We divide the devices into
180 * families named after the first major device, E810 and similar devices, and
181 * E822 and similar devices.
182 *
183 * - E822 based devices have additional support for fine grained Vernier
184 * calibration which requires significant setup
185 * - The layout of timestamp data in the PHY register blocks is different
186 * - The way timer synchronization commands are issued is different.
187 *
188 * To support this, very low level functions have an e810 or e822 suffix
189 * indicating what type of device they work on. Higher level abstractions for
190 * tasks that can be done on both devices do not have the suffix and will
191 * correctly look up the appropriate low level function when running.
192 *
193 * Functions which only make sense on a single device family may not have
194 * a suitable generic implementation
195 */
196
197 /**
198 * ice_get_ptp_src_clock_index - determine source clock index
199 * @hw: pointer to HW struct
200 *
201 * Determine the source clock index currently in use, based on device
202 * capabilities reported during initialization.
203 */
ice_get_ptp_src_clock_index(struct ice_hw * hw)204 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw)
205 {
206 return hw->func_caps.ts_func_info.tmr_index_assoc;
207 }
208
209 /**
210 * ice_ptp_read_src_incval - Read source timer increment value
211 * @hw: pointer to HW struct
212 *
213 * Read the increment value of the source timer and return it.
214 */
ice_ptp_read_src_incval(struct ice_hw * hw)215 static u64 ice_ptp_read_src_incval(struct ice_hw *hw)
216 {
217 u32 lo, hi;
218 u8 tmr_idx;
219
220 tmr_idx = ice_get_ptp_src_clock_index(hw);
221
222 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
223 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
224
225 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
226 }
227
228 /**
229 * ice_read_cgu_reg_e82x - Read a CGU register
230 * @hw: pointer to the HW struct
231 * @addr: Register address to read
232 * @val: storage for register value read
233 *
234 * Read the contents of a register of the Clock Generation Unit. Only
235 * applicable to E822 devices.
236 *
237 * Return: 0 on success, other error codes when failed to read from CGU
238 */
ice_read_cgu_reg_e82x(struct ice_hw * hw,u32 addr,u32 * val)239 static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
240 {
241 struct ice_sbq_msg_input cgu_msg = {
242 .opcode = ice_sbq_msg_rd,
243 .dest_dev = cgu,
244 .msg_addr_low = addr
245 };
246 int err;
247
248 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD);
249 if (err) {
250 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
251 addr, err);
252 return err;
253 }
254
255 *val = cgu_msg.data;
256
257 return 0;
258 }
259
260 /**
261 * ice_write_cgu_reg_e82x - Write a CGU register
262 * @hw: pointer to the HW struct
263 * @addr: Register address to write
264 * @val: value to write into the register
265 *
266 * Write the specified value to a register of the Clock Generation Unit. Only
267 * applicable to E822 devices.
268 *
269 * Return: 0 on success, other error codes when failed to write to CGU
270 */
ice_write_cgu_reg_e82x(struct ice_hw * hw,u32 addr,u32 val)271 static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)
272 {
273 struct ice_sbq_msg_input cgu_msg = {
274 .opcode = ice_sbq_msg_wr,
275 .dest_dev = cgu,
276 .msg_addr_low = addr,
277 .data = val
278 };
279 int err;
280
281 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD);
282 if (err) {
283 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
284 addr, err);
285 return err;
286 }
287
288 return err;
289 }
290
291 /**
292 * ice_clk_freq_str - Convert time_ref_freq to string
293 * @clk_freq: Clock frequency
294 *
295 * Return: specified TIME_REF clock frequency converted to a string
296 */
ice_clk_freq_str(enum ice_time_ref_freq clk_freq)297 static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq)
298 {
299 switch (clk_freq) {
300 case ICE_TIME_REF_FREQ_25_000:
301 return "25 MHz";
302 case ICE_TIME_REF_FREQ_122_880:
303 return "122.88 MHz";
304 case ICE_TIME_REF_FREQ_125_000:
305 return "125 MHz";
306 case ICE_TIME_REF_FREQ_153_600:
307 return "153.6 MHz";
308 case ICE_TIME_REF_FREQ_156_250:
309 return "156.25 MHz";
310 case ICE_TIME_REF_FREQ_245_760:
311 return "245.76 MHz";
312 default:
313 return "Unknown";
314 }
315 }
316
317 /**
318 * ice_clk_src_str - Convert time_ref_src to string
319 * @clk_src: Clock source
320 *
321 * Return: specified clock source converted to its string name
322 */
ice_clk_src_str(enum ice_clk_src clk_src)323 static const char *ice_clk_src_str(enum ice_clk_src clk_src)
324 {
325 switch (clk_src) {
326 case ICE_CLK_SRC_TCXO:
327 return "TCXO";
328 case ICE_CLK_SRC_TIME_REF:
329 return "TIME_REF";
330 default:
331 return "Unknown";
332 }
333 }
334
335 /**
336 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
337 * @hw: pointer to the HW struct
338 * @clk_freq: Clock frequency to program
339 * @clk_src: Clock source to select (TIME_REF, or TCXO)
340 *
341 * Configure the Clock Generation Unit with the desired clock frequency and
342 * time reference, enabling the PLL which drives the PTP hardware clock.
343 *
344 * Return:
345 * * %0 - success
346 * * %-EINVAL - input parameters are incorrect
347 * * %-EBUSY - failed to lock TS PLL
348 * * %other - CGU read/write failure
349 */
ice_cfg_cgu_pll_e82x(struct ice_hw * hw,enum ice_time_ref_freq clk_freq,enum ice_clk_src clk_src)350 static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
351 enum ice_time_ref_freq clk_freq,
352 enum ice_clk_src clk_src)
353 {
354 union tspll_ro_bwm_lf bwm_lf;
355 union nac_cgu_dword19 dw19;
356 union nac_cgu_dword22 dw22;
357 union nac_cgu_dword24 dw24;
358 union nac_cgu_dword9 dw9;
359 int err;
360
361 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
362 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
363 clk_freq);
364 return -EINVAL;
365 }
366
367 if (clk_src >= NUM_ICE_CLK_SRC) {
368 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
369 clk_src);
370 return -EINVAL;
371 }
372
373 if (clk_src == ICE_CLK_SRC_TCXO &&
374 clk_freq != ICE_TIME_REF_FREQ_25_000) {
375 dev_warn(ice_hw_to_dev(hw),
376 "TCXO only supports 25 MHz frequency\n");
377 return -EINVAL;
378 }
379
380 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
381 if (err)
382 return err;
383
384 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
385 if (err)
386 return err;
387
388 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
389 if (err)
390 return err;
391
392 /* Log the current clock configuration */
393 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
394 dw24.ts_pll_enable ? "enabled" : "disabled",
395 ice_clk_src_str(dw24.time_ref_sel),
396 ice_clk_freq_str(dw9.time_ref_freq_sel),
397 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
398
399 /* Disable the PLL before changing the clock source or frequency */
400 if (dw24.ts_pll_enable) {
401 dw24.ts_pll_enable = 0;
402
403 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
404 if (err)
405 return err;
406 }
407
408 /* Set the frequency */
409 dw9.time_ref_freq_sel = clk_freq;
410 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
411 if (err)
412 return err;
413
414 /* Configure the TS PLL feedback divisor */
415 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
416 if (err)
417 return err;
418
419 dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
420 dw19.tspll_ndivratio = 1;
421
422 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
423 if (err)
424 return err;
425
426 /* Configure the TS PLL post divisor */
427 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
428 if (err)
429 return err;
430
431 dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
432 dw22.time1588clk_sel_div2 = 0;
433
434 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
435 if (err)
436 return err;
437
438 /* Configure the TS PLL pre divisor and clock source */
439 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
440 if (err)
441 return err;
442
443 dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
444 dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
445 dw24.time_ref_sel = clk_src;
446
447 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
448 if (err)
449 return err;
450
451 /* Finally, enable the PLL */
452 dw24.ts_pll_enable = 1;
453
454 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
455 if (err)
456 return err;
457
458 /* Wait to verify if the PLL locks */
459 usleep_range(1000, 5000);
460
461 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
462 if (err)
463 return err;
464
465 if (!bwm_lf.plllock_true_lock_cri) {
466 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
467 return -EBUSY;
468 }
469
470 /* Log the current clock configuration */
471 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
472 dw24.ts_pll_enable ? "enabled" : "disabled",
473 ice_clk_src_str(dw24.time_ref_sel),
474 ice_clk_freq_str(dw9.time_ref_freq_sel),
475 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
476
477 return 0;
478 }
479
480 /**
481 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C
482 * @hw: pointer to the HW struct
483 * @clk_freq: Clock frequency to program
484 * @clk_src: Clock source to select (TIME_REF, or TCXO)
485 *
486 * Configure the Clock Generation Unit with the desired clock frequency and
487 * time reference, enabling the PLL which drives the PTP hardware clock.
488 *
489 * Return:
490 * * %0 - success
491 * * %-EINVAL - input parameters are incorrect
492 * * %-EBUSY - failed to lock TS PLL
493 * * %other - CGU read/write failure
494 */
ice_cfg_cgu_pll_e825c(struct ice_hw * hw,enum ice_time_ref_freq clk_freq,enum ice_clk_src clk_src)495 static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
496 enum ice_time_ref_freq clk_freq,
497 enum ice_clk_src clk_src)
498 {
499 union tspll_ro_lock_e825c ro_lock;
500 union nac_cgu_dword16_e825c dw16;
501 union nac_cgu_dword23_e825c dw23;
502 union nac_cgu_dword19 dw19;
503 union nac_cgu_dword22 dw22;
504 union nac_cgu_dword24 dw24;
505 union nac_cgu_dword9 dw9;
506 int err;
507
508 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
509 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
510 clk_freq);
511 return -EINVAL;
512 }
513
514 if (clk_src >= NUM_ICE_CLK_SRC) {
515 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
516 clk_src);
517 return -EINVAL;
518 }
519
520 if (clk_src == ICE_CLK_SRC_TCXO &&
521 clk_freq != ICE_TIME_REF_FREQ_156_250) {
522 dev_warn(ice_hw_to_dev(hw),
523 "TCXO only supports 156.25 MHz frequency\n");
524 return -EINVAL;
525 }
526
527 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
528 if (err)
529 return err;
530
531 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
532 if (err)
533 return err;
534
535 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val);
536 if (err)
537 return err;
538
539 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
540 if (err)
541 return err;
542
543 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
544 if (err)
545 return err;
546
547 /* Log the current clock configuration */
548 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
549 dw24.ts_pll_enable ? "enabled" : "disabled",
550 ice_clk_src_str(dw23.time_ref_sel),
551 ice_clk_freq_str(dw9.time_ref_freq_sel),
552 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
553
554 /* Disable the PLL before changing the clock source or frequency */
555 if (dw23.ts_pll_enable) {
556 dw23.ts_pll_enable = 0;
557
558 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C,
559 dw23.val);
560 if (err)
561 return err;
562 }
563
564 /* Set the frequency */
565 dw9.time_ref_freq_sel = clk_freq;
566
567 /* Enable the correct receiver */
568 if (clk_src == ICE_CLK_SRC_TCXO) {
569 dw9.time_ref_en = 0;
570 dw9.clk_eref0_en = 1;
571 } else {
572 dw9.time_ref_en = 1;
573 dw9.clk_eref0_en = 0;
574 }
575 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
576 if (err)
577 return err;
578
579 /* Choose the referenced frequency */
580 dw16.tspll_ck_refclkfreq =
581 e825c_cgu_params[clk_freq].tspll_ck_refclkfreq;
582 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val);
583 if (err)
584 return err;
585
586 /* Configure the TS PLL feedback divisor */
587 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
588 if (err)
589 return err;
590
591 dw19.tspll_fbdiv_intgr =
592 e825c_cgu_params[clk_freq].tspll_fbdiv_intgr;
593 dw19.tspll_ndivratio =
594 e825c_cgu_params[clk_freq].tspll_ndivratio;
595
596 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
597 if (err)
598 return err;
599
600 /* Configure the TS PLL post divisor */
601 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
602 if (err)
603 return err;
604
605 /* These two are constant for E825C */
606 dw22.time1588clk_div = 5;
607 dw22.time1588clk_sel_div2 = 0;
608
609 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
610 if (err)
611 return err;
612
613 /* Configure the TS PLL pre divisor and clock source */
614 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
615 if (err)
616 return err;
617
618 dw23.ref1588_ck_div =
619 e825c_cgu_params[clk_freq].ref1588_ck_div;
620 dw23.time_ref_sel = clk_src;
621
622 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
623 if (err)
624 return err;
625
626 dw24.tspll_fbdiv_frac =
627 e825c_cgu_params[clk_freq].tspll_fbdiv_frac;
628
629 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
630 if (err)
631 return err;
632
633 /* Finally, enable the PLL */
634 dw23.ts_pll_enable = 1;
635
636 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
637 if (err)
638 return err;
639
640 /* Wait to verify if the PLL locks */
641 usleep_range(1000, 5000);
642
643 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
644 if (err)
645 return err;
646
647 if (!ro_lock.plllock_true_lock_cri) {
648 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
649 return -EBUSY;
650 }
651
652 /* Log the current clock configuration */
653 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
654 dw24.ts_pll_enable ? "enabled" : "disabled",
655 ice_clk_src_str(dw23.time_ref_sel),
656 ice_clk_freq_str(dw9.time_ref_freq_sel),
657 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
658
659 return 0;
660 }
661
662 #define ICE_ONE_PPS_OUT_AMP_MAX 3
663
664 /**
665 * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU
666 * @hw: pointer to the HW struct
667 * @enable: true to enable 1PPS output, false to disable it
668 *
669 * Return: 0 on success, other negative error code when CGU read/write failed
670 */
ice_cgu_cfg_pps_out(struct ice_hw * hw,bool enable)671 int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable)
672 {
673 union nac_cgu_dword9 dw9;
674 int err;
675
676 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
677 if (err)
678 return err;
679
680 dw9.one_pps_out_en = enable;
681 dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
682 return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
683 }
684
685 /**
686 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits
687 * @hw: pointer to the HW struct
688 *
689 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
690 * losing TS PLL lock, but always show current state.
691 *
692 * Return: 0 on success, other error codes when failed to read/write CGU
693 */
ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw * hw)694 static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw)
695 {
696 union tspll_cntr_bist_settings cntr_bist;
697 int err;
698
699 err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
700 &cntr_bist.val);
701 if (err)
702 return err;
703
704 /* Disable sticky lock detection so lock err reported is accurate */
705 cntr_bist.i_plllock_sel_0 = 0;
706 cntr_bist.i_plllock_sel_1 = 0;
707
708 return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
709 cntr_bist.val);
710 }
711
712 /**
713 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C
714 * @hw: pointer to the HW struct
715 *
716 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
717 * losing TS PLL lock, but always show current state.
718 *
719 * Return: 0 on success, other error codes when failed to read/write CGU
720 */
ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw * hw)721 static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw)
722 {
723 union tspll_bw_tdc_e825c bw_tdc;
724 int err;
725
726 err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
727 if (err)
728 return err;
729
730 bw_tdc.i_plllock_sel_1_0 = 0;
731
732 return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
733 }
734
735 /**
736 * ice_init_cgu_e82x - Initialize CGU with settings from firmware
737 * @hw: pointer to the HW structure
738 *
739 * Initialize the Clock Generation Unit of the E822 device.
740 *
741 * Return: 0 on success, other error codes when failed to read/write/cfg CGU
742 */
ice_init_cgu_e82x(struct ice_hw * hw)743 static int ice_init_cgu_e82x(struct ice_hw *hw)
744 {
745 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
746 int err;
747
748 /* Disable sticky lock detection so lock err reported is accurate */
749 if (ice_is_e825c(hw))
750 err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw);
751 else
752 err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw);
753 if (err)
754 return err;
755
756 /* Configure the CGU PLL using the parameters from the function
757 * capabilities.
758 */
759 if (ice_is_e825c(hw))
760 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref,
761 (enum ice_clk_src)ts_info->clk_src);
762 else
763 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref,
764 (enum ice_clk_src)ts_info->clk_src);
765
766 return err;
767 }
768
769 /**
770 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value
771 * @hw: pointer to HW struct
772 * @cmd: Timer command
773 *
774 * Return: the source timer command register value for the given PTP timer
775 * command.
776 */
ice_ptp_tmr_cmd_to_src_reg(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)777 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw,
778 enum ice_ptp_tmr_cmd cmd)
779 {
780 u32 cmd_val, tmr_idx;
781
782 switch (cmd) {
783 case ICE_PTP_INIT_TIME:
784 cmd_val = GLTSYN_CMD_INIT_TIME;
785 break;
786 case ICE_PTP_INIT_INCVAL:
787 cmd_val = GLTSYN_CMD_INIT_INCVAL;
788 break;
789 case ICE_PTP_ADJ_TIME:
790 cmd_val = GLTSYN_CMD_ADJ_TIME;
791 break;
792 case ICE_PTP_ADJ_TIME_AT_TIME:
793 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
794 break;
795 case ICE_PTP_NOP:
796 case ICE_PTP_READ_TIME:
797 cmd_val = GLTSYN_CMD_READ_TIME;
798 break;
799 default:
800 dev_warn(ice_hw_to_dev(hw),
801 "Ignoring unrecognized timer command %u\n", cmd);
802 cmd_val = 0;
803 }
804
805 tmr_idx = ice_get_ptp_src_clock_index(hw);
806
807 return tmr_idx << SEL_CPK_SRC | cmd_val;
808 }
809
810 /**
811 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value
812 * @hw: pointer to HW struct
813 * @cmd: Timer command
814 *
815 * Note that some hardware families use a different command register value for
816 * the PHY ports, while other hardware families use the same register values
817 * as the source timer.
818 *
819 * Return: the PHY port timer command register value for the given PTP timer
820 * command.
821 */
ice_ptp_tmr_cmd_to_port_reg(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)822 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw,
823 enum ice_ptp_tmr_cmd cmd)
824 {
825 u32 cmd_val, tmr_idx;
826
827 /* Certain hardware families share the same register values for the
828 * port register and source timer register.
829 */
830 switch (ice_get_phy_model(hw)) {
831 case ICE_PHY_E810:
832 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810;
833 default:
834 break;
835 }
836
837 switch (cmd) {
838 case ICE_PTP_INIT_TIME:
839 cmd_val = PHY_CMD_INIT_TIME;
840 break;
841 case ICE_PTP_INIT_INCVAL:
842 cmd_val = PHY_CMD_INIT_INCVAL;
843 break;
844 case ICE_PTP_ADJ_TIME:
845 cmd_val = PHY_CMD_ADJ_TIME;
846 break;
847 case ICE_PTP_ADJ_TIME_AT_TIME:
848 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME;
849 break;
850 case ICE_PTP_READ_TIME:
851 cmd_val = PHY_CMD_READ_TIME;
852 break;
853 case ICE_PTP_NOP:
854 cmd_val = 0;
855 break;
856 default:
857 dev_warn(ice_hw_to_dev(hw),
858 "Ignoring unrecognized timer command %u\n", cmd);
859 cmd_val = 0;
860 }
861
862 tmr_idx = ice_get_ptp_src_clock_index(hw);
863
864 return tmr_idx << SEL_PHY_SRC | cmd_val;
865 }
866
867 /**
868 * ice_ptp_src_cmd - Prepare source timer for a timer command
869 * @hw: pointer to HW structure
870 * @cmd: Timer command
871 *
872 * Prepare the source timer for an upcoming timer sync command.
873 */
ice_ptp_src_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)874 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
875 {
876 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd);
877
878 wr32(hw, GLTSYN_CMD, cmd_val);
879 }
880
881 /**
882 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
883 * @hw: pointer to HW struct
884 *
885 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
886 * write immediately. This triggers the hardware to begin executing all of the
887 * source and PHY timer commands synchronously.
888 */
ice_ptp_exec_tmr_cmd(struct ice_hw * hw)889 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
890 {
891 struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
892
893 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock);
894 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
895 ice_flush(hw);
896 }
897
898 /* 56G PHY device functions
899 *
900 * The following functions operate on devices with the ETH 56G PHY.
901 */
902
903 /**
904 * ice_write_phy_eth56g - Write a PHY port register
905 * @hw: pointer to the HW struct
906 * @phy_idx: PHY index
907 * @addr: PHY register address
908 * @val: Value to write
909 *
910 * Return: 0 on success, other error codes when failed to write to PHY
911 */
ice_write_phy_eth56g(struct ice_hw * hw,u8 phy_idx,u32 addr,u32 val)912 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
913 u32 val)
914 {
915 struct ice_sbq_msg_input phy_msg;
916 int err;
917
918 phy_msg.opcode = ice_sbq_msg_wr;
919
920 phy_msg.msg_addr_low = lower_16_bits(addr);
921 phy_msg.msg_addr_high = upper_16_bits(addr);
922
923 phy_msg.data = val;
924 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx];
925
926 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD);
927
928 if (err)
929 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
930 err);
931
932 return err;
933 }
934
935 /**
936 * ice_read_phy_eth56g - Read a PHY port register
937 * @hw: pointer to the HW struct
938 * @phy_idx: PHY index
939 * @addr: PHY register address
940 * @val: Value to write
941 *
942 * Return: 0 on success, other error codes when failed to read from PHY
943 */
ice_read_phy_eth56g(struct ice_hw * hw,u8 phy_idx,u32 addr,u32 * val)944 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
945 u32 *val)
946 {
947 struct ice_sbq_msg_input phy_msg;
948 int err;
949
950 phy_msg.opcode = ice_sbq_msg_rd;
951
952 phy_msg.msg_addr_low = lower_16_bits(addr);
953 phy_msg.msg_addr_high = upper_16_bits(addr);
954
955 phy_msg.data = 0;
956 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx];
957
958 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD);
959 if (err) {
960 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
961 err);
962 return err;
963 }
964
965 *val = phy_msg.data;
966
967 return 0;
968 }
969
970 /**
971 * ice_phy_res_address_eth56g - Calculate a PHY port register address
972 * @port: Port number to be written
973 * @res_type: resource type (register/memory)
974 * @offset: Offset from PHY port register base
975 * @addr: The result address
976 *
977 * Return:
978 * * %0 - success
979 * * %EINVAL - invalid port number or resource type
980 */
ice_phy_res_address_eth56g(u8 port,enum eth56g_res_type res_type,u32 offset,u32 * addr)981 static int ice_phy_res_address_eth56g(u8 port, enum eth56g_res_type res_type,
982 u32 offset, u32 *addr)
983 {
984 u8 lane = port % ICE_PORTS_PER_QUAD;
985 u8 phy = ICE_GET_QUAD_NUM(port);
986
987 if (res_type >= NUM_ETH56G_PHY_RES)
988 return -EINVAL;
989
990 *addr = eth56g_phy_res[res_type].base[phy] +
991 lane * eth56g_phy_res[res_type].step + offset;
992 return 0;
993 }
994
995 /**
996 * ice_write_port_eth56g - Write a PHY port register
997 * @hw: pointer to the HW struct
998 * @offset: PHY register offset
999 * @port: Port number
1000 * @val: Value to write
1001 * @res_type: resource type (register/memory)
1002 *
1003 * Return:
1004 * * %0 - success
1005 * * %EINVAL - invalid port number or resource type
1006 * * %other - failed to write to PHY
1007 */
ice_write_port_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val,enum eth56g_res_type res_type)1008 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1009 u32 val, enum eth56g_res_type res_type)
1010 {
1011 u8 phy_port = port % hw->ptp.ports_per_phy;
1012 u8 phy_idx = port / hw->ptp.ports_per_phy;
1013 u32 addr;
1014 int err;
1015
1016 if (port >= hw->ptp.num_lports)
1017 return -EINVAL;
1018
1019 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr);
1020 if (err)
1021 return err;
1022
1023 return ice_write_phy_eth56g(hw, phy_idx, addr, val);
1024 }
1025
1026 /**
1027 * ice_read_port_eth56g - Read a PHY port register
1028 * @hw: pointer to the HW struct
1029 * @offset: PHY register offset
1030 * @port: Port number
1031 * @val: Value to write
1032 * @res_type: resource type (register/memory)
1033 *
1034 * Return:
1035 * * %0 - success
1036 * * %EINVAL - invalid port number or resource type
1037 * * %other - failed to read from PHY
1038 */
ice_read_port_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 * val,enum eth56g_res_type res_type)1039 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1040 u32 *val, enum eth56g_res_type res_type)
1041 {
1042 u8 phy_port = port % hw->ptp.ports_per_phy;
1043 u8 phy_idx = port / hw->ptp.ports_per_phy;
1044 u32 addr;
1045 int err;
1046
1047 if (port >= hw->ptp.num_lports)
1048 return -EINVAL;
1049
1050 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr);
1051 if (err)
1052 return err;
1053
1054 return ice_read_phy_eth56g(hw, phy_idx, addr, val);
1055 }
1056
1057 /**
1058 * ice_write_ptp_reg_eth56g - Write a PHY port register
1059 * @hw: pointer to the HW struct
1060 * @port: Port number to be written
1061 * @offset: Offset from PHY port register base
1062 * @val: Value to write
1063 *
1064 * Return:
1065 * * %0 - success
1066 * * %EINVAL - invalid port number or resource type
1067 * * %other - failed to write to PHY
1068 */
ice_write_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 val)1069 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1070 u32 val)
1071 {
1072 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
1073 }
1074
1075 /**
1076 * ice_write_mac_reg_eth56g - Write a MAC PHY port register
1077 * parameter
1078 * @hw: pointer to the HW struct
1079 * @port: Port number to be written
1080 * @offset: Offset from PHY port register base
1081 * @val: Value to write
1082 *
1083 * Return:
1084 * * %0 - success
1085 * * %EINVAL - invalid port number or resource type
1086 * * %other - failed to write to PHY
1087 */
ice_write_mac_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)1088 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1089 u32 val)
1090 {
1091 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
1092 }
1093
1094 /**
1095 * ice_write_xpcs_reg_eth56g - Write a PHY port register
1096 * @hw: pointer to the HW struct
1097 * @port: Port number to be written
1098 * @offset: Offset from PHY port register base
1099 * @val: Value to write
1100 *
1101 * Return:
1102 * * %0 - success
1103 * * %EINVAL - invalid port number or resource type
1104 * * %other - failed to write to PHY
1105 */
ice_write_xpcs_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)1106 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1107 u32 val)
1108 {
1109 return ice_write_port_eth56g(hw, port, offset, val,
1110 ETH56G_PHY_REG_XPCS);
1111 }
1112
1113 /**
1114 * ice_read_ptp_reg_eth56g - Read a PHY port register
1115 * @hw: pointer to the HW struct
1116 * @port: Port number to be read
1117 * @offset: Offset from PHY port register base
1118 * @val: Pointer to the value to read (out param)
1119 *
1120 * Return:
1121 * * %0 - success
1122 * * %EINVAL - invalid port number or resource type
1123 * * %other - failed to read from PHY
1124 */
ice_read_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1125 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1126 u32 *val)
1127 {
1128 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
1129 }
1130
1131 /**
1132 * ice_read_mac_reg_eth56g - Read a PHY port register
1133 * @hw: pointer to the HW struct
1134 * @port: Port number to be read
1135 * @offset: Offset from PHY port register base
1136 * @val: Pointer to the value to read (out param)
1137 *
1138 * Return:
1139 * * %0 - success
1140 * * %EINVAL - invalid port number or resource type
1141 * * %other - failed to read from PHY
1142 */
ice_read_mac_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1143 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1144 u32 *val)
1145 {
1146 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
1147 }
1148
1149 /**
1150 * ice_read_gpcs_reg_eth56g - Read a PHY port register
1151 * @hw: pointer to the HW struct
1152 * @port: Port number to be read
1153 * @offset: Offset from PHY port register base
1154 * @val: Pointer to the value to read (out param)
1155 *
1156 * Return:
1157 * * %0 - success
1158 * * %EINVAL - invalid port number or resource type
1159 * * %other - failed to read from PHY
1160 */
ice_read_gpcs_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1161 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1162 u32 *val)
1163 {
1164 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS);
1165 }
1166
1167 /**
1168 * ice_read_port_mem_eth56g - Read a PHY port memory location
1169 * @hw: pointer to the HW struct
1170 * @port: Port number to be read
1171 * @offset: Offset from PHY port register base
1172 * @val: Pointer to the value to read (out param)
1173 *
1174 * Return:
1175 * * %0 - success
1176 * * %EINVAL - invalid port number or resource type
1177 * * %other - failed to read from PHY
1178 */
ice_read_port_mem_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1179 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1180 u32 *val)
1181 {
1182 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
1183 }
1184
1185 /**
1186 * ice_write_port_mem_eth56g - Write a PHY port memory location
1187 * @hw: pointer to the HW struct
1188 * @port: Port number to be read
1189 * @offset: Offset from PHY port register base
1190 * @val: Pointer to the value to read (out param)
1191 *
1192 * Return:
1193 * * %0 - success
1194 * * %EINVAL - invalid port number or resource type
1195 * * %other - failed to write to PHY
1196 */
ice_write_port_mem_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 val)1197 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1198 u32 val)
1199 {
1200 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
1201 }
1202
1203 /**
1204 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
1205 * @low_addr: the low address to check
1206 * @high_addr: on return, contains the high address of the 64bit register
1207 *
1208 * Write the appropriate high register offset to use.
1209 *
1210 * Return: true if the provided low address is one of the known 64bit PHY values
1211 * represented as two 32bit registers, false otherwise.
1212 */
ice_is_64b_phy_reg_eth56g(u16 low_addr,u16 * high_addr)1213 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
1214 {
1215 switch (low_addr) {
1216 case PHY_REG_TX_TIMER_INC_PRE_L:
1217 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U;
1218 return true;
1219 case PHY_REG_RX_TIMER_INC_PRE_L:
1220 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U;
1221 return true;
1222 case PHY_REG_TX_CAPTURE_L:
1223 *high_addr = PHY_REG_TX_CAPTURE_U;
1224 return true;
1225 case PHY_REG_RX_CAPTURE_L:
1226 *high_addr = PHY_REG_RX_CAPTURE_U;
1227 return true;
1228 case PHY_REG_TOTAL_TX_OFFSET_L:
1229 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U;
1230 return true;
1231 case PHY_REG_TOTAL_RX_OFFSET_L:
1232 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U;
1233 return true;
1234 case PHY_REG_TX_MEMORY_STATUS_L:
1235 *high_addr = PHY_REG_TX_MEMORY_STATUS_U;
1236 return true;
1237 default:
1238 return false;
1239 }
1240 }
1241
1242 /**
1243 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register
1244 * @low_addr: the low address to check
1245 * @high_addr: on return, contains the high address of the 40bit value
1246 *
1247 * Write the appropriate high register offset to use.
1248 *
1249 * Return: true if the provided low address is one of the known 40bit PHY
1250 * values split into two registers with the lower 8 bits in the low register and
1251 * the upper 32 bits in the high register, false otherwise.
1252 */
ice_is_40b_phy_reg_eth56g(u16 low_addr,u16 * high_addr)1253 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
1254 {
1255 switch (low_addr) {
1256 case PHY_REG_TIMETUS_L:
1257 *high_addr = PHY_REG_TIMETUS_U;
1258 return true;
1259 case PHY_PCS_REF_TUS_L:
1260 *high_addr = PHY_PCS_REF_TUS_U;
1261 return true;
1262 case PHY_PCS_REF_INC_L:
1263 *high_addr = PHY_PCS_REF_INC_U;
1264 return true;
1265 default:
1266 return false;
1267 }
1268 }
1269
1270 /**
1271 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers
1272 * @hw: pointer to the HW struct
1273 * @port: PHY port to read from
1274 * @low_addr: offset of the lower register to read from
1275 * @val: on return, the contents of the 64bit value from the PHY registers
1276 * @res_type: resource type
1277 *
1278 * Check if the caller has specified a known 40 bit register offset and read
1279 * the two registers associated with a 40bit value and return it in the val
1280 * pointer.
1281 *
1282 * Return:
1283 * * %0 - success
1284 * * %EINVAL - not a 64 bit register
1285 * * %other - failed to read from PHY
1286 */
ice_read_64b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val,enum eth56g_res_type res_type)1287 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
1288 u64 *val, enum eth56g_res_type res_type)
1289 {
1290 u16 high_addr;
1291 u32 lo, hi;
1292 int err;
1293
1294 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
1295 return -EINVAL;
1296
1297 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type);
1298 if (err) {
1299 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d",
1300 low_addr, err);
1301 return err;
1302 }
1303
1304 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type);
1305 if (err) {
1306 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d",
1307 high_addr, err);
1308 return err;
1309 }
1310
1311 *val = ((u64)hi << 32) | lo;
1312
1313 return 0;
1314 }
1315
1316 /**
1317 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers
1318 * @hw: pointer to the HW struct
1319 * @port: PHY port to read from
1320 * @low_addr: offset of the lower register to read from
1321 * @val: on return, the contents of the 64bit value from the PHY registers
1322 *
1323 * Check if the caller has specified a known 40 bit register offset and read
1324 * the two registers associated with a 40bit value and return it in the val
1325 * pointer.
1326 *
1327 * Return:
1328 * * %0 - success
1329 * * %EINVAL - not a 64 bit register
1330 * * %other - failed to read from PHY
1331 */
ice_read_64b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val)1332 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
1333 u64 *val)
1334 {
1335 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val,
1336 ETH56G_PHY_REG_PTP);
1337 }
1338
1339 /**
1340 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY
1341 * @hw: pointer to the HW struct
1342 * @port: port to write to
1343 * @low_addr: offset of the low register
1344 * @val: 40b value to write
1345 * @res_type: resource type
1346 *
1347 * Check if the caller has specified a known 40 bit register offset and write
1348 * provided 40b value to the two associated registers by splitting it up into
1349 * two chunks, the lower 8 bits and the upper 32 bits.
1350 *
1351 * Return:
1352 * * %0 - success
1353 * * %EINVAL - not a 40 bit register
1354 * * %other - failed to write to PHY
1355 */
ice_write_40b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val,enum eth56g_res_type res_type)1356 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
1357 u16 low_addr, u64 val,
1358 enum eth56g_res_type res_type)
1359 {
1360 u16 high_addr;
1361 u32 lo, hi;
1362 int err;
1363
1364 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr))
1365 return -EINVAL;
1366
1367 lo = FIELD_GET(P_REG_40B_LOW_M, val);
1368 hi = (u32)(val >> P_REG_40B_HIGH_S);
1369
1370 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
1371 if (err) {
1372 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
1373 low_addr, err);
1374 return err;
1375 }
1376
1377 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
1378 if (err) {
1379 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
1380 high_addr, err);
1381 return err;
1382 }
1383
1384 return 0;
1385 }
1386
1387 /**
1388 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY
1389 * @hw: pointer to the HW struct
1390 * @port: port to write to
1391 * @low_addr: offset of the low register
1392 * @val: 40b value to write
1393 *
1394 * Check if the caller has specified a known 40 bit register offset and write
1395 * provided 40b value to the two associated registers by splitting it up into
1396 * two chunks, the lower 8 bits and the upper 32 bits.
1397 *
1398 * Return:
1399 * * %0 - success
1400 * * %EINVAL - not a 40 bit register
1401 * * %other - failed to write to PHY
1402 */
ice_write_40b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)1403 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
1404 u16 low_addr, u64 val)
1405 {
1406 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val,
1407 ETH56G_PHY_REG_PTP);
1408 }
1409
1410 /**
1411 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers
1412 * @hw: pointer to the HW struct
1413 * @port: PHY port to read from
1414 * @low_addr: offset of the lower register to read from
1415 * @val: the contents of the 64bit value to write to PHY
1416 * @res_type: resource type
1417 *
1418 * Check if the caller has specified a known 64 bit register offset and write
1419 * the 64bit value to the two associated 32bit PHY registers.
1420 *
1421 * Return:
1422 * * %0 - success
1423 * * %EINVAL - not a 64 bit register
1424 * * %other - failed to write to PHY
1425 */
ice_write_64b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val,enum eth56g_res_type res_type)1426 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
1427 u16 low_addr, u64 val,
1428 enum eth56g_res_type res_type)
1429 {
1430 u16 high_addr;
1431 u32 lo, hi;
1432 int err;
1433
1434 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
1435 return -EINVAL;
1436
1437 lo = lower_32_bits(val);
1438 hi = upper_32_bits(val);
1439
1440 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
1441 if (err) {
1442 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
1443 low_addr, err);
1444 return err;
1445 }
1446
1447 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
1448 if (err) {
1449 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
1450 high_addr, err);
1451 return err;
1452 }
1453
1454 return 0;
1455 }
1456
1457 /**
1458 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers
1459 * @hw: pointer to the HW struct
1460 * @port: PHY port to read from
1461 * @low_addr: offset of the lower register to read from
1462 * @val: the contents of the 64bit value to write to PHY
1463 *
1464 * Check if the caller has specified a known 64 bit register offset and write
1465 * the 64bit value to the two associated 32bit PHY registers.
1466 *
1467 * Return:
1468 * * %0 - success
1469 * * %EINVAL - not a 64 bit register
1470 * * %other - failed to write to PHY
1471 */
ice_write_64b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)1472 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
1473 u16 low_addr, u64 val)
1474 {
1475 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val,
1476 ETH56G_PHY_REG_PTP);
1477 }
1478
1479 /**
1480 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory
1481 * @hw: pointer to the HW struct
1482 * @port: the port to read from
1483 * @idx: the timestamp index to read
1484 * @tstamp: on return, the 40bit timestamp value
1485 *
1486 * Read a 40bit timestamp value out of the two associated entries in the
1487 * port memory block of the internal PHYs of the 56G devices.
1488 *
1489 * Return:
1490 * * %0 - success
1491 * * %other - failed to read from PHY
1492 */
ice_read_ptp_tstamp_eth56g(struct ice_hw * hw,u8 port,u8 idx,u64 * tstamp)1493 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx,
1494 u64 *tstamp)
1495 {
1496 u16 lo_addr, hi_addr;
1497 u32 lo, hi;
1498 int err;
1499
1500 lo_addr = (u16)PHY_TSTAMP_L(idx);
1501 hi_addr = (u16)PHY_TSTAMP_U(idx);
1502
1503 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo);
1504 if (err) {
1505 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
1506 err);
1507 return err;
1508 }
1509
1510 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi);
1511 if (err) {
1512 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
1513 err);
1514 return err;
1515 }
1516
1517 /* For 56G based internal PHYs, the timestamp is reported with the
1518 * lower 8 bits in the low register, and the upper 32 bits in the high
1519 * register.
1520 */
1521 *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) |
1522 FIELD_PREP(TS_PHY_LOW_M, lo);
1523
1524 return 0;
1525 }
1526
1527 /**
1528 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block
1529 * @hw: pointer to the HW struct
1530 * @port: the quad to read from
1531 * @idx: the timestamp index to reset
1532 *
1533 * Read and then forcibly clear the timestamp index to ensure the valid bit is
1534 * cleared and the timestamp status bit is reset in the PHY port memory of
1535 * internal PHYs of the 56G devices.
1536 *
1537 * To directly clear the contents of the timestamp block entirely, discarding
1538 * all timestamp data at once, software should instead use
1539 * ice_ptp_reset_ts_memory_quad_eth56g().
1540 *
1541 * This function should only be called on an idx whose bit is set according to
1542 * ice_get_phy_tx_tstamp_ready().
1543 *
1544 * Return:
1545 * * %0 - success
1546 * * %other - failed to write to PHY
1547 */
ice_clear_ptp_tstamp_eth56g(struct ice_hw * hw,u8 port,u8 idx)1548 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx)
1549 {
1550 u64 unused_tstamp;
1551 u16 lo_addr;
1552 int err;
1553
1554 /* Read the timestamp register to ensure the timestamp status bit is
1555 * cleared.
1556 */
1557 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp);
1558 if (err) {
1559 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n",
1560 port, idx, err);
1561 }
1562
1563 lo_addr = (u16)PHY_TSTAMP_L(idx);
1564
1565 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0);
1566 if (err) {
1567 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n",
1568 port, idx, err);
1569 return err;
1570 }
1571
1572 return 0;
1573 }
1574
1575 /**
1576 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block
1577 * @hw: pointer to the HW struct
1578 */
ice_ptp_reset_ts_memory_eth56g(struct ice_hw * hw)1579 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw)
1580 {
1581 unsigned int port;
1582
1583 for (port = 0; port < hw->ptp.num_lports; port++) {
1584 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
1585 0);
1586 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U,
1587 0);
1588 }
1589 }
1590
1591 /**
1592 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time
1593 * @hw: pointer to the HW struct
1594 * @port: port number
1595 * @time: time to initialize the PHY port clocks to
1596 *
1597 * Write a new initial time value into registers of a specific PHY port.
1598 *
1599 * Return:
1600 * * %0 - success
1601 * * %other - failed to write to PHY
1602 */
ice_ptp_prep_port_time_eth56g(struct ice_hw * hw,u8 port,u64 time)1603 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port,
1604 u64 time)
1605 {
1606 int err;
1607
1608 /* Tx case */
1609 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
1610 time);
1611 if (err)
1612 return err;
1613
1614 /* Rx case */
1615 return ice_write_64b_ptp_reg_eth56g(hw, port,
1616 PHY_REG_RX_TIMER_INC_PRE_L, time);
1617 }
1618
1619 /**
1620 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time
1621 * @hw: pointer to the HW struct
1622 * @time: Time to initialize the PHY port clocks to
1623 *
1624 * Program the PHY port registers with a new initial time value. The port
1625 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
1626 * command. The time value is the upper 32 bits of the PHY timer, usually in
1627 * units of nominal nanoseconds.
1628 *
1629 * Return:
1630 * * %0 - success
1631 * * %other - failed to write to PHY
1632 */
ice_ptp_prep_phy_time_eth56g(struct ice_hw * hw,u32 time)1633 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time)
1634 {
1635 u64 phy_time;
1636 u8 port;
1637
1638 /* The time represents the upper 32 bits of the PHY timer, so we need
1639 * to shift to account for this when programming.
1640 */
1641 phy_time = (u64)time << 32;
1642
1643 for (port = 0; port < hw->ptp.num_lports; port++) {
1644 int err;
1645
1646 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time);
1647 if (err) {
1648 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
1649 port, err);
1650 return err;
1651 }
1652 }
1653
1654 return 0;
1655 }
1656
1657 /**
1658 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust
1659 * @hw: pointer to HW struct
1660 * @port: Port number to be programmed
1661 * @time: time in cycles to adjust the port clocks
1662 *
1663 * Program the port for an atomic adjustment by writing the Tx and Rx timer
1664 * registers. The atomic adjustment won't be completed until the driver issues
1665 * an ICE_PTP_ADJ_TIME command.
1666 *
1667 * Note that time is not in units of nanoseconds. It is in clock time
1668 * including the lower sub-nanosecond portion of the port timer.
1669 *
1670 * Negative adjustments are supported using 2s complement arithmetic.
1671 *
1672 * Return:
1673 * * %0 - success
1674 * * %other - failed to write to PHY
1675 */
ice_ptp_prep_port_adj_eth56g(struct ice_hw * hw,u8 port,s64 time)1676 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time)
1677 {
1678 u32 l_time, u_time;
1679 int err;
1680
1681 l_time = lower_32_bits(time);
1682 u_time = upper_32_bits(time);
1683
1684 /* Tx case */
1685 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
1686 l_time);
1687 if (err)
1688 goto exit_err;
1689
1690 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U,
1691 u_time);
1692 if (err)
1693 goto exit_err;
1694
1695 /* Rx case */
1696 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L,
1697 l_time);
1698 if (err)
1699 goto exit_err;
1700
1701 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U,
1702 u_time);
1703 if (err)
1704 goto exit_err;
1705
1706 return 0;
1707
1708 exit_err:
1709 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
1710 port, err);
1711 return err;
1712 }
1713
1714 /**
1715 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
1716 * @hw: pointer to HW struct
1717 * @adj: adjustment in nanoseconds
1718 *
1719 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
1720 * Tx and Rx port registers. The actual adjustment is completed by issuing an
1721 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
1722 *
1723 * Return:
1724 * * %0 - success
1725 * * %other - failed to write to PHY
1726 */
ice_ptp_prep_phy_adj_eth56g(struct ice_hw * hw,s32 adj)1727 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj)
1728 {
1729 s64 cycles;
1730 u8 port;
1731
1732 /* The port clock supports adjustment of the sub-nanosecond portion of
1733 * the clock (lowest 32 bits). We shift the provided adjustment in
1734 * nanoseconds by 32 to calculate the appropriate adjustment to program
1735 * into the PHY ports.
1736 */
1737 cycles = (s64)adj << 32;
1738
1739 for (port = 0; port < hw->ptp.num_lports; port++) {
1740 int err;
1741
1742 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles);
1743 if (err)
1744 return err;
1745 }
1746
1747 return 0;
1748 }
1749
1750 /**
1751 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
1752 * @hw: pointer to HW struct
1753 * @incval: new increment value to prepare
1754 *
1755 * Prepare each of the PHY ports for a new increment value by programming the
1756 * port's TIMETUS registers. The new increment value will be updated after
1757 * issuing an ICE_PTP_INIT_INCVAL command.
1758 *
1759 * Return:
1760 * * %0 - success
1761 * * %other - failed to write to PHY
1762 */
ice_ptp_prep_phy_incval_eth56g(struct ice_hw * hw,u64 incval)1763 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval)
1764 {
1765 u8 port;
1766
1767 for (port = 0; port < hw->ptp.num_lports; port++) {
1768 int err;
1769
1770 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
1771 incval);
1772 if (err) {
1773 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
1774 port, err);
1775 return err;
1776 }
1777 }
1778
1779 return 0;
1780 }
1781
1782 /**
1783 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture
1784 * @hw: pointer to HW struct
1785 * @port: Port number to read
1786 * @tx_ts: on return, the Tx port time capture
1787 * @rx_ts: on return, the Rx port time capture
1788 *
1789 * Read the port's Tx and Rx local time capture values.
1790 *
1791 * Return:
1792 * * %0 - success
1793 * * %other - failed to read from PHY
1794 */
ice_ptp_read_port_capture_eth56g(struct ice_hw * hw,u8 port,u64 * tx_ts,u64 * rx_ts)1795 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port,
1796 u64 *tx_ts, u64 *rx_ts)
1797 {
1798 int err;
1799
1800 /* Tx case */
1801 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,
1802 tx_ts);
1803 if (err) {
1804 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
1805 err);
1806 return err;
1807 }
1808
1809 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts);
1810
1811 /* Rx case */
1812 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,
1813 rx_ts);
1814 if (err) {
1815 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
1816 err);
1817 return err;
1818 }
1819
1820 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts);
1821
1822 return 0;
1823 }
1824
1825 /**
1826 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command
1827 * @hw: pointer to HW struct
1828 * @port: Port to which cmd has to be sent
1829 * @cmd: Command to be sent to the port
1830 *
1831 * Prepare the requested port for an upcoming timer sync command.
1832 *
1833 * Return:
1834 * * %0 - success
1835 * * %other - failed to write to PHY
1836 */
ice_ptp_write_port_cmd_eth56g(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)1837 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port,
1838 enum ice_ptp_tmr_cmd cmd)
1839 {
1840 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
1841 int err;
1842
1843 /* Tx case */
1844 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val);
1845 if (err) {
1846 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
1847 err);
1848 return err;
1849 }
1850
1851 /* Rx case */
1852 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val);
1853 if (err) {
1854 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
1855 err);
1856 return err;
1857 }
1858
1859 return 0;
1860 }
1861
1862 /**
1863 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type
1864 * @li: pointer to link information struct
1865 *
1866 * Return: simplified ETH56G PHY speed
1867 */
1868 static enum ice_eth56g_link_spd
ice_phy_get_speed_eth56g(struct ice_link_status * li)1869 ice_phy_get_speed_eth56g(struct ice_link_status *li)
1870 {
1871 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low,
1872 li->phy_type_high);
1873
1874 switch (speed) {
1875 case ICE_AQ_LINK_SPEED_1000MB:
1876 return ICE_ETH56G_LNK_SPD_1G;
1877 case ICE_AQ_LINK_SPEED_2500MB:
1878 return ICE_ETH56G_LNK_SPD_2_5G;
1879 case ICE_AQ_LINK_SPEED_10GB:
1880 return ICE_ETH56G_LNK_SPD_10G;
1881 case ICE_AQ_LINK_SPEED_25GB:
1882 return ICE_ETH56G_LNK_SPD_25G;
1883 case ICE_AQ_LINK_SPEED_40GB:
1884 return ICE_ETH56G_LNK_SPD_40G;
1885 case ICE_AQ_LINK_SPEED_50GB:
1886 switch (li->phy_type_low) {
1887 case ICE_PHY_TYPE_LOW_50GBASE_SR:
1888 case ICE_PHY_TYPE_LOW_50GBASE_FR:
1889 case ICE_PHY_TYPE_LOW_50GBASE_LR:
1890 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
1891 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
1892 case ICE_PHY_TYPE_LOW_50G_AUI1:
1893 return ICE_ETH56G_LNK_SPD_50G;
1894 default:
1895 return ICE_ETH56G_LNK_SPD_50G2;
1896 }
1897 case ICE_AQ_LINK_SPEED_100GB:
1898 if (li->phy_type_high ||
1899 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2)
1900 return ICE_ETH56G_LNK_SPD_100G2;
1901 else
1902 return ICE_ETH56G_LNK_SPD_100G;
1903 default:
1904 return ICE_ETH56G_LNK_SPD_1G;
1905 }
1906 }
1907
1908 /**
1909 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle
1910 * @hw: pointer to the HW struct
1911 * @port: port to configure
1912 *
1913 * Configure the number of TUs for the PAR and PCS clocks used as part of the
1914 * timestamp calibration process.
1915 *
1916 * Return:
1917 * * %0 - success
1918 * * %other - PHY read/write failed
1919 */
ice_phy_cfg_parpcs_eth56g(struct ice_hw * hw,u8 port)1920 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
1921 {
1922 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
1923 u32 val;
1924 int err;
1925
1926 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH,
1927 ICE_ETH56G_NOMINAL_THRESH4);
1928 if (err) {
1929 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d",
1930 err);
1931 return err;
1932 }
1933
1934 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
1935 case ICE_ETH56G_LNK_SPD_1G:
1936 case ICE_ETH56G_LNK_SPD_2_5G:
1937 err = ice_read_ptp_reg_eth56g(hw, port_blk,
1938 PHY_GPCS_CONFIG_REG0, &val);
1939 if (err) {
1940 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d",
1941 err);
1942 return err;
1943 }
1944
1945 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M;
1946 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M,
1947 ICE_ETH56G_NOMINAL_TX_THRESH);
1948
1949 err = ice_write_ptp_reg_eth56g(hw, port_blk,
1950 PHY_GPCS_CONFIG_REG0, val);
1951 if (err) {
1952 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d",
1953 err);
1954 return err;
1955 }
1956 break;
1957 default:
1958 break;
1959 }
1960
1961 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L,
1962 ICE_ETH56G_NOMINAL_PCS_REF_TUS);
1963 if (err) {
1964 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d",
1965 err);
1966 return err;
1967 }
1968
1969 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L,
1970 ICE_ETH56G_NOMINAL_PCS_REF_INC);
1971 if (err) {
1972 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d",
1973 err);
1974 return err;
1975 }
1976
1977 return 0;
1978 }
1979
1980 /**
1981 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings
1982 * @hw: Pointer to the HW struct
1983 * @port: Port to configure
1984 *
1985 * Return:
1986 * * %0 - success
1987 * * %other - PHY read/write failed
1988 */
ice_phy_cfg_ptp_1step_eth56g(struct ice_hw * hw,u8 port)1989 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port)
1990 {
1991 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
1992 u8 blk_port = port & (ICE_PORTS_PER_QUAD - 1);
1993 bool enable, sfd_ena;
1994 u32 val, peer_delay;
1995 int err;
1996
1997 enable = hw->ptp.phy.eth56g.onestep_ena;
1998 peer_delay = hw->ptp.phy.eth56g.peer_delay;
1999 sfd_ena = hw->ptp.phy.eth56g.sfd_ena;
2000
2001 /* PHY_PTP_1STEP_CONFIG */
2002 err = ice_read_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, &val);
2003 if (err)
2004 return err;
2005
2006 if (enable)
2007 val |= blk_port;
2008 else
2009 val &= ~blk_port;
2010
2011 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M);
2012
2013 err = ice_write_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, val);
2014 if (err)
2015 return err;
2016
2017 /* PHY_PTP_1STEP_PEER_DELAY */
2018 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay);
2019 if (peer_delay)
2020 val |= PHY_PTP_1STEP_PD_ADD_PD_M;
2021 val |= PHY_PTP_1STEP_PD_DLY_V_M;
2022 err = ice_write_ptp_reg_eth56g(hw, port_blk,
2023 PHY_PTP_1STEP_PEER_DELAY(blk_port), val);
2024 if (err)
2025 return err;
2026
2027 val &= ~PHY_PTP_1STEP_PD_DLY_V_M;
2028 err = ice_write_ptp_reg_eth56g(hw, port_blk,
2029 PHY_PTP_1STEP_PEER_DELAY(blk_port), val);
2030 if (err)
2031 return err;
2032
2033 /* PHY_MAC_XIF_MODE */
2034 err = ice_read_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, &val);
2035 if (err)
2036 return err;
2037
2038 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M |
2039 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M);
2040
2041 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
2042 case ICE_ETH56G_LNK_SPD_1G:
2043 case ICE_ETH56G_LNK_SPD_2_5G:
2044 val |= PHY_MAC_XIF_GMII_TS_SEL_M;
2045 break;
2046 default:
2047 break;
2048 }
2049
2050 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) |
2051 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) |
2052 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena);
2053
2054 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, val);
2055 }
2056
2057 /**
2058 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values
2059 * @a: multiplier value
2060 * @b: multiplicand value
2061 *
2062 * Return: result of multiplication
2063 */
mul_u32_u32_fx_q9(u32 a,u32 b)2064 static u32 mul_u32_u32_fx_q9(u32 a, u32 b)
2065 {
2066 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W);
2067 }
2068
2069 /**
2070 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow
2071 * @a: first value
2072 * @b: second value
2073 *
2074 * Return: result of addition
2075 */
add_u32_u32_fx(u32 a,u32 b)2076 static u32 add_u32_u32_fx(u32 a, u32 b)
2077 {
2078 return lower_32_bits(((u64)a + b));
2079 }
2080
2081 /**
2082 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value
2083 * @hw: pointer to the HW struct
2084 * @port: port to configure
2085 * @bs: bitslip multiplier
2086 * @fc: FC-FEC enabled
2087 * @rs: RS-FEC enabled
2088 * @spd: link speed
2089 *
2090 * Return: calculated bitslip value
2091 */
ice_ptp_calc_bitslip_eth56g(struct ice_hw * hw,u8 port,u32 bs,bool fc,bool rs,enum ice_eth56g_link_spd spd)2092 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs,
2093 bool fc, bool rs,
2094 enum ice_eth56g_link_spd spd)
2095 {
2096 u8 port_offset = port & (ICE_PORTS_PER_QUAD - 1);
2097 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
2098 u32 bitslip;
2099 int err;
2100
2101 if (!bs || rs)
2102 return 0;
2103
2104 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G)
2105 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP,
2106 &bitslip);
2107 else
2108 err = ice_read_ptp_reg_eth56g(hw, port_blk,
2109 PHY_REG_SD_BIT_SLIP(port_offset),
2110 &bitslip);
2111 if (err)
2112 return 0;
2113
2114 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) {
2115 /* Bitslip register value of 0 corresponds to 10 so substitute
2116 * it for calculations
2117 */
2118 bitslip = 10;
2119 } else if (spd == ICE_ETH56G_LNK_SPD_10G ||
2120 spd == ICE_ETH56G_LNK_SPD_25G) {
2121 if (fc)
2122 bitslip = bitslip * 2 + 32;
2123 else
2124 bitslip = (u32)((s32)bitslip * -1 + 20);
2125 }
2126
2127 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W;
2128 return mul_u32_u32_fx_q9(bitslip, bs);
2129 }
2130
2131 /**
2132 * ice_ptp_calc_deskew_eth56g - Calculate deskew value
2133 * @hw: pointer to the HW struct
2134 * @port: port to configure
2135 * @ds: deskew multiplier
2136 * @rs: RS-FEC enabled
2137 * @spd: link speed
2138 *
2139 * Return: calculated deskew value
2140 */
ice_ptp_calc_deskew_eth56g(struct ice_hw * hw,u8 port,u32 ds,bool rs,enum ice_eth56g_link_spd spd)2141 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds,
2142 bool rs, enum ice_eth56g_link_spd spd)
2143 {
2144 u32 deskew_i, deskew_f;
2145 int err;
2146
2147 if (!ds)
2148 return 0;
2149
2150 read_poll_timeout(ice_read_ptp_reg_eth56g, err,
2151 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500,
2152 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0,
2153 &deskew_i);
2154 if (err)
2155 return err;
2156
2157 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i);
2158 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i);
2159
2160 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2)
2161 ds = 0x633; /* 3.1 */
2162 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G)
2163 ds = 0x31b; /* 1.552 */
2164
2165 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i);
2166 /* Shift 3 fractional bits to the end of the integer part */
2167 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W;
2168 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds);
2169 }
2170
2171 /**
2172 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values
2173 * @hw: pointer to the HW struct
2174 * @port: port to configure
2175 * @spd: link speed
2176 * @cfg: structure to store output values
2177 * @fc: FC-FEC enabled
2178 * @rs: RS-FEC enabled
2179 *
2180 * Return:
2181 * * %0 - success
2182 * * %other - failed to write to PHY
2183 */
ice_phy_set_offsets_eth56g(struct ice_hw * hw,u8 port,enum ice_eth56g_link_spd spd,const struct ice_eth56g_mac_reg_cfg * cfg,bool fc,bool rs)2184 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port,
2185 enum ice_eth56g_link_spd spd,
2186 const struct ice_eth56g_mac_reg_cfg *cfg,
2187 bool fc, bool rs)
2188 {
2189 u32 rx_offset, tx_offset, bs_ds;
2190 bool onestep, sfd;
2191
2192 onestep = hw->ptp.phy.eth56g.onestep_ena;
2193 sfd = hw->ptp.phy.eth56g.sfd_ena;
2194 bs_ds = cfg->rx_offset.bs_ds;
2195
2196 if (fc)
2197 rx_offset = cfg->rx_offset.fc;
2198 else if (rs)
2199 rx_offset = cfg->rx_offset.rs;
2200 else
2201 rx_offset = cfg->rx_offset.no_fec;
2202
2203 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes);
2204 if (sfd)
2205 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd);
2206
2207 if (spd < ICE_ETH56G_LNK_SPD_40G)
2208 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs,
2209 spd);
2210 else
2211 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd);
2212 rx_offset = add_u32_u32_fx(rx_offset, bs_ds);
2213 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT |
2214 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC;
2215
2216 if (fc)
2217 tx_offset = cfg->tx_offset.fc;
2218 else if (rs)
2219 tx_offset = cfg->tx_offset.rs;
2220 else
2221 tx_offset = cfg->tx_offset.no_fec;
2222 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd +
2223 cfg->tx_offset.onestep * onestep;
2224
2225 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset);
2226 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset);
2227 }
2228
2229 /**
2230 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP
2231 * @hw: Pointer to the HW struct
2232 * @port: Port to configure
2233 *
2234 * Return:
2235 * * %0 - success
2236 * * %other - failed to write to PHY
2237 */
ice_phy_cfg_mac_eth56g(struct ice_hw * hw,u8 port)2238 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port)
2239 {
2240 const struct ice_eth56g_mac_reg_cfg *cfg;
2241 enum ice_eth56g_link_spd spd;
2242 struct ice_link_status *li;
2243 bool fc = false;
2244 bool rs = false;
2245 bool onestep;
2246 u32 val;
2247 int err;
2248
2249 onestep = hw->ptp.phy.eth56g.onestep_ena;
2250 li = &hw->port_info->phy.link_info;
2251 spd = ice_phy_get_speed_eth56g(li);
2252 if (!!(li->an_info & ICE_AQ_FEC_EN)) {
2253 if (spd == ICE_ETH56G_LNK_SPD_10G) {
2254 fc = true;
2255 } else {
2256 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN);
2257 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN);
2258 }
2259 }
2260 cfg = ð56g_mac_cfg[spd];
2261
2262 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0);
2263 if (err)
2264 return err;
2265
2266 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0);
2267 if (err)
2268 return err;
2269
2270 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M,
2271 cfg->tx_mode.def + rs * cfg->tx_mode.rs) |
2272 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) |
2273 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M,
2274 cfg->tx_cw_dly.def +
2275 onestep * cfg->tx_cw_dly.onestep) |
2276 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M,
2277 cfg->rx_mode.def + rs * cfg->rx_mode.rs) |
2278 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M,
2279 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) |
2280 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M,
2281 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) |
2282 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk);
2283 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val);
2284 if (err)
2285 return err;
2286
2287 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME,
2288 cfg->blktime);
2289 if (err)
2290 return err;
2291
2292 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs);
2293 if (err)
2294 return err;
2295
2296 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs)
2297 val = 0;
2298 else
2299 val = cfg->mktime;
2300
2301 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val);
2302 }
2303
2304 /**
2305 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt
2306 * @hw: pointer to the HW struct
2307 * @port: the timestamp port
2308 * @ena: enable or disable interrupt
2309 * @threshold: interrupt threshold
2310 *
2311 * Configure TX timestamp interrupt for the specified port
2312 *
2313 * Return:
2314 * * %0 - success
2315 * * %other - PHY read/write failed
2316 */
ice_phy_cfg_intr_eth56g(struct ice_hw * hw,u8 port,bool ena,u8 threshold)2317 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold)
2318 {
2319 int err;
2320 u32 val;
2321
2322 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);
2323 if (err)
2324 return err;
2325
2326 if (ena) {
2327 val |= PHY_TS_INT_CONFIG_ENA_M;
2328 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M;
2329 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold);
2330 } else {
2331 val &= ~PHY_TS_INT_CONFIG_ENA_M;
2332 }
2333
2334 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);
2335 }
2336
2337 /**
2338 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time
2339 * @hw: pointer to the HW struct
2340 * @port: the PHY port to read
2341 * @phy_time: on return, the 64bit PHY timer value
2342 * @phc_time: on return, the lower 64bits of PHC time
2343 *
2344 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
2345 * and PHC timer values.
2346 *
2347 * Return:
2348 * * %0 - success
2349 * * %other - PHY read/write failed
2350 */
ice_read_phy_and_phc_time_eth56g(struct ice_hw * hw,u8 port,u64 * phy_time,u64 * phc_time)2351 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port,
2352 u64 *phy_time, u64 *phc_time)
2353 {
2354 u64 tx_time, rx_time;
2355 u32 zo, lo;
2356 u8 tmr_idx;
2357 int err;
2358
2359 tmr_idx = ice_get_ptp_src_clock_index(hw);
2360
2361 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
2362 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
2363
2364 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
2365 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
2366 if (err)
2367 return err;
2368
2369 /* Issue the sync to start the ICE_PTP_READ_TIME capture */
2370 ice_ptp_exec_tmr_cmd(hw);
2371
2372 /* Read the captured PHC time from the shadow time registers */
2373 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
2374 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
2375 *phc_time = (u64)lo << 32 | zo;
2376
2377 /* Read the captured PHY time from the PHY shadow registers */
2378 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);
2379 if (err)
2380 return err;
2381
2382 /* If the PHY Tx and Rx timers don't match, log a warning message.
2383 * Note that this should not happen in normal circumstances since the
2384 * driver always programs them together.
2385 */
2386 if (tx_time != rx_time)
2387 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
2388 port, tx_time, rx_time);
2389
2390 *phy_time = tx_time;
2391
2392 return 0;
2393 }
2394
2395 /**
2396 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer
2397 * @hw: pointer to the HW struct
2398 * @port: the PHY port to synchronize
2399 *
2400 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
2401 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
2402 * simultaneous read of the PHY timer and PHC timer. Then we use the
2403 * difference to calculate an appropriate 2s complement addition to add
2404 * to the PHY timer in order to ensure it reads the same value as the
2405 * primary PHC timer.
2406 *
2407 * Return:
2408 * * %0 - success
2409 * * %-EBUSY- failed to acquire PTP semaphore
2410 * * %other - PHY read/write failed
2411 */
ice_sync_phy_timer_eth56g(struct ice_hw * hw,u8 port)2412 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
2413 {
2414 u64 phc_time, phy_time, difference;
2415 int err;
2416
2417 if (!ice_ptp_lock(hw)) {
2418 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
2419 return -EBUSY;
2420 }
2421
2422 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
2423 if (err)
2424 goto err_unlock;
2425
2426 /* Calculate the amount required to add to the port time in order for
2427 * it to match the PHC time.
2428 *
2429 * Note that the port adjustment is done using 2s complement
2430 * arithmetic. This is convenient since it means that we can simply
2431 * calculate the difference between the PHC time and the port time,
2432 * and it will be interpreted correctly.
2433 */
2434
2435 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2436 difference = phc_time - phy_time;
2437
2438 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference);
2439 if (err)
2440 goto err_unlock;
2441
2442 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
2443 if (err)
2444 goto err_unlock;
2445
2446 /* Issue the sync to activate the time adjustment */
2447 ice_ptp_exec_tmr_cmd(hw);
2448
2449 /* Re-capture the timer values to flush the command registers and
2450 * verify that the time was properly adjusted.
2451 */
2452 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
2453 if (err)
2454 goto err_unlock;
2455
2456 dev_info(ice_hw_to_dev(hw),
2457 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
2458 port, phy_time, phc_time);
2459
2460 err_unlock:
2461 ice_ptp_unlock(hw);
2462 return err;
2463 }
2464
2465 /**
2466 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer
2467 * @hw: pointer to the HW struct
2468 * @port: the PHY port to stop
2469 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS
2470 *
2471 * Stop the clock of a PHY port. This must be done as part of the flow to
2472 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2473 * initialized or when link speed changes.
2474 *
2475 * Return:
2476 * * %0 - success
2477 * * %other - failed to write to PHY
2478 */
ice_stop_phy_timer_eth56g(struct ice_hw * hw,u8 port,bool soft_reset)2479 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
2480 {
2481 int err;
2482
2483 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);
2484 if (err)
2485 return err;
2486
2487 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);
2488 if (err)
2489 return err;
2490
2491 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
2492
2493 return 0;
2494 }
2495
2496 /**
2497 * ice_start_phy_timer_eth56g - Start the PHY clock timer
2498 * @hw: pointer to the HW struct
2499 * @port: the PHY port to start
2500 *
2501 * Start the clock of a PHY port. This must be done as part of the flow to
2502 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2503 * initialized or when link speed changes.
2504 *
2505 * Return:
2506 * * %0 - success
2507 * * %other - PHY read/write failed
2508 */
ice_start_phy_timer_eth56g(struct ice_hw * hw,u8 port)2509 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)
2510 {
2511 u32 lo, hi;
2512 u64 incval;
2513 u8 tmr_idx;
2514 int err;
2515
2516 tmr_idx = ice_get_ptp_src_clock_index(hw);
2517
2518 err = ice_stop_phy_timer_eth56g(hw, port, false);
2519 if (err)
2520 return err;
2521
2522 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2523
2524 err = ice_phy_cfg_parpcs_eth56g(hw, port);
2525 if (err)
2526 return err;
2527
2528 err = ice_phy_cfg_ptp_1step_eth56g(hw, port);
2529 if (err)
2530 return err;
2531
2532 err = ice_phy_cfg_mac_eth56g(hw, port);
2533 if (err)
2534 return err;
2535
2536 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
2537 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
2538 incval = (u64)hi << 32 | lo;
2539
2540 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval);
2541 if (err)
2542 return err;
2543
2544 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
2545 if (err)
2546 return err;
2547
2548 ice_ptp_exec_tmr_cmd(hw);
2549
2550 err = ice_sync_phy_timer_eth56g(hw, port);
2551 if (err)
2552 return err;
2553
2554 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1);
2555 if (err)
2556 return err;
2557
2558 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);
2559 if (err)
2560 return err;
2561
2562 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
2563
2564 return 0;
2565 }
2566
2567 /**
2568 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access
2569 * @hw: pointer to HW struct
2570 * @enable: Enable or disable access
2571 *
2572 * Enable sideband devices (PHY and others) access.
2573 */
ice_sb_access_ena_eth56g(struct ice_hw * hw,bool enable)2574 static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable)
2575 {
2576 u32 val = rd32(hw, PF_SB_REM_DEV_CTL);
2577
2578 if (enable)
2579 val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1);
2580 else
2581 val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1));
2582
2583 wr32(hw, PF_SB_REM_DEV_CTL, val);
2584 }
2585
2586 /**
2587 * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization
2588 * @hw: pointer to HW struct
2589 *
2590 * Perform PHC initialization steps specific to E82X devices.
2591 *
2592 * Return:
2593 * * %0 - success
2594 * * %other - failed to initialize CGU
2595 */
ice_ptp_init_phc_eth56g(struct ice_hw * hw)2596 static int ice_ptp_init_phc_eth56g(struct ice_hw *hw)
2597 {
2598 ice_sb_access_ena_eth56g(hw, true);
2599 /* Initialize the Clock Generation Unit */
2600 return ice_init_cgu_e82x(hw);
2601 }
2602
2603 /**
2604 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status
2605 * @hw: pointer to the HW struct
2606 * @ts_status: the timestamp mask pointer
2607 *
2608 * Read the PHY Tx timestamp status mask indicating which ports have Tx
2609 * timestamps available.
2610 *
2611 * Return:
2612 * * %0 - success
2613 * * %other - failed to read from PHY
2614 */
ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw * hw,u32 * ts_status)2615 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
2616 {
2617 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g;
2618 u8 phy, mask;
2619 u32 status;
2620
2621 mask = (1 << hw->ptp.ports_per_phy) - 1;
2622 *ts_status = 0;
2623
2624 for (phy = 0; phy < params->num_phys; phy++) {
2625 int err;
2626
2627 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status);
2628 if (err)
2629 return err;
2630
2631 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy);
2632 }
2633
2634 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status);
2635
2636 return 0;
2637 }
2638
2639 /**
2640 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register
2641 * @hw: pointer to the HW struct
2642 * @port: the PHY port to read from
2643 * @tstamp_ready: contents of the Tx memory status register
2644 *
2645 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in
2646 * the PHY are ready. A set bit means the corresponding timestamp is valid and
2647 * ready to be captured from the PHY timestamp block.
2648 *
2649 * Return:
2650 * * %0 - success
2651 * * %other - failed to read from PHY
2652 */
ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw * hw,u8 port,u64 * tstamp_ready)2653 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port,
2654 u64 *tstamp_ready)
2655 {
2656 int err;
2657
2658 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
2659 tstamp_ready);
2660 if (err) {
2661 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n",
2662 port, err);
2663 return err;
2664 }
2665
2666 return 0;
2667 }
2668
2669 /**
2670 * ice_is_muxed_topo - detect breakout 2x50G topology for E825C
2671 * @hw: pointer to the HW struct
2672 *
2673 * Return: true if it's 2x50 breakout topology, false otherwise
2674 */
ice_is_muxed_topo(struct ice_hw * hw)2675 static bool ice_is_muxed_topo(struct ice_hw *hw)
2676 {
2677 u8 link_topo;
2678 bool mux;
2679 u32 val;
2680
2681 val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG);
2682 mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M, val);
2683 val = rd32(hw, GLGEN_MAC_LINK_TOPO);
2684 link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val);
2685
2686 return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS);
2687 }
2688
2689 /**
2690 * ice_ptp_init_phy_e825c - initialize PHY parameters
2691 * @hw: pointer to the HW struct
2692 */
ice_ptp_init_phy_e825c(struct ice_hw * hw)2693 static void ice_ptp_init_phy_e825c(struct ice_hw *hw)
2694 {
2695 struct ice_ptp_hw *ptp = &hw->ptp;
2696 struct ice_eth56g_params *params;
2697 u8 phy;
2698
2699 ptp->phy_model = ICE_PHY_ETH56G;
2700 params = &ptp->phy.eth56g;
2701 params->onestep_ena = false;
2702 params->peer_delay = 0;
2703 params->sfd_ena = false;
2704 params->phy_addr[0] = eth56g_phy_0;
2705 params->phy_addr[1] = eth56g_phy_1;
2706 params->num_phys = 2;
2707 ptp->ports_per_phy = 4;
2708 ptp->num_lports = params->num_phys * ptp->ports_per_phy;
2709
2710 ice_sb_access_ena_eth56g(hw, true);
2711 for (phy = 0; phy < params->num_phys; phy++) {
2712 u32 phy_rev;
2713 int err;
2714
2715 err = ice_read_phy_eth56g(hw, phy, PHY_REG_REVISION, &phy_rev);
2716 if (err || phy_rev != PHY_REVISION_ETH56G) {
2717 ptp->phy_model = ICE_PHY_UNSUP;
2718 return;
2719 }
2720 }
2721
2722 ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw);
2723 }
2724
2725 /* E822 family functions
2726 *
2727 * The following functions operate on the E822 family of devices.
2728 */
2729
2730 /**
2731 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access
2732 * @hw: pointer to the HW struct
2733 * @msg: the PHY message buffer to fill in
2734 * @port: the port to access
2735 * @offset: the register offset
2736 */
ice_fill_phy_msg_e82x(struct ice_hw * hw,struct ice_sbq_msg_input * msg,u8 port,u16 offset)2737 static void ice_fill_phy_msg_e82x(struct ice_hw *hw,
2738 struct ice_sbq_msg_input *msg, u8 port,
2739 u16 offset)
2740 {
2741 int phy_port, phy, quadtype;
2742
2743 phy_port = port % hw->ptp.ports_per_phy;
2744 phy = port / hw->ptp.ports_per_phy;
2745 quadtype = ICE_GET_QUAD_NUM(port) %
2746 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy);
2747
2748 if (quadtype == 0) {
2749 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
2750 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port);
2751 } else {
2752 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port);
2753 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port);
2754 }
2755
2756 if (phy == 0)
2757 msg->dest_dev = rmn_0;
2758 else if (phy == 1)
2759 msg->dest_dev = rmn_1;
2760 else
2761 msg->dest_dev = rmn_2;
2762 }
2763
2764 /**
2765 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register
2766 * @low_addr: the low address to check
2767 * @high_addr: on return, contains the high address of the 64bit register
2768 *
2769 * Checks if the provided low address is one of the known 64bit PHY values
2770 * represented as two 32bit registers. If it is, return the appropriate high
2771 * register offset to use.
2772 */
ice_is_64b_phy_reg_e82x(u16 low_addr,u16 * high_addr)2773 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr)
2774 {
2775 switch (low_addr) {
2776 case P_REG_PAR_PCS_TX_OFFSET_L:
2777 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U;
2778 return true;
2779 case P_REG_PAR_PCS_RX_OFFSET_L:
2780 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U;
2781 return true;
2782 case P_REG_PAR_TX_TIME_L:
2783 *high_addr = P_REG_PAR_TX_TIME_U;
2784 return true;
2785 case P_REG_PAR_RX_TIME_L:
2786 *high_addr = P_REG_PAR_RX_TIME_U;
2787 return true;
2788 case P_REG_TOTAL_TX_OFFSET_L:
2789 *high_addr = P_REG_TOTAL_TX_OFFSET_U;
2790 return true;
2791 case P_REG_TOTAL_RX_OFFSET_L:
2792 *high_addr = P_REG_TOTAL_RX_OFFSET_U;
2793 return true;
2794 case P_REG_UIX66_10G_40G_L:
2795 *high_addr = P_REG_UIX66_10G_40G_U;
2796 return true;
2797 case P_REG_UIX66_25G_100G_L:
2798 *high_addr = P_REG_UIX66_25G_100G_U;
2799 return true;
2800 case P_REG_TX_CAPTURE_L:
2801 *high_addr = P_REG_TX_CAPTURE_U;
2802 return true;
2803 case P_REG_RX_CAPTURE_L:
2804 *high_addr = P_REG_RX_CAPTURE_U;
2805 return true;
2806 case P_REG_TX_TIMER_INC_PRE_L:
2807 *high_addr = P_REG_TX_TIMER_INC_PRE_U;
2808 return true;
2809 case P_REG_RX_TIMER_INC_PRE_L:
2810 *high_addr = P_REG_RX_TIMER_INC_PRE_U;
2811 return true;
2812 default:
2813 return false;
2814 }
2815 }
2816
2817 /**
2818 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register
2819 * @low_addr: the low address to check
2820 * @high_addr: on return, contains the high address of the 40bit value
2821 *
2822 * Checks if the provided low address is one of the known 40bit PHY values
2823 * split into two registers with the lower 8 bits in the low register and the
2824 * upper 32 bits in the high register. If it is, return the appropriate high
2825 * register offset to use.
2826 */
ice_is_40b_phy_reg_e82x(u16 low_addr,u16 * high_addr)2827 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr)
2828 {
2829 switch (low_addr) {
2830 case P_REG_TIMETUS_L:
2831 *high_addr = P_REG_TIMETUS_U;
2832 return true;
2833 case P_REG_PAR_RX_TUS_L:
2834 *high_addr = P_REG_PAR_RX_TUS_U;
2835 return true;
2836 case P_REG_PAR_TX_TUS_L:
2837 *high_addr = P_REG_PAR_TX_TUS_U;
2838 return true;
2839 case P_REG_PCS_RX_TUS_L:
2840 *high_addr = P_REG_PCS_RX_TUS_U;
2841 return true;
2842 case P_REG_PCS_TX_TUS_L:
2843 *high_addr = P_REG_PCS_TX_TUS_U;
2844 return true;
2845 case P_REG_DESK_PAR_RX_TUS_L:
2846 *high_addr = P_REG_DESK_PAR_RX_TUS_U;
2847 return true;
2848 case P_REG_DESK_PAR_TX_TUS_L:
2849 *high_addr = P_REG_DESK_PAR_TX_TUS_U;
2850 return true;
2851 case P_REG_DESK_PCS_RX_TUS_L:
2852 *high_addr = P_REG_DESK_PCS_RX_TUS_U;
2853 return true;
2854 case P_REG_DESK_PCS_TX_TUS_L:
2855 *high_addr = P_REG_DESK_PCS_TX_TUS_U;
2856 return true;
2857 default:
2858 return false;
2859 }
2860 }
2861
2862 /**
2863 * ice_read_phy_reg_e82x - Read a PHY register
2864 * @hw: pointer to the HW struct
2865 * @port: PHY port to read from
2866 * @offset: PHY register offset to read
2867 * @val: on return, the contents read from the PHY
2868 *
2869 * Read a PHY register for the given port over the device sideband queue.
2870 */
2871 static int
ice_read_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 offset,u32 * val)2872 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
2873 {
2874 struct ice_sbq_msg_input msg = {0};
2875 int err;
2876
2877 ice_fill_phy_msg_e82x(hw, &msg, port, offset);
2878 msg.opcode = ice_sbq_msg_rd;
2879
2880 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
2881 if (err) {
2882 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2883 err);
2884 return err;
2885 }
2886
2887 *val = msg.data;
2888
2889 return 0;
2890 }
2891
2892 /**
2893 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers
2894 * @hw: pointer to the HW struct
2895 * @port: PHY port to read from
2896 * @low_addr: offset of the lower register to read from
2897 * @val: on return, the contents of the 64bit value from the PHY registers
2898 *
2899 * Reads the two registers associated with a 64bit value and returns it in the
2900 * val pointer. The offset always specifies the lower register offset to use.
2901 * The high offset is looked up. This function only operates on registers
2902 * known to be two parts of a 64bit value.
2903 */
2904 static int
ice_read_64b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val)2905 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
2906 {
2907 u32 low, high;
2908 u16 high_addr;
2909 int err;
2910
2911 /* Only operate on registers known to be split into two 32bit
2912 * registers.
2913 */
2914 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) {
2915 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
2916 low_addr);
2917 return -EINVAL;
2918 }
2919
2920 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low);
2921 if (err) {
2922 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",
2923 low_addr, err);
2924 return err;
2925 }
2926
2927 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high);
2928 if (err) {
2929 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",
2930 high_addr, err);
2931 return err;
2932 }
2933
2934 *val = (u64)high << 32 | low;
2935
2936 return 0;
2937 }
2938
2939 /**
2940 * ice_write_phy_reg_e82x - Write a PHY register
2941 * @hw: pointer to the HW struct
2942 * @port: PHY port to write to
2943 * @offset: PHY register offset to write
2944 * @val: The value to write to the register
2945 *
2946 * Write a PHY register for the given port over the device sideband queue.
2947 */
2948 static int
ice_write_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 offset,u32 val)2949 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val)
2950 {
2951 struct ice_sbq_msg_input msg = {0};
2952 int err;
2953
2954 ice_fill_phy_msg_e82x(hw, &msg, port, offset);
2955 msg.opcode = ice_sbq_msg_wr;
2956 msg.data = val;
2957
2958 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
2959 if (err) {
2960 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2961 err);
2962 return err;
2963 }
2964
2965 return 0;
2966 }
2967
2968 /**
2969 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY
2970 * @hw: pointer to the HW struct
2971 * @port: port to write to
2972 * @low_addr: offset of the low register
2973 * @val: 40b value to write
2974 *
2975 * Write the provided 40b value to the two associated registers by splitting
2976 * it up into two chunks, the lower 8 bits and the upper 32 bits.
2977 */
2978 static int
ice_write_40b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)2979 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
2980 {
2981 u32 low, high;
2982 u16 high_addr;
2983 int err;
2984
2985 /* Only operate on registers known to be split into a lower 8 bit
2986 * register and an upper 32 bit register.
2987 */
2988 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) {
2989 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",
2990 low_addr);
2991 return -EINVAL;
2992 }
2993 low = FIELD_GET(P_REG_40B_LOW_M, val);
2994 high = (u32)(val >> P_REG_40B_HIGH_S);
2995
2996 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
2997 if (err) {
2998 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
2999 low_addr, err);
3000 return err;
3001 }
3002
3003 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
3004 if (err) {
3005 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
3006 high_addr, err);
3007 return err;
3008 }
3009
3010 return 0;
3011 }
3012
3013 /**
3014 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers
3015 * @hw: pointer to the HW struct
3016 * @port: PHY port to read from
3017 * @low_addr: offset of the lower register to read from
3018 * @val: the contents of the 64bit value to write to PHY
3019 *
3020 * Write the 64bit value to the two associated 32bit PHY registers. The offset
3021 * is always specified as the lower register, and the high address is looked
3022 * up. This function only operates on registers known to be two parts of
3023 * a 64bit value.
3024 */
3025 static int
ice_write_64b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)3026 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
3027 {
3028 u32 low, high;
3029 u16 high_addr;
3030 int err;
3031
3032 /* Only operate on registers known to be split into two 32bit
3033 * registers.
3034 */
3035 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) {
3036 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
3037 low_addr);
3038 return -EINVAL;
3039 }
3040
3041 low = lower_32_bits(val);
3042 high = upper_32_bits(val);
3043
3044 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
3045 if (err) {
3046 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
3047 low_addr, err);
3048 return err;
3049 }
3050
3051 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
3052 if (err) {
3053 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
3054 high_addr, err);
3055 return err;
3056 }
3057
3058 return 0;
3059 }
3060
3061 /**
3062 * ice_fill_quad_msg_e82x - Fill message data for quad register access
3063 * @hw: pointer to the HW struct
3064 * @msg: the PHY message buffer to fill in
3065 * @quad: the quad to access
3066 * @offset: the register offset
3067 *
3068 * Fill a message buffer for accessing a register in a quad shared between
3069 * multiple PHYs.
3070 *
3071 * Return:
3072 * * %0 - OK
3073 * * %-EINVAL - invalid quad number
3074 */
ice_fill_quad_msg_e82x(struct ice_hw * hw,struct ice_sbq_msg_input * msg,u8 quad,u16 offset)3075 static int ice_fill_quad_msg_e82x(struct ice_hw *hw,
3076 struct ice_sbq_msg_input *msg, u8 quad,
3077 u16 offset)
3078 {
3079 u32 addr;
3080
3081 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports))
3082 return -EINVAL;
3083
3084 msg->dest_dev = rmn_0;
3085
3086 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy)))
3087 addr = Q_0_BASE + offset;
3088 else
3089 addr = Q_1_BASE + offset;
3090
3091 msg->msg_addr_low = lower_16_bits(addr);
3092 msg->msg_addr_high = upper_16_bits(addr);
3093
3094 return 0;
3095 }
3096
3097 /**
3098 * ice_read_quad_reg_e82x - Read a PHY quad register
3099 * @hw: pointer to the HW struct
3100 * @quad: quad to read from
3101 * @offset: quad register offset to read
3102 * @val: on return, the contents read from the quad
3103 *
3104 * Read a quad register over the device sideband queue. Quad registers are
3105 * shared between multiple PHYs.
3106 */
3107 int
ice_read_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 * val)3108 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
3109 {
3110 struct ice_sbq_msg_input msg = {0};
3111 int err;
3112
3113 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
3114 if (err)
3115 return err;
3116
3117 msg.opcode = ice_sbq_msg_rd;
3118
3119 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
3120 if (err) {
3121 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
3122 err);
3123 return err;
3124 }
3125
3126 *val = msg.data;
3127
3128 return 0;
3129 }
3130
3131 /**
3132 * ice_write_quad_reg_e82x - Write a PHY quad register
3133 * @hw: pointer to the HW struct
3134 * @quad: quad to write to
3135 * @offset: quad register offset to write
3136 * @val: The value to write to the register
3137 *
3138 * Write a quad register over the device sideband queue. Quad registers are
3139 * shared between multiple PHYs.
3140 */
3141 int
ice_write_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 val)3142 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
3143 {
3144 struct ice_sbq_msg_input msg = {0};
3145 int err;
3146
3147 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
3148 if (err)
3149 return err;
3150
3151 msg.opcode = ice_sbq_msg_wr;
3152 msg.data = val;
3153
3154 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
3155 if (err) {
3156 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
3157 err);
3158 return err;
3159 }
3160
3161 return 0;
3162 }
3163
3164 /**
3165 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block
3166 * @hw: pointer to the HW struct
3167 * @quad: the quad to read from
3168 * @idx: the timestamp index to read
3169 * @tstamp: on return, the 40bit timestamp value
3170 *
3171 * Read a 40bit timestamp value out of the two associated registers in the
3172 * quad memory block that is shared between the internal PHYs of the E822
3173 * family of devices.
3174 */
3175 static int
ice_read_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx,u64 * tstamp)3176 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
3177 {
3178 u16 lo_addr, hi_addr;
3179 u32 lo, hi;
3180 int err;
3181
3182 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
3183 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
3184
3185 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo);
3186 if (err) {
3187 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
3188 err);
3189 return err;
3190 }
3191
3192 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi);
3193 if (err) {
3194 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
3195 err);
3196 return err;
3197 }
3198
3199 /* For E822 based internal PHYs, the timestamp is reported with the
3200 * lower 8 bits in the low register, and the upper 32 bits in the high
3201 * register.
3202 */
3203 *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) | FIELD_PREP(TS_PHY_LOW_M, lo);
3204
3205 return 0;
3206 }
3207
3208 /**
3209 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block
3210 * @hw: pointer to the HW struct
3211 * @quad: the quad to read from
3212 * @idx: the timestamp index to reset
3213 *
3214 * Read the timestamp out of the quad to clear its timestamp status bit from
3215 * the PHY quad block that is shared between the internal PHYs of the E822
3216 * devices.
3217 *
3218 * Note that unlike E810, software cannot directly write to the quad memory
3219 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function
3220 * to determine which timestamps are valid. Reading a timestamp auto-clears
3221 * the valid bit.
3222 *
3223 * To directly clear the contents of the timestamp block entirely, discarding
3224 * all timestamp data at once, software should instead use
3225 * ice_ptp_reset_ts_memory_quad_e82x().
3226 *
3227 * This function should only be called on an idx whose bit is set according to
3228 * ice_get_phy_tx_tstamp_ready().
3229 */
3230 static int
ice_clear_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx)3231 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx)
3232 {
3233 u64 unused_tstamp;
3234 int err;
3235
3236 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp);
3237 if (err) {
3238 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n",
3239 quad, idx, err);
3240 return err;
3241 }
3242
3243 return 0;
3244 }
3245
3246 /**
3247 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block
3248 * @hw: pointer to the HW struct
3249 * @quad: the quad to read from
3250 *
3251 * Clear all timestamps from the PHY quad block that is shared between the
3252 * internal PHYs on the E822 devices.
3253 */
ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw * hw,u8 quad)3254 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad)
3255 {
3256 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
3257 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
3258 }
3259
3260 /**
3261 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
3262 * @hw: pointer to the HW struct
3263 */
ice_ptp_reset_ts_memory_e82x(struct ice_hw * hw)3264 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw)
3265 {
3266 unsigned int quad;
3267
3268 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++)
3269 ice_ptp_reset_ts_memory_quad_e82x(hw, quad);
3270 }
3271
3272 /**
3273 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
3274 * @hw: pointer to the HW struct
3275 *
3276 * Set the window length used for the vernier port calibration process.
3277 */
ice_ptp_set_vernier_wl(struct ice_hw * hw)3278 static int ice_ptp_set_vernier_wl(struct ice_hw *hw)
3279 {
3280 u8 port;
3281
3282 for (port = 0; port < hw->ptp.num_lports; port++) {
3283 int err;
3284
3285 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL,
3286 PTP_VERNIER_WL);
3287 if (err) {
3288 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n",
3289 port, err);
3290 return err;
3291 }
3292 }
3293
3294 return 0;
3295 }
3296
3297 /**
3298 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization
3299 * @hw: pointer to HW struct
3300 *
3301 * Perform PHC initialization steps specific to E822 devices.
3302 */
ice_ptp_init_phc_e82x(struct ice_hw * hw)3303 static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
3304 {
3305 int err;
3306 u32 val;
3307
3308 /* Enable reading switch and PHY registers over the sideband queue */
3309 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
3310 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
3311 val = rd32(hw, PF_SB_REM_DEV_CTL);
3312 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);
3313 wr32(hw, PF_SB_REM_DEV_CTL, val);
3314
3315 /* Initialize the Clock Generation Unit */
3316 err = ice_init_cgu_e82x(hw);
3317 if (err)
3318 return err;
3319
3320 /* Set window length for all the ports */
3321 return ice_ptp_set_vernier_wl(hw);
3322 }
3323
3324 /**
3325 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time
3326 * @hw: pointer to the HW struct
3327 * @time: Time to initialize the PHY port clocks to
3328 *
3329 * Program the PHY port registers with a new initial time value. The port
3330 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
3331 * command. The time value is the upper 32 bits of the PHY timer, usually in
3332 * units of nominal nanoseconds.
3333 */
3334 static int
ice_ptp_prep_phy_time_e82x(struct ice_hw * hw,u32 time)3335 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time)
3336 {
3337 u64 phy_time;
3338 u8 port;
3339 int err;
3340
3341 /* The time represents the upper 32 bits of the PHY timer, so we need
3342 * to shift to account for this when programming.
3343 */
3344 phy_time = (u64)time << 32;
3345
3346 for (port = 0; port < hw->ptp.num_lports; port++) {
3347 /* Tx case */
3348 err = ice_write_64b_phy_reg_e82x(hw, port,
3349 P_REG_TX_TIMER_INC_PRE_L,
3350 phy_time);
3351 if (err)
3352 goto exit_err;
3353
3354 /* Rx case */
3355 err = ice_write_64b_phy_reg_e82x(hw, port,
3356 P_REG_RX_TIMER_INC_PRE_L,
3357 phy_time);
3358 if (err)
3359 goto exit_err;
3360 }
3361
3362 return 0;
3363
3364 exit_err:
3365 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
3366 port, err);
3367
3368 return err;
3369 }
3370
3371 /**
3372 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust
3373 * @hw: pointer to HW struct
3374 * @port: Port number to be programmed
3375 * @time: time in cycles to adjust the port Tx and Rx clocks
3376 *
3377 * Program the port for an atomic adjustment by writing the Tx and Rx timer
3378 * registers. The atomic adjustment won't be completed until the driver issues
3379 * an ICE_PTP_ADJ_TIME command.
3380 *
3381 * Note that time is not in units of nanoseconds. It is in clock time
3382 * including the lower sub-nanosecond portion of the port timer.
3383 *
3384 * Negative adjustments are supported using 2s complement arithmetic.
3385 */
3386 static int
ice_ptp_prep_port_adj_e82x(struct ice_hw * hw,u8 port,s64 time)3387 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time)
3388 {
3389 u32 l_time, u_time;
3390 int err;
3391
3392 l_time = lower_32_bits(time);
3393 u_time = upper_32_bits(time);
3394
3395 /* Tx case */
3396 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L,
3397 l_time);
3398 if (err)
3399 goto exit_err;
3400
3401 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U,
3402 u_time);
3403 if (err)
3404 goto exit_err;
3405
3406 /* Rx case */
3407 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L,
3408 l_time);
3409 if (err)
3410 goto exit_err;
3411
3412 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U,
3413 u_time);
3414 if (err)
3415 goto exit_err;
3416
3417 return 0;
3418
3419 exit_err:
3420 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
3421 port, err);
3422 return err;
3423 }
3424
3425 /**
3426 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment
3427 * @hw: pointer to HW struct
3428 * @adj: adjustment in nanoseconds
3429 *
3430 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
3431 * Tx and Rx port registers. The actual adjustment is completed by issuing an
3432 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
3433 */
3434 static int
ice_ptp_prep_phy_adj_e82x(struct ice_hw * hw,s32 adj)3435 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj)
3436 {
3437 s64 cycles;
3438 u8 port;
3439
3440 /* The port clock supports adjustment of the sub-nanosecond portion of
3441 * the clock. We shift the provided adjustment in nanoseconds to
3442 * calculate the appropriate adjustment to program into the PHY ports.
3443 */
3444 if (adj > 0)
3445 cycles = (s64)adj << 32;
3446 else
3447 cycles = -(((s64)-adj) << 32);
3448
3449 for (port = 0; port < hw->ptp.num_lports; port++) {
3450 int err;
3451
3452 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles);
3453 if (err)
3454 return err;
3455 }
3456
3457 return 0;
3458 }
3459
3460 /**
3461 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment
3462 * @hw: pointer to HW struct
3463 * @incval: new increment value to prepare
3464 *
3465 * Prepare each of the PHY ports for a new increment value by programming the
3466 * port's TIMETUS registers. The new increment value will be updated after
3467 * issuing an ICE_PTP_INIT_INCVAL command.
3468 */
3469 static int
ice_ptp_prep_phy_incval_e82x(struct ice_hw * hw,u64 incval)3470 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval)
3471 {
3472 int err;
3473 u8 port;
3474
3475 for (port = 0; port < hw->ptp.num_lports; port++) {
3476 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L,
3477 incval);
3478 if (err)
3479 goto exit_err;
3480 }
3481
3482 return 0;
3483
3484 exit_err:
3485 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
3486 port, err);
3487
3488 return err;
3489 }
3490
3491 /**
3492 * ice_ptp_read_port_capture - Read a port's local time capture
3493 * @hw: pointer to HW struct
3494 * @port: Port number to read
3495 * @tx_ts: on return, the Tx port time capture
3496 * @rx_ts: on return, the Rx port time capture
3497 *
3498 * Read the port's Tx and Rx local time capture values.
3499 *
3500 * Note this has no equivalent for the E810 devices.
3501 */
3502 static int
ice_ptp_read_port_capture(struct ice_hw * hw,u8 port,u64 * tx_ts,u64 * rx_ts)3503 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
3504 {
3505 int err;
3506
3507 /* Tx case */
3508 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
3509 if (err) {
3510 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
3511 err);
3512 return err;
3513 }
3514
3515 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
3516 (unsigned long long)*tx_ts);
3517
3518 /* Rx case */
3519 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
3520 if (err) {
3521 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
3522 err);
3523 return err;
3524 }
3525
3526 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
3527 (unsigned long long)*rx_ts);
3528
3529 return 0;
3530 }
3531
3532 /**
3533 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command
3534 * @hw: pointer to HW struct
3535 * @port: Port to which cmd has to be sent
3536 * @cmd: Command to be sent to the port
3537 *
3538 * Prepare the requested port for an upcoming timer sync command.
3539 *
3540 * Note there is no equivalent of this operation on E810, as that device
3541 * always handles all external PHYs internally.
3542 *
3543 * Return:
3544 * * %0 - success
3545 * * %other - failed to write to PHY
3546 */
ice_ptp_write_port_cmd_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)3547 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port,
3548 enum ice_ptp_tmr_cmd cmd)
3549 {
3550 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
3551 int err;
3552
3553 /* Tx case */
3554 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val);
3555 if (err) {
3556 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
3557 err);
3558 return err;
3559 }
3560
3561 /* Rx case */
3562 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD,
3563 val | TS_CMD_RX_TYPE);
3564 if (err) {
3565 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
3566 err);
3567 return err;
3568 }
3569
3570 return 0;
3571 }
3572
3573 /* E822 Vernier calibration functions
3574 *
3575 * The following functions are used as part of the vernier calibration of
3576 * a port. This calibration increases the precision of the timestamps on the
3577 * port.
3578 */
3579
3580 /**
3581 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode
3582 * @hw: pointer to HW struct
3583 * @port: the port to read from
3584 * @link_out: if non-NULL, holds link speed on success
3585 * @fec_out: if non-NULL, holds FEC algorithm on success
3586 *
3587 * Read the serdes data for the PHY port and extract the link speed and FEC
3588 * algorithm.
3589 */
3590 static int
ice_phy_get_speed_and_fec_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_link_spd * link_out,enum ice_ptp_fec_mode * fec_out)3591 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port,
3592 enum ice_ptp_link_spd *link_out,
3593 enum ice_ptp_fec_mode *fec_out)
3594 {
3595 enum ice_ptp_link_spd link;
3596 enum ice_ptp_fec_mode fec;
3597 u32 serdes;
3598 int err;
3599
3600 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes);
3601 if (err) {
3602 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
3603 return err;
3604 }
3605
3606 /* Determine the FEC algorithm */
3607 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes);
3608
3609 serdes &= P_REG_LINK_SPEED_SERDES_M;
3610
3611 /* Determine the link speed */
3612 if (fec == ICE_PTP_FEC_MODE_RS_FEC) {
3613 switch (serdes) {
3614 case ICE_PTP_SERDES_25G:
3615 link = ICE_PTP_LNK_SPD_25G_RS;
3616 break;
3617 case ICE_PTP_SERDES_50G:
3618 link = ICE_PTP_LNK_SPD_50G_RS;
3619 break;
3620 case ICE_PTP_SERDES_100G:
3621 link = ICE_PTP_LNK_SPD_100G_RS;
3622 break;
3623 default:
3624 return -EIO;
3625 }
3626 } else {
3627 switch (serdes) {
3628 case ICE_PTP_SERDES_1G:
3629 link = ICE_PTP_LNK_SPD_1G;
3630 break;
3631 case ICE_PTP_SERDES_10G:
3632 link = ICE_PTP_LNK_SPD_10G;
3633 break;
3634 case ICE_PTP_SERDES_25G:
3635 link = ICE_PTP_LNK_SPD_25G;
3636 break;
3637 case ICE_PTP_SERDES_40G:
3638 link = ICE_PTP_LNK_SPD_40G;
3639 break;
3640 case ICE_PTP_SERDES_50G:
3641 link = ICE_PTP_LNK_SPD_50G;
3642 break;
3643 default:
3644 return -EIO;
3645 }
3646 }
3647
3648 if (link_out)
3649 *link_out = link;
3650 if (fec_out)
3651 *fec_out = fec;
3652
3653 return 0;
3654 }
3655
3656 /**
3657 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp
3658 * @hw: pointer to HW struct
3659 * @port: to configure the quad for
3660 */
ice_phy_cfg_lane_e82x(struct ice_hw * hw,u8 port)3661 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port)
3662 {
3663 enum ice_ptp_link_spd link_spd;
3664 int err;
3665 u32 val;
3666 u8 quad;
3667
3668 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL);
3669 if (err) {
3670 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n",
3671 err);
3672 return;
3673 }
3674
3675 quad = ICE_GET_QUAD_NUM(port);
3676
3677 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
3678 if (err) {
3679 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n",
3680 err);
3681 return;
3682 }
3683
3684 if (link_spd >= ICE_PTP_LNK_SPD_40G)
3685 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
3686 else
3687 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
3688
3689 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
3690 if (err) {
3691 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n",
3692 err);
3693 return;
3694 }
3695 }
3696
3697 /**
3698 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822
3699 * @hw: pointer to the HW structure
3700 * @port: the port to configure
3701 *
3702 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC
3703 * hardware clock time units (TUs). That is, determine the number of TUs per
3704 * serdes unit interval, and program the UIX registers with this conversion.
3705 *
3706 * This conversion is used as part of the calibration process when determining
3707 * the additional error of a timestamp vs the real time of transmission or
3708 * receipt of the packet.
3709 *
3710 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers
3711 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks.
3712 *
3713 * To calculate the conversion ratio, we use the following facts:
3714 *
3715 * a) the clock frequency in Hz (cycles per second)
3716 * b) the number of TUs per cycle (the increment value of the clock)
3717 * c) 1 second per 1 billion nanoseconds
3718 * d) the duration of 66 UIs in nanoseconds
3719 *
3720 * Given these facts, we can use the following table to work out what ratios
3721 * to multiply in order to get the number of TUs per 66 UIs:
3722 *
3723 * cycles | 1 second | incval (TUs) | nanoseconds
3724 * -------+--------------+--------------+-------------
3725 * second | 1 billion ns | cycle | 66 UIs
3726 *
3727 * To perform the multiplication using integers without too much loss of
3728 * precision, we can take use the following equation:
3729 *
3730 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion)
3731 *
3732 * We scale up to using 6600 UI instead of 66 in order to avoid fractional
3733 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns)
3734 *
3735 * The increment value has a maximum expected range of about 34 bits, while
3736 * the frequency value is about 29 bits. Multiplying these values shouldn't
3737 * overflow the 64 bits. However, we must then further multiply them again by
3738 * the Serdes unit interval duration. To avoid overflow here, we split the
3739 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and
3740 * a divide by 390,625,000. This does lose some precision, but avoids
3741 * miscalculation due to arithmetic overflow.
3742 */
ice_phy_cfg_uix_e82x(struct ice_hw * hw,u8 port)3743 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port)
3744 {
3745 u64 cur_freq, clk_incval, tu_per_sec, uix;
3746 int err;
3747
3748 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3749 clk_incval = ice_ptp_read_src_incval(hw);
3750
3751 /* Calculate TUs per second divided by 256 */
3752 tu_per_sec = (cur_freq * clk_incval) >> 8;
3753
3754 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */
3755 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
3756
3757 /* Program the 10Gb/40Gb conversion ratio */
3758 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000);
3759
3760 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L,
3761 uix);
3762 if (err) {
3763 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n",
3764 err);
3765 return err;
3766 }
3767
3768 /* Program the 25Gb/100Gb conversion ratio */
3769 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000);
3770
3771 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L,
3772 uix);
3773 if (err) {
3774 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n",
3775 err);
3776 return err;
3777 }
3778
3779 return 0;
3780 }
3781
3782 /**
3783 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle
3784 * @hw: pointer to the HW struct
3785 * @port: port to configure
3786 *
3787 * Configure the number of TUs for the PAR and PCS clocks used as part of the
3788 * timestamp calibration process. This depends on the link speed, as the PHY
3789 * uses different markers depending on the speed.
3790 *
3791 * 1Gb/10Gb/25Gb:
3792 * - Tx/Rx PAR/PCS markers
3793 *
3794 * 25Gb RS:
3795 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3796 *
3797 * 40Gb/50Gb:
3798 * - Tx/Rx PAR/PCS markers
3799 * - Rx Deskew PAR/PCS markers
3800 *
3801 * 50G RS and 100GB RS:
3802 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3803 * - Rx Deskew PAR/PCS markers
3804 * - Tx PAR/PCS markers
3805 *
3806 * To calculate the conversion, we use the PHC clock frequency (cycles per
3807 * second), the increment value (TUs per cycle), and the related PHY clock
3808 * frequency to calculate the TUs per unit of the PHY link clock. The
3809 * following table shows how the units convert:
3810 *
3811 * cycles | TUs | second
3812 * -------+-------+--------
3813 * second | cycle | cycles
3814 *
3815 * For each conversion register, look up the appropriate frequency from the
3816 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program
3817 * this to the appropriate register, preparing hardware to perform timestamp
3818 * calibration to calculate the total Tx or Rx offset to adjust the timestamp
3819 * in order to calibrate for the internal PHY delays.
3820 *
3821 * Note that the increment value ranges up to ~34 bits, and the clock
3822 * frequency is ~29 bits, so multiplying them together should fit within the
3823 * 64 bit arithmetic.
3824 */
ice_phy_cfg_parpcs_e82x(struct ice_hw * hw,u8 port)3825 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port)
3826 {
3827 u64 cur_freq, clk_incval, tu_per_sec, phy_tus;
3828 enum ice_ptp_link_spd link_spd;
3829 enum ice_ptp_fec_mode fec_mode;
3830 int err;
3831
3832 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
3833 if (err)
3834 return err;
3835
3836 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3837 clk_incval = ice_ptp_read_src_incval(hw);
3838
3839 /* Calculate TUs per cycle of the PHC clock */
3840 tu_per_sec = cur_freq * clk_incval;
3841
3842 /* For each PHY conversion register, look up the appropriate link
3843 * speed frequency and determine the TUs per that clock's cycle time.
3844 * Split this into a high and low value and then program the
3845 * appropriate register. If that link speed does not use the
3846 * associated register, write zeros to clear it instead.
3847 */
3848
3849 /* P_REG_PAR_TX_TUS */
3850 if (e822_vernier[link_spd].tx_par_clk)
3851 phy_tus = div_u64(tu_per_sec,
3852 e822_vernier[link_spd].tx_par_clk);
3853 else
3854 phy_tus = 0;
3855
3856 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L,
3857 phy_tus);
3858 if (err)
3859 return err;
3860
3861 /* P_REG_PAR_RX_TUS */
3862 if (e822_vernier[link_spd].rx_par_clk)
3863 phy_tus = div_u64(tu_per_sec,
3864 e822_vernier[link_spd].rx_par_clk);
3865 else
3866 phy_tus = 0;
3867
3868 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L,
3869 phy_tus);
3870 if (err)
3871 return err;
3872
3873 /* P_REG_PCS_TX_TUS */
3874 if (e822_vernier[link_spd].tx_pcs_clk)
3875 phy_tus = div_u64(tu_per_sec,
3876 e822_vernier[link_spd].tx_pcs_clk);
3877 else
3878 phy_tus = 0;
3879
3880 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L,
3881 phy_tus);
3882 if (err)
3883 return err;
3884
3885 /* P_REG_PCS_RX_TUS */
3886 if (e822_vernier[link_spd].rx_pcs_clk)
3887 phy_tus = div_u64(tu_per_sec,
3888 e822_vernier[link_spd].rx_pcs_clk);
3889 else
3890 phy_tus = 0;
3891
3892 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L,
3893 phy_tus);
3894 if (err)
3895 return err;
3896
3897 /* P_REG_DESK_PAR_TX_TUS */
3898 if (e822_vernier[link_spd].tx_desk_rsgb_par)
3899 phy_tus = div_u64(tu_per_sec,
3900 e822_vernier[link_spd].tx_desk_rsgb_par);
3901 else
3902 phy_tus = 0;
3903
3904 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L,
3905 phy_tus);
3906 if (err)
3907 return err;
3908
3909 /* P_REG_DESK_PAR_RX_TUS */
3910 if (e822_vernier[link_spd].rx_desk_rsgb_par)
3911 phy_tus = div_u64(tu_per_sec,
3912 e822_vernier[link_spd].rx_desk_rsgb_par);
3913 else
3914 phy_tus = 0;
3915
3916 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L,
3917 phy_tus);
3918 if (err)
3919 return err;
3920
3921 /* P_REG_DESK_PCS_TX_TUS */
3922 if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
3923 phy_tus = div_u64(tu_per_sec,
3924 e822_vernier[link_spd].tx_desk_rsgb_pcs);
3925 else
3926 phy_tus = 0;
3927
3928 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L,
3929 phy_tus);
3930 if (err)
3931 return err;
3932
3933 /* P_REG_DESK_PCS_RX_TUS */
3934 if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
3935 phy_tus = div_u64(tu_per_sec,
3936 e822_vernier[link_spd].rx_desk_rsgb_pcs);
3937 else
3938 phy_tus = 0;
3939
3940 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L,
3941 phy_tus);
3942 }
3943
3944 /**
3945 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port
3946 * @hw: pointer to the HW struct
3947 * @link_spd: the Link speed to calculate for
3948 *
3949 * Calculate the fixed offset due to known static latency data.
3950 */
3951 static u64
ice_calc_fixed_tx_offset_e82x(struct ice_hw * hw,enum ice_ptp_link_spd link_spd)3952 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
3953 {
3954 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
3955
3956 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3957 clk_incval = ice_ptp_read_src_incval(hw);
3958
3959 /* Calculate TUs per second */
3960 tu_per_sec = cur_freq * clk_incval;
3961
3962 /* Calculate number of TUs to add for the fixed Tx latency. Since the
3963 * latency measurement is in 1/100th of a nanosecond, we need to
3964 * multiply by tu_per_sec and then divide by 1e11. This calculation
3965 * overflows 64 bit integer arithmetic, so break it up into two
3966 * divisions by 1e4 first then by 1e7.
3967 */
3968 fixed_offset = div_u64(tu_per_sec, 10000);
3969 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
3970 fixed_offset = div_u64(fixed_offset, 10000000);
3971
3972 return fixed_offset;
3973 }
3974
3975 /**
3976 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset
3977 * @hw: pointer to the HW struct
3978 * @port: the PHY port to configure
3979 *
3980 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to
3981 * adjust Tx timestamps by. This is calculated by combining some known static
3982 * latency along with the Vernier offset computations done by hardware.
3983 *
3984 * This function will not return successfully until the Tx offset calculations
3985 * have been completed, which requires waiting until at least one packet has
3986 * been transmitted by the device. It is safe to call this function
3987 * periodically until calibration succeeds, as it will only program the offset
3988 * once.
3989 *
3990 * To avoid overflow, when calculating the offset based on the known static
3991 * latency values, we use measurements in 1/100th of a nanosecond, and divide
3992 * the TUs per second up front. This avoids overflow while allowing
3993 * calculation of the adjustment using integer arithmetic.
3994 *
3995 * Returns zero on success, -EBUSY if the hardware vernier offset
3996 * calibration has not completed, or another error code on failure.
3997 */
ice_phy_cfg_tx_offset_e82x(struct ice_hw * hw,u8 port)3998 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port)
3999 {
4000 enum ice_ptp_link_spd link_spd;
4001 enum ice_ptp_fec_mode fec_mode;
4002 u64 total_offset, val;
4003 int err;
4004 u32 reg;
4005
4006 /* Nothing to do if we've already programmed the offset */
4007 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®);
4008 if (err) {
4009 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n",
4010 port, err);
4011 return err;
4012 }
4013
4014 if (reg)
4015 return 0;
4016
4017 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®);
4018 if (err) {
4019 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",
4020 port, err);
4021 return err;
4022 }
4023
4024 if (!(reg & P_REG_TX_OV_STATUS_OV_M))
4025 return -EBUSY;
4026
4027 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
4028 if (err)
4029 return err;
4030
4031 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd);
4032
4033 /* Read the first Vernier offset from the PHY register and add it to
4034 * the total offset.
4035 */
4036 if (link_spd == ICE_PTP_LNK_SPD_1G ||
4037 link_spd == ICE_PTP_LNK_SPD_10G ||
4038 link_spd == ICE_PTP_LNK_SPD_25G ||
4039 link_spd == ICE_PTP_LNK_SPD_25G_RS ||
4040 link_spd == ICE_PTP_LNK_SPD_40G ||
4041 link_spd == ICE_PTP_LNK_SPD_50G) {
4042 err = ice_read_64b_phy_reg_e82x(hw, port,
4043 P_REG_PAR_PCS_TX_OFFSET_L,
4044 &val);
4045 if (err)
4046 return err;
4047
4048 total_offset += val;
4049 }
4050
4051 /* For Tx, we only need to use the second Vernier offset for
4052 * multi-lane link speeds with RS-FEC. The lanes will always be
4053 * aligned.
4054 */
4055 if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||
4056 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
4057 err = ice_read_64b_phy_reg_e82x(hw, port,
4058 P_REG_PAR_TX_TIME_L,
4059 &val);
4060 if (err)
4061 return err;
4062
4063 total_offset += val;
4064 }
4065
4066 /* Now that the total offset has been calculated, program it to the
4067 * PHY and indicate that the Tx offset is ready. After this,
4068 * timestamps will be enabled.
4069 */
4070 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L,
4071 total_offset);
4072 if (err)
4073 return err;
4074
4075 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1);
4076 if (err)
4077 return err;
4078
4079 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n",
4080 port);
4081
4082 return 0;
4083 }
4084
4085 /**
4086 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx
4087 * @hw: pointer to the HW struct
4088 * @port: the PHY port to adjust for
4089 * @link_spd: the current link speed of the PHY
4090 * @fec_mode: the current FEC mode of the PHY
4091 * @pmd_adj: on return, the amount to adjust the Rx total offset by
4092 *
4093 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY.
4094 * This varies by link speed and FEC mode. The value calculated accounts for
4095 * various delays caused when receiving a packet.
4096 */
4097 static int
ice_phy_calc_pmd_adj_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_link_spd link_spd,enum ice_ptp_fec_mode fec_mode,u64 * pmd_adj)4098 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port,
4099 enum ice_ptp_link_spd link_spd,
4100 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
4101 {
4102 u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
4103 u8 pmd_align;
4104 u32 val;
4105 int err;
4106
4107 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val);
4108 if (err) {
4109 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n",
4110 err);
4111 return err;
4112 }
4113
4114 pmd_align = (u8)val;
4115
4116 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
4117 clk_incval = ice_ptp_read_src_incval(hw);
4118
4119 /* Calculate TUs per second */
4120 tu_per_sec = cur_freq * clk_incval;
4121
4122 /* The PMD alignment adjustment measurement depends on the link speed,
4123 * and whether FEC is enabled. For each link speed, the alignment
4124 * adjustment is calculated by dividing a value by the length of
4125 * a Time Unit in nanoseconds.
4126 *
4127 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8
4128 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33)
4129 * 10G w/FEC: align * 0.1 * 32/33
4130 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33)
4131 * 25G w/FEC: align * 0.4 * 32/33
4132 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33)
4133 * 40G w/FEC: align * 0.1 * 32/33
4134 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33)
4135 * 50G w/FEC: align * 0.8 * 32/33
4136 *
4137 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33.
4138 *
4139 * To allow for calculating this value using integer arithmetic, we
4140 * instead start with the number of TUs per second, (inverse of the
4141 * length of a Time Unit in nanoseconds), multiply by a value based
4142 * on the PMD alignment register, and then divide by the right value
4143 * calculated based on the table above. To avoid integer overflow this
4144 * division is broken up into a step of dividing by 125 first.
4145 */
4146 if (link_spd == ICE_PTP_LNK_SPD_1G) {
4147 if (pmd_align == 4)
4148 mult = 10;
4149 else
4150 mult = (pmd_align + 6) % 10;
4151 } else if (link_spd == ICE_PTP_LNK_SPD_10G ||
4152 link_spd == ICE_PTP_LNK_SPD_25G ||
4153 link_spd == ICE_PTP_LNK_SPD_40G ||
4154 link_spd == ICE_PTP_LNK_SPD_50G) {
4155 /* If Clause 74 FEC, always calculate PMD adjust */
4156 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74)
4157 mult = pmd_align;
4158 else
4159 mult = 0;
4160 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS ||
4161 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
4162 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
4163 if (pmd_align < 17)
4164 mult = pmd_align + 40;
4165 else
4166 mult = pmd_align;
4167 } else {
4168 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n",
4169 link_spd);
4170 mult = 0;
4171 }
4172
4173 /* In some cases, there's no need to adjust for the PMD alignment */
4174 if (!mult) {
4175 *pmd_adj = 0;
4176 return 0;
4177 }
4178
4179 /* Calculate the adjustment by multiplying TUs per second by the
4180 * appropriate multiplier and divisor. To avoid overflow, we first
4181 * divide by 125, and then handle remaining divisor based on the link
4182 * speed pmd_adj_divisor value.
4183 */
4184 adj = div_u64(tu_per_sec, 125);
4185 adj *= mult;
4186 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor);
4187
4188 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
4189 * cycle count is necessary.
4190 */
4191 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) {
4192 u64 cycle_adj;
4193 u8 rx_cycle;
4194
4195 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT,
4196 &val);
4197 if (err) {
4198 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n",
4199 err);
4200 return err;
4201 }
4202
4203 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M;
4204 if (rx_cycle) {
4205 mult = (4 - rx_cycle) * 40;
4206
4207 cycle_adj = div_u64(tu_per_sec, 125);
4208 cycle_adj *= mult;
4209 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
4210
4211 adj += cycle_adj;
4212 }
4213 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) {
4214 u64 cycle_adj;
4215 u8 rx_cycle;
4216
4217 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT,
4218 &val);
4219 if (err) {
4220 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n",
4221 err);
4222 return err;
4223 }
4224
4225 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M;
4226 if (rx_cycle) {
4227 mult = rx_cycle * 40;
4228
4229 cycle_adj = div_u64(tu_per_sec, 125);
4230 cycle_adj *= mult;
4231 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
4232
4233 adj += cycle_adj;
4234 }
4235 }
4236
4237 /* Return the calculated adjustment */
4238 *pmd_adj = adj;
4239
4240 return 0;
4241 }
4242
4243 /**
4244 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port
4245 * @hw: pointer to HW struct
4246 * @link_spd: The Link speed to calculate for
4247 *
4248 * Determine the fixed Rx latency for a given link speed.
4249 */
4250 static u64
ice_calc_fixed_rx_offset_e82x(struct ice_hw * hw,enum ice_ptp_link_spd link_spd)4251 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
4252 {
4253 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
4254
4255 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
4256 clk_incval = ice_ptp_read_src_incval(hw);
4257
4258 /* Calculate TUs per second */
4259 tu_per_sec = cur_freq * clk_incval;
4260
4261 /* Calculate number of TUs to add for the fixed Rx latency. Since the
4262 * latency measurement is in 1/100th of a nanosecond, we need to
4263 * multiply by tu_per_sec and then divide by 1e11. This calculation
4264 * overflows 64 bit integer arithmetic, so break it up into two
4265 * divisions by 1e4 first then by 1e7.
4266 */
4267 fixed_offset = div_u64(tu_per_sec, 10000);
4268 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
4269 fixed_offset = div_u64(fixed_offset, 10000000);
4270
4271 return fixed_offset;
4272 }
4273
4274 /**
4275 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset
4276 * @hw: pointer to the HW struct
4277 * @port: the PHY port to configure
4278 *
4279 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to
4280 * adjust Rx timestamps by. This combines calculations from the Vernier offset
4281 * measurements taken in hardware with some data about known fixed delay as
4282 * well as adjusting for multi-lane alignment delay.
4283 *
4284 * This function will not return successfully until the Rx offset calculations
4285 * have been completed, which requires waiting until at least one packet has
4286 * been received by the device. It is safe to call this function periodically
4287 * until calibration succeeds, as it will only program the offset once.
4288 *
4289 * This function must be called only after the offset registers are valid,
4290 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
4291 * has measured the offset.
4292 *
4293 * To avoid overflow, when calculating the offset based on the known static
4294 * latency values, we use measurements in 1/100th of a nanosecond, and divide
4295 * the TUs per second up front. This avoids overflow while allowing
4296 * calculation of the adjustment using integer arithmetic.
4297 *
4298 * Returns zero on success, -EBUSY if the hardware vernier offset
4299 * calibration has not completed, or another error code on failure.
4300 */
ice_phy_cfg_rx_offset_e82x(struct ice_hw * hw,u8 port)4301 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port)
4302 {
4303 enum ice_ptp_link_spd link_spd;
4304 enum ice_ptp_fec_mode fec_mode;
4305 u64 total_offset, pmd, val;
4306 int err;
4307 u32 reg;
4308
4309 /* Nothing to do if we've already programmed the offset */
4310 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®);
4311 if (err) {
4312 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n",
4313 port, err);
4314 return err;
4315 }
4316
4317 if (reg)
4318 return 0;
4319
4320 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®);
4321 if (err) {
4322 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",
4323 port, err);
4324 return err;
4325 }
4326
4327 if (!(reg & P_REG_RX_OV_STATUS_OV_M))
4328 return -EBUSY;
4329
4330 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
4331 if (err)
4332 return err;
4333
4334 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd);
4335
4336 /* Read the first Vernier offset from the PHY register and add it to
4337 * the total offset.
4338 */
4339 err = ice_read_64b_phy_reg_e82x(hw, port,
4340 P_REG_PAR_PCS_RX_OFFSET_L,
4341 &val);
4342 if (err)
4343 return err;
4344
4345 total_offset += val;
4346
4347 /* For Rx, all multi-lane link speeds include a second Vernier
4348 * calibration, because the lanes might not be aligned.
4349 */
4350 if (link_spd == ICE_PTP_LNK_SPD_40G ||
4351 link_spd == ICE_PTP_LNK_SPD_50G ||
4352 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
4353 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
4354 err = ice_read_64b_phy_reg_e82x(hw, port,
4355 P_REG_PAR_RX_TIME_L,
4356 &val);
4357 if (err)
4358 return err;
4359
4360 total_offset += val;
4361 }
4362
4363 /* In addition, Rx must account for the PMD alignment */
4364 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd);
4365 if (err)
4366 return err;
4367
4368 /* For RS-FEC, this adjustment adds delay, but for other modes, it
4369 * subtracts delay.
4370 */
4371 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC)
4372 total_offset += pmd;
4373 else
4374 total_offset -= pmd;
4375
4376 /* Now that the total offset has been calculated, program it to the
4377 * PHY and indicate that the Rx offset is ready. After this,
4378 * timestamps will be enabled.
4379 */
4380 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L,
4381 total_offset);
4382 if (err)
4383 return err;
4384
4385 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1);
4386 if (err)
4387 return err;
4388
4389 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n",
4390 port);
4391
4392 return 0;
4393 }
4394
4395 /**
4396 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers
4397 * @hw: pointer to the HW struct
4398 *
4399 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted
4400 * and received timestamps as invalid.
4401 *
4402 * Return: 0 on success, other error codes when failed to write to PHY
4403 */
ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw * hw)4404 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw)
4405 {
4406 u8 port;
4407
4408 for (port = 0; port < hw->ptp.num_lports; port++) {
4409 int err;
4410
4411 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
4412 if (err) {
4413 dev_warn(ice_hw_to_dev(hw),
4414 "Failed to clear PHY TX_OFFSET_READY register\n");
4415 return err;
4416 }
4417
4418 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
4419 if (err) {
4420 dev_warn(ice_hw_to_dev(hw),
4421 "Failed to clear PHY RX_OFFSET_READY register\n");
4422 return err;
4423 }
4424 }
4425
4426 return 0;
4427 }
4428
4429 /**
4430 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
4431 * @hw: pointer to the HW struct
4432 * @port: the PHY port to read
4433 * @phy_time: on return, the 64bit PHY timer value
4434 * @phc_time: on return, the lower 64bits of PHC time
4435 *
4436 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
4437 * and PHC timer values.
4438 */
4439 static int
ice_read_phy_and_phc_time_e82x(struct ice_hw * hw,u8 port,u64 * phy_time,u64 * phc_time)4440 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time,
4441 u64 *phc_time)
4442 {
4443 u64 tx_time, rx_time;
4444 u32 zo, lo;
4445 u8 tmr_idx;
4446 int err;
4447
4448 tmr_idx = ice_get_ptp_src_clock_index(hw);
4449
4450 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
4451 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
4452
4453 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
4454 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
4455 if (err)
4456 return err;
4457
4458 /* Issue the sync to start the ICE_PTP_READ_TIME capture */
4459 ice_ptp_exec_tmr_cmd(hw);
4460
4461 /* Read the captured PHC time from the shadow time registers */
4462 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
4463 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
4464 *phc_time = (u64)lo << 32 | zo;
4465
4466 /* Read the captured PHY time from the PHY shadow registers */
4467 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
4468 if (err)
4469 return err;
4470
4471 /* If the PHY Tx and Rx timers don't match, log a warning message.
4472 * Note that this should not happen in normal circumstances since the
4473 * driver always programs them together.
4474 */
4475 if (tx_time != rx_time)
4476 dev_warn(ice_hw_to_dev(hw),
4477 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
4478 port, (unsigned long long)tx_time,
4479 (unsigned long long)rx_time);
4480
4481 *phy_time = tx_time;
4482
4483 return 0;
4484 }
4485
4486 /**
4487 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer
4488 * @hw: pointer to the HW struct
4489 * @port: the PHY port to synchronize
4490 *
4491 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
4492 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
4493 * simultaneous read of the PHY timer and PHC timer. Then we use the
4494 * difference to calculate an appropriate 2s complement addition to add
4495 * to the PHY timer in order to ensure it reads the same value as the
4496 * primary PHC timer.
4497 */
ice_sync_phy_timer_e82x(struct ice_hw * hw,u8 port)4498 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port)
4499 {
4500 u64 phc_time, phy_time, difference;
4501 int err;
4502
4503 if (!ice_ptp_lock(hw)) {
4504 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
4505 return -EBUSY;
4506 }
4507
4508 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
4509 if (err)
4510 goto err_unlock;
4511
4512 /* Calculate the amount required to add to the port time in order for
4513 * it to match the PHC time.
4514 *
4515 * Note that the port adjustment is done using 2s complement
4516 * arithmetic. This is convenient since it means that we can simply
4517 * calculate the difference between the PHC time and the port time,
4518 * and it will be interpreted correctly.
4519 */
4520 difference = phc_time - phy_time;
4521
4522 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference);
4523 if (err)
4524 goto err_unlock;
4525
4526 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
4527 if (err)
4528 goto err_unlock;
4529
4530 /* Do not perform any action on the main timer */
4531 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
4532
4533 /* Issue the sync to activate the time adjustment */
4534 ice_ptp_exec_tmr_cmd(hw);
4535
4536 /* Re-capture the timer values to flush the command registers and
4537 * verify that the time was properly adjusted.
4538 */
4539 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
4540 if (err)
4541 goto err_unlock;
4542
4543 dev_info(ice_hw_to_dev(hw),
4544 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
4545 port, (unsigned long long)phy_time,
4546 (unsigned long long)phc_time);
4547
4548 ice_ptp_unlock(hw);
4549
4550 return 0;
4551
4552 err_unlock:
4553 ice_ptp_unlock(hw);
4554 return err;
4555 }
4556
4557 /**
4558 * ice_stop_phy_timer_e82x - Stop the PHY clock timer
4559 * @hw: pointer to the HW struct
4560 * @port: the PHY port to stop
4561 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS
4562 *
4563 * Stop the clock of a PHY port. This must be done as part of the flow to
4564 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4565 * initialized or when link speed changes.
4566 */
4567 int
ice_stop_phy_timer_e82x(struct ice_hw * hw,u8 port,bool soft_reset)4568 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset)
4569 {
4570 int err;
4571 u32 val;
4572
4573 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
4574 if (err)
4575 return err;
4576
4577 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
4578 if (err)
4579 return err;
4580
4581 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
4582 if (err)
4583 return err;
4584
4585 val &= ~P_REG_PS_START_M;
4586 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4587 if (err)
4588 return err;
4589
4590 val &= ~P_REG_PS_ENA_CLK_M;
4591 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4592 if (err)
4593 return err;
4594
4595 if (soft_reset) {
4596 val |= P_REG_PS_SFT_RESET_M;
4597 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4598 if (err)
4599 return err;
4600 }
4601
4602 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
4603
4604 return 0;
4605 }
4606
4607 /**
4608 * ice_start_phy_timer_e82x - Start the PHY clock timer
4609 * @hw: pointer to the HW struct
4610 * @port: the PHY port to start
4611 *
4612 * Start the clock of a PHY port. This must be done as part of the flow to
4613 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4614 * initialized or when link speed changes.
4615 *
4616 * Hardware will take Vernier measurements on Tx or Rx of packets.
4617 */
ice_start_phy_timer_e82x(struct ice_hw * hw,u8 port)4618 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port)
4619 {
4620 u32 lo, hi, val;
4621 u64 incval;
4622 u8 tmr_idx;
4623 int err;
4624
4625 tmr_idx = ice_get_ptp_src_clock_index(hw);
4626
4627 err = ice_stop_phy_timer_e82x(hw, port, false);
4628 if (err)
4629 return err;
4630
4631 ice_phy_cfg_lane_e82x(hw, port);
4632
4633 err = ice_phy_cfg_uix_e82x(hw, port);
4634 if (err)
4635 return err;
4636
4637 err = ice_phy_cfg_parpcs_e82x(hw, port);
4638 if (err)
4639 return err;
4640
4641 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
4642 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
4643 incval = (u64)hi << 32 | lo;
4644
4645 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval);
4646 if (err)
4647 return err;
4648
4649 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
4650 if (err)
4651 return err;
4652
4653 /* Do not perform any action on the main timer */
4654 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
4655
4656 ice_ptp_exec_tmr_cmd(hw);
4657
4658 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
4659 if (err)
4660 return err;
4661
4662 val |= P_REG_PS_SFT_RESET_M;
4663 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4664 if (err)
4665 return err;
4666
4667 val |= P_REG_PS_START_M;
4668 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4669 if (err)
4670 return err;
4671
4672 val &= ~P_REG_PS_SFT_RESET_M;
4673 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4674 if (err)
4675 return err;
4676
4677 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
4678 if (err)
4679 return err;
4680
4681 ice_ptp_exec_tmr_cmd(hw);
4682
4683 val |= P_REG_PS_ENA_CLK_M;
4684 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4685 if (err)
4686 return err;
4687
4688 val |= P_REG_PS_LOAD_OFFSET_M;
4689 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4690 if (err)
4691 return err;
4692
4693 ice_ptp_exec_tmr_cmd(hw);
4694
4695 err = ice_sync_phy_timer_e82x(hw, port);
4696 if (err)
4697 return err;
4698
4699 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
4700
4701 return 0;
4702 }
4703
4704 /**
4705 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register
4706 * @hw: pointer to the HW struct
4707 * @quad: the timestamp quad to read from
4708 * @tstamp_ready: contents of the Tx memory status register
4709 *
4710 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in
4711 * the PHY are ready. A set bit means the corresponding timestamp is valid and
4712 * ready to be captured from the PHY timestamp block.
4713 */
4714 static int
ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw * hw,u8 quad,u64 * tstamp_ready)4715 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
4716 {
4717 u32 hi, lo;
4718 int err;
4719
4720 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi);
4721 if (err) {
4722 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",
4723 quad, err);
4724 return err;
4725 }
4726
4727 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo);
4728 if (err) {
4729 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",
4730 quad, err);
4731 return err;
4732 }
4733
4734 *tstamp_ready = (u64)hi << 32 | (u64)lo;
4735
4736 return 0;
4737 }
4738
4739 /**
4740 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
4741 * @hw: pointer to the HW struct
4742 * @quad: the timestamp quad
4743 * @ena: enable or disable interrupt
4744 * @threshold: interrupt threshold
4745 *
4746 * Configure TX timestamp interrupt for the specified quad
4747 *
4748 * Return: 0 on success, other error codes when failed to read/write quad
4749 */
4750
ice_phy_cfg_intr_e82x(struct ice_hw * hw,u8 quad,bool ena,u8 threshold)4751 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)
4752 {
4753 int err;
4754 u32 val;
4755
4756 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
4757 if (err)
4758 return err;
4759
4760 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
4761 if (ena) {
4762 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
4763 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
4764 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold);
4765 }
4766
4767 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
4768 }
4769
4770 /**
4771 * ice_ptp_init_phy_e82x - initialize PHY parameters
4772 * @ptp: pointer to the PTP HW struct
4773 */
ice_ptp_init_phy_e82x(struct ice_ptp_hw * ptp)4774 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp)
4775 {
4776 ptp->phy_model = ICE_PHY_E82X;
4777 ptp->num_lports = 8;
4778 ptp->ports_per_phy = 8;
4779 }
4780
4781 /* E810 functions
4782 *
4783 * The following functions operate on the E810 series devices which use
4784 * a separate external PHY.
4785 */
4786
4787 /**
4788 * ice_read_phy_reg_e810 - Read register from external PHY on E810
4789 * @hw: pointer to the HW struct
4790 * @addr: the address to read from
4791 * @val: On return, the value read from the PHY
4792 *
4793 * Read a register from the external PHY on the E810 device.
4794 */
ice_read_phy_reg_e810(struct ice_hw * hw,u32 addr,u32 * val)4795 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)
4796 {
4797 struct ice_sbq_msg_input msg = {0};
4798 int err;
4799
4800 msg.msg_addr_low = lower_16_bits(addr);
4801 msg.msg_addr_high = upper_16_bits(addr);
4802 msg.opcode = ice_sbq_msg_rd;
4803 msg.dest_dev = rmn_0;
4804
4805 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
4806 if (err) {
4807 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
4808 err);
4809 return err;
4810 }
4811
4812 *val = msg.data;
4813
4814 return 0;
4815 }
4816
4817 /**
4818 * ice_write_phy_reg_e810 - Write register on external PHY on E810
4819 * @hw: pointer to the HW struct
4820 * @addr: the address to writem to
4821 * @val: the value to write to the PHY
4822 *
4823 * Write a value to a register of the external PHY on the E810 device.
4824 */
ice_write_phy_reg_e810(struct ice_hw * hw,u32 addr,u32 val)4825 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)
4826 {
4827 struct ice_sbq_msg_input msg = {0};
4828 int err;
4829
4830 msg.msg_addr_low = lower_16_bits(addr);
4831 msg.msg_addr_high = upper_16_bits(addr);
4832 msg.opcode = ice_sbq_msg_wr;
4833 msg.dest_dev = rmn_0;
4834 msg.data = val;
4835
4836 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
4837 if (err) {
4838 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
4839 err);
4840 return err;
4841 }
4842
4843 return 0;
4844 }
4845
4846 /**
4847 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW
4848 * @hw: pointer to the HW struct
4849 * @idx: the timestamp index to read
4850 * @hi: 8 bit timestamp high value
4851 * @lo: 32 bit timestamp low value
4852 *
4853 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
4854 * timestamp block of the external PHY on the E810 device using the low latency
4855 * timestamp read.
4856 */
4857 static int
ice_read_phy_tstamp_ll_e810(struct ice_hw * hw,u8 idx,u8 * hi,u32 * lo)4858 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo)
4859 {
4860 u32 val;
4861 u8 i;
4862
4863 /* Write TS index to read to the PF register so the FW can read it */
4864 val = FIELD_PREP(TS_LL_READ_TS_IDX, idx) | TS_LL_READ_TS;
4865 wr32(hw, PF_SB_ATQBAL, val);
4866
4867 /* Read the register repeatedly until the FW provides us the TS */
4868 for (i = TS_LL_READ_RETRIES; i > 0; i--) {
4869 val = rd32(hw, PF_SB_ATQBAL);
4870
4871 /* When the bit is cleared, the TS is ready in the register */
4872 if (!(FIELD_GET(TS_LL_READ_TS, val))) {
4873 /* High 8 bit value of the TS is on the bits 16:23 */
4874 *hi = FIELD_GET(TS_LL_READ_TS_HIGH, val);
4875
4876 /* Read the low 32 bit value and set the TS valid bit */
4877 *lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID;
4878 return 0;
4879 }
4880
4881 udelay(10);
4882 }
4883
4884 /* FW failed to provide the TS in time */
4885 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n");
4886 return -EINVAL;
4887 }
4888
4889 /**
4890 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq
4891 * @hw: pointer to the HW struct
4892 * @lport: the lport to read from
4893 * @idx: the timestamp index to read
4894 * @hi: 8 bit timestamp high value
4895 * @lo: 32 bit timestamp low value
4896 *
4897 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
4898 * timestamp block of the external PHY on the E810 device using sideband queue.
4899 */
4900 static int
ice_read_phy_tstamp_sbq_e810(struct ice_hw * hw,u8 lport,u8 idx,u8 * hi,u32 * lo)4901 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi,
4902 u32 *lo)
4903 {
4904 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
4905 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
4906 u32 lo_val, hi_val;
4907 int err;
4908
4909 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);
4910 if (err) {
4911 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
4912 err);
4913 return err;
4914 }
4915
4916 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val);
4917 if (err) {
4918 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
4919 err);
4920 return err;
4921 }
4922
4923 *lo = lo_val;
4924 *hi = (u8)hi_val;
4925
4926 return 0;
4927 }
4928
4929 /**
4930 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
4931 * @hw: pointer to the HW struct
4932 * @lport: the lport to read from
4933 * @idx: the timestamp index to read
4934 * @tstamp: on return, the 40bit timestamp value
4935 *
4936 * Read a 40bit timestamp value out of the timestamp block of the external PHY
4937 * on the E810 device.
4938 */
4939 static int
ice_read_phy_tstamp_e810(struct ice_hw * hw,u8 lport,u8 idx,u64 * tstamp)4940 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
4941 {
4942 u32 lo = 0;
4943 u8 hi = 0;
4944 int err;
4945
4946 if (hw->dev_caps.ts_dev_info.ts_ll_read)
4947 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo);
4948 else
4949 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo);
4950
4951 if (err)
4952 return err;
4953
4954 /* For E810 devices, the timestamp is reported with the lower 32 bits
4955 * in the low register, and the upper 8 bits in the high register.
4956 */
4957 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M);
4958
4959 return 0;
4960 }
4961
4962 /**
4963 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
4964 * @hw: pointer to the HW struct
4965 * @lport: the lport to read from
4966 * @idx: the timestamp index to reset
4967 *
4968 * Read the timestamp and then forcibly overwrite its value to clear the valid
4969 * bit from the timestamp block of the external PHY on the E810 device.
4970 *
4971 * This function should only be called on an idx whose bit is set according to
4972 * ice_get_phy_tx_tstamp_ready().
4973 */
ice_clear_phy_tstamp_e810(struct ice_hw * hw,u8 lport,u8 idx)4974 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
4975 {
4976 u32 lo_addr, hi_addr;
4977 u64 unused_tstamp;
4978 int err;
4979
4980 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp);
4981 if (err) {
4982 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n",
4983 lport, idx, err);
4984 return err;
4985 }
4986
4987 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
4988 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
4989
4990 err = ice_write_phy_reg_e810(hw, lo_addr, 0);
4991 if (err) {
4992 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n",
4993 lport, idx, err);
4994 return err;
4995 }
4996
4997 err = ice_write_phy_reg_e810(hw, hi_addr, 0);
4998 if (err) {
4999 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n",
5000 lport, idx, err);
5001 return err;
5002 }
5003
5004 return 0;
5005 }
5006
5007 /**
5008 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
5009 * @hw: pointer to HW struct
5010 *
5011 * Perform E810-specific PTP hardware clock initialization steps.
5012 *
5013 * Return: 0 on success, other error codes when failed to initialize TimeSync
5014 */
ice_ptp_init_phc_e810(struct ice_hw * hw)5015 static int ice_ptp_init_phc_e810(struct ice_hw *hw)
5016 {
5017 u8 tmr_idx;
5018 int err;
5019
5020 /* Ensure synchronization delay is zero */
5021 wr32(hw, GLTSYN_SYNC_DLAY, 0);
5022
5023 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5024 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
5025 GLTSYN_ENA_TSYN_ENA_M);
5026 if (err)
5027 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
5028 err);
5029
5030 return err;
5031 }
5032
5033 /**
5034 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
5035 * @hw: Board private structure
5036 * @time: Time to initialize the PHY port clock to
5037 *
5038 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
5039 * initial clock time. The time will not actually be programmed until the
5040 * driver issues an ICE_PTP_INIT_TIME command.
5041 *
5042 * The time value is the upper 32 bits of the PHY timer, usually in units of
5043 * nominal nanoseconds.
5044 */
ice_ptp_prep_phy_time_e810(struct ice_hw * hw,u32 time)5045 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
5046 {
5047 u8 tmr_idx;
5048 int err;
5049
5050 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5051 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
5052 if (err) {
5053 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n",
5054 err);
5055 return err;
5056 }
5057
5058 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
5059 if (err) {
5060 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n",
5061 err);
5062 return err;
5063 }
5064
5065 return 0;
5066 }
5067
5068 /**
5069 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
5070 * @hw: pointer to HW struct
5071 * @adj: adjustment value to program
5072 *
5073 * Prepare the PHY port for an atomic adjustment by programming the PHY
5074 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment
5075 * is completed by issuing an ICE_PTP_ADJ_TIME sync command.
5076 *
5077 * The adjustment value only contains the portion used for the upper 32bits of
5078 * the PHY timer, usually in units of nominal nanoseconds. Negative
5079 * adjustments are supported using 2s complement arithmetic.
5080 */
ice_ptp_prep_phy_adj_e810(struct ice_hw * hw,s32 adj)5081 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj)
5082 {
5083 u8 tmr_idx;
5084 int err;
5085
5086 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5087
5088 /* Adjustments are represented as signed 2's complement values in
5089 * nanoseconds. Sub-nanosecond adjustment is not supported.
5090 */
5091 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0);
5092 if (err) {
5093 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n",
5094 err);
5095 return err;
5096 }
5097
5098 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj);
5099 if (err) {
5100 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n",
5101 err);
5102 return err;
5103 }
5104
5105 return 0;
5106 }
5107
5108 /**
5109 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
5110 * @hw: pointer to HW struct
5111 * @incval: The new 40bit increment value to prepare
5112 *
5113 * Prepare the PHY port for a new increment value by programming the PHY
5114 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is
5115 * completed by issuing an ICE_PTP_INIT_INCVAL command.
5116 */
ice_ptp_prep_phy_incval_e810(struct ice_hw * hw,u64 incval)5117 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
5118 {
5119 u32 high, low;
5120 u8 tmr_idx;
5121 int err;
5122
5123 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5124 low = lower_32_bits(incval);
5125 high = upper_32_bits(incval);
5126
5127 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
5128 if (err) {
5129 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n",
5130 err);
5131 return err;
5132 }
5133
5134 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
5135 if (err) {
5136 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n",
5137 err);
5138 return err;
5139 }
5140
5141 return 0;
5142 }
5143
5144 /**
5145 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
5146 * @hw: pointer to HW struct
5147 * @cmd: Command to be sent to the port
5148 *
5149 * Prepare the external PHYs connected to this device for a timer sync
5150 * command.
5151 */
ice_ptp_port_cmd_e810(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5152 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5153 {
5154 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
5155
5156 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val);
5157 }
5158
5159 /**
5160 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
5161 * @hw: pointer to the HW struct
5162 * @port: the PHY port to read
5163 * @tstamp_ready: contents of the Tx memory status register
5164 *
5165 * E810 devices do not use a Tx memory status register. Instead simply
5166 * indicate that all timestamps are currently ready.
5167 */
5168 static int
ice_get_phy_tx_tstamp_ready_e810(struct ice_hw * hw,u8 port,u64 * tstamp_ready)5169 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)
5170 {
5171 *tstamp_ready = 0xFFFFFFFFFFFFFFFF;
5172 return 0;
5173 }
5174
5175 /* E810 SMA functions
5176 *
5177 * The following functions operate specifically on E810 hardware and are used
5178 * to access the extended GPIOs available.
5179 */
5180
5181 /**
5182 * ice_get_pca9575_handle
5183 * @hw: pointer to the hw struct
5184 * @pca9575_handle: GPIO controller's handle
5185 *
5186 * Find and return the GPIO controller's handle in the netlist.
5187 * When found - the value will be cached in the hw structure and following calls
5188 * will return cached value
5189 */
5190 static int
ice_get_pca9575_handle(struct ice_hw * hw,u16 * pca9575_handle)5191 ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)
5192 {
5193 struct ice_aqc_get_link_topo *cmd;
5194 struct ice_aq_desc desc;
5195 int status;
5196 u8 idx;
5197
5198 /* If handle was read previously return cached value */
5199 if (hw->io_expander_handle) {
5200 *pca9575_handle = hw->io_expander_handle;
5201 return 0;
5202 }
5203
5204 /* If handle was not detected read it from the netlist */
5205 cmd = &desc.params.get_link_topo;
5206 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
5207
5208 /* Set node type to GPIO controller */
5209 cmd->addr.topo_params.node_type_ctx =
5210 (ICE_AQC_LINK_TOPO_NODE_TYPE_M &
5211 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL);
5212
5213 #define SW_PCA9575_SFP_TOPO_IDX 2
5214 #define SW_PCA9575_QSFP_TOPO_IDX 1
5215
5216 /* Check if the SW IO expander controlling SMA exists in the netlist. */
5217 if (hw->device_id == ICE_DEV_ID_E810C_SFP)
5218 idx = SW_PCA9575_SFP_TOPO_IDX;
5219 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP)
5220 idx = SW_PCA9575_QSFP_TOPO_IDX;
5221 else
5222 return -EOPNOTSUPP;
5223
5224 cmd->addr.topo_params.index = idx;
5225
5226 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5227 if (status)
5228 return -EOPNOTSUPP;
5229
5230 /* Verify if we found the right IO expander type */
5231 if (desc.params.get_link_topo.node_part_num !=
5232 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575)
5233 return -EOPNOTSUPP;
5234
5235 /* If present save the handle and return it */
5236 hw->io_expander_handle =
5237 le16_to_cpu(desc.params.get_link_topo.addr.handle);
5238 *pca9575_handle = hw->io_expander_handle;
5239
5240 return 0;
5241 }
5242
5243 /**
5244 * ice_read_sma_ctrl
5245 * @hw: pointer to the hw struct
5246 * @data: pointer to data to be read from the GPIO controller
5247 *
5248 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
5249 * PCA9575 expander, so only bits 3-7 in data are valid.
5250 */
ice_read_sma_ctrl(struct ice_hw * hw,u8 * data)5251 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data)
5252 {
5253 int status;
5254 u16 handle;
5255 u8 i;
5256
5257 status = ice_get_pca9575_handle(hw, &handle);
5258 if (status)
5259 return status;
5260
5261 *data = 0;
5262
5263 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) {
5264 bool pin;
5265
5266 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
5267 &pin, NULL);
5268 if (status)
5269 break;
5270 *data |= (u8)(!pin) << i;
5271 }
5272
5273 return status;
5274 }
5275
5276 /**
5277 * ice_write_sma_ctrl
5278 * @hw: pointer to the hw struct
5279 * @data: data to be written to the GPIO controller
5280 *
5281 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
5282 * of the PCA9575 expander, so only bits 3-7 in data are valid.
5283 */
ice_write_sma_ctrl(struct ice_hw * hw,u8 data)5284 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data)
5285 {
5286 int status;
5287 u16 handle;
5288 u8 i;
5289
5290 status = ice_get_pca9575_handle(hw, &handle);
5291 if (status)
5292 return status;
5293
5294 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) {
5295 bool pin;
5296
5297 pin = !(data & (1 << i));
5298 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
5299 pin, NULL);
5300 if (status)
5301 break;
5302 }
5303
5304 return status;
5305 }
5306
5307 /**
5308 * ice_read_pca9575_reg
5309 * @hw: pointer to the hw struct
5310 * @offset: GPIO controller register offset
5311 * @data: pointer to data to be read from the GPIO controller
5312 *
5313 * Read the register from the GPIO controller
5314 */
ice_read_pca9575_reg(struct ice_hw * hw,u8 offset,u8 * data)5315 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)
5316 {
5317 struct ice_aqc_link_topo_addr link_topo;
5318 __le16 addr;
5319 u16 handle;
5320 int err;
5321
5322 memset(&link_topo, 0, sizeof(link_topo));
5323
5324 err = ice_get_pca9575_handle(hw, &handle);
5325 if (err)
5326 return err;
5327
5328 link_topo.handle = cpu_to_le16(handle);
5329 link_topo.topo_params.node_type_ctx =
5330 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M,
5331 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED);
5332
5333 addr = cpu_to_le16((u16)offset);
5334
5335 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);
5336 }
5337
5338 /**
5339 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM
5340 * @hw: pointer to the HW struct
5341 * @entries: returns the SDP available connections section from NVM
5342 * @num_entries: returns the number of valid entries
5343 *
5344 * Return: 0 on success, negative error code if NVM read failed or section does
5345 * not exist or is corrupted
5346 */
ice_ptp_read_sdp_ac(struct ice_hw * hw,__le16 * entries,uint * num_entries)5347 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries)
5348 {
5349 __le16 data;
5350 u32 offset;
5351 int err;
5352
5353 err = ice_acquire_nvm(hw, ICE_RES_READ);
5354 if (err)
5355 goto exit;
5356
5357 /* Read the offset of SDP_AC */
5358 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET;
5359 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true,
5360 NULL);
5361 if (err)
5362 goto exit;
5363
5364 /* Check if section exist */
5365 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data));
5366 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) {
5367 err = -EINVAL;
5368 goto exit;
5369 }
5370
5371 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) {
5372 offset &= ICE_AQC_NVM_SDP_AC_PTR_M;
5373 offset *= ICE_AQC_NVM_SECTOR_UNIT;
5374 } else {
5375 offset *= sizeof(data);
5376 }
5377
5378 /* Skip reading section length and read the number of valid entries */
5379 offset += sizeof(data);
5380 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true,
5381 NULL);
5382 if (err)
5383 goto exit;
5384 *num_entries = le16_to_cpu(data);
5385
5386 /* Read SDP configuration section */
5387 offset += sizeof(data);
5388 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data),
5389 entries, false, true, NULL);
5390
5391 exit:
5392 if (err)
5393 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n");
5394 ice_release_nvm(hw);
5395 return err;
5396 }
5397
5398 /**
5399 * ice_ptp_init_phy_e810 - initialize PHY parameters
5400 * @ptp: pointer to the PTP HW struct
5401 */
ice_ptp_init_phy_e810(struct ice_ptp_hw * ptp)5402 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp)
5403 {
5404 ptp->phy_model = ICE_PHY_E810;
5405 ptp->num_lports = 8;
5406 ptp->ports_per_phy = 4;
5407 }
5408
5409 /* Device agnostic functions
5410 *
5411 * The following functions implement shared behavior common to both E822 and
5412 * E810 devices, possibly calling a device specific implementation where
5413 * necessary.
5414 */
5415
5416 /**
5417 * ice_ptp_lock - Acquire PTP global semaphore register lock
5418 * @hw: pointer to the HW struct
5419 *
5420 * Acquire the global PTP hardware semaphore lock. Returns true if the lock
5421 * was acquired, false otherwise.
5422 *
5423 * The PFTSYN_SEM register sets the busy bit on read, returning the previous
5424 * value. If software sees the busy bit cleared, this means that this function
5425 * acquired the lock (and the busy bit is now set). If software sees the busy
5426 * bit set, it means that another function acquired the lock.
5427 *
5428 * Software must clear the busy bit with a write to release the lock for other
5429 * functions when done.
5430 */
ice_ptp_lock(struct ice_hw * hw)5431 bool ice_ptp_lock(struct ice_hw *hw)
5432 {
5433 u32 hw_lock;
5434 int i;
5435
5436 #define MAX_TRIES 15
5437
5438 for (i = 0; i < MAX_TRIES; i++) {
5439 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
5440 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M;
5441 if (hw_lock) {
5442 /* Somebody is holding the lock */
5443 usleep_range(5000, 6000);
5444 continue;
5445 }
5446
5447 break;
5448 }
5449
5450 return !hw_lock;
5451 }
5452
5453 /**
5454 * ice_ptp_unlock - Release PTP global semaphore register lock
5455 * @hw: pointer to the HW struct
5456 *
5457 * Release the global PTP hardware semaphore lock. This is done by writing to
5458 * the PFTSYN_SEM register.
5459 */
ice_ptp_unlock(struct ice_hw * hw)5460 void ice_ptp_unlock(struct ice_hw *hw)
5461 {
5462 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
5463 }
5464
5465 /**
5466 * ice_ptp_init_hw - Initialize hw based on device type
5467 * @hw: pointer to the HW structure
5468 *
5469 * Determine the PHY model for the device, and initialize hw
5470 * for use by other functions.
5471 */
ice_ptp_init_hw(struct ice_hw * hw)5472 void ice_ptp_init_hw(struct ice_hw *hw)
5473 {
5474 struct ice_ptp_hw *ptp = &hw->ptp;
5475
5476 if (ice_is_e822(hw) || ice_is_e823(hw))
5477 ice_ptp_init_phy_e82x(ptp);
5478 else if (ice_is_e810(hw))
5479 ice_ptp_init_phy_e810(ptp);
5480 else if (ice_is_e825c(hw))
5481 ice_ptp_init_phy_e825c(hw);
5482 else
5483 ptp->phy_model = ICE_PHY_UNSUP;
5484 }
5485
5486 /**
5487 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command
5488 * @hw: pointer to HW struct
5489 * @port: Port to which cmd has to be sent
5490 * @cmd: Command to be sent to the port
5491 *
5492 * Prepare one port for the upcoming timer sync command. Do not use this for
5493 * programming only a single port, instead use ice_ptp_one_port_cmd() to
5494 * ensure non-modified ports get properly initialized to ICE_PTP_NOP.
5495 *
5496 * Return:
5497 * * %0 - success
5498 * %-EBUSY - PHY type not supported
5499 * * %other - failed to write port command
5500 */
ice_ptp_write_port_cmd(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)5501 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port,
5502 enum ice_ptp_tmr_cmd cmd)
5503 {
5504 switch (ice_get_phy_model(hw)) {
5505 case ICE_PHY_ETH56G:
5506 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd);
5507 case ICE_PHY_E82X:
5508 return ice_ptp_write_port_cmd_e82x(hw, port, cmd);
5509 default:
5510 return -EOPNOTSUPP;
5511 }
5512 }
5513
5514 /**
5515 * ice_ptp_one_port_cmd - Program one PHY port for a timer command
5516 * @hw: pointer to HW struct
5517 * @configured_port: the port that should execute the command
5518 * @configured_cmd: the command to be executed on the configured port
5519 *
5520 * Prepare one port for executing a timer command, while preparing all other
5521 * ports to ICE_PTP_NOP. This allows executing a command on a single port
5522 * while ensuring all other ports do not execute stale commands.
5523 *
5524 * Return:
5525 * * %0 - success
5526 * * %other - failed to write port command
5527 */
ice_ptp_one_port_cmd(struct ice_hw * hw,u8 configured_port,enum ice_ptp_tmr_cmd configured_cmd)5528 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
5529 enum ice_ptp_tmr_cmd configured_cmd)
5530 {
5531 u32 port;
5532
5533 for (port = 0; port < hw->ptp.num_lports; port++) {
5534 int err;
5535
5536 /* Program the configured port with the configured command,
5537 * program all other ports with ICE_PTP_NOP.
5538 */
5539 if (port == configured_port)
5540 err = ice_ptp_write_port_cmd(hw, port, configured_cmd);
5541 else
5542 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP);
5543
5544 if (err)
5545 return err;
5546 }
5547
5548 return 0;
5549 }
5550
5551 /**
5552 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command
5553 * @hw: pointer to HW struct
5554 * @cmd: the timer command to setup
5555 *
5556 * Prepare all PHY ports on this device for the requested timer command. For
5557 * some families this can be done in one shot, but for other families each
5558 * port must be configured individually.
5559 *
5560 * Return:
5561 * * %0 - success
5562 * * %other - failed to write port command
5563 */
ice_ptp_port_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5564 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5565 {
5566 u32 port;
5567
5568 /* PHY models which can program all ports simultaneously */
5569 switch (ice_get_phy_model(hw)) {
5570 case ICE_PHY_E810:
5571 return ice_ptp_port_cmd_e810(hw, cmd);
5572 default:
5573 break;
5574 }
5575
5576 /* PHY models which require programming each port separately */
5577 for (port = 0; port < hw->ptp.num_lports; port++) {
5578 int err;
5579
5580 err = ice_ptp_write_port_cmd(hw, port, cmd);
5581 if (err)
5582 return err;
5583 }
5584
5585 return 0;
5586 }
5587
5588 /**
5589 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
5590 * @hw: pointer to HW struct
5591 * @cmd: the command to issue
5592 *
5593 * Prepare the source timer and PHY timers and then trigger the requested
5594 * command. This causes the shadow registers previously written in preparation
5595 * for the command to be synchronously applied to both the source and PHY
5596 * timers.
5597 */
ice_ptp_tmr_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5598 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5599 {
5600 int err;
5601
5602 /* First, prepare the source timer */
5603 ice_ptp_src_cmd(hw, cmd);
5604
5605 /* Next, prepare the ports */
5606 err = ice_ptp_port_cmd(hw, cmd);
5607 if (err) {
5608 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",
5609 cmd, err);
5610 return err;
5611 }
5612
5613 /* Write the sync command register to drive both source and PHY timer
5614 * commands synchronously
5615 */
5616 ice_ptp_exec_tmr_cmd(hw);
5617
5618 return 0;
5619 }
5620
5621 /**
5622 * ice_ptp_init_time - Initialize device time to provided value
5623 * @hw: pointer to HW struct
5624 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)
5625 *
5626 * Initialize the device to the specified time provided. This requires a three
5627 * step process:
5628 *
5629 * 1) write the new init time to the source timer shadow registers
5630 * 2) write the new init time to the PHY timer shadow registers
5631 * 3) issue an init_time timer command to synchronously switch both the source
5632 * and port timers to the new init time value at the next clock cycle.
5633 */
ice_ptp_init_time(struct ice_hw * hw,u64 time)5634 int ice_ptp_init_time(struct ice_hw *hw, u64 time)
5635 {
5636 u8 tmr_idx;
5637 int err;
5638
5639 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5640
5641 /* Source timers */
5642 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time));
5643 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time));
5644 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
5645
5646 /* PHY timers */
5647 /* Fill Rx and Tx ports and send msg to PHY */
5648 switch (ice_get_phy_model(hw)) {
5649 case ICE_PHY_ETH56G:
5650 err = ice_ptp_prep_phy_time_eth56g(hw,
5651 (u32)(time & 0xFFFFFFFF));
5652 break;
5653 case ICE_PHY_E810:
5654 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
5655 break;
5656 case ICE_PHY_E82X:
5657 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF);
5658 break;
5659 default:
5660 err = -EOPNOTSUPP;
5661 }
5662
5663 if (err)
5664 return err;
5665
5666 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME);
5667 }
5668
5669 /**
5670 * ice_ptp_write_incval - Program PHC with new increment value
5671 * @hw: pointer to HW struct
5672 * @incval: Source timer increment value per clock cycle
5673 *
5674 * Program the PHC with a new increment value. This requires a three-step
5675 * process:
5676 *
5677 * 1) Write the increment value to the source timer shadow registers
5678 * 2) Write the increment value to the PHY timer shadow registers
5679 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both
5680 * the source and port timers to the new increment value at the next clock
5681 * cycle.
5682 */
ice_ptp_write_incval(struct ice_hw * hw,u64 incval)5683 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
5684 {
5685 u8 tmr_idx;
5686 int err;
5687
5688 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5689
5690 /* Shadow Adjust */
5691 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval));
5692 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval));
5693
5694 switch (ice_get_phy_model(hw)) {
5695 case ICE_PHY_ETH56G:
5696 err = ice_ptp_prep_phy_incval_eth56g(hw, incval);
5697 break;
5698 case ICE_PHY_E810:
5699 err = ice_ptp_prep_phy_incval_e810(hw, incval);
5700 break;
5701 case ICE_PHY_E82X:
5702 err = ice_ptp_prep_phy_incval_e82x(hw, incval);
5703 break;
5704 default:
5705 err = -EOPNOTSUPP;
5706 }
5707
5708 if (err)
5709 return err;
5710
5711 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL);
5712 }
5713
5714 /**
5715 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
5716 * @hw: pointer to HW struct
5717 * @incval: Source timer increment value per clock cycle
5718 *
5719 * Program a new PHC incval while holding the PTP semaphore.
5720 */
ice_ptp_write_incval_locked(struct ice_hw * hw,u64 incval)5721 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
5722 {
5723 int err;
5724
5725 if (!ice_ptp_lock(hw))
5726 return -EBUSY;
5727
5728 err = ice_ptp_write_incval(hw, incval);
5729
5730 ice_ptp_unlock(hw);
5731
5732 return err;
5733 }
5734
5735 /**
5736 * ice_ptp_adj_clock - Adjust PHC clock time atomically
5737 * @hw: pointer to HW struct
5738 * @adj: Adjustment in nanoseconds
5739 *
5740 * Perform an atomic adjustment of the PHC time by the specified number of
5741 * nanoseconds. This requires a three-step process:
5742 *
5743 * 1) Write the adjustment to the source timer shadow registers
5744 * 2) Write the adjustment to the PHY timer shadow registers
5745 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the
5746 * adjustment to both the source and port timers at the next clock cycle.
5747 */
ice_ptp_adj_clock(struct ice_hw * hw,s32 adj)5748 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)
5749 {
5750 u8 tmr_idx;
5751 int err;
5752
5753 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5754
5755 /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
5756 * For an ICE_PTP_ADJ_TIME command, this set of registers represents
5757 * the value to add to the clock time. It supports subtraction by
5758 * interpreting the value as a 2's complement integer.
5759 */
5760 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
5761 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
5762
5763 switch (ice_get_phy_model(hw)) {
5764 case ICE_PHY_ETH56G:
5765 err = ice_ptp_prep_phy_adj_eth56g(hw, adj);
5766 break;
5767 case ICE_PHY_E810:
5768 err = ice_ptp_prep_phy_adj_e810(hw, adj);
5769 break;
5770 case ICE_PHY_E82X:
5771 err = ice_ptp_prep_phy_adj_e82x(hw, adj);
5772 break;
5773 default:
5774 err = -EOPNOTSUPP;
5775 }
5776
5777 if (err)
5778 return err;
5779
5780 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME);
5781 }
5782
5783 /**
5784 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
5785 * @hw: pointer to the HW struct
5786 * @block: the block to read from
5787 * @idx: the timestamp index to read
5788 * @tstamp: on return, the 40bit timestamp value
5789 *
5790 * Read a 40bit timestamp value out of the timestamp block. For E822 devices,
5791 * the block is the quad to read from. For E810 devices, the block is the
5792 * logical port to read from.
5793 */
ice_read_phy_tstamp(struct ice_hw * hw,u8 block,u8 idx,u64 * tstamp)5794 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
5795 {
5796 switch (ice_get_phy_model(hw)) {
5797 case ICE_PHY_ETH56G:
5798 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp);
5799 case ICE_PHY_E810:
5800 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
5801 case ICE_PHY_E82X:
5802 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp);
5803 default:
5804 return -EOPNOTSUPP;
5805 }
5806 }
5807
5808 /**
5809 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
5810 * @hw: pointer to the HW struct
5811 * @block: the block to read from
5812 * @idx: the timestamp index to reset
5813 *
5814 * Clear a timestamp from the timestamp block, discarding its value without
5815 * returning it. This resets the memory status bit for the timestamp index
5816 * allowing it to be reused for another timestamp in the future.
5817 *
5818 * For E822 devices, the block number is the PHY quad to clear from. For E810
5819 * devices, the block number is the logical port to clear from.
5820 *
5821 * This function must only be called on a timestamp index whose valid bit is
5822 * set according to ice_get_phy_tx_tstamp_ready().
5823 */
ice_clear_phy_tstamp(struct ice_hw * hw,u8 block,u8 idx)5824 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
5825 {
5826 switch (ice_get_phy_model(hw)) {
5827 case ICE_PHY_ETH56G:
5828 return ice_clear_ptp_tstamp_eth56g(hw, block, idx);
5829 case ICE_PHY_E810:
5830 return ice_clear_phy_tstamp_e810(hw, block, idx);
5831 case ICE_PHY_E82X:
5832 return ice_clear_phy_tstamp_e82x(hw, block, idx);
5833 default:
5834 return -EOPNOTSUPP;
5835 }
5836 }
5837
5838 /**
5839 * ice_get_pf_c827_idx - find and return the C827 index for the current pf
5840 * @hw: pointer to the hw struct
5841 * @idx: index of the found C827 PHY
5842 * Return:
5843 * * 0 - success
5844 * * negative - failure
5845 */
ice_get_pf_c827_idx(struct ice_hw * hw,u8 * idx)5846 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx)
5847 {
5848 struct ice_aqc_get_link_topo cmd;
5849 u8 node_part_number;
5850 u16 node_handle;
5851 int status;
5852 u8 ctx;
5853
5854 if (hw->mac_type != ICE_MAC_E810)
5855 return -ENODEV;
5856
5857 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) {
5858 *idx = C827_0;
5859 return 0;
5860 }
5861
5862 memset(&cmd, 0, sizeof(cmd));
5863
5864 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S;
5865 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S;
5866 cmd.addr.topo_params.node_type_ctx = ctx;
5867
5868 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number,
5869 &node_handle);
5870 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827)
5871 return -ENOENT;
5872
5873 if (node_handle == E810C_QSFP_C827_0_HANDLE)
5874 *idx = C827_0;
5875 else if (node_handle == E810C_QSFP_C827_1_HANDLE)
5876 *idx = C827_1;
5877 else
5878 return -EIO;
5879
5880 return 0;
5881 }
5882
5883 /**
5884 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
5885 * @hw: pointer to the HW struct
5886 */
ice_ptp_reset_ts_memory(struct ice_hw * hw)5887 void ice_ptp_reset_ts_memory(struct ice_hw *hw)
5888 {
5889 switch (ice_get_phy_model(hw)) {
5890 case ICE_PHY_ETH56G:
5891 ice_ptp_reset_ts_memory_eth56g(hw);
5892 break;
5893 case ICE_PHY_E82X:
5894 ice_ptp_reset_ts_memory_e82x(hw);
5895 break;
5896 case ICE_PHY_E810:
5897 default:
5898 return;
5899 }
5900 }
5901
5902 /**
5903 * ice_ptp_init_phc - Initialize PTP hardware clock
5904 * @hw: pointer to the HW struct
5905 *
5906 * Perform the steps required to initialize the PTP hardware clock.
5907 */
ice_ptp_init_phc(struct ice_hw * hw)5908 int ice_ptp_init_phc(struct ice_hw *hw)
5909 {
5910 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5911
5912 /* Enable source clocks */
5913 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
5914
5915 /* Clear event err indications for auxiliary pins */
5916 (void)rd32(hw, GLTSYN_STAT(src_idx));
5917
5918 switch (ice_get_phy_model(hw)) {
5919 case ICE_PHY_ETH56G:
5920 return ice_ptp_init_phc_eth56g(hw);
5921 case ICE_PHY_E810:
5922 return ice_ptp_init_phc_e810(hw);
5923 case ICE_PHY_E82X:
5924 return ice_ptp_init_phc_e82x(hw);
5925 default:
5926 return -EOPNOTSUPP;
5927 }
5928 }
5929
5930 /**
5931 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
5932 * @hw: pointer to the HW struct
5933 * @block: the timestamp block to check
5934 * @tstamp_ready: storage for the PHY Tx memory status information
5935 *
5936 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value
5937 * which indicates which timestamps in the block may be captured. A set bit
5938 * means the timestamp can be read. An unset bit means the timestamp is not
5939 * ready and software should avoid reading the register.
5940 */
ice_get_phy_tx_tstamp_ready(struct ice_hw * hw,u8 block,u64 * tstamp_ready)5941 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
5942 {
5943 switch (ice_get_phy_model(hw)) {
5944 case ICE_PHY_ETH56G:
5945 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block,
5946 tstamp_ready);
5947 case ICE_PHY_E810:
5948 return ice_get_phy_tx_tstamp_ready_e810(hw, block,
5949 tstamp_ready);
5950 case ICE_PHY_E82X:
5951 return ice_get_phy_tx_tstamp_ready_e82x(hw, block,
5952 tstamp_ready);
5953 break;
5954 default:
5955 return -EOPNOTSUPP;
5956 }
5957 }
5958
5959 /**
5960 * ice_cgu_get_pin_desc_e823 - get pin description array
5961 * @hw: pointer to the hw struct
5962 * @input: if request is done against input or output pin
5963 * @size: number of inputs/outputs
5964 *
5965 * Return: pointer to pin description array associated to given hw.
5966 */
5967 static const struct ice_cgu_pin_desc *
ice_cgu_get_pin_desc_e823(struct ice_hw * hw,bool input,int * size)5968 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size)
5969 {
5970 static const struct ice_cgu_pin_desc *t;
5971
5972 if (hw->cgu_part_number ==
5973 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) {
5974 if (input) {
5975 t = ice_e823_zl_cgu_inputs;
5976 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs);
5977 } else {
5978 t = ice_e823_zl_cgu_outputs;
5979 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs);
5980 }
5981 } else if (hw->cgu_part_number ==
5982 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) {
5983 if (input) {
5984 t = ice_e823_si_cgu_inputs;
5985 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs);
5986 } else {
5987 t = ice_e823_si_cgu_outputs;
5988 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs);
5989 }
5990 } else {
5991 t = NULL;
5992 *size = 0;
5993 }
5994
5995 return t;
5996 }
5997
5998 /**
5999 * ice_cgu_get_pin_desc - get pin description array
6000 * @hw: pointer to the hw struct
6001 * @input: if request is done against input or output pins
6002 * @size: size of array returned by function
6003 *
6004 * Return: pointer to pin description array associated to given hw.
6005 */
6006 static const struct ice_cgu_pin_desc *
ice_cgu_get_pin_desc(struct ice_hw * hw,bool input,int * size)6007 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size)
6008 {
6009 const struct ice_cgu_pin_desc *t = NULL;
6010
6011 switch (hw->device_id) {
6012 case ICE_DEV_ID_E810C_SFP:
6013 if (input) {
6014 t = ice_e810t_sfp_cgu_inputs;
6015 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs);
6016 } else {
6017 t = ice_e810t_sfp_cgu_outputs;
6018 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs);
6019 }
6020 break;
6021 case ICE_DEV_ID_E810C_QSFP:
6022 if (input) {
6023 t = ice_e810t_qsfp_cgu_inputs;
6024 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs);
6025 } else {
6026 t = ice_e810t_qsfp_cgu_outputs;
6027 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs);
6028 }
6029 break;
6030 case ICE_DEV_ID_E823L_10G_BASE_T:
6031 case ICE_DEV_ID_E823L_1GBE:
6032 case ICE_DEV_ID_E823L_BACKPLANE:
6033 case ICE_DEV_ID_E823L_QSFP:
6034 case ICE_DEV_ID_E823L_SFP:
6035 case ICE_DEV_ID_E823C_10G_BASE_T:
6036 case ICE_DEV_ID_E823C_BACKPLANE:
6037 case ICE_DEV_ID_E823C_QSFP:
6038 case ICE_DEV_ID_E823C_SFP:
6039 case ICE_DEV_ID_E823C_SGMII:
6040 t = ice_cgu_get_pin_desc_e823(hw, input, size);
6041 break;
6042 default:
6043 break;
6044 }
6045
6046 return t;
6047 }
6048
6049 /**
6050 * ice_cgu_get_num_pins - get pin description array size
6051 * @hw: pointer to the hw struct
6052 * @input: if request is done against input or output pins
6053 *
6054 * Return: size of pin description array for given hw.
6055 */
ice_cgu_get_num_pins(struct ice_hw * hw,bool input)6056 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input)
6057 {
6058 const struct ice_cgu_pin_desc *t;
6059 int size;
6060
6061 t = ice_cgu_get_pin_desc(hw, input, &size);
6062 if (t)
6063 return size;
6064
6065 return 0;
6066 }
6067
6068 /**
6069 * ice_cgu_get_pin_type - get pin's type
6070 * @hw: pointer to the hw struct
6071 * @pin: pin index
6072 * @input: if request is done against input or output pin
6073 *
6074 * Return: type of a pin.
6075 */
ice_cgu_get_pin_type(struct ice_hw * hw,u8 pin,bool input)6076 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input)
6077 {
6078 const struct ice_cgu_pin_desc *t;
6079 int t_size;
6080
6081 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6082
6083 if (!t)
6084 return 0;
6085
6086 if (pin >= t_size)
6087 return 0;
6088
6089 return t[pin].type;
6090 }
6091
6092 /**
6093 * ice_cgu_get_pin_freq_supp - get pin's supported frequency
6094 * @hw: pointer to the hw struct
6095 * @pin: pin index
6096 * @input: if request is done against input or output pin
6097 * @num: output number of supported frequencies
6098 *
6099 * Get frequency supported number and array of supported frequencies.
6100 *
6101 * Return: array of supported frequencies for given pin.
6102 */
6103 struct dpll_pin_frequency *
ice_cgu_get_pin_freq_supp(struct ice_hw * hw,u8 pin,bool input,u8 * num)6104 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num)
6105 {
6106 const struct ice_cgu_pin_desc *t;
6107 int t_size;
6108
6109 *num = 0;
6110 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6111 if (!t)
6112 return NULL;
6113 if (pin >= t_size)
6114 return NULL;
6115 *num = t[pin].freq_supp_num;
6116
6117 return t[pin].freq_supp;
6118 }
6119
6120 /**
6121 * ice_cgu_get_pin_name - get pin's name
6122 * @hw: pointer to the hw struct
6123 * @pin: pin index
6124 * @input: if request is done against input or output pin
6125 *
6126 * Return:
6127 * * null terminated char array with name
6128 * * NULL in case of failure
6129 */
ice_cgu_get_pin_name(struct ice_hw * hw,u8 pin,bool input)6130 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input)
6131 {
6132 const struct ice_cgu_pin_desc *t;
6133 int t_size;
6134
6135 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6136
6137 if (!t)
6138 return NULL;
6139
6140 if (pin >= t_size)
6141 return NULL;
6142
6143 return t[pin].name;
6144 }
6145
6146 /**
6147 * ice_get_cgu_state - get the state of the DPLL
6148 * @hw: pointer to the hw struct
6149 * @dpll_idx: Index of internal DPLL unit
6150 * @last_dpll_state: last known state of DPLL
6151 * @pin: pointer to a buffer for returning currently active pin
6152 * @ref_state: reference clock state
6153 * @eec_mode: eec mode of the DPLL
6154 * @phase_offset: pointer to a buffer for returning phase offset
6155 * @dpll_state: state of the DPLL (output)
6156 *
6157 * This function will read the state of the DPLL(dpll_idx). Non-null
6158 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to
6159 * retrieve currently active pin, state, mode and phase_offset respectively.
6160 *
6161 * Return: state of the DPLL
6162 */
ice_get_cgu_state(struct ice_hw * hw,u8 dpll_idx,enum dpll_lock_status last_dpll_state,u8 * pin,u8 * ref_state,u8 * eec_mode,s64 * phase_offset,enum dpll_lock_status * dpll_state)6163 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
6164 enum dpll_lock_status last_dpll_state, u8 *pin,
6165 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
6166 enum dpll_lock_status *dpll_state)
6167 {
6168 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config;
6169 s64 hw_phase_offset;
6170 int status;
6171
6172 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state,
6173 &hw_dpll_state, &hw_config,
6174 &hw_phase_offset, &hw_eec_mode);
6175 if (status)
6176 return status;
6177
6178 if (pin)
6179 /* current ref pin in dpll_state_refsel_status_X register */
6180 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL;
6181 if (phase_offset)
6182 *phase_offset = hw_phase_offset;
6183 if (ref_state)
6184 *ref_state = hw_ref_state;
6185 if (eec_mode)
6186 *eec_mode = hw_eec_mode;
6187 if (!dpll_state)
6188 return 0;
6189
6190 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ
6191 * it would never return to FREERUN. This aligns to ITU-T G.781
6192 * Recommendation. We cannot report HOLDOVER as HO memory is cleared
6193 * while switching to another reference.
6194 * Only for situations where previous state was either: "LOCKED without
6195 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN.
6196 */
6197 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) {
6198 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY)
6199 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ;
6200 else
6201 *dpll_state = DPLL_LOCK_STATUS_LOCKED;
6202 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ ||
6203 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) {
6204 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER;
6205 } else {
6206 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED;
6207 }
6208
6209 return 0;
6210 }
6211
6212 /**
6213 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins
6214 * @hw: pointer to the hw struct
6215 * @base_idx: returns index of first recovered clock pin on device
6216 * @pin_num: returns number of recovered clock pins available on device
6217 *
6218 * Based on hw provide caller info about recovery clock pins available on the
6219 * board.
6220 *
6221 * Return:
6222 * * 0 - success, information is valid
6223 * * negative - failure, information is not valid
6224 */
ice_get_cgu_rclk_pin_info(struct ice_hw * hw,u8 * base_idx,u8 * pin_num)6225 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num)
6226 {
6227 u8 phy_idx;
6228 int ret;
6229
6230 switch (hw->device_id) {
6231 case ICE_DEV_ID_E810C_SFP:
6232 case ICE_DEV_ID_E810C_QSFP:
6233
6234 ret = ice_get_pf_c827_idx(hw, &phy_idx);
6235 if (ret)
6236 return ret;
6237 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN);
6238 *pin_num = ICE_E810_RCLK_PINS_NUM;
6239 ret = 0;
6240 break;
6241 case ICE_DEV_ID_E823L_10G_BASE_T:
6242 case ICE_DEV_ID_E823L_1GBE:
6243 case ICE_DEV_ID_E823L_BACKPLANE:
6244 case ICE_DEV_ID_E823L_QSFP:
6245 case ICE_DEV_ID_E823L_SFP:
6246 case ICE_DEV_ID_E823C_10G_BASE_T:
6247 case ICE_DEV_ID_E823C_BACKPLANE:
6248 case ICE_DEV_ID_E823C_QSFP:
6249 case ICE_DEV_ID_E823C_SFP:
6250 case ICE_DEV_ID_E823C_SGMII:
6251 *pin_num = ICE_E82X_RCLK_PINS_NUM;
6252 ret = 0;
6253 if (hw->cgu_part_number ==
6254 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032)
6255 *base_idx = ZL_REF1P;
6256 else if (hw->cgu_part_number ==
6257 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384)
6258 *base_idx = SI_REF1P;
6259 else
6260 ret = -ENODEV;
6261
6262 break;
6263 default:
6264 ret = -ENODEV;
6265 break;
6266 }
6267
6268 return ret;
6269 }
6270
6271 /**
6272 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities
6273 * @hw: pointer to the hw struct
6274 * @pin_id: id of a pin
6275 * @caps: capabilities to modify
6276 *
6277 * Return:
6278 * * 0 - success, state capabilities were modified
6279 * * negative - failure, capabilities were not modified
6280 */
ice_cgu_get_output_pin_state_caps(struct ice_hw * hw,u8 pin_id,unsigned long * caps)6281 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
6282 unsigned long *caps)
6283 {
6284 bool can_change = true;
6285
6286 switch (hw->device_id) {
6287 case ICE_DEV_ID_E810C_SFP:
6288 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3)
6289 can_change = false;
6290 break;
6291 case ICE_DEV_ID_E810C_QSFP:
6292 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4)
6293 can_change = false;
6294 break;
6295 case ICE_DEV_ID_E823L_10G_BASE_T:
6296 case ICE_DEV_ID_E823L_1GBE:
6297 case ICE_DEV_ID_E823L_BACKPLANE:
6298 case ICE_DEV_ID_E823L_QSFP:
6299 case ICE_DEV_ID_E823L_SFP:
6300 case ICE_DEV_ID_E823C_10G_BASE_T:
6301 case ICE_DEV_ID_E823C_BACKPLANE:
6302 case ICE_DEV_ID_E823C_QSFP:
6303 case ICE_DEV_ID_E823C_SFP:
6304 case ICE_DEV_ID_E823C_SGMII:
6305 if (hw->cgu_part_number ==
6306 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 &&
6307 pin_id == ZL_OUT2)
6308 can_change = false;
6309 else if (hw->cgu_part_number ==
6310 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 &&
6311 pin_id == SI_OUT1)
6312 can_change = false;
6313 break;
6314 default:
6315 return -EINVAL;
6316 }
6317 if (can_change)
6318 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
6319 else
6320 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
6321
6322 return 0;
6323 }
6324