1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2021, Intel Corporation. */
3
4 #include <linux/delay.h>
5 #include <linux/iopoll.h>
6 #include "ice_common.h"
7 #include "ice_ptp_hw.h"
8 #include "ice_ptp_consts.h"
9 #include "ice_cgu_regs.h"
10
11 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = {
12 DPLL_PIN_FREQUENCY_1PPS,
13 DPLL_PIN_FREQUENCY_10MHZ,
14 };
15
16 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = {
17 DPLL_PIN_FREQUENCY_1PPS,
18 };
19
20 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = {
21 DPLL_PIN_FREQUENCY_10MHZ,
22 };
23
24 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
31 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
32 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
33 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
34 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
36 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
37 };
38
39 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, },
47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, },
48 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
49 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
50 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
51 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
53 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
54 };
55
56 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {
57 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
58 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
59 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
60 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
61 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
62 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
63 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
64 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
65 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
66 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
67 };
68
69 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {
70 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
71 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
72 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
73 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
74 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
75 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
76 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
77 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
78 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
79 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
80 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
81 };
82
83 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {
84 { "NONE", SI_REF0P, 0, 0 },
85 { "NONE", SI_REF0N, 0, 0 },
86 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 },
87 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 },
88 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT,
89 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
90 { "NONE", SI_REF2N, 0, 0 },
91 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT,
92 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
93 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT,
94 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
95 };
96
97 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = {
98 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
99 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
100 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
101 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
102 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
103 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
104 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
105 };
106
107 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = {
108 { "NONE", ZL_REF0P, 0, 0 },
109 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT,
110 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
111 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 },
112 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 },
113 { "NONE", ZL_REF2P, 0, 0 },
114 { "NONE", ZL_REF2N, 0, 0 },
115 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT,
116 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
117 { "NONE", ZL_REF3N, 0, 0 },
118 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT,
119 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
120 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 },
121 };
122
123 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = {
124 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
125 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
126 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
127 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
128 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
129 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
130 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
131 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
132 { "NONE", ZL_OUT5, 0, 0 },
133 };
134
135 /* Low level functions for interacting with and managing the device clock used
136 * for the Precision Time Protocol.
137 *
138 * The ice hardware represents the current time using three registers:
139 *
140 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R
141 * +---------------+ +---------------+ +---------------+
142 * | 32 bits | | 32 bits | | 32 bits |
143 * +---------------+ +---------------+ +---------------+
144 *
145 * The registers are incremented every clock tick using a 40bit increment
146 * value defined over two registers:
147 *
148 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L
149 * +---------------+ +---------------+
150 * | 8 bit s | | 32 bits |
151 * +---------------+ +---------------+
152 *
153 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L
154 * registers every clock source tick. Depending on the specific device
155 * configuration, the clock source frequency could be one of a number of
156 * values.
157 *
158 * For E810 devices, the increment frequency is 812.5 MHz
159 *
160 * For E822 devices the clock can be derived from different sources, and the
161 * increment has an effective frequency of one of the following:
162 * - 823.4375 MHz
163 * - 783.36 MHz
164 * - 796.875 MHz
165 * - 816 MHz
166 * - 830.078125 MHz
167 * - 783.36 MHz
168 *
169 * The hardware captures timestamps in the PHY for incoming packets, and for
170 * outgoing packets on request. To support this, the PHY maintains a timer
171 * that matches the lower 64 bits of the global source timer.
172 *
173 * In order to ensure that the PHY timers and the source timer are equivalent,
174 * shadow registers are used to prepare the desired initial values. A special
175 * sync command is issued to trigger copying from the shadow registers into
176 * the appropriate source and PHY registers simultaneously.
177 *
178 * The driver supports devices which have different PHYs with subtly different
179 * mechanisms to program and control the timers. We divide the devices into
180 * families named after the first major device, E810 and similar devices, and
181 * E822 and similar devices.
182 *
183 * - E822 based devices have additional support for fine grained Vernier
184 * calibration which requires significant setup
185 * - The layout of timestamp data in the PHY register blocks is different
186 * - The way timer synchronization commands are issued is different.
187 *
188 * To support this, very low level functions have an e810 or e822 suffix
189 * indicating what type of device they work on. Higher level abstractions for
190 * tasks that can be done on both devices do not have the suffix and will
191 * correctly look up the appropriate low level function when running.
192 *
193 * Functions which only make sense on a single device family may not have
194 * a suitable generic implementation
195 */
196
197 /**
198 * ice_get_ptp_src_clock_index - determine source clock index
199 * @hw: pointer to HW struct
200 *
201 * Determine the source clock index currently in use, based on device
202 * capabilities reported during initialization.
203 */
ice_get_ptp_src_clock_index(struct ice_hw * hw)204 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw)
205 {
206 return hw->func_caps.ts_func_info.tmr_index_assoc;
207 }
208
209 /**
210 * ice_ptp_read_src_incval - Read source timer increment value
211 * @hw: pointer to HW struct
212 *
213 * Read the increment value of the source timer and return it.
214 */
ice_ptp_read_src_incval(struct ice_hw * hw)215 static u64 ice_ptp_read_src_incval(struct ice_hw *hw)
216 {
217 u32 lo, hi;
218 u8 tmr_idx;
219
220 tmr_idx = ice_get_ptp_src_clock_index(hw);
221
222 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
223 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
224
225 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
226 }
227
228 /**
229 * ice_read_cgu_reg_e82x - Read a CGU register
230 * @hw: pointer to the HW struct
231 * @addr: Register address to read
232 * @val: storage for register value read
233 *
234 * Read the contents of a register of the Clock Generation Unit. Only
235 * applicable to E822 devices.
236 *
237 * Return: 0 on success, other error codes when failed to read from CGU
238 */
ice_read_cgu_reg_e82x(struct ice_hw * hw,u32 addr,u32 * val)239 static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
240 {
241 struct ice_sbq_msg_input cgu_msg = {
242 .opcode = ice_sbq_msg_rd,
243 .dest_dev = cgu,
244 .msg_addr_low = addr
245 };
246 int err;
247
248 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD);
249 if (err) {
250 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
251 addr, err);
252 return err;
253 }
254
255 *val = cgu_msg.data;
256
257 return 0;
258 }
259
260 /**
261 * ice_write_cgu_reg_e82x - Write a CGU register
262 * @hw: pointer to the HW struct
263 * @addr: Register address to write
264 * @val: value to write into the register
265 *
266 * Write the specified value to a register of the Clock Generation Unit. Only
267 * applicable to E822 devices.
268 *
269 * Return: 0 on success, other error codes when failed to write to CGU
270 */
ice_write_cgu_reg_e82x(struct ice_hw * hw,u32 addr,u32 val)271 static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)
272 {
273 struct ice_sbq_msg_input cgu_msg = {
274 .opcode = ice_sbq_msg_wr,
275 .dest_dev = cgu,
276 .msg_addr_low = addr,
277 .data = val
278 };
279 int err;
280
281 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD);
282 if (err) {
283 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
284 addr, err);
285 return err;
286 }
287
288 return err;
289 }
290
291 /**
292 * ice_clk_freq_str - Convert time_ref_freq to string
293 * @clk_freq: Clock frequency
294 *
295 * Return: specified TIME_REF clock frequency converted to a string
296 */
ice_clk_freq_str(enum ice_time_ref_freq clk_freq)297 static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq)
298 {
299 switch (clk_freq) {
300 case ICE_TIME_REF_FREQ_25_000:
301 return "25 MHz";
302 case ICE_TIME_REF_FREQ_122_880:
303 return "122.88 MHz";
304 case ICE_TIME_REF_FREQ_125_000:
305 return "125 MHz";
306 case ICE_TIME_REF_FREQ_153_600:
307 return "153.6 MHz";
308 case ICE_TIME_REF_FREQ_156_250:
309 return "156.25 MHz";
310 case ICE_TIME_REF_FREQ_245_760:
311 return "245.76 MHz";
312 default:
313 return "Unknown";
314 }
315 }
316
317 /**
318 * ice_clk_src_str - Convert time_ref_src to string
319 * @clk_src: Clock source
320 *
321 * Return: specified clock source converted to its string name
322 */
ice_clk_src_str(enum ice_clk_src clk_src)323 static const char *ice_clk_src_str(enum ice_clk_src clk_src)
324 {
325 switch (clk_src) {
326 case ICE_CLK_SRC_TCXO:
327 return "TCXO";
328 case ICE_CLK_SRC_TIME_REF:
329 return "TIME_REF";
330 default:
331 return "Unknown";
332 }
333 }
334
335 /**
336 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
337 * @hw: pointer to the HW struct
338 * @clk_freq: Clock frequency to program
339 * @clk_src: Clock source to select (TIME_REF, or TCXO)
340 *
341 * Configure the Clock Generation Unit with the desired clock frequency and
342 * time reference, enabling the PLL which drives the PTP hardware clock.
343 *
344 * Return:
345 * * %0 - success
346 * * %-EINVAL - input parameters are incorrect
347 * * %-EBUSY - failed to lock TS PLL
348 * * %other - CGU read/write failure
349 */
ice_cfg_cgu_pll_e82x(struct ice_hw * hw,enum ice_time_ref_freq clk_freq,enum ice_clk_src clk_src)350 static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
351 enum ice_time_ref_freq clk_freq,
352 enum ice_clk_src clk_src)
353 {
354 union tspll_ro_bwm_lf bwm_lf;
355 union nac_cgu_dword19 dw19;
356 union nac_cgu_dword22 dw22;
357 union nac_cgu_dword24 dw24;
358 union nac_cgu_dword9 dw9;
359 int err;
360
361 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
362 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
363 clk_freq);
364 return -EINVAL;
365 }
366
367 if (clk_src >= NUM_ICE_CLK_SRC) {
368 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
369 clk_src);
370 return -EINVAL;
371 }
372
373 if (clk_src == ICE_CLK_SRC_TCXO &&
374 clk_freq != ICE_TIME_REF_FREQ_25_000) {
375 dev_warn(ice_hw_to_dev(hw),
376 "TCXO only supports 25 MHz frequency\n");
377 return -EINVAL;
378 }
379
380 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
381 if (err)
382 return err;
383
384 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
385 if (err)
386 return err;
387
388 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
389 if (err)
390 return err;
391
392 /* Log the current clock configuration */
393 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
394 str_enabled_disabled(dw24.ts_pll_enable),
395 ice_clk_src_str(dw24.time_ref_sel),
396 ice_clk_freq_str(dw9.time_ref_freq_sel),
397 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
398
399 /* Disable the PLL before changing the clock source or frequency */
400 if (dw24.ts_pll_enable) {
401 dw24.ts_pll_enable = 0;
402
403 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
404 if (err)
405 return err;
406 }
407
408 /* Set the frequency */
409 dw9.time_ref_freq_sel = clk_freq;
410 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
411 if (err)
412 return err;
413
414 /* Configure the TS PLL feedback divisor */
415 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
416 if (err)
417 return err;
418
419 dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
420 dw19.tspll_ndivratio = 1;
421
422 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
423 if (err)
424 return err;
425
426 /* Configure the TS PLL post divisor */
427 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
428 if (err)
429 return err;
430
431 dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
432 dw22.time1588clk_sel_div2 = 0;
433
434 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
435 if (err)
436 return err;
437
438 /* Configure the TS PLL pre divisor and clock source */
439 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
440 if (err)
441 return err;
442
443 dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
444 dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
445 dw24.time_ref_sel = clk_src;
446
447 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
448 if (err)
449 return err;
450
451 /* Finally, enable the PLL */
452 dw24.ts_pll_enable = 1;
453
454 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
455 if (err)
456 return err;
457
458 /* Wait to verify if the PLL locks */
459 usleep_range(1000, 5000);
460
461 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
462 if (err)
463 return err;
464
465 if (!bwm_lf.plllock_true_lock_cri) {
466 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
467 return -EBUSY;
468 }
469
470 /* Log the current clock configuration */
471 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
472 str_enabled_disabled(dw24.ts_pll_enable),
473 ice_clk_src_str(dw24.time_ref_sel),
474 ice_clk_freq_str(dw9.time_ref_freq_sel),
475 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
476
477 return 0;
478 }
479
480 /**
481 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C
482 * @hw: pointer to the HW struct
483 * @clk_freq: Clock frequency to program
484 * @clk_src: Clock source to select (TIME_REF, or TCXO)
485 *
486 * Configure the Clock Generation Unit with the desired clock frequency and
487 * time reference, enabling the PLL which drives the PTP hardware clock.
488 *
489 * Return:
490 * * %0 - success
491 * * %-EINVAL - input parameters are incorrect
492 * * %-EBUSY - failed to lock TS PLL
493 * * %other - CGU read/write failure
494 */
ice_cfg_cgu_pll_e825c(struct ice_hw * hw,enum ice_time_ref_freq clk_freq,enum ice_clk_src clk_src)495 static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
496 enum ice_time_ref_freq clk_freq,
497 enum ice_clk_src clk_src)
498 {
499 union tspll_ro_lock_e825c ro_lock;
500 union nac_cgu_dword16_e825c dw16;
501 union nac_cgu_dword23_e825c dw23;
502 union nac_cgu_dword19 dw19;
503 union nac_cgu_dword22 dw22;
504 union nac_cgu_dword24 dw24;
505 union nac_cgu_dword9 dw9;
506 int err;
507
508 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
509 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
510 clk_freq);
511 return -EINVAL;
512 }
513
514 if (clk_src >= NUM_ICE_CLK_SRC) {
515 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
516 clk_src);
517 return -EINVAL;
518 }
519
520 if (clk_src == ICE_CLK_SRC_TCXO &&
521 clk_freq != ICE_TIME_REF_FREQ_156_250) {
522 dev_warn(ice_hw_to_dev(hw),
523 "TCXO only supports 156.25 MHz frequency\n");
524 return -EINVAL;
525 }
526
527 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
528 if (err)
529 return err;
530
531 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
532 if (err)
533 return err;
534
535 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val);
536 if (err)
537 return err;
538
539 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
540 if (err)
541 return err;
542
543 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
544 if (err)
545 return err;
546
547 /* Log the current clock configuration */
548 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
549 str_enabled_disabled(dw24.ts_pll_enable),
550 ice_clk_src_str(dw23.time_ref_sel),
551 ice_clk_freq_str(dw9.time_ref_freq_sel),
552 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
553
554 /* Disable the PLL before changing the clock source or frequency */
555 if (dw23.ts_pll_enable) {
556 dw23.ts_pll_enable = 0;
557
558 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C,
559 dw23.val);
560 if (err)
561 return err;
562 }
563
564 /* Set the frequency */
565 dw9.time_ref_freq_sel = clk_freq;
566
567 /* Enable the correct receiver */
568 if (clk_src == ICE_CLK_SRC_TCXO) {
569 dw9.time_ref_en = 0;
570 dw9.clk_eref0_en = 1;
571 } else {
572 dw9.time_ref_en = 1;
573 dw9.clk_eref0_en = 0;
574 }
575 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
576 if (err)
577 return err;
578
579 /* Choose the referenced frequency */
580 dw16.tspll_ck_refclkfreq =
581 e825c_cgu_params[clk_freq].tspll_ck_refclkfreq;
582 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val);
583 if (err)
584 return err;
585
586 /* Configure the TS PLL feedback divisor */
587 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
588 if (err)
589 return err;
590
591 dw19.tspll_fbdiv_intgr =
592 e825c_cgu_params[clk_freq].tspll_fbdiv_intgr;
593 dw19.tspll_ndivratio =
594 e825c_cgu_params[clk_freq].tspll_ndivratio;
595
596 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
597 if (err)
598 return err;
599
600 /* Configure the TS PLL post divisor */
601 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
602 if (err)
603 return err;
604
605 /* These two are constant for E825C */
606 dw22.time1588clk_div = 5;
607 dw22.time1588clk_sel_div2 = 0;
608
609 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
610 if (err)
611 return err;
612
613 /* Configure the TS PLL pre divisor and clock source */
614 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
615 if (err)
616 return err;
617
618 dw23.ref1588_ck_div =
619 e825c_cgu_params[clk_freq].ref1588_ck_div;
620 dw23.time_ref_sel = clk_src;
621
622 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
623 if (err)
624 return err;
625
626 dw24.tspll_fbdiv_frac =
627 e825c_cgu_params[clk_freq].tspll_fbdiv_frac;
628
629 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
630 if (err)
631 return err;
632
633 /* Finally, enable the PLL */
634 dw23.ts_pll_enable = 1;
635
636 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
637 if (err)
638 return err;
639
640 /* Wait to verify if the PLL locks */
641 usleep_range(1000, 5000);
642
643 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
644 if (err)
645 return err;
646
647 if (!ro_lock.plllock_true_lock_cri) {
648 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
649 return -EBUSY;
650 }
651
652 /* Log the current clock configuration */
653 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
654 str_enabled_disabled(dw24.ts_pll_enable),
655 ice_clk_src_str(dw23.time_ref_sel),
656 ice_clk_freq_str(dw9.time_ref_freq_sel),
657 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
658
659 return 0;
660 }
661
662 #define ICE_ONE_PPS_OUT_AMP_MAX 3
663
664 /**
665 * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU
666 * @hw: pointer to the HW struct
667 * @enable: true to enable 1PPS output, false to disable it
668 *
669 * Return: 0 on success, other negative error code when CGU read/write failed
670 */
ice_cgu_cfg_pps_out(struct ice_hw * hw,bool enable)671 int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable)
672 {
673 union nac_cgu_dword9 dw9;
674 int err;
675
676 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
677 if (err)
678 return err;
679
680 dw9.one_pps_out_en = enable;
681 dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
682 return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
683 }
684
685 /**
686 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits
687 * @hw: pointer to the HW struct
688 *
689 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
690 * losing TS PLL lock, but always show current state.
691 *
692 * Return: 0 on success, other error codes when failed to read/write CGU
693 */
ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw * hw)694 static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw)
695 {
696 union tspll_cntr_bist_settings cntr_bist;
697 int err;
698
699 err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
700 &cntr_bist.val);
701 if (err)
702 return err;
703
704 /* Disable sticky lock detection so lock err reported is accurate */
705 cntr_bist.i_plllock_sel_0 = 0;
706 cntr_bist.i_plllock_sel_1 = 0;
707
708 return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
709 cntr_bist.val);
710 }
711
712 /**
713 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C
714 * @hw: pointer to the HW struct
715 *
716 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
717 * losing TS PLL lock, but always show current state.
718 *
719 * Return: 0 on success, other error codes when failed to read/write CGU
720 */
ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw * hw)721 static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw)
722 {
723 union tspll_bw_tdc_e825c bw_tdc;
724 int err;
725
726 err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
727 if (err)
728 return err;
729
730 bw_tdc.i_plllock_sel_1_0 = 0;
731
732 return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
733 }
734
735 /**
736 * ice_init_cgu_e82x - Initialize CGU with settings from firmware
737 * @hw: pointer to the HW structure
738 *
739 * Initialize the Clock Generation Unit of the E822 device.
740 *
741 * Return: 0 on success, other error codes when failed to read/write/cfg CGU
742 */
ice_init_cgu_e82x(struct ice_hw * hw)743 static int ice_init_cgu_e82x(struct ice_hw *hw)
744 {
745 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
746 int err;
747
748 /* Disable sticky lock detection so lock err reported is accurate */
749 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
750 err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw);
751 else
752 err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw);
753 if (err)
754 return err;
755
756 /* Configure the CGU PLL using the parameters from the function
757 * capabilities.
758 */
759 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
760 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref,
761 (enum ice_clk_src)ts_info->clk_src);
762 else
763 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref,
764 (enum ice_clk_src)ts_info->clk_src);
765
766 return err;
767 }
768
769 /**
770 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value
771 * @hw: pointer to HW struct
772 * @cmd: Timer command
773 *
774 * Return: the source timer command register value for the given PTP timer
775 * command.
776 */
ice_ptp_tmr_cmd_to_src_reg(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)777 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw,
778 enum ice_ptp_tmr_cmd cmd)
779 {
780 u32 cmd_val, tmr_idx;
781
782 switch (cmd) {
783 case ICE_PTP_INIT_TIME:
784 cmd_val = GLTSYN_CMD_INIT_TIME;
785 break;
786 case ICE_PTP_INIT_INCVAL:
787 cmd_val = GLTSYN_CMD_INIT_INCVAL;
788 break;
789 case ICE_PTP_ADJ_TIME:
790 cmd_val = GLTSYN_CMD_ADJ_TIME;
791 break;
792 case ICE_PTP_ADJ_TIME_AT_TIME:
793 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
794 break;
795 case ICE_PTP_NOP:
796 case ICE_PTP_READ_TIME:
797 cmd_val = GLTSYN_CMD_READ_TIME;
798 break;
799 default:
800 dev_warn(ice_hw_to_dev(hw),
801 "Ignoring unrecognized timer command %u\n", cmd);
802 cmd_val = 0;
803 }
804
805 tmr_idx = ice_get_ptp_src_clock_index(hw);
806
807 return tmr_idx << SEL_CPK_SRC | cmd_val;
808 }
809
810 /**
811 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value
812 * @hw: pointer to HW struct
813 * @cmd: Timer command
814 *
815 * Note that some hardware families use a different command register value for
816 * the PHY ports, while other hardware families use the same register values
817 * as the source timer.
818 *
819 * Return: the PHY port timer command register value for the given PTP timer
820 * command.
821 */
ice_ptp_tmr_cmd_to_port_reg(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)822 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw,
823 enum ice_ptp_tmr_cmd cmd)
824 {
825 u32 cmd_val, tmr_idx;
826
827 /* Certain hardware families share the same register values for the
828 * port register and source timer register.
829 */
830 switch (hw->mac_type) {
831 case ICE_MAC_E810:
832 case ICE_MAC_E830:
833 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810;
834 default:
835 break;
836 }
837
838 switch (cmd) {
839 case ICE_PTP_INIT_TIME:
840 cmd_val = PHY_CMD_INIT_TIME;
841 break;
842 case ICE_PTP_INIT_INCVAL:
843 cmd_val = PHY_CMD_INIT_INCVAL;
844 break;
845 case ICE_PTP_ADJ_TIME:
846 cmd_val = PHY_CMD_ADJ_TIME;
847 break;
848 case ICE_PTP_ADJ_TIME_AT_TIME:
849 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME;
850 break;
851 case ICE_PTP_READ_TIME:
852 cmd_val = PHY_CMD_READ_TIME;
853 break;
854 case ICE_PTP_NOP:
855 cmd_val = 0;
856 break;
857 default:
858 dev_warn(ice_hw_to_dev(hw),
859 "Ignoring unrecognized timer command %u\n", cmd);
860 cmd_val = 0;
861 }
862
863 tmr_idx = ice_get_ptp_src_clock_index(hw);
864
865 return tmr_idx << SEL_PHY_SRC | cmd_val;
866 }
867
868 /**
869 * ice_ptp_src_cmd - Prepare source timer for a timer command
870 * @hw: pointer to HW structure
871 * @cmd: Timer command
872 *
873 * Prepare the source timer for an upcoming timer sync command.
874 */
ice_ptp_src_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)875 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
876 {
877 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd);
878
879 wr32(hw, GLTSYN_CMD, cmd_val);
880 }
881
882 /**
883 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
884 * @hw: pointer to HW struct
885 *
886 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
887 * write immediately. This triggers the hardware to begin executing all of the
888 * source and PHY timer commands synchronously.
889 */
ice_ptp_exec_tmr_cmd(struct ice_hw * hw)890 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
891 {
892 struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
893
894 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock);
895 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
896 ice_flush(hw);
897 }
898
899 /**
900 * ice_ptp_cfg_sync_delay - Configure PHC to PHY synchronization delay
901 * @hw: pointer to HW struct
902 * @delay: delay between PHC and PHY SYNC command execution in nanoseconds
903 */
ice_ptp_cfg_sync_delay(const struct ice_hw * hw,u32 delay)904 static void ice_ptp_cfg_sync_delay(const struct ice_hw *hw, u32 delay)
905 {
906 wr32(hw, GLTSYN_SYNC_DLAY, delay);
907 ice_flush(hw);
908 }
909
910 /* 56G PHY device functions
911 *
912 * The following functions operate on devices with the ETH 56G PHY.
913 */
914
915 /**
916 * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number
917 * @hw: pointer to the HW struct
918 * @port: destination port
919 *
920 * Return: destination sideband queue PHY device.
921 */
ice_ptp_get_dest_dev_e825(struct ice_hw * hw,u8 port)922 static enum ice_sbq_msg_dev ice_ptp_get_dest_dev_e825(struct ice_hw *hw,
923 u8 port)
924 {
925 /* On a single complex E825, PHY 0 is always destination device phy_0
926 * and PHY 1 is phy_0_peer.
927 */
928 if (port >= hw->ptp.ports_per_phy)
929 return eth56g_phy_1;
930 else
931 return eth56g_phy_0;
932 }
933
934 /**
935 * ice_write_phy_eth56g - Write a PHY port register
936 * @hw: pointer to the HW struct
937 * @port: destination port
938 * @addr: PHY register address
939 * @val: Value to write
940 *
941 * Return: 0 on success, other error codes when failed to write to PHY
942 */
ice_write_phy_eth56g(struct ice_hw * hw,u8 port,u32 addr,u32 val)943 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val)
944 {
945 struct ice_sbq_msg_input msg = {
946 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port),
947 .opcode = ice_sbq_msg_wr,
948 .msg_addr_low = lower_16_bits(addr),
949 .msg_addr_high = upper_16_bits(addr),
950 .data = val
951 };
952 int err;
953
954 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
955 if (err)
956 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
957 err);
958
959 return err;
960 }
961
962 /**
963 * ice_read_phy_eth56g - Read a PHY port register
964 * @hw: pointer to the HW struct
965 * @port: destination port
966 * @addr: PHY register address
967 * @val: Value to write
968 *
969 * Return: 0 on success, other error codes when failed to read from PHY
970 */
ice_read_phy_eth56g(struct ice_hw * hw,u8 port,u32 addr,u32 * val)971 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 *val)
972 {
973 struct ice_sbq_msg_input msg = {
974 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port),
975 .opcode = ice_sbq_msg_rd,
976 .msg_addr_low = lower_16_bits(addr),
977 .msg_addr_high = upper_16_bits(addr)
978 };
979 int err;
980
981 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
982 if (err)
983 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
984 err);
985 else
986 *val = msg.data;
987
988 return err;
989 }
990
991 /**
992 * ice_phy_res_address_eth56g - Calculate a PHY port register address
993 * @hw: pointer to the HW struct
994 * @lane: Lane number to be written
995 * @res_type: resource type (register/memory)
996 * @offset: Offset from PHY port register base
997 * @addr: The result address
998 *
999 * Return:
1000 * * %0 - success
1001 * * %EINVAL - invalid port number or resource type
1002 */
ice_phy_res_address_eth56g(struct ice_hw * hw,u8 lane,enum eth56g_res_type res_type,u32 offset,u32 * addr)1003 static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane,
1004 enum eth56g_res_type res_type,
1005 u32 offset,
1006 u32 *addr)
1007 {
1008 if (res_type >= NUM_ETH56G_PHY_RES)
1009 return -EINVAL;
1010
1011 /* Lanes 4..7 are in fact 0..3 on a second PHY */
1012 lane %= hw->ptp.ports_per_phy;
1013 *addr = eth56g_phy_res[res_type].base_addr +
1014 lane * eth56g_phy_res[res_type].step + offset;
1015
1016 return 0;
1017 }
1018
1019 /**
1020 * ice_write_port_eth56g - Write a PHY port register
1021 * @hw: pointer to the HW struct
1022 * @offset: PHY register offset
1023 * @port: Port number
1024 * @val: Value to write
1025 * @res_type: resource type (register/memory)
1026 *
1027 * Return:
1028 * * %0 - success
1029 * * %EINVAL - invalid port number or resource type
1030 * * %other - failed to write to PHY
1031 */
ice_write_port_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val,enum eth56g_res_type res_type)1032 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1033 u32 val, enum eth56g_res_type res_type)
1034 {
1035 u32 addr;
1036 int err;
1037
1038 if (port >= hw->ptp.num_lports)
1039 return -EINVAL;
1040
1041 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr);
1042 if (err)
1043 return err;
1044
1045 return ice_write_phy_eth56g(hw, port, addr, val);
1046 }
1047
1048 /**
1049 * ice_read_port_eth56g - Read a PHY port register
1050 * @hw: pointer to the HW struct
1051 * @offset: PHY register offset
1052 * @port: Port number
1053 * @val: Value to write
1054 * @res_type: resource type (register/memory)
1055 *
1056 * Return:
1057 * * %0 - success
1058 * * %EINVAL - invalid port number or resource type
1059 * * %other - failed to read from PHY
1060 */
ice_read_port_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 * val,enum eth56g_res_type res_type)1061 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1062 u32 *val, enum eth56g_res_type res_type)
1063 {
1064 u32 addr;
1065 int err;
1066
1067 if (port >= hw->ptp.num_lports)
1068 return -EINVAL;
1069
1070 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr);
1071 if (err)
1072 return err;
1073
1074 return ice_read_phy_eth56g(hw, port, addr, val);
1075 }
1076
1077 /**
1078 * ice_write_ptp_reg_eth56g - Write a PHY port register
1079 * @hw: pointer to the HW struct
1080 * @port: Port number to be written
1081 * @offset: Offset from PHY port register base
1082 * @val: Value to write
1083 *
1084 * Return:
1085 * * %0 - success
1086 * * %EINVAL - invalid port number or resource type
1087 * * %other - failed to write to PHY
1088 */
ice_write_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 val)1089 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1090 u32 val)
1091 {
1092 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
1093 }
1094
1095 /**
1096 * ice_write_mac_reg_eth56g - Write a MAC PHY port register
1097 * parameter
1098 * @hw: pointer to the HW struct
1099 * @port: Port number to be written
1100 * @offset: Offset from PHY port register base
1101 * @val: Value to write
1102 *
1103 * Return:
1104 * * %0 - success
1105 * * %EINVAL - invalid port number or resource type
1106 * * %other - failed to write to PHY
1107 */
ice_write_mac_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)1108 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1109 u32 val)
1110 {
1111 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
1112 }
1113
1114 /**
1115 * ice_write_xpcs_reg_eth56g - Write a PHY port register
1116 * @hw: pointer to the HW struct
1117 * @port: Port number to be written
1118 * @offset: Offset from PHY port register base
1119 * @val: Value to write
1120 *
1121 * Return:
1122 * * %0 - success
1123 * * %EINVAL - invalid port number or resource type
1124 * * %other - failed to write to PHY
1125 */
ice_write_xpcs_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)1126 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1127 u32 val)
1128 {
1129 return ice_write_port_eth56g(hw, port, offset, val,
1130 ETH56G_PHY_REG_XPCS);
1131 }
1132
1133 /**
1134 * ice_read_ptp_reg_eth56g - Read a PHY port register
1135 * @hw: pointer to the HW struct
1136 * @port: Port number to be read
1137 * @offset: Offset from PHY port register base
1138 * @val: Pointer to the value to read (out param)
1139 *
1140 * Return:
1141 * * %0 - success
1142 * * %EINVAL - invalid port number or resource type
1143 * * %other - failed to read from PHY
1144 */
ice_read_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1145 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1146 u32 *val)
1147 {
1148 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
1149 }
1150
1151 /**
1152 * ice_read_mac_reg_eth56g - Read a PHY port register
1153 * @hw: pointer to the HW struct
1154 * @port: Port number to be read
1155 * @offset: Offset from PHY port register base
1156 * @val: Pointer to the value to read (out param)
1157 *
1158 * Return:
1159 * * %0 - success
1160 * * %EINVAL - invalid port number or resource type
1161 * * %other - failed to read from PHY
1162 */
ice_read_mac_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1163 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1164 u32 *val)
1165 {
1166 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
1167 }
1168
1169 /**
1170 * ice_read_gpcs_reg_eth56g - Read a PHY port register
1171 * @hw: pointer to the HW struct
1172 * @port: Port number to be read
1173 * @offset: Offset from PHY port register base
1174 * @val: Pointer to the value to read (out param)
1175 *
1176 * Return:
1177 * * %0 - success
1178 * * %EINVAL - invalid port number or resource type
1179 * * %other - failed to read from PHY
1180 */
ice_read_gpcs_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1181 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1182 u32 *val)
1183 {
1184 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS);
1185 }
1186
1187 /**
1188 * ice_read_port_mem_eth56g - Read a PHY port memory location
1189 * @hw: pointer to the HW struct
1190 * @port: Port number to be read
1191 * @offset: Offset from PHY port register base
1192 * @val: Pointer to the value to read (out param)
1193 *
1194 * Return:
1195 * * %0 - success
1196 * * %EINVAL - invalid port number or resource type
1197 * * %other - failed to read from PHY
1198 */
ice_read_port_mem_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1199 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1200 u32 *val)
1201 {
1202 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
1203 }
1204
1205 /**
1206 * ice_write_port_mem_eth56g - Write a PHY port memory location
1207 * @hw: pointer to the HW struct
1208 * @port: Port number to be read
1209 * @offset: Offset from PHY port register base
1210 * @val: Pointer to the value to read (out param)
1211 *
1212 * Return:
1213 * * %0 - success
1214 * * %EINVAL - invalid port number or resource type
1215 * * %other - failed to write to PHY
1216 */
ice_write_port_mem_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 val)1217 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1218 u32 val)
1219 {
1220 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
1221 }
1222
1223 /**
1224 * ice_write_quad_ptp_reg_eth56g - Write a PHY quad register
1225 * @hw: pointer to the HW struct
1226 * @offset: PHY register offset
1227 * @port: Port number
1228 * @val: Value to write
1229 *
1230 * Return:
1231 * * %0 - success
1232 * * %EIO - invalid port number or resource type
1233 * * %other - failed to write to PHY
1234 */
ice_write_quad_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)1235 static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
1236 u32 offset, u32 val)
1237 {
1238 u32 addr;
1239
1240 if (port >= hw->ptp.num_lports)
1241 return -EIO;
1242
1243 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
1244
1245 return ice_write_phy_eth56g(hw, port, addr, val);
1246 }
1247
1248 /**
1249 * ice_read_quad_ptp_reg_eth56g - Read a PHY quad register
1250 * @hw: pointer to the HW struct
1251 * @offset: PHY register offset
1252 * @port: Port number
1253 * @val: Value to read
1254 *
1255 * Return:
1256 * * %0 - success
1257 * * %EIO - invalid port number or resource type
1258 * * %other - failed to read from PHY
1259 */
ice_read_quad_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 * val)1260 static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
1261 u32 offset, u32 *val)
1262 {
1263 u32 addr;
1264
1265 if (port >= hw->ptp.num_lports)
1266 return -EIO;
1267
1268 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
1269
1270 return ice_read_phy_eth56g(hw, port, addr, val);
1271 }
1272
1273 /**
1274 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
1275 * @low_addr: the low address to check
1276 * @high_addr: on return, contains the high address of the 64bit register
1277 *
1278 * Write the appropriate high register offset to use.
1279 *
1280 * Return: true if the provided low address is one of the known 64bit PHY values
1281 * represented as two 32bit registers, false otherwise.
1282 */
ice_is_64b_phy_reg_eth56g(u16 low_addr,u16 * high_addr)1283 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
1284 {
1285 switch (low_addr) {
1286 case PHY_REG_TX_TIMER_INC_PRE_L:
1287 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U;
1288 return true;
1289 case PHY_REG_RX_TIMER_INC_PRE_L:
1290 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U;
1291 return true;
1292 case PHY_REG_TX_CAPTURE_L:
1293 *high_addr = PHY_REG_TX_CAPTURE_U;
1294 return true;
1295 case PHY_REG_RX_CAPTURE_L:
1296 *high_addr = PHY_REG_RX_CAPTURE_U;
1297 return true;
1298 case PHY_REG_TOTAL_TX_OFFSET_L:
1299 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U;
1300 return true;
1301 case PHY_REG_TOTAL_RX_OFFSET_L:
1302 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U;
1303 return true;
1304 case PHY_REG_TX_MEMORY_STATUS_L:
1305 *high_addr = PHY_REG_TX_MEMORY_STATUS_U;
1306 return true;
1307 default:
1308 return false;
1309 }
1310 }
1311
1312 /**
1313 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register
1314 * @low_addr: the low address to check
1315 * @high_addr: on return, contains the high address of the 40bit value
1316 *
1317 * Write the appropriate high register offset to use.
1318 *
1319 * Return: true if the provided low address is one of the known 40bit PHY
1320 * values split into two registers with the lower 8 bits in the low register and
1321 * the upper 32 bits in the high register, false otherwise.
1322 */
ice_is_40b_phy_reg_eth56g(u16 low_addr,u16 * high_addr)1323 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
1324 {
1325 switch (low_addr) {
1326 case PHY_REG_TIMETUS_L:
1327 *high_addr = PHY_REG_TIMETUS_U;
1328 return true;
1329 case PHY_PCS_REF_TUS_L:
1330 *high_addr = PHY_PCS_REF_TUS_U;
1331 return true;
1332 case PHY_PCS_REF_INC_L:
1333 *high_addr = PHY_PCS_REF_INC_U;
1334 return true;
1335 default:
1336 return false;
1337 }
1338 }
1339
1340 /**
1341 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers
1342 * @hw: pointer to the HW struct
1343 * @port: PHY port to read from
1344 * @low_addr: offset of the lower register to read from
1345 * @val: on return, the contents of the 64bit value from the PHY registers
1346 * @res_type: resource type
1347 *
1348 * Check if the caller has specified a known 40 bit register offset and read
1349 * the two registers associated with a 40bit value and return it in the val
1350 * pointer.
1351 *
1352 * Return:
1353 * * %0 - success
1354 * * %EINVAL - not a 64 bit register
1355 * * %other - failed to read from PHY
1356 */
ice_read_64b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val,enum eth56g_res_type res_type)1357 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
1358 u64 *val, enum eth56g_res_type res_type)
1359 {
1360 u16 high_addr;
1361 u32 lo, hi;
1362 int err;
1363
1364 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
1365 return -EINVAL;
1366
1367 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type);
1368 if (err) {
1369 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d",
1370 low_addr, err);
1371 return err;
1372 }
1373
1374 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type);
1375 if (err) {
1376 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d",
1377 high_addr, err);
1378 return err;
1379 }
1380
1381 *val = ((u64)hi << 32) | lo;
1382
1383 return 0;
1384 }
1385
1386 /**
1387 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers
1388 * @hw: pointer to the HW struct
1389 * @port: PHY port to read from
1390 * @low_addr: offset of the lower register to read from
1391 * @val: on return, the contents of the 64bit value from the PHY registers
1392 *
1393 * Check if the caller has specified a known 40 bit register offset and read
1394 * the two registers associated with a 40bit value and return it in the val
1395 * pointer.
1396 *
1397 * Return:
1398 * * %0 - success
1399 * * %EINVAL - not a 64 bit register
1400 * * %other - failed to read from PHY
1401 */
ice_read_64b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val)1402 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
1403 u64 *val)
1404 {
1405 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val,
1406 ETH56G_PHY_REG_PTP);
1407 }
1408
1409 /**
1410 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY
1411 * @hw: pointer to the HW struct
1412 * @port: port to write to
1413 * @low_addr: offset of the low register
1414 * @val: 40b value to write
1415 * @res_type: resource type
1416 *
1417 * Check if the caller has specified a known 40 bit register offset and write
1418 * provided 40b value to the two associated registers by splitting it up into
1419 * two chunks, the lower 8 bits and the upper 32 bits.
1420 *
1421 * Return:
1422 * * %0 - success
1423 * * %EINVAL - not a 40 bit register
1424 * * %other - failed to write to PHY
1425 */
ice_write_40b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val,enum eth56g_res_type res_type)1426 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
1427 u16 low_addr, u64 val,
1428 enum eth56g_res_type res_type)
1429 {
1430 u16 high_addr;
1431 u32 lo, hi;
1432 int err;
1433
1434 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr))
1435 return -EINVAL;
1436
1437 lo = FIELD_GET(P_REG_40B_LOW_M, val);
1438 hi = (u32)(val >> P_REG_40B_HIGH_S);
1439
1440 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
1441 if (err) {
1442 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
1443 low_addr, err);
1444 return err;
1445 }
1446
1447 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
1448 if (err) {
1449 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
1450 high_addr, err);
1451 return err;
1452 }
1453
1454 return 0;
1455 }
1456
1457 /**
1458 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY
1459 * @hw: pointer to the HW struct
1460 * @port: port to write to
1461 * @low_addr: offset of the low register
1462 * @val: 40b value to write
1463 *
1464 * Check if the caller has specified a known 40 bit register offset and write
1465 * provided 40b value to the two associated registers by splitting it up into
1466 * two chunks, the lower 8 bits and the upper 32 bits.
1467 *
1468 * Return:
1469 * * %0 - success
1470 * * %EINVAL - not a 40 bit register
1471 * * %other - failed to write to PHY
1472 */
ice_write_40b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)1473 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
1474 u16 low_addr, u64 val)
1475 {
1476 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val,
1477 ETH56G_PHY_REG_PTP);
1478 }
1479
1480 /**
1481 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers
1482 * @hw: pointer to the HW struct
1483 * @port: PHY port to read from
1484 * @low_addr: offset of the lower register to read from
1485 * @val: the contents of the 64bit value to write to PHY
1486 * @res_type: resource type
1487 *
1488 * Check if the caller has specified a known 64 bit register offset and write
1489 * the 64bit value to the two associated 32bit PHY registers.
1490 *
1491 * Return:
1492 * * %0 - success
1493 * * %EINVAL - not a 64 bit register
1494 * * %other - failed to write to PHY
1495 */
ice_write_64b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val,enum eth56g_res_type res_type)1496 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
1497 u16 low_addr, u64 val,
1498 enum eth56g_res_type res_type)
1499 {
1500 u16 high_addr;
1501 u32 lo, hi;
1502 int err;
1503
1504 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
1505 return -EINVAL;
1506
1507 lo = lower_32_bits(val);
1508 hi = upper_32_bits(val);
1509
1510 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
1511 if (err) {
1512 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
1513 low_addr, err);
1514 return err;
1515 }
1516
1517 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
1518 if (err) {
1519 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
1520 high_addr, err);
1521 return err;
1522 }
1523
1524 return 0;
1525 }
1526
1527 /**
1528 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers
1529 * @hw: pointer to the HW struct
1530 * @port: PHY port to read from
1531 * @low_addr: offset of the lower register to read from
1532 * @val: the contents of the 64bit value to write to PHY
1533 *
1534 * Check if the caller has specified a known 64 bit register offset and write
1535 * the 64bit value to the two associated 32bit PHY registers.
1536 *
1537 * Return:
1538 * * %0 - success
1539 * * %EINVAL - not a 64 bit register
1540 * * %other - failed to write to PHY
1541 */
ice_write_64b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)1542 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
1543 u16 low_addr, u64 val)
1544 {
1545 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val,
1546 ETH56G_PHY_REG_PTP);
1547 }
1548
1549 /**
1550 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory
1551 * @hw: pointer to the HW struct
1552 * @port: the port to read from
1553 * @idx: the timestamp index to read
1554 * @tstamp: on return, the 40bit timestamp value
1555 *
1556 * Read a 40bit timestamp value out of the two associated entries in the
1557 * port memory block of the internal PHYs of the 56G devices.
1558 *
1559 * Return:
1560 * * %0 - success
1561 * * %other - failed to read from PHY
1562 */
ice_read_ptp_tstamp_eth56g(struct ice_hw * hw,u8 port,u8 idx,u64 * tstamp)1563 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx,
1564 u64 *tstamp)
1565 {
1566 u16 lo_addr, hi_addr;
1567 u32 lo, hi;
1568 int err;
1569
1570 lo_addr = (u16)PHY_TSTAMP_L(idx);
1571 hi_addr = (u16)PHY_TSTAMP_U(idx);
1572
1573 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo);
1574 if (err) {
1575 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
1576 err);
1577 return err;
1578 }
1579
1580 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi);
1581 if (err) {
1582 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
1583 err);
1584 return err;
1585 }
1586
1587 /* For 56G based internal PHYs, the timestamp is reported with the
1588 * lower 8 bits in the low register, and the upper 32 bits in the high
1589 * register.
1590 */
1591 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) |
1592 FIELD_PREP(PHY_40B_LOW_M, lo);
1593 return 0;
1594 }
1595
1596 /**
1597 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block
1598 * @hw: pointer to the HW struct
1599 * @port: the quad to read from
1600 * @idx: the timestamp index to reset
1601 *
1602 * Read and then forcibly clear the timestamp index to ensure the valid bit is
1603 * cleared and the timestamp status bit is reset in the PHY port memory of
1604 * internal PHYs of the 56G devices.
1605 *
1606 * To directly clear the contents of the timestamp block entirely, discarding
1607 * all timestamp data at once, software should instead use
1608 * ice_ptp_reset_ts_memory_quad_eth56g().
1609 *
1610 * This function should only be called on an idx whose bit is set according to
1611 * ice_get_phy_tx_tstamp_ready().
1612 *
1613 * Return:
1614 * * %0 - success
1615 * * %other - failed to write to PHY
1616 */
ice_clear_ptp_tstamp_eth56g(struct ice_hw * hw,u8 port,u8 idx)1617 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx)
1618 {
1619 u64 unused_tstamp;
1620 u16 lo_addr;
1621 int err;
1622
1623 /* Read the timestamp register to ensure the timestamp status bit is
1624 * cleared.
1625 */
1626 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp);
1627 if (err) {
1628 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n",
1629 port, idx, err);
1630 }
1631
1632 lo_addr = (u16)PHY_TSTAMP_L(idx);
1633
1634 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0);
1635 if (err) {
1636 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n",
1637 port, idx, err);
1638 return err;
1639 }
1640
1641 return 0;
1642 }
1643
1644 /**
1645 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block
1646 * @hw: pointer to the HW struct
1647 */
ice_ptp_reset_ts_memory_eth56g(struct ice_hw * hw)1648 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw)
1649 {
1650 unsigned int port;
1651
1652 for (port = 0; port < hw->ptp.num_lports; port++) {
1653 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
1654 0);
1655 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U,
1656 0);
1657 }
1658 }
1659
1660 /**
1661 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time
1662 * @hw: pointer to the HW struct
1663 * @port: port number
1664 * @time: time to initialize the PHY port clocks to
1665 *
1666 * Write a new initial time value into registers of a specific PHY port.
1667 *
1668 * Return:
1669 * * %0 - success
1670 * * %other - failed to write to PHY
1671 */
ice_ptp_prep_port_time_eth56g(struct ice_hw * hw,u8 port,u64 time)1672 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port,
1673 u64 time)
1674 {
1675 int err;
1676
1677 /* Tx case */
1678 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
1679 time);
1680 if (err)
1681 return err;
1682
1683 /* Rx case */
1684 return ice_write_64b_ptp_reg_eth56g(hw, port,
1685 PHY_REG_RX_TIMER_INC_PRE_L, time);
1686 }
1687
1688 /**
1689 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time
1690 * @hw: pointer to the HW struct
1691 * @time: Time to initialize the PHY port clocks to
1692 *
1693 * Program the PHY port registers with a new initial time value. The port
1694 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
1695 * command. The time value is the upper 32 bits of the PHY timer, usually in
1696 * units of nominal nanoseconds.
1697 *
1698 * Return:
1699 * * %0 - success
1700 * * %other - failed to write to PHY
1701 */
ice_ptp_prep_phy_time_eth56g(struct ice_hw * hw,u32 time)1702 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time)
1703 {
1704 u64 phy_time;
1705 u8 port;
1706
1707 /* The time represents the upper 32 bits of the PHY timer, so we need
1708 * to shift to account for this when programming.
1709 */
1710 phy_time = (u64)time << 32;
1711
1712 for (port = 0; port < hw->ptp.num_lports; port++) {
1713 int err;
1714
1715 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time);
1716 if (err) {
1717 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
1718 port, err);
1719 return err;
1720 }
1721 }
1722
1723 return 0;
1724 }
1725
1726 /**
1727 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust
1728 * @hw: pointer to HW struct
1729 * @port: Port number to be programmed
1730 * @time: time in cycles to adjust the port clocks
1731 *
1732 * Program the port for an atomic adjustment by writing the Tx and Rx timer
1733 * registers. The atomic adjustment won't be completed until the driver issues
1734 * an ICE_PTP_ADJ_TIME command.
1735 *
1736 * Note that time is not in units of nanoseconds. It is in clock time
1737 * including the lower sub-nanosecond portion of the port timer.
1738 *
1739 * Negative adjustments are supported using 2s complement arithmetic.
1740 *
1741 * Return:
1742 * * %0 - success
1743 * * %other - failed to write to PHY
1744 */
ice_ptp_prep_port_adj_eth56g(struct ice_hw * hw,u8 port,s64 time)1745 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time)
1746 {
1747 u32 l_time, u_time;
1748 int err;
1749
1750 l_time = lower_32_bits(time);
1751 u_time = upper_32_bits(time);
1752
1753 /* Tx case */
1754 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
1755 l_time);
1756 if (err)
1757 goto exit_err;
1758
1759 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U,
1760 u_time);
1761 if (err)
1762 goto exit_err;
1763
1764 /* Rx case */
1765 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L,
1766 l_time);
1767 if (err)
1768 goto exit_err;
1769
1770 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U,
1771 u_time);
1772 if (err)
1773 goto exit_err;
1774
1775 return 0;
1776
1777 exit_err:
1778 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
1779 port, err);
1780 return err;
1781 }
1782
1783 /**
1784 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
1785 * @hw: pointer to HW struct
1786 * @adj: adjustment in nanoseconds
1787 *
1788 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
1789 * Tx and Rx port registers. The actual adjustment is completed by issuing an
1790 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
1791 *
1792 * Return:
1793 * * %0 - success
1794 * * %other - failed to write to PHY
1795 */
ice_ptp_prep_phy_adj_eth56g(struct ice_hw * hw,s32 adj)1796 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj)
1797 {
1798 s64 cycles;
1799 u8 port;
1800
1801 /* The port clock supports adjustment of the sub-nanosecond portion of
1802 * the clock (lowest 32 bits). We shift the provided adjustment in
1803 * nanoseconds by 32 to calculate the appropriate adjustment to program
1804 * into the PHY ports.
1805 */
1806 cycles = (s64)adj << 32;
1807
1808 for (port = 0; port < hw->ptp.num_lports; port++) {
1809 int err;
1810
1811 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles);
1812 if (err)
1813 return err;
1814 }
1815
1816 return 0;
1817 }
1818
1819 /**
1820 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
1821 * @hw: pointer to HW struct
1822 * @incval: new increment value to prepare
1823 *
1824 * Prepare each of the PHY ports for a new increment value by programming the
1825 * port's TIMETUS registers. The new increment value will be updated after
1826 * issuing an ICE_PTP_INIT_INCVAL command.
1827 *
1828 * Return:
1829 * * %0 - success
1830 * * %other - failed to write to PHY
1831 */
ice_ptp_prep_phy_incval_eth56g(struct ice_hw * hw,u64 incval)1832 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval)
1833 {
1834 u8 port;
1835
1836 for (port = 0; port < hw->ptp.num_lports; port++) {
1837 int err;
1838
1839 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
1840 incval);
1841 if (err) {
1842 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
1843 port, err);
1844 return err;
1845 }
1846 }
1847
1848 return 0;
1849 }
1850
1851 /**
1852 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture
1853 * @hw: pointer to HW struct
1854 * @port: Port number to read
1855 * @tx_ts: on return, the Tx port time capture
1856 * @rx_ts: on return, the Rx port time capture
1857 *
1858 * Read the port's Tx and Rx local time capture values.
1859 *
1860 * Return:
1861 * * %0 - success
1862 * * %other - failed to read from PHY
1863 */
ice_ptp_read_port_capture_eth56g(struct ice_hw * hw,u8 port,u64 * tx_ts,u64 * rx_ts)1864 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port,
1865 u64 *tx_ts, u64 *rx_ts)
1866 {
1867 int err;
1868
1869 /* Tx case */
1870 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,
1871 tx_ts);
1872 if (err) {
1873 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
1874 err);
1875 return err;
1876 }
1877
1878 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts);
1879
1880 /* Rx case */
1881 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,
1882 rx_ts);
1883 if (err) {
1884 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
1885 err);
1886 return err;
1887 }
1888
1889 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts);
1890
1891 return 0;
1892 }
1893
1894 /**
1895 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command
1896 * @hw: pointer to HW struct
1897 * @port: Port to which cmd has to be sent
1898 * @cmd: Command to be sent to the port
1899 *
1900 * Prepare the requested port for an upcoming timer sync command.
1901 *
1902 * Return:
1903 * * %0 - success
1904 * * %other - failed to write to PHY
1905 */
ice_ptp_write_port_cmd_eth56g(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)1906 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port,
1907 enum ice_ptp_tmr_cmd cmd)
1908 {
1909 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
1910 int err;
1911
1912 /* Tx case */
1913 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val);
1914 if (err) {
1915 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
1916 err);
1917 return err;
1918 }
1919
1920 /* Rx case */
1921 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val);
1922 if (err) {
1923 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
1924 err);
1925 return err;
1926 }
1927
1928 return 0;
1929 }
1930
1931 /**
1932 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type
1933 * @li: pointer to link information struct
1934 *
1935 * Return: simplified ETH56G PHY speed
1936 */
1937 static enum ice_eth56g_link_spd
ice_phy_get_speed_eth56g(struct ice_link_status * li)1938 ice_phy_get_speed_eth56g(struct ice_link_status *li)
1939 {
1940 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low,
1941 li->phy_type_high);
1942
1943 switch (speed) {
1944 case ICE_AQ_LINK_SPEED_1000MB:
1945 return ICE_ETH56G_LNK_SPD_1G;
1946 case ICE_AQ_LINK_SPEED_2500MB:
1947 return ICE_ETH56G_LNK_SPD_2_5G;
1948 case ICE_AQ_LINK_SPEED_10GB:
1949 return ICE_ETH56G_LNK_SPD_10G;
1950 case ICE_AQ_LINK_SPEED_25GB:
1951 return ICE_ETH56G_LNK_SPD_25G;
1952 case ICE_AQ_LINK_SPEED_40GB:
1953 return ICE_ETH56G_LNK_SPD_40G;
1954 case ICE_AQ_LINK_SPEED_50GB:
1955 switch (li->phy_type_low) {
1956 case ICE_PHY_TYPE_LOW_50GBASE_SR:
1957 case ICE_PHY_TYPE_LOW_50GBASE_FR:
1958 case ICE_PHY_TYPE_LOW_50GBASE_LR:
1959 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
1960 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
1961 case ICE_PHY_TYPE_LOW_50G_AUI1:
1962 return ICE_ETH56G_LNK_SPD_50G;
1963 default:
1964 return ICE_ETH56G_LNK_SPD_50G2;
1965 }
1966 case ICE_AQ_LINK_SPEED_100GB:
1967 if (li->phy_type_high ||
1968 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2)
1969 return ICE_ETH56G_LNK_SPD_100G2;
1970 else
1971 return ICE_ETH56G_LNK_SPD_100G;
1972 default:
1973 return ICE_ETH56G_LNK_SPD_1G;
1974 }
1975 }
1976
1977 /**
1978 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle
1979 * @hw: pointer to the HW struct
1980 * @port: port to configure
1981 *
1982 * Configure the number of TUs for the PAR and PCS clocks used as part of the
1983 * timestamp calibration process.
1984 *
1985 * Return:
1986 * * %0 - success
1987 * * %other - PHY read/write failed
1988 */
ice_phy_cfg_parpcs_eth56g(struct ice_hw * hw,u8 port)1989 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
1990 {
1991 u32 val;
1992 int err;
1993
1994 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH,
1995 ICE_ETH56G_NOMINAL_THRESH4);
1996 if (err) {
1997 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d",
1998 err);
1999 return err;
2000 }
2001
2002 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
2003 case ICE_ETH56G_LNK_SPD_1G:
2004 case ICE_ETH56G_LNK_SPD_2_5G:
2005 err = ice_read_quad_ptp_reg_eth56g(hw, port,
2006 PHY_GPCS_CONFIG_REG0, &val);
2007 if (err) {
2008 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d",
2009 err);
2010 return err;
2011 }
2012
2013 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M;
2014 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M,
2015 ICE_ETH56G_NOMINAL_TX_THRESH);
2016
2017 err = ice_write_quad_ptp_reg_eth56g(hw, port,
2018 PHY_GPCS_CONFIG_REG0, val);
2019 if (err) {
2020 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d",
2021 err);
2022 return err;
2023 }
2024 break;
2025 default:
2026 break;
2027 }
2028
2029 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L,
2030 ICE_ETH56G_NOMINAL_PCS_REF_TUS);
2031 if (err) {
2032 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d",
2033 err);
2034 return err;
2035 }
2036
2037 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L,
2038 ICE_ETH56G_NOMINAL_PCS_REF_INC);
2039 if (err) {
2040 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d",
2041 err);
2042 return err;
2043 }
2044
2045 return 0;
2046 }
2047
2048 /**
2049 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings
2050 * @hw: Pointer to the HW struct
2051 * @port: Port to configure
2052 *
2053 * Return:
2054 * * %0 - success
2055 * * %other - PHY read/write failed
2056 */
ice_phy_cfg_ptp_1step_eth56g(struct ice_hw * hw,u8 port)2057 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port)
2058 {
2059 u8 quad_lane = port % ICE_PORTS_PER_QUAD;
2060 u32 addr, val, peer_delay;
2061 bool enable, sfd_ena;
2062 int err;
2063
2064 enable = hw->ptp.phy.eth56g.onestep_ena;
2065 peer_delay = hw->ptp.phy.eth56g.peer_delay;
2066 sfd_ena = hw->ptp.phy.eth56g.sfd_ena;
2067
2068 addr = PHY_PTP_1STEP_CONFIG;
2069 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &val);
2070 if (err)
2071 return err;
2072
2073 if (enable)
2074 val |= BIT(quad_lane);
2075 else
2076 val &= ~BIT(quad_lane);
2077
2078 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M);
2079
2080 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val);
2081 if (err)
2082 return err;
2083
2084 addr = PHY_PTP_1STEP_PEER_DELAY(quad_lane);
2085 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay);
2086 if (peer_delay)
2087 val |= PHY_PTP_1STEP_PD_ADD_PD_M;
2088 val |= PHY_PTP_1STEP_PD_DLY_V_M;
2089 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val);
2090 if (err)
2091 return err;
2092
2093 val &= ~PHY_PTP_1STEP_PD_DLY_V_M;
2094 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val);
2095 if (err)
2096 return err;
2097
2098 addr = PHY_MAC_XIF_MODE;
2099 err = ice_read_mac_reg_eth56g(hw, port, addr, &val);
2100 if (err)
2101 return err;
2102
2103 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M |
2104 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M);
2105
2106 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
2107 case ICE_ETH56G_LNK_SPD_1G:
2108 case ICE_ETH56G_LNK_SPD_2_5G:
2109 val |= PHY_MAC_XIF_GMII_TS_SEL_M;
2110 break;
2111 default:
2112 break;
2113 }
2114
2115 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) |
2116 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) |
2117 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena);
2118
2119 return ice_write_mac_reg_eth56g(hw, port, addr, val);
2120 }
2121
2122 /**
2123 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values
2124 * @a: multiplier value
2125 * @b: multiplicand value
2126 *
2127 * Return: result of multiplication
2128 */
mul_u32_u32_fx_q9(u32 a,u32 b)2129 static u32 mul_u32_u32_fx_q9(u32 a, u32 b)
2130 {
2131 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W);
2132 }
2133
2134 /**
2135 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow
2136 * @a: first value
2137 * @b: second value
2138 *
2139 * Return: result of addition
2140 */
add_u32_u32_fx(u32 a,u32 b)2141 static u32 add_u32_u32_fx(u32 a, u32 b)
2142 {
2143 return lower_32_bits(((u64)a + b));
2144 }
2145
2146 /**
2147 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value
2148 * @hw: pointer to the HW struct
2149 * @port: port to configure
2150 * @bs: bitslip multiplier
2151 * @fc: FC-FEC enabled
2152 * @rs: RS-FEC enabled
2153 * @spd: link speed
2154 *
2155 * Return: calculated bitslip value
2156 */
ice_ptp_calc_bitslip_eth56g(struct ice_hw * hw,u8 port,u32 bs,bool fc,bool rs,enum ice_eth56g_link_spd spd)2157 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs,
2158 bool fc, bool rs,
2159 enum ice_eth56g_link_spd spd)
2160 {
2161 u32 bitslip;
2162 int err;
2163
2164 if (!bs || rs)
2165 return 0;
2166
2167 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) {
2168 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP,
2169 &bitslip);
2170 } else {
2171 u8 quad_lane = port % ICE_PORTS_PER_QUAD;
2172 u32 addr;
2173
2174 addr = PHY_REG_SD_BIT_SLIP(quad_lane);
2175 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &bitslip);
2176 }
2177 if (err)
2178 return 0;
2179
2180 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) {
2181 /* Bitslip register value of 0 corresponds to 10 so substitute
2182 * it for calculations
2183 */
2184 bitslip = 10;
2185 } else if (spd == ICE_ETH56G_LNK_SPD_10G ||
2186 spd == ICE_ETH56G_LNK_SPD_25G) {
2187 if (fc)
2188 bitslip = bitslip * 2 + 32;
2189 else
2190 bitslip = (u32)((s32)bitslip * -1 + 20);
2191 }
2192
2193 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W;
2194 return mul_u32_u32_fx_q9(bitslip, bs);
2195 }
2196
2197 /**
2198 * ice_ptp_calc_deskew_eth56g - Calculate deskew value
2199 * @hw: pointer to the HW struct
2200 * @port: port to configure
2201 * @ds: deskew multiplier
2202 * @rs: RS-FEC enabled
2203 * @spd: link speed
2204 *
2205 * Return: calculated deskew value
2206 */
ice_ptp_calc_deskew_eth56g(struct ice_hw * hw,u8 port,u32 ds,bool rs,enum ice_eth56g_link_spd spd)2207 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds,
2208 bool rs, enum ice_eth56g_link_spd spd)
2209 {
2210 u32 deskew_i, deskew_f;
2211 int err;
2212
2213 if (!ds)
2214 return 0;
2215
2216 read_poll_timeout(ice_read_ptp_reg_eth56g, err,
2217 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500,
2218 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0,
2219 &deskew_i);
2220 if (err)
2221 return err;
2222
2223 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i);
2224 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i);
2225
2226 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2)
2227 ds = 0x633; /* 3.1 */
2228 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G)
2229 ds = 0x31b; /* 1.552 */
2230
2231 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i);
2232 /* Shift 3 fractional bits to the end of the integer part */
2233 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W;
2234 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds);
2235 }
2236
2237 /**
2238 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values
2239 * @hw: pointer to the HW struct
2240 * @port: port to configure
2241 * @spd: link speed
2242 * @cfg: structure to store output values
2243 * @fc: FC-FEC enabled
2244 * @rs: RS-FEC enabled
2245 *
2246 * Return:
2247 * * %0 - success
2248 * * %other - failed to write to PHY
2249 */
ice_phy_set_offsets_eth56g(struct ice_hw * hw,u8 port,enum ice_eth56g_link_spd spd,const struct ice_eth56g_mac_reg_cfg * cfg,bool fc,bool rs)2250 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port,
2251 enum ice_eth56g_link_spd spd,
2252 const struct ice_eth56g_mac_reg_cfg *cfg,
2253 bool fc, bool rs)
2254 {
2255 u32 rx_offset, tx_offset, bs_ds;
2256 bool onestep, sfd;
2257
2258 onestep = hw->ptp.phy.eth56g.onestep_ena;
2259 sfd = hw->ptp.phy.eth56g.sfd_ena;
2260 bs_ds = cfg->rx_offset.bs_ds;
2261
2262 if (fc)
2263 rx_offset = cfg->rx_offset.fc;
2264 else if (rs)
2265 rx_offset = cfg->rx_offset.rs;
2266 else
2267 rx_offset = cfg->rx_offset.no_fec;
2268
2269 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes);
2270 if (sfd)
2271 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd);
2272
2273 if (spd < ICE_ETH56G_LNK_SPD_40G)
2274 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs,
2275 spd);
2276 else
2277 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd);
2278 rx_offset = add_u32_u32_fx(rx_offset, bs_ds);
2279 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT |
2280 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC;
2281
2282 if (fc)
2283 tx_offset = cfg->tx_offset.fc;
2284 else if (rs)
2285 tx_offset = cfg->tx_offset.rs;
2286 else
2287 tx_offset = cfg->tx_offset.no_fec;
2288 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd +
2289 cfg->tx_offset.onestep * onestep;
2290
2291 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset);
2292 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset);
2293 }
2294
2295 /**
2296 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP
2297 * @hw: Pointer to the HW struct
2298 * @port: Port to configure
2299 *
2300 * Return:
2301 * * %0 - success
2302 * * %other - failed to write to PHY
2303 */
ice_phy_cfg_mac_eth56g(struct ice_hw * hw,u8 port)2304 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port)
2305 {
2306 const struct ice_eth56g_mac_reg_cfg *cfg;
2307 enum ice_eth56g_link_spd spd;
2308 struct ice_link_status *li;
2309 bool fc = false;
2310 bool rs = false;
2311 bool onestep;
2312 u32 val;
2313 int err;
2314
2315 onestep = hw->ptp.phy.eth56g.onestep_ena;
2316 li = &hw->port_info->phy.link_info;
2317 spd = ice_phy_get_speed_eth56g(li);
2318 if (!!(li->an_info & ICE_AQ_FEC_EN)) {
2319 if (spd == ICE_ETH56G_LNK_SPD_10G) {
2320 fc = true;
2321 } else {
2322 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN);
2323 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN);
2324 }
2325 }
2326 cfg = ð56g_mac_cfg[spd];
2327
2328 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0);
2329 if (err)
2330 return err;
2331
2332 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0);
2333 if (err)
2334 return err;
2335
2336 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M,
2337 cfg->tx_mode.def + rs * cfg->tx_mode.rs) |
2338 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) |
2339 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M,
2340 cfg->tx_cw_dly.def +
2341 onestep * cfg->tx_cw_dly.onestep) |
2342 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M,
2343 cfg->rx_mode.def + rs * cfg->rx_mode.rs) |
2344 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M,
2345 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) |
2346 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M,
2347 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) |
2348 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk);
2349 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val);
2350 if (err)
2351 return err;
2352
2353 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME,
2354 cfg->blktime);
2355 if (err)
2356 return err;
2357
2358 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs);
2359 if (err)
2360 return err;
2361
2362 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs)
2363 val = 0;
2364 else
2365 val = cfg->mktime;
2366
2367 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val);
2368 }
2369
2370 /**
2371 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt
2372 * @hw: pointer to the HW struct
2373 * @port: the timestamp port
2374 * @ena: enable or disable interrupt
2375 * @threshold: interrupt threshold
2376 *
2377 * Configure TX timestamp interrupt for the specified port
2378 *
2379 * Return:
2380 * * %0 - success
2381 * * %other - PHY read/write failed
2382 */
ice_phy_cfg_intr_eth56g(struct ice_hw * hw,u8 port,bool ena,u8 threshold)2383 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold)
2384 {
2385 int err;
2386 u32 val;
2387
2388 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);
2389 if (err)
2390 return err;
2391
2392 if (ena) {
2393 val |= PHY_TS_INT_CONFIG_ENA_M;
2394 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M;
2395 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold);
2396 } else {
2397 val &= ~PHY_TS_INT_CONFIG_ENA_M;
2398 }
2399
2400 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);
2401 }
2402
2403 /**
2404 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time
2405 * @hw: pointer to the HW struct
2406 * @port: the PHY port to read
2407 * @phy_time: on return, the 64bit PHY timer value
2408 * @phc_time: on return, the lower 64bits of PHC time
2409 *
2410 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
2411 * and PHC timer values.
2412 *
2413 * Return:
2414 * * %0 - success
2415 * * %other - PHY read/write failed
2416 */
ice_read_phy_and_phc_time_eth56g(struct ice_hw * hw,u8 port,u64 * phy_time,u64 * phc_time)2417 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port,
2418 u64 *phy_time, u64 *phc_time)
2419 {
2420 u64 tx_time, rx_time;
2421 u32 zo, lo;
2422 u8 tmr_idx;
2423 int err;
2424
2425 tmr_idx = ice_get_ptp_src_clock_index(hw);
2426
2427 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
2428 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
2429
2430 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
2431 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
2432 if (err)
2433 return err;
2434
2435 /* Issue the sync to start the ICE_PTP_READ_TIME capture */
2436 ice_ptp_exec_tmr_cmd(hw);
2437
2438 /* Read the captured PHC time from the shadow time registers */
2439 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
2440 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
2441 *phc_time = (u64)lo << 32 | zo;
2442
2443 /* Read the captured PHY time from the PHY shadow registers */
2444 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);
2445 if (err)
2446 return err;
2447
2448 /* If the PHY Tx and Rx timers don't match, log a warning message.
2449 * Note that this should not happen in normal circumstances since the
2450 * driver always programs them together.
2451 */
2452 if (tx_time != rx_time)
2453 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
2454 port, tx_time, rx_time);
2455
2456 *phy_time = tx_time;
2457
2458 return 0;
2459 }
2460
2461 /**
2462 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer
2463 * @hw: pointer to the HW struct
2464 * @port: the PHY port to synchronize
2465 *
2466 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
2467 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
2468 * simultaneous read of the PHY timer and PHC timer. Then we use the
2469 * difference to calculate an appropriate 2s complement addition to add
2470 * to the PHY timer in order to ensure it reads the same value as the
2471 * primary PHC timer.
2472 *
2473 * Return:
2474 * * %0 - success
2475 * * %-EBUSY- failed to acquire PTP semaphore
2476 * * %other - PHY read/write failed
2477 */
ice_sync_phy_timer_eth56g(struct ice_hw * hw,u8 port)2478 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
2479 {
2480 u64 phc_time, phy_time, difference;
2481 int err;
2482
2483 if (!ice_ptp_lock(hw)) {
2484 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
2485 return -EBUSY;
2486 }
2487
2488 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
2489 if (err)
2490 goto err_unlock;
2491
2492 /* Calculate the amount required to add to the port time in order for
2493 * it to match the PHC time.
2494 *
2495 * Note that the port adjustment is done using 2s complement
2496 * arithmetic. This is convenient since it means that we can simply
2497 * calculate the difference between the PHC time and the port time,
2498 * and it will be interpreted correctly.
2499 */
2500
2501 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2502 difference = phc_time - phy_time;
2503
2504 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference);
2505 if (err)
2506 goto err_unlock;
2507
2508 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
2509 if (err)
2510 goto err_unlock;
2511
2512 /* Issue the sync to activate the time adjustment */
2513 ice_ptp_exec_tmr_cmd(hw);
2514
2515 /* Re-capture the timer values to flush the command registers and
2516 * verify that the time was properly adjusted.
2517 */
2518 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
2519 if (err)
2520 goto err_unlock;
2521
2522 dev_info(ice_hw_to_dev(hw),
2523 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
2524 port, phy_time, phc_time);
2525
2526 err_unlock:
2527 ice_ptp_unlock(hw);
2528 return err;
2529 }
2530
2531 /**
2532 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer
2533 * @hw: pointer to the HW struct
2534 * @port: the PHY port to stop
2535 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS
2536 *
2537 * Stop the clock of a PHY port. This must be done as part of the flow to
2538 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2539 * initialized or when link speed changes.
2540 *
2541 * Return:
2542 * * %0 - success
2543 * * %other - failed to write to PHY
2544 */
ice_stop_phy_timer_eth56g(struct ice_hw * hw,u8 port,bool soft_reset)2545 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
2546 {
2547 int err;
2548
2549 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);
2550 if (err)
2551 return err;
2552
2553 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);
2554 if (err)
2555 return err;
2556
2557 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
2558
2559 return 0;
2560 }
2561
2562 /**
2563 * ice_start_phy_timer_eth56g - Start the PHY clock timer
2564 * @hw: pointer to the HW struct
2565 * @port: the PHY port to start
2566 *
2567 * Start the clock of a PHY port. This must be done as part of the flow to
2568 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2569 * initialized or when link speed changes.
2570 *
2571 * Return:
2572 * * %0 - success
2573 * * %other - PHY read/write failed
2574 */
ice_start_phy_timer_eth56g(struct ice_hw * hw,u8 port)2575 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)
2576 {
2577 u32 lo, hi;
2578 u64 incval;
2579 u8 tmr_idx;
2580 int err;
2581
2582 tmr_idx = ice_get_ptp_src_clock_index(hw);
2583
2584 err = ice_stop_phy_timer_eth56g(hw, port, false);
2585 if (err)
2586 return err;
2587
2588 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2589
2590 err = ice_phy_cfg_parpcs_eth56g(hw, port);
2591 if (err)
2592 return err;
2593
2594 err = ice_phy_cfg_ptp_1step_eth56g(hw, port);
2595 if (err)
2596 return err;
2597
2598 err = ice_phy_cfg_mac_eth56g(hw, port);
2599 if (err)
2600 return err;
2601
2602 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
2603 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
2604 incval = (u64)hi << 32 | lo;
2605
2606 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval);
2607 if (err)
2608 return err;
2609
2610 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
2611 if (err)
2612 return err;
2613
2614 ice_ptp_exec_tmr_cmd(hw);
2615
2616 err = ice_sync_phy_timer_eth56g(hw, port);
2617 if (err)
2618 return err;
2619
2620 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1);
2621 if (err)
2622 return err;
2623
2624 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);
2625 if (err)
2626 return err;
2627
2628 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
2629
2630 return 0;
2631 }
2632
2633 /**
2634 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access
2635 * @hw: pointer to HW struct
2636 * @enable: Enable or disable access
2637 *
2638 * Enable sideband devices (PHY and others) access.
2639 */
ice_sb_access_ena_eth56g(struct ice_hw * hw,bool enable)2640 static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable)
2641 {
2642 u32 val = rd32(hw, PF_SB_REM_DEV_CTL);
2643
2644 if (enable)
2645 val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1);
2646 else
2647 val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1));
2648
2649 wr32(hw, PF_SB_REM_DEV_CTL, val);
2650 }
2651
2652 /**
2653 * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization
2654 * @hw: pointer to HW struct
2655 *
2656 * Perform E825-specific PTP hardware clock initialization steps.
2657 *
2658 * Return: 0 on success, negative error code otherwise.
2659 */
ice_ptp_init_phc_e825(struct ice_hw * hw)2660 static int ice_ptp_init_phc_e825(struct ice_hw *hw)
2661 {
2662 ice_sb_access_ena_eth56g(hw, true);
2663
2664 /* Initialize the Clock Generation Unit */
2665 return ice_init_cgu_e82x(hw);
2666 }
2667
2668 /**
2669 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status
2670 * @hw: pointer to the HW struct
2671 * @ts_status: the timestamp mask pointer
2672 *
2673 * Read the PHY Tx timestamp status mask indicating which ports have Tx
2674 * timestamps available.
2675 *
2676 * Return:
2677 * * %0 - success
2678 * * %other - failed to read from PHY
2679 */
ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw * hw,u32 * ts_status)2680 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
2681 {
2682 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g;
2683 u8 phy, mask;
2684 u32 status;
2685
2686 mask = (1 << hw->ptp.ports_per_phy) - 1;
2687 *ts_status = 0;
2688
2689 for (phy = 0; phy < params->num_phys; phy++) {
2690 int err;
2691
2692 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status);
2693 if (err)
2694 return err;
2695
2696 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy);
2697 }
2698
2699 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status);
2700
2701 return 0;
2702 }
2703
2704 /**
2705 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register
2706 * @hw: pointer to the HW struct
2707 * @port: the PHY port to read from
2708 * @tstamp_ready: contents of the Tx memory status register
2709 *
2710 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in
2711 * the PHY are ready. A set bit means the corresponding timestamp is valid and
2712 * ready to be captured from the PHY timestamp block.
2713 *
2714 * Return:
2715 * * %0 - success
2716 * * %other - failed to read from PHY
2717 */
ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw * hw,u8 port,u64 * tstamp_ready)2718 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port,
2719 u64 *tstamp_ready)
2720 {
2721 int err;
2722
2723 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
2724 tstamp_ready);
2725 if (err) {
2726 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n",
2727 port, err);
2728 return err;
2729 }
2730
2731 return 0;
2732 }
2733
2734 /**
2735 * ice_ptp_init_phy_e825 - initialize PHY parameters
2736 * @hw: pointer to the HW struct
2737 */
ice_ptp_init_phy_e825(struct ice_hw * hw)2738 static void ice_ptp_init_phy_e825(struct ice_hw *hw)
2739 {
2740 struct ice_ptp_hw *ptp = &hw->ptp;
2741 struct ice_eth56g_params *params;
2742
2743 params = &ptp->phy.eth56g;
2744 params->onestep_ena = false;
2745 params->peer_delay = 0;
2746 params->sfd_ena = false;
2747 params->num_phys = 2;
2748 ptp->ports_per_phy = 4;
2749 ptp->num_lports = params->num_phys * ptp->ports_per_phy;
2750
2751 ice_sb_access_ena_eth56g(hw, true);
2752 }
2753
2754 /* E822 family functions
2755 *
2756 * The following functions operate on the E822 family of devices.
2757 */
2758
2759 /**
2760 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access
2761 * @hw: pointer to the HW struct
2762 * @msg: the PHY message buffer to fill in
2763 * @port: the port to access
2764 * @offset: the register offset
2765 */
ice_fill_phy_msg_e82x(struct ice_hw * hw,struct ice_sbq_msg_input * msg,u8 port,u16 offset)2766 static void ice_fill_phy_msg_e82x(struct ice_hw *hw,
2767 struct ice_sbq_msg_input *msg, u8 port,
2768 u16 offset)
2769 {
2770 int phy_port, quadtype;
2771
2772 phy_port = port % hw->ptp.ports_per_phy;
2773 quadtype = ICE_GET_QUAD_NUM(port) %
2774 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy);
2775
2776 if (quadtype == 0) {
2777 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
2778 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port);
2779 } else {
2780 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port);
2781 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port);
2782 }
2783
2784 msg->dest_dev = rmn_0;
2785 }
2786
2787 /**
2788 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register
2789 * @low_addr: the low address to check
2790 * @high_addr: on return, contains the high address of the 64bit register
2791 *
2792 * Checks if the provided low address is one of the known 64bit PHY values
2793 * represented as two 32bit registers. If it is, return the appropriate high
2794 * register offset to use.
2795 */
ice_is_64b_phy_reg_e82x(u16 low_addr,u16 * high_addr)2796 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr)
2797 {
2798 switch (low_addr) {
2799 case P_REG_PAR_PCS_TX_OFFSET_L:
2800 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U;
2801 return true;
2802 case P_REG_PAR_PCS_RX_OFFSET_L:
2803 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U;
2804 return true;
2805 case P_REG_PAR_TX_TIME_L:
2806 *high_addr = P_REG_PAR_TX_TIME_U;
2807 return true;
2808 case P_REG_PAR_RX_TIME_L:
2809 *high_addr = P_REG_PAR_RX_TIME_U;
2810 return true;
2811 case P_REG_TOTAL_TX_OFFSET_L:
2812 *high_addr = P_REG_TOTAL_TX_OFFSET_U;
2813 return true;
2814 case P_REG_TOTAL_RX_OFFSET_L:
2815 *high_addr = P_REG_TOTAL_RX_OFFSET_U;
2816 return true;
2817 case P_REG_UIX66_10G_40G_L:
2818 *high_addr = P_REG_UIX66_10G_40G_U;
2819 return true;
2820 case P_REG_UIX66_25G_100G_L:
2821 *high_addr = P_REG_UIX66_25G_100G_U;
2822 return true;
2823 case P_REG_TX_CAPTURE_L:
2824 *high_addr = P_REG_TX_CAPTURE_U;
2825 return true;
2826 case P_REG_RX_CAPTURE_L:
2827 *high_addr = P_REG_RX_CAPTURE_U;
2828 return true;
2829 case P_REG_TX_TIMER_INC_PRE_L:
2830 *high_addr = P_REG_TX_TIMER_INC_PRE_U;
2831 return true;
2832 case P_REG_RX_TIMER_INC_PRE_L:
2833 *high_addr = P_REG_RX_TIMER_INC_PRE_U;
2834 return true;
2835 default:
2836 return false;
2837 }
2838 }
2839
2840 /**
2841 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register
2842 * @low_addr: the low address to check
2843 * @high_addr: on return, contains the high address of the 40bit value
2844 *
2845 * Checks if the provided low address is one of the known 40bit PHY values
2846 * split into two registers with the lower 8 bits in the low register and the
2847 * upper 32 bits in the high register. If it is, return the appropriate high
2848 * register offset to use.
2849 */
ice_is_40b_phy_reg_e82x(u16 low_addr,u16 * high_addr)2850 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr)
2851 {
2852 switch (low_addr) {
2853 case P_REG_TIMETUS_L:
2854 *high_addr = P_REG_TIMETUS_U;
2855 return true;
2856 case P_REG_PAR_RX_TUS_L:
2857 *high_addr = P_REG_PAR_RX_TUS_U;
2858 return true;
2859 case P_REG_PAR_TX_TUS_L:
2860 *high_addr = P_REG_PAR_TX_TUS_U;
2861 return true;
2862 case P_REG_PCS_RX_TUS_L:
2863 *high_addr = P_REG_PCS_RX_TUS_U;
2864 return true;
2865 case P_REG_PCS_TX_TUS_L:
2866 *high_addr = P_REG_PCS_TX_TUS_U;
2867 return true;
2868 case P_REG_DESK_PAR_RX_TUS_L:
2869 *high_addr = P_REG_DESK_PAR_RX_TUS_U;
2870 return true;
2871 case P_REG_DESK_PAR_TX_TUS_L:
2872 *high_addr = P_REG_DESK_PAR_TX_TUS_U;
2873 return true;
2874 case P_REG_DESK_PCS_RX_TUS_L:
2875 *high_addr = P_REG_DESK_PCS_RX_TUS_U;
2876 return true;
2877 case P_REG_DESK_PCS_TX_TUS_L:
2878 *high_addr = P_REG_DESK_PCS_TX_TUS_U;
2879 return true;
2880 default:
2881 return false;
2882 }
2883 }
2884
2885 /**
2886 * ice_read_phy_reg_e82x - Read a PHY register
2887 * @hw: pointer to the HW struct
2888 * @port: PHY port to read from
2889 * @offset: PHY register offset to read
2890 * @val: on return, the contents read from the PHY
2891 *
2892 * Read a PHY register for the given port over the device sideband queue.
2893 */
2894 static int
ice_read_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 offset,u32 * val)2895 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
2896 {
2897 struct ice_sbq_msg_input msg = {0};
2898 int err;
2899
2900 ice_fill_phy_msg_e82x(hw, &msg, port, offset);
2901 msg.opcode = ice_sbq_msg_rd;
2902
2903 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
2904 if (err) {
2905 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2906 err);
2907 return err;
2908 }
2909
2910 *val = msg.data;
2911
2912 return 0;
2913 }
2914
2915 /**
2916 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers
2917 * @hw: pointer to the HW struct
2918 * @port: PHY port to read from
2919 * @low_addr: offset of the lower register to read from
2920 * @val: on return, the contents of the 64bit value from the PHY registers
2921 *
2922 * Reads the two registers associated with a 64bit value and returns it in the
2923 * val pointer. The offset always specifies the lower register offset to use.
2924 * The high offset is looked up. This function only operates on registers
2925 * known to be two parts of a 64bit value.
2926 */
2927 static int
ice_read_64b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val)2928 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
2929 {
2930 u32 low, high;
2931 u16 high_addr;
2932 int err;
2933
2934 /* Only operate on registers known to be split into two 32bit
2935 * registers.
2936 */
2937 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) {
2938 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
2939 low_addr);
2940 return -EINVAL;
2941 }
2942
2943 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low);
2944 if (err) {
2945 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",
2946 low_addr, err);
2947 return err;
2948 }
2949
2950 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high);
2951 if (err) {
2952 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",
2953 high_addr, err);
2954 return err;
2955 }
2956
2957 *val = (u64)high << 32 | low;
2958
2959 return 0;
2960 }
2961
2962 /**
2963 * ice_write_phy_reg_e82x - Write a PHY register
2964 * @hw: pointer to the HW struct
2965 * @port: PHY port to write to
2966 * @offset: PHY register offset to write
2967 * @val: The value to write to the register
2968 *
2969 * Write a PHY register for the given port over the device sideband queue.
2970 */
2971 static int
ice_write_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 offset,u32 val)2972 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val)
2973 {
2974 struct ice_sbq_msg_input msg = {0};
2975 int err;
2976
2977 ice_fill_phy_msg_e82x(hw, &msg, port, offset);
2978 msg.opcode = ice_sbq_msg_wr;
2979 msg.data = val;
2980
2981 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
2982 if (err) {
2983 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2984 err);
2985 return err;
2986 }
2987
2988 return 0;
2989 }
2990
2991 /**
2992 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY
2993 * @hw: pointer to the HW struct
2994 * @port: port to write to
2995 * @low_addr: offset of the low register
2996 * @val: 40b value to write
2997 *
2998 * Write the provided 40b value to the two associated registers by splitting
2999 * it up into two chunks, the lower 8 bits and the upper 32 bits.
3000 */
3001 static int
ice_write_40b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)3002 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
3003 {
3004 u32 low, high;
3005 u16 high_addr;
3006 int err;
3007
3008 /* Only operate on registers known to be split into a lower 8 bit
3009 * register and an upper 32 bit register.
3010 */
3011 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) {
3012 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",
3013 low_addr);
3014 return -EINVAL;
3015 }
3016 low = FIELD_GET(P_REG_40B_LOW_M, val);
3017 high = (u32)(val >> P_REG_40B_HIGH_S);
3018
3019 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
3020 if (err) {
3021 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
3022 low_addr, err);
3023 return err;
3024 }
3025
3026 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
3027 if (err) {
3028 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
3029 high_addr, err);
3030 return err;
3031 }
3032
3033 return 0;
3034 }
3035
3036 /**
3037 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers
3038 * @hw: pointer to the HW struct
3039 * @port: PHY port to read from
3040 * @low_addr: offset of the lower register to read from
3041 * @val: the contents of the 64bit value to write to PHY
3042 *
3043 * Write the 64bit value to the two associated 32bit PHY registers. The offset
3044 * is always specified as the lower register, and the high address is looked
3045 * up. This function only operates on registers known to be two parts of
3046 * a 64bit value.
3047 */
3048 static int
ice_write_64b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)3049 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
3050 {
3051 u32 low, high;
3052 u16 high_addr;
3053 int err;
3054
3055 /* Only operate on registers known to be split into two 32bit
3056 * registers.
3057 */
3058 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) {
3059 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
3060 low_addr);
3061 return -EINVAL;
3062 }
3063
3064 low = lower_32_bits(val);
3065 high = upper_32_bits(val);
3066
3067 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
3068 if (err) {
3069 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
3070 low_addr, err);
3071 return err;
3072 }
3073
3074 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
3075 if (err) {
3076 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
3077 high_addr, err);
3078 return err;
3079 }
3080
3081 return 0;
3082 }
3083
3084 /**
3085 * ice_fill_quad_msg_e82x - Fill message data for quad register access
3086 * @hw: pointer to the HW struct
3087 * @msg: the PHY message buffer to fill in
3088 * @quad: the quad to access
3089 * @offset: the register offset
3090 *
3091 * Fill a message buffer for accessing a register in a quad shared between
3092 * multiple PHYs.
3093 *
3094 * Return:
3095 * * %0 - OK
3096 * * %-EINVAL - invalid quad number
3097 */
ice_fill_quad_msg_e82x(struct ice_hw * hw,struct ice_sbq_msg_input * msg,u8 quad,u16 offset)3098 static int ice_fill_quad_msg_e82x(struct ice_hw *hw,
3099 struct ice_sbq_msg_input *msg, u8 quad,
3100 u16 offset)
3101 {
3102 u32 addr;
3103
3104 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports))
3105 return -EINVAL;
3106
3107 msg->dest_dev = rmn_0;
3108
3109 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy)))
3110 addr = Q_0_BASE + offset;
3111 else
3112 addr = Q_1_BASE + offset;
3113
3114 msg->msg_addr_low = lower_16_bits(addr);
3115 msg->msg_addr_high = upper_16_bits(addr);
3116
3117 return 0;
3118 }
3119
3120 /**
3121 * ice_read_quad_reg_e82x - Read a PHY quad register
3122 * @hw: pointer to the HW struct
3123 * @quad: quad to read from
3124 * @offset: quad register offset to read
3125 * @val: on return, the contents read from the quad
3126 *
3127 * Read a quad register over the device sideband queue. Quad registers are
3128 * shared between multiple PHYs.
3129 */
3130 int
ice_read_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 * val)3131 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
3132 {
3133 struct ice_sbq_msg_input msg = {0};
3134 int err;
3135
3136 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
3137 if (err)
3138 return err;
3139
3140 msg.opcode = ice_sbq_msg_rd;
3141
3142 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
3143 if (err) {
3144 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
3145 err);
3146 return err;
3147 }
3148
3149 *val = msg.data;
3150
3151 return 0;
3152 }
3153
3154 /**
3155 * ice_write_quad_reg_e82x - Write a PHY quad register
3156 * @hw: pointer to the HW struct
3157 * @quad: quad to write to
3158 * @offset: quad register offset to write
3159 * @val: The value to write to the register
3160 *
3161 * Write a quad register over the device sideband queue. Quad registers are
3162 * shared between multiple PHYs.
3163 */
3164 int
ice_write_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 val)3165 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
3166 {
3167 struct ice_sbq_msg_input msg = {0};
3168 int err;
3169
3170 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
3171 if (err)
3172 return err;
3173
3174 msg.opcode = ice_sbq_msg_wr;
3175 msg.data = val;
3176
3177 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
3178 if (err) {
3179 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
3180 err);
3181 return err;
3182 }
3183
3184 return 0;
3185 }
3186
3187 /**
3188 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block
3189 * @hw: pointer to the HW struct
3190 * @quad: the quad to read from
3191 * @idx: the timestamp index to read
3192 * @tstamp: on return, the 40bit timestamp value
3193 *
3194 * Read a 40bit timestamp value out of the two associated registers in the
3195 * quad memory block that is shared between the internal PHYs of the E822
3196 * family of devices.
3197 */
3198 static int
ice_read_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx,u64 * tstamp)3199 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
3200 {
3201 u16 lo_addr, hi_addr;
3202 u32 lo, hi;
3203 int err;
3204
3205 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
3206 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
3207
3208 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo);
3209 if (err) {
3210 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
3211 err);
3212 return err;
3213 }
3214
3215 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi);
3216 if (err) {
3217 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
3218 err);
3219 return err;
3220 }
3221
3222 /* For E822 based internal PHYs, the timestamp is reported with the
3223 * lower 8 bits in the low register, and the upper 32 bits in the high
3224 * register.
3225 */
3226 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) |
3227 FIELD_PREP(PHY_40B_LOW_M, lo);
3228
3229 return 0;
3230 }
3231
3232 /**
3233 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block
3234 * @hw: pointer to the HW struct
3235 * @quad: the quad to read from
3236 * @idx: the timestamp index to reset
3237 *
3238 * Read the timestamp out of the quad to clear its timestamp status bit from
3239 * the PHY quad block that is shared between the internal PHYs of the E822
3240 * devices.
3241 *
3242 * Note that unlike E810, software cannot directly write to the quad memory
3243 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function
3244 * to determine which timestamps are valid. Reading a timestamp auto-clears
3245 * the valid bit.
3246 *
3247 * To directly clear the contents of the timestamp block entirely, discarding
3248 * all timestamp data at once, software should instead use
3249 * ice_ptp_reset_ts_memory_quad_e82x().
3250 *
3251 * This function should only be called on an idx whose bit is set according to
3252 * ice_get_phy_tx_tstamp_ready().
3253 */
3254 static int
ice_clear_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx)3255 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx)
3256 {
3257 u64 unused_tstamp;
3258 int err;
3259
3260 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp);
3261 if (err) {
3262 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n",
3263 quad, idx, err);
3264 return err;
3265 }
3266
3267 return 0;
3268 }
3269
3270 /**
3271 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block
3272 * @hw: pointer to the HW struct
3273 * @quad: the quad to read from
3274 *
3275 * Clear all timestamps from the PHY quad block that is shared between the
3276 * internal PHYs on the E822 devices.
3277 */
ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw * hw,u8 quad)3278 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad)
3279 {
3280 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
3281 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
3282 }
3283
3284 /**
3285 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
3286 * @hw: pointer to the HW struct
3287 */
ice_ptp_reset_ts_memory_e82x(struct ice_hw * hw)3288 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw)
3289 {
3290 unsigned int quad;
3291
3292 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++)
3293 ice_ptp_reset_ts_memory_quad_e82x(hw, quad);
3294 }
3295
3296 /**
3297 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
3298 * @hw: pointer to the HW struct
3299 *
3300 * Set the window length used for the vernier port calibration process.
3301 */
ice_ptp_set_vernier_wl(struct ice_hw * hw)3302 static int ice_ptp_set_vernier_wl(struct ice_hw *hw)
3303 {
3304 u8 port;
3305
3306 for (port = 0; port < hw->ptp.num_lports; port++) {
3307 int err;
3308
3309 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL,
3310 PTP_VERNIER_WL);
3311 if (err) {
3312 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n",
3313 port, err);
3314 return err;
3315 }
3316 }
3317
3318 return 0;
3319 }
3320
3321 /**
3322 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization
3323 * @hw: pointer to HW struct
3324 *
3325 * Perform PHC initialization steps specific to E822 devices.
3326 */
ice_ptp_init_phc_e82x(struct ice_hw * hw)3327 static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
3328 {
3329 int err;
3330 u32 val;
3331
3332 /* Enable reading switch and PHY registers over the sideband queue */
3333 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
3334 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
3335 val = rd32(hw, PF_SB_REM_DEV_CTL);
3336 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);
3337 wr32(hw, PF_SB_REM_DEV_CTL, val);
3338
3339 /* Initialize the Clock Generation Unit */
3340 err = ice_init_cgu_e82x(hw);
3341 if (err)
3342 return err;
3343
3344 /* Set window length for all the ports */
3345 return ice_ptp_set_vernier_wl(hw);
3346 }
3347
3348 /**
3349 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time
3350 * @hw: pointer to the HW struct
3351 * @time: Time to initialize the PHY port clocks to
3352 *
3353 * Program the PHY port registers with a new initial time value. The port
3354 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
3355 * command. The time value is the upper 32 bits of the PHY timer, usually in
3356 * units of nominal nanoseconds.
3357 */
3358 static int
ice_ptp_prep_phy_time_e82x(struct ice_hw * hw,u32 time)3359 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time)
3360 {
3361 u64 phy_time;
3362 u8 port;
3363 int err;
3364
3365 /* The time represents the upper 32 bits of the PHY timer, so we need
3366 * to shift to account for this when programming.
3367 */
3368 phy_time = (u64)time << 32;
3369
3370 for (port = 0; port < hw->ptp.num_lports; port++) {
3371 /* Tx case */
3372 err = ice_write_64b_phy_reg_e82x(hw, port,
3373 P_REG_TX_TIMER_INC_PRE_L,
3374 phy_time);
3375 if (err)
3376 goto exit_err;
3377
3378 /* Rx case */
3379 err = ice_write_64b_phy_reg_e82x(hw, port,
3380 P_REG_RX_TIMER_INC_PRE_L,
3381 phy_time);
3382 if (err)
3383 goto exit_err;
3384 }
3385
3386 return 0;
3387
3388 exit_err:
3389 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
3390 port, err);
3391
3392 return err;
3393 }
3394
3395 /**
3396 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust
3397 * @hw: pointer to HW struct
3398 * @port: Port number to be programmed
3399 * @time: time in cycles to adjust the port Tx and Rx clocks
3400 *
3401 * Program the port for an atomic adjustment by writing the Tx and Rx timer
3402 * registers. The atomic adjustment won't be completed until the driver issues
3403 * an ICE_PTP_ADJ_TIME command.
3404 *
3405 * Note that time is not in units of nanoseconds. It is in clock time
3406 * including the lower sub-nanosecond portion of the port timer.
3407 *
3408 * Negative adjustments are supported using 2s complement arithmetic.
3409 */
3410 static int
ice_ptp_prep_port_adj_e82x(struct ice_hw * hw,u8 port,s64 time)3411 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time)
3412 {
3413 u32 l_time, u_time;
3414 int err;
3415
3416 l_time = lower_32_bits(time);
3417 u_time = upper_32_bits(time);
3418
3419 /* Tx case */
3420 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L,
3421 l_time);
3422 if (err)
3423 goto exit_err;
3424
3425 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U,
3426 u_time);
3427 if (err)
3428 goto exit_err;
3429
3430 /* Rx case */
3431 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L,
3432 l_time);
3433 if (err)
3434 goto exit_err;
3435
3436 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U,
3437 u_time);
3438 if (err)
3439 goto exit_err;
3440
3441 return 0;
3442
3443 exit_err:
3444 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
3445 port, err);
3446 return err;
3447 }
3448
3449 /**
3450 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment
3451 * @hw: pointer to HW struct
3452 * @adj: adjustment in nanoseconds
3453 *
3454 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
3455 * Tx and Rx port registers. The actual adjustment is completed by issuing an
3456 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
3457 */
3458 static int
ice_ptp_prep_phy_adj_e82x(struct ice_hw * hw,s32 adj)3459 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj)
3460 {
3461 s64 cycles;
3462 u8 port;
3463
3464 /* The port clock supports adjustment of the sub-nanosecond portion of
3465 * the clock. We shift the provided adjustment in nanoseconds to
3466 * calculate the appropriate adjustment to program into the PHY ports.
3467 */
3468 if (adj > 0)
3469 cycles = (s64)adj << 32;
3470 else
3471 cycles = -(((s64)-adj) << 32);
3472
3473 for (port = 0; port < hw->ptp.num_lports; port++) {
3474 int err;
3475
3476 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles);
3477 if (err)
3478 return err;
3479 }
3480
3481 return 0;
3482 }
3483
3484 /**
3485 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment
3486 * @hw: pointer to HW struct
3487 * @incval: new increment value to prepare
3488 *
3489 * Prepare each of the PHY ports for a new increment value by programming the
3490 * port's TIMETUS registers. The new increment value will be updated after
3491 * issuing an ICE_PTP_INIT_INCVAL command.
3492 */
3493 static int
ice_ptp_prep_phy_incval_e82x(struct ice_hw * hw,u64 incval)3494 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval)
3495 {
3496 int err;
3497 u8 port;
3498
3499 for (port = 0; port < hw->ptp.num_lports; port++) {
3500 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L,
3501 incval);
3502 if (err)
3503 goto exit_err;
3504 }
3505
3506 return 0;
3507
3508 exit_err:
3509 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
3510 port, err);
3511
3512 return err;
3513 }
3514
3515 /**
3516 * ice_ptp_read_port_capture - Read a port's local time capture
3517 * @hw: pointer to HW struct
3518 * @port: Port number to read
3519 * @tx_ts: on return, the Tx port time capture
3520 * @rx_ts: on return, the Rx port time capture
3521 *
3522 * Read the port's Tx and Rx local time capture values.
3523 *
3524 * Note this has no equivalent for the E810 devices.
3525 */
3526 static int
ice_ptp_read_port_capture(struct ice_hw * hw,u8 port,u64 * tx_ts,u64 * rx_ts)3527 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
3528 {
3529 int err;
3530
3531 /* Tx case */
3532 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
3533 if (err) {
3534 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
3535 err);
3536 return err;
3537 }
3538
3539 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
3540 (unsigned long long)*tx_ts);
3541
3542 /* Rx case */
3543 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
3544 if (err) {
3545 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
3546 err);
3547 return err;
3548 }
3549
3550 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
3551 (unsigned long long)*rx_ts);
3552
3553 return 0;
3554 }
3555
3556 /**
3557 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command
3558 * @hw: pointer to HW struct
3559 * @port: Port to which cmd has to be sent
3560 * @cmd: Command to be sent to the port
3561 *
3562 * Prepare the requested port for an upcoming timer sync command.
3563 *
3564 * Note there is no equivalent of this operation on E810, as that device
3565 * always handles all external PHYs internally.
3566 *
3567 * Return:
3568 * * %0 - success
3569 * * %other - failed to write to PHY
3570 */
ice_ptp_write_port_cmd_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)3571 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port,
3572 enum ice_ptp_tmr_cmd cmd)
3573 {
3574 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
3575 int err;
3576
3577 /* Tx case */
3578 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val);
3579 if (err) {
3580 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
3581 err);
3582 return err;
3583 }
3584
3585 /* Rx case */
3586 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD,
3587 val | TS_CMD_RX_TYPE);
3588 if (err) {
3589 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
3590 err);
3591 return err;
3592 }
3593
3594 return 0;
3595 }
3596
3597 /* E822 Vernier calibration functions
3598 *
3599 * The following functions are used as part of the vernier calibration of
3600 * a port. This calibration increases the precision of the timestamps on the
3601 * port.
3602 */
3603
3604 /**
3605 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode
3606 * @hw: pointer to HW struct
3607 * @port: the port to read from
3608 * @link_out: if non-NULL, holds link speed on success
3609 * @fec_out: if non-NULL, holds FEC algorithm on success
3610 *
3611 * Read the serdes data for the PHY port and extract the link speed and FEC
3612 * algorithm.
3613 */
3614 static int
ice_phy_get_speed_and_fec_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_link_spd * link_out,enum ice_ptp_fec_mode * fec_out)3615 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port,
3616 enum ice_ptp_link_spd *link_out,
3617 enum ice_ptp_fec_mode *fec_out)
3618 {
3619 enum ice_ptp_link_spd link;
3620 enum ice_ptp_fec_mode fec;
3621 u32 serdes;
3622 int err;
3623
3624 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes);
3625 if (err) {
3626 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
3627 return err;
3628 }
3629
3630 /* Determine the FEC algorithm */
3631 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes);
3632
3633 serdes &= P_REG_LINK_SPEED_SERDES_M;
3634
3635 /* Determine the link speed */
3636 if (fec == ICE_PTP_FEC_MODE_RS_FEC) {
3637 switch (serdes) {
3638 case ICE_PTP_SERDES_25G:
3639 link = ICE_PTP_LNK_SPD_25G_RS;
3640 break;
3641 case ICE_PTP_SERDES_50G:
3642 link = ICE_PTP_LNK_SPD_50G_RS;
3643 break;
3644 case ICE_PTP_SERDES_100G:
3645 link = ICE_PTP_LNK_SPD_100G_RS;
3646 break;
3647 default:
3648 return -EIO;
3649 }
3650 } else {
3651 switch (serdes) {
3652 case ICE_PTP_SERDES_1G:
3653 link = ICE_PTP_LNK_SPD_1G;
3654 break;
3655 case ICE_PTP_SERDES_10G:
3656 link = ICE_PTP_LNK_SPD_10G;
3657 break;
3658 case ICE_PTP_SERDES_25G:
3659 link = ICE_PTP_LNK_SPD_25G;
3660 break;
3661 case ICE_PTP_SERDES_40G:
3662 link = ICE_PTP_LNK_SPD_40G;
3663 break;
3664 case ICE_PTP_SERDES_50G:
3665 link = ICE_PTP_LNK_SPD_50G;
3666 break;
3667 default:
3668 return -EIO;
3669 }
3670 }
3671
3672 if (link_out)
3673 *link_out = link;
3674 if (fec_out)
3675 *fec_out = fec;
3676
3677 return 0;
3678 }
3679
3680 /**
3681 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp
3682 * @hw: pointer to HW struct
3683 * @port: to configure the quad for
3684 */
ice_phy_cfg_lane_e82x(struct ice_hw * hw,u8 port)3685 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port)
3686 {
3687 enum ice_ptp_link_spd link_spd;
3688 int err;
3689 u32 val;
3690 u8 quad;
3691
3692 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL);
3693 if (err) {
3694 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n",
3695 err);
3696 return;
3697 }
3698
3699 quad = ICE_GET_QUAD_NUM(port);
3700
3701 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
3702 if (err) {
3703 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n",
3704 err);
3705 return;
3706 }
3707
3708 if (link_spd >= ICE_PTP_LNK_SPD_40G)
3709 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
3710 else
3711 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
3712
3713 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
3714 if (err) {
3715 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n",
3716 err);
3717 return;
3718 }
3719 }
3720
3721 /**
3722 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822
3723 * @hw: pointer to the HW structure
3724 * @port: the port to configure
3725 *
3726 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC
3727 * hardware clock time units (TUs). That is, determine the number of TUs per
3728 * serdes unit interval, and program the UIX registers with this conversion.
3729 *
3730 * This conversion is used as part of the calibration process when determining
3731 * the additional error of a timestamp vs the real time of transmission or
3732 * receipt of the packet.
3733 *
3734 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers
3735 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks.
3736 *
3737 * To calculate the conversion ratio, we use the following facts:
3738 *
3739 * a) the clock frequency in Hz (cycles per second)
3740 * b) the number of TUs per cycle (the increment value of the clock)
3741 * c) 1 second per 1 billion nanoseconds
3742 * d) the duration of 66 UIs in nanoseconds
3743 *
3744 * Given these facts, we can use the following table to work out what ratios
3745 * to multiply in order to get the number of TUs per 66 UIs:
3746 *
3747 * cycles | 1 second | incval (TUs) | nanoseconds
3748 * -------+--------------+--------------+-------------
3749 * second | 1 billion ns | cycle | 66 UIs
3750 *
3751 * To perform the multiplication using integers without too much loss of
3752 * precision, we can take use the following equation:
3753 *
3754 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion)
3755 *
3756 * We scale up to using 6600 UI instead of 66 in order to avoid fractional
3757 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns)
3758 *
3759 * The increment value has a maximum expected range of about 34 bits, while
3760 * the frequency value is about 29 bits. Multiplying these values shouldn't
3761 * overflow the 64 bits. However, we must then further multiply them again by
3762 * the Serdes unit interval duration. To avoid overflow here, we split the
3763 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and
3764 * a divide by 390,625,000. This does lose some precision, but avoids
3765 * miscalculation due to arithmetic overflow.
3766 */
ice_phy_cfg_uix_e82x(struct ice_hw * hw,u8 port)3767 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port)
3768 {
3769 u64 cur_freq, clk_incval, tu_per_sec, uix;
3770 int err;
3771
3772 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3773 clk_incval = ice_ptp_read_src_incval(hw);
3774
3775 /* Calculate TUs per second divided by 256 */
3776 tu_per_sec = (cur_freq * clk_incval) >> 8;
3777
3778 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */
3779 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
3780
3781 /* Program the 10Gb/40Gb conversion ratio */
3782 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000);
3783
3784 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L,
3785 uix);
3786 if (err) {
3787 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n",
3788 err);
3789 return err;
3790 }
3791
3792 /* Program the 25Gb/100Gb conversion ratio */
3793 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000);
3794
3795 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L,
3796 uix);
3797 if (err) {
3798 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n",
3799 err);
3800 return err;
3801 }
3802
3803 return 0;
3804 }
3805
3806 /**
3807 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle
3808 * @hw: pointer to the HW struct
3809 * @port: port to configure
3810 *
3811 * Configure the number of TUs for the PAR and PCS clocks used as part of the
3812 * timestamp calibration process. This depends on the link speed, as the PHY
3813 * uses different markers depending on the speed.
3814 *
3815 * 1Gb/10Gb/25Gb:
3816 * - Tx/Rx PAR/PCS markers
3817 *
3818 * 25Gb RS:
3819 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3820 *
3821 * 40Gb/50Gb:
3822 * - Tx/Rx PAR/PCS markers
3823 * - Rx Deskew PAR/PCS markers
3824 *
3825 * 50G RS and 100GB RS:
3826 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3827 * - Rx Deskew PAR/PCS markers
3828 * - Tx PAR/PCS markers
3829 *
3830 * To calculate the conversion, we use the PHC clock frequency (cycles per
3831 * second), the increment value (TUs per cycle), and the related PHY clock
3832 * frequency to calculate the TUs per unit of the PHY link clock. The
3833 * following table shows how the units convert:
3834 *
3835 * cycles | TUs | second
3836 * -------+-------+--------
3837 * second | cycle | cycles
3838 *
3839 * For each conversion register, look up the appropriate frequency from the
3840 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program
3841 * this to the appropriate register, preparing hardware to perform timestamp
3842 * calibration to calculate the total Tx or Rx offset to adjust the timestamp
3843 * in order to calibrate for the internal PHY delays.
3844 *
3845 * Note that the increment value ranges up to ~34 bits, and the clock
3846 * frequency is ~29 bits, so multiplying them together should fit within the
3847 * 64 bit arithmetic.
3848 */
ice_phy_cfg_parpcs_e82x(struct ice_hw * hw,u8 port)3849 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port)
3850 {
3851 u64 cur_freq, clk_incval, tu_per_sec, phy_tus;
3852 enum ice_ptp_link_spd link_spd;
3853 enum ice_ptp_fec_mode fec_mode;
3854 int err;
3855
3856 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
3857 if (err)
3858 return err;
3859
3860 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3861 clk_incval = ice_ptp_read_src_incval(hw);
3862
3863 /* Calculate TUs per cycle of the PHC clock */
3864 tu_per_sec = cur_freq * clk_incval;
3865
3866 /* For each PHY conversion register, look up the appropriate link
3867 * speed frequency and determine the TUs per that clock's cycle time.
3868 * Split this into a high and low value and then program the
3869 * appropriate register. If that link speed does not use the
3870 * associated register, write zeros to clear it instead.
3871 */
3872
3873 /* P_REG_PAR_TX_TUS */
3874 if (e822_vernier[link_spd].tx_par_clk)
3875 phy_tus = div_u64(tu_per_sec,
3876 e822_vernier[link_spd].tx_par_clk);
3877 else
3878 phy_tus = 0;
3879
3880 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L,
3881 phy_tus);
3882 if (err)
3883 return err;
3884
3885 /* P_REG_PAR_RX_TUS */
3886 if (e822_vernier[link_spd].rx_par_clk)
3887 phy_tus = div_u64(tu_per_sec,
3888 e822_vernier[link_spd].rx_par_clk);
3889 else
3890 phy_tus = 0;
3891
3892 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L,
3893 phy_tus);
3894 if (err)
3895 return err;
3896
3897 /* P_REG_PCS_TX_TUS */
3898 if (e822_vernier[link_spd].tx_pcs_clk)
3899 phy_tus = div_u64(tu_per_sec,
3900 e822_vernier[link_spd].tx_pcs_clk);
3901 else
3902 phy_tus = 0;
3903
3904 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L,
3905 phy_tus);
3906 if (err)
3907 return err;
3908
3909 /* P_REG_PCS_RX_TUS */
3910 if (e822_vernier[link_spd].rx_pcs_clk)
3911 phy_tus = div_u64(tu_per_sec,
3912 e822_vernier[link_spd].rx_pcs_clk);
3913 else
3914 phy_tus = 0;
3915
3916 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L,
3917 phy_tus);
3918 if (err)
3919 return err;
3920
3921 /* P_REG_DESK_PAR_TX_TUS */
3922 if (e822_vernier[link_spd].tx_desk_rsgb_par)
3923 phy_tus = div_u64(tu_per_sec,
3924 e822_vernier[link_spd].tx_desk_rsgb_par);
3925 else
3926 phy_tus = 0;
3927
3928 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L,
3929 phy_tus);
3930 if (err)
3931 return err;
3932
3933 /* P_REG_DESK_PAR_RX_TUS */
3934 if (e822_vernier[link_spd].rx_desk_rsgb_par)
3935 phy_tus = div_u64(tu_per_sec,
3936 e822_vernier[link_spd].rx_desk_rsgb_par);
3937 else
3938 phy_tus = 0;
3939
3940 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L,
3941 phy_tus);
3942 if (err)
3943 return err;
3944
3945 /* P_REG_DESK_PCS_TX_TUS */
3946 if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
3947 phy_tus = div_u64(tu_per_sec,
3948 e822_vernier[link_spd].tx_desk_rsgb_pcs);
3949 else
3950 phy_tus = 0;
3951
3952 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L,
3953 phy_tus);
3954 if (err)
3955 return err;
3956
3957 /* P_REG_DESK_PCS_RX_TUS */
3958 if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
3959 phy_tus = div_u64(tu_per_sec,
3960 e822_vernier[link_spd].rx_desk_rsgb_pcs);
3961 else
3962 phy_tus = 0;
3963
3964 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L,
3965 phy_tus);
3966 }
3967
3968 /**
3969 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port
3970 * @hw: pointer to the HW struct
3971 * @link_spd: the Link speed to calculate for
3972 *
3973 * Calculate the fixed offset due to known static latency data.
3974 */
3975 static u64
ice_calc_fixed_tx_offset_e82x(struct ice_hw * hw,enum ice_ptp_link_spd link_spd)3976 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
3977 {
3978 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
3979
3980 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3981 clk_incval = ice_ptp_read_src_incval(hw);
3982
3983 /* Calculate TUs per second */
3984 tu_per_sec = cur_freq * clk_incval;
3985
3986 /* Calculate number of TUs to add for the fixed Tx latency. Since the
3987 * latency measurement is in 1/100th of a nanosecond, we need to
3988 * multiply by tu_per_sec and then divide by 1e11. This calculation
3989 * overflows 64 bit integer arithmetic, so break it up into two
3990 * divisions by 1e4 first then by 1e7.
3991 */
3992 fixed_offset = div_u64(tu_per_sec, 10000);
3993 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
3994 fixed_offset = div_u64(fixed_offset, 10000000);
3995
3996 return fixed_offset;
3997 }
3998
3999 /**
4000 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset
4001 * @hw: pointer to the HW struct
4002 * @port: the PHY port to configure
4003 *
4004 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to
4005 * adjust Tx timestamps by. This is calculated by combining some known static
4006 * latency along with the Vernier offset computations done by hardware.
4007 *
4008 * This function will not return successfully until the Tx offset calculations
4009 * have been completed, which requires waiting until at least one packet has
4010 * been transmitted by the device. It is safe to call this function
4011 * periodically until calibration succeeds, as it will only program the offset
4012 * once.
4013 *
4014 * To avoid overflow, when calculating the offset based on the known static
4015 * latency values, we use measurements in 1/100th of a nanosecond, and divide
4016 * the TUs per second up front. This avoids overflow while allowing
4017 * calculation of the adjustment using integer arithmetic.
4018 *
4019 * Returns zero on success, -EBUSY if the hardware vernier offset
4020 * calibration has not completed, or another error code on failure.
4021 */
ice_phy_cfg_tx_offset_e82x(struct ice_hw * hw,u8 port)4022 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port)
4023 {
4024 enum ice_ptp_link_spd link_spd;
4025 enum ice_ptp_fec_mode fec_mode;
4026 u64 total_offset, val;
4027 int err;
4028 u32 reg;
4029
4030 /* Nothing to do if we've already programmed the offset */
4031 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®);
4032 if (err) {
4033 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n",
4034 port, err);
4035 return err;
4036 }
4037
4038 if (reg)
4039 return 0;
4040
4041 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®);
4042 if (err) {
4043 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",
4044 port, err);
4045 return err;
4046 }
4047
4048 if (!(reg & P_REG_TX_OV_STATUS_OV_M))
4049 return -EBUSY;
4050
4051 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
4052 if (err)
4053 return err;
4054
4055 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd);
4056
4057 /* Read the first Vernier offset from the PHY register and add it to
4058 * the total offset.
4059 */
4060 if (link_spd == ICE_PTP_LNK_SPD_1G ||
4061 link_spd == ICE_PTP_LNK_SPD_10G ||
4062 link_spd == ICE_PTP_LNK_SPD_25G ||
4063 link_spd == ICE_PTP_LNK_SPD_25G_RS ||
4064 link_spd == ICE_PTP_LNK_SPD_40G ||
4065 link_spd == ICE_PTP_LNK_SPD_50G) {
4066 err = ice_read_64b_phy_reg_e82x(hw, port,
4067 P_REG_PAR_PCS_TX_OFFSET_L,
4068 &val);
4069 if (err)
4070 return err;
4071
4072 total_offset += val;
4073 }
4074
4075 /* For Tx, we only need to use the second Vernier offset for
4076 * multi-lane link speeds with RS-FEC. The lanes will always be
4077 * aligned.
4078 */
4079 if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||
4080 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
4081 err = ice_read_64b_phy_reg_e82x(hw, port,
4082 P_REG_PAR_TX_TIME_L,
4083 &val);
4084 if (err)
4085 return err;
4086
4087 total_offset += val;
4088 }
4089
4090 /* Now that the total offset has been calculated, program it to the
4091 * PHY and indicate that the Tx offset is ready. After this,
4092 * timestamps will be enabled.
4093 */
4094 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L,
4095 total_offset);
4096 if (err)
4097 return err;
4098
4099 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1);
4100 if (err)
4101 return err;
4102
4103 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n",
4104 port);
4105
4106 return 0;
4107 }
4108
4109 /**
4110 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx
4111 * @hw: pointer to the HW struct
4112 * @port: the PHY port to adjust for
4113 * @link_spd: the current link speed of the PHY
4114 * @fec_mode: the current FEC mode of the PHY
4115 * @pmd_adj: on return, the amount to adjust the Rx total offset by
4116 *
4117 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY.
4118 * This varies by link speed and FEC mode. The value calculated accounts for
4119 * various delays caused when receiving a packet.
4120 */
4121 static int
ice_phy_calc_pmd_adj_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_link_spd link_spd,enum ice_ptp_fec_mode fec_mode,u64 * pmd_adj)4122 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port,
4123 enum ice_ptp_link_spd link_spd,
4124 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
4125 {
4126 u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
4127 u8 pmd_align;
4128 u32 val;
4129 int err;
4130
4131 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val);
4132 if (err) {
4133 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n",
4134 err);
4135 return err;
4136 }
4137
4138 pmd_align = (u8)val;
4139
4140 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
4141 clk_incval = ice_ptp_read_src_incval(hw);
4142
4143 /* Calculate TUs per second */
4144 tu_per_sec = cur_freq * clk_incval;
4145
4146 /* The PMD alignment adjustment measurement depends on the link speed,
4147 * and whether FEC is enabled. For each link speed, the alignment
4148 * adjustment is calculated by dividing a value by the length of
4149 * a Time Unit in nanoseconds.
4150 *
4151 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8
4152 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33)
4153 * 10G w/FEC: align * 0.1 * 32/33
4154 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33)
4155 * 25G w/FEC: align * 0.4 * 32/33
4156 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33)
4157 * 40G w/FEC: align * 0.1 * 32/33
4158 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33)
4159 * 50G w/FEC: align * 0.8 * 32/33
4160 *
4161 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33.
4162 *
4163 * To allow for calculating this value using integer arithmetic, we
4164 * instead start with the number of TUs per second, (inverse of the
4165 * length of a Time Unit in nanoseconds), multiply by a value based
4166 * on the PMD alignment register, and then divide by the right value
4167 * calculated based on the table above. To avoid integer overflow this
4168 * division is broken up into a step of dividing by 125 first.
4169 */
4170 if (link_spd == ICE_PTP_LNK_SPD_1G) {
4171 if (pmd_align == 4)
4172 mult = 10;
4173 else
4174 mult = (pmd_align + 6) % 10;
4175 } else if (link_spd == ICE_PTP_LNK_SPD_10G ||
4176 link_spd == ICE_PTP_LNK_SPD_25G ||
4177 link_spd == ICE_PTP_LNK_SPD_40G ||
4178 link_spd == ICE_PTP_LNK_SPD_50G) {
4179 /* If Clause 74 FEC, always calculate PMD adjust */
4180 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74)
4181 mult = pmd_align;
4182 else
4183 mult = 0;
4184 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS ||
4185 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
4186 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
4187 if (pmd_align < 17)
4188 mult = pmd_align + 40;
4189 else
4190 mult = pmd_align;
4191 } else {
4192 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n",
4193 link_spd);
4194 mult = 0;
4195 }
4196
4197 /* In some cases, there's no need to adjust for the PMD alignment */
4198 if (!mult) {
4199 *pmd_adj = 0;
4200 return 0;
4201 }
4202
4203 /* Calculate the adjustment by multiplying TUs per second by the
4204 * appropriate multiplier and divisor. To avoid overflow, we first
4205 * divide by 125, and then handle remaining divisor based on the link
4206 * speed pmd_adj_divisor value.
4207 */
4208 adj = div_u64(tu_per_sec, 125);
4209 adj *= mult;
4210 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor);
4211
4212 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
4213 * cycle count is necessary.
4214 */
4215 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) {
4216 u64 cycle_adj;
4217 u8 rx_cycle;
4218
4219 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT,
4220 &val);
4221 if (err) {
4222 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n",
4223 err);
4224 return err;
4225 }
4226
4227 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M;
4228 if (rx_cycle) {
4229 mult = (4 - rx_cycle) * 40;
4230
4231 cycle_adj = div_u64(tu_per_sec, 125);
4232 cycle_adj *= mult;
4233 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
4234
4235 adj += cycle_adj;
4236 }
4237 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) {
4238 u64 cycle_adj;
4239 u8 rx_cycle;
4240
4241 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT,
4242 &val);
4243 if (err) {
4244 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n",
4245 err);
4246 return err;
4247 }
4248
4249 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M;
4250 if (rx_cycle) {
4251 mult = rx_cycle * 40;
4252
4253 cycle_adj = div_u64(tu_per_sec, 125);
4254 cycle_adj *= mult;
4255 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
4256
4257 adj += cycle_adj;
4258 }
4259 }
4260
4261 /* Return the calculated adjustment */
4262 *pmd_adj = adj;
4263
4264 return 0;
4265 }
4266
4267 /**
4268 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port
4269 * @hw: pointer to HW struct
4270 * @link_spd: The Link speed to calculate for
4271 *
4272 * Determine the fixed Rx latency for a given link speed.
4273 */
4274 static u64
ice_calc_fixed_rx_offset_e82x(struct ice_hw * hw,enum ice_ptp_link_spd link_spd)4275 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
4276 {
4277 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
4278
4279 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
4280 clk_incval = ice_ptp_read_src_incval(hw);
4281
4282 /* Calculate TUs per second */
4283 tu_per_sec = cur_freq * clk_incval;
4284
4285 /* Calculate number of TUs to add for the fixed Rx latency. Since the
4286 * latency measurement is in 1/100th of a nanosecond, we need to
4287 * multiply by tu_per_sec and then divide by 1e11. This calculation
4288 * overflows 64 bit integer arithmetic, so break it up into two
4289 * divisions by 1e4 first then by 1e7.
4290 */
4291 fixed_offset = div_u64(tu_per_sec, 10000);
4292 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
4293 fixed_offset = div_u64(fixed_offset, 10000000);
4294
4295 return fixed_offset;
4296 }
4297
4298 /**
4299 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset
4300 * @hw: pointer to the HW struct
4301 * @port: the PHY port to configure
4302 *
4303 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to
4304 * adjust Rx timestamps by. This combines calculations from the Vernier offset
4305 * measurements taken in hardware with some data about known fixed delay as
4306 * well as adjusting for multi-lane alignment delay.
4307 *
4308 * This function will not return successfully until the Rx offset calculations
4309 * have been completed, which requires waiting until at least one packet has
4310 * been received by the device. It is safe to call this function periodically
4311 * until calibration succeeds, as it will only program the offset once.
4312 *
4313 * This function must be called only after the offset registers are valid,
4314 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
4315 * has measured the offset.
4316 *
4317 * To avoid overflow, when calculating the offset based on the known static
4318 * latency values, we use measurements in 1/100th of a nanosecond, and divide
4319 * the TUs per second up front. This avoids overflow while allowing
4320 * calculation of the adjustment using integer arithmetic.
4321 *
4322 * Returns zero on success, -EBUSY if the hardware vernier offset
4323 * calibration has not completed, or another error code on failure.
4324 */
ice_phy_cfg_rx_offset_e82x(struct ice_hw * hw,u8 port)4325 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port)
4326 {
4327 enum ice_ptp_link_spd link_spd;
4328 enum ice_ptp_fec_mode fec_mode;
4329 u64 total_offset, pmd, val;
4330 int err;
4331 u32 reg;
4332
4333 /* Nothing to do if we've already programmed the offset */
4334 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®);
4335 if (err) {
4336 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n",
4337 port, err);
4338 return err;
4339 }
4340
4341 if (reg)
4342 return 0;
4343
4344 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®);
4345 if (err) {
4346 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",
4347 port, err);
4348 return err;
4349 }
4350
4351 if (!(reg & P_REG_RX_OV_STATUS_OV_M))
4352 return -EBUSY;
4353
4354 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
4355 if (err)
4356 return err;
4357
4358 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd);
4359
4360 /* Read the first Vernier offset from the PHY register and add it to
4361 * the total offset.
4362 */
4363 err = ice_read_64b_phy_reg_e82x(hw, port,
4364 P_REG_PAR_PCS_RX_OFFSET_L,
4365 &val);
4366 if (err)
4367 return err;
4368
4369 total_offset += val;
4370
4371 /* For Rx, all multi-lane link speeds include a second Vernier
4372 * calibration, because the lanes might not be aligned.
4373 */
4374 if (link_spd == ICE_PTP_LNK_SPD_40G ||
4375 link_spd == ICE_PTP_LNK_SPD_50G ||
4376 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
4377 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
4378 err = ice_read_64b_phy_reg_e82x(hw, port,
4379 P_REG_PAR_RX_TIME_L,
4380 &val);
4381 if (err)
4382 return err;
4383
4384 total_offset += val;
4385 }
4386
4387 /* In addition, Rx must account for the PMD alignment */
4388 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd);
4389 if (err)
4390 return err;
4391
4392 /* For RS-FEC, this adjustment adds delay, but for other modes, it
4393 * subtracts delay.
4394 */
4395 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC)
4396 total_offset += pmd;
4397 else
4398 total_offset -= pmd;
4399
4400 /* Now that the total offset has been calculated, program it to the
4401 * PHY and indicate that the Rx offset is ready. After this,
4402 * timestamps will be enabled.
4403 */
4404 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L,
4405 total_offset);
4406 if (err)
4407 return err;
4408
4409 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1);
4410 if (err)
4411 return err;
4412
4413 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n",
4414 port);
4415
4416 return 0;
4417 }
4418
4419 /**
4420 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers
4421 * @hw: pointer to the HW struct
4422 *
4423 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted
4424 * and received timestamps as invalid.
4425 *
4426 * Return: 0 on success, other error codes when failed to write to PHY
4427 */
ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw * hw)4428 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw)
4429 {
4430 u8 port;
4431
4432 for (port = 0; port < hw->ptp.num_lports; port++) {
4433 int err;
4434
4435 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
4436 if (err) {
4437 dev_warn(ice_hw_to_dev(hw),
4438 "Failed to clear PHY TX_OFFSET_READY register\n");
4439 return err;
4440 }
4441
4442 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
4443 if (err) {
4444 dev_warn(ice_hw_to_dev(hw),
4445 "Failed to clear PHY RX_OFFSET_READY register\n");
4446 return err;
4447 }
4448 }
4449
4450 return 0;
4451 }
4452
4453 /**
4454 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
4455 * @hw: pointer to the HW struct
4456 * @port: the PHY port to read
4457 * @phy_time: on return, the 64bit PHY timer value
4458 * @phc_time: on return, the lower 64bits of PHC time
4459 *
4460 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
4461 * and PHC timer values.
4462 */
4463 static int
ice_read_phy_and_phc_time_e82x(struct ice_hw * hw,u8 port,u64 * phy_time,u64 * phc_time)4464 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time,
4465 u64 *phc_time)
4466 {
4467 u64 tx_time, rx_time;
4468 u32 zo, lo;
4469 u8 tmr_idx;
4470 int err;
4471
4472 tmr_idx = ice_get_ptp_src_clock_index(hw);
4473
4474 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
4475 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
4476
4477 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
4478 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
4479 if (err)
4480 return err;
4481
4482 /* Issue the sync to start the ICE_PTP_READ_TIME capture */
4483 ice_ptp_exec_tmr_cmd(hw);
4484
4485 /* Read the captured PHC time from the shadow time registers */
4486 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
4487 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
4488 *phc_time = (u64)lo << 32 | zo;
4489
4490 /* Read the captured PHY time from the PHY shadow registers */
4491 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
4492 if (err)
4493 return err;
4494
4495 /* If the PHY Tx and Rx timers don't match, log a warning message.
4496 * Note that this should not happen in normal circumstances since the
4497 * driver always programs them together.
4498 */
4499 if (tx_time != rx_time)
4500 dev_warn(ice_hw_to_dev(hw),
4501 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
4502 port, (unsigned long long)tx_time,
4503 (unsigned long long)rx_time);
4504
4505 *phy_time = tx_time;
4506
4507 return 0;
4508 }
4509
4510 /**
4511 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer
4512 * @hw: pointer to the HW struct
4513 * @port: the PHY port to synchronize
4514 *
4515 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
4516 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
4517 * simultaneous read of the PHY timer and PHC timer. Then we use the
4518 * difference to calculate an appropriate 2s complement addition to add
4519 * to the PHY timer in order to ensure it reads the same value as the
4520 * primary PHC timer.
4521 */
ice_sync_phy_timer_e82x(struct ice_hw * hw,u8 port)4522 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port)
4523 {
4524 u64 phc_time, phy_time, difference;
4525 int err;
4526
4527 if (!ice_ptp_lock(hw)) {
4528 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
4529 return -EBUSY;
4530 }
4531
4532 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
4533 if (err)
4534 goto err_unlock;
4535
4536 /* Calculate the amount required to add to the port time in order for
4537 * it to match the PHC time.
4538 *
4539 * Note that the port adjustment is done using 2s complement
4540 * arithmetic. This is convenient since it means that we can simply
4541 * calculate the difference between the PHC time and the port time,
4542 * and it will be interpreted correctly.
4543 */
4544 difference = phc_time - phy_time;
4545
4546 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference);
4547 if (err)
4548 goto err_unlock;
4549
4550 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
4551 if (err)
4552 goto err_unlock;
4553
4554 /* Do not perform any action on the main timer */
4555 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
4556
4557 /* Issue the sync to activate the time adjustment */
4558 ice_ptp_exec_tmr_cmd(hw);
4559
4560 /* Re-capture the timer values to flush the command registers and
4561 * verify that the time was properly adjusted.
4562 */
4563 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
4564 if (err)
4565 goto err_unlock;
4566
4567 dev_info(ice_hw_to_dev(hw),
4568 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
4569 port, (unsigned long long)phy_time,
4570 (unsigned long long)phc_time);
4571
4572 ice_ptp_unlock(hw);
4573
4574 return 0;
4575
4576 err_unlock:
4577 ice_ptp_unlock(hw);
4578 return err;
4579 }
4580
4581 /**
4582 * ice_stop_phy_timer_e82x - Stop the PHY clock timer
4583 * @hw: pointer to the HW struct
4584 * @port: the PHY port to stop
4585 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS
4586 *
4587 * Stop the clock of a PHY port. This must be done as part of the flow to
4588 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4589 * initialized or when link speed changes.
4590 */
4591 int
ice_stop_phy_timer_e82x(struct ice_hw * hw,u8 port,bool soft_reset)4592 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset)
4593 {
4594 int err;
4595 u32 val;
4596
4597 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
4598 if (err)
4599 return err;
4600
4601 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
4602 if (err)
4603 return err;
4604
4605 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
4606 if (err)
4607 return err;
4608
4609 val &= ~P_REG_PS_START_M;
4610 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4611 if (err)
4612 return err;
4613
4614 val &= ~P_REG_PS_ENA_CLK_M;
4615 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4616 if (err)
4617 return err;
4618
4619 if (soft_reset) {
4620 val |= P_REG_PS_SFT_RESET_M;
4621 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4622 if (err)
4623 return err;
4624 }
4625
4626 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
4627
4628 return 0;
4629 }
4630
4631 /**
4632 * ice_start_phy_timer_e82x - Start the PHY clock timer
4633 * @hw: pointer to the HW struct
4634 * @port: the PHY port to start
4635 *
4636 * Start the clock of a PHY port. This must be done as part of the flow to
4637 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4638 * initialized or when link speed changes.
4639 *
4640 * Hardware will take Vernier measurements on Tx or Rx of packets.
4641 */
ice_start_phy_timer_e82x(struct ice_hw * hw,u8 port)4642 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port)
4643 {
4644 u32 lo, hi, val;
4645 u64 incval;
4646 u8 tmr_idx;
4647 int err;
4648
4649 tmr_idx = ice_get_ptp_src_clock_index(hw);
4650
4651 err = ice_stop_phy_timer_e82x(hw, port, false);
4652 if (err)
4653 return err;
4654
4655 ice_phy_cfg_lane_e82x(hw, port);
4656
4657 err = ice_phy_cfg_uix_e82x(hw, port);
4658 if (err)
4659 return err;
4660
4661 err = ice_phy_cfg_parpcs_e82x(hw, port);
4662 if (err)
4663 return err;
4664
4665 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
4666 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
4667 incval = (u64)hi << 32 | lo;
4668
4669 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval);
4670 if (err)
4671 return err;
4672
4673 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
4674 if (err)
4675 return err;
4676
4677 /* Do not perform any action on the main timer */
4678 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
4679
4680 ice_ptp_exec_tmr_cmd(hw);
4681
4682 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
4683 if (err)
4684 return err;
4685
4686 val |= P_REG_PS_SFT_RESET_M;
4687 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4688 if (err)
4689 return err;
4690
4691 val |= P_REG_PS_START_M;
4692 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4693 if (err)
4694 return err;
4695
4696 val &= ~P_REG_PS_SFT_RESET_M;
4697 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4698 if (err)
4699 return err;
4700
4701 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
4702 if (err)
4703 return err;
4704
4705 ice_ptp_exec_tmr_cmd(hw);
4706
4707 val |= P_REG_PS_ENA_CLK_M;
4708 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4709 if (err)
4710 return err;
4711
4712 val |= P_REG_PS_LOAD_OFFSET_M;
4713 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4714 if (err)
4715 return err;
4716
4717 ice_ptp_exec_tmr_cmd(hw);
4718
4719 err = ice_sync_phy_timer_e82x(hw, port);
4720 if (err)
4721 return err;
4722
4723 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
4724
4725 return 0;
4726 }
4727
4728 /**
4729 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register
4730 * @hw: pointer to the HW struct
4731 * @quad: the timestamp quad to read from
4732 * @tstamp_ready: contents of the Tx memory status register
4733 *
4734 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in
4735 * the PHY are ready. A set bit means the corresponding timestamp is valid and
4736 * ready to be captured from the PHY timestamp block.
4737 */
4738 static int
ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw * hw,u8 quad,u64 * tstamp_ready)4739 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
4740 {
4741 u32 hi, lo;
4742 int err;
4743
4744 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi);
4745 if (err) {
4746 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",
4747 quad, err);
4748 return err;
4749 }
4750
4751 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo);
4752 if (err) {
4753 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",
4754 quad, err);
4755 return err;
4756 }
4757
4758 *tstamp_ready = (u64)hi << 32 | (u64)lo;
4759
4760 return 0;
4761 }
4762
4763 /**
4764 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
4765 * @hw: pointer to the HW struct
4766 * @quad: the timestamp quad
4767 * @ena: enable or disable interrupt
4768 * @threshold: interrupt threshold
4769 *
4770 * Configure TX timestamp interrupt for the specified quad
4771 *
4772 * Return: 0 on success, other error codes when failed to read/write quad
4773 */
4774
ice_phy_cfg_intr_e82x(struct ice_hw * hw,u8 quad,bool ena,u8 threshold)4775 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)
4776 {
4777 int err;
4778 u32 val;
4779
4780 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
4781 if (err)
4782 return err;
4783
4784 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
4785 if (ena) {
4786 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
4787 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
4788 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold);
4789 }
4790
4791 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
4792 }
4793
4794 /**
4795 * ice_ptp_init_phy_e82x - initialize PHY parameters
4796 * @ptp: pointer to the PTP HW struct
4797 */
ice_ptp_init_phy_e82x(struct ice_ptp_hw * ptp)4798 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp)
4799 {
4800 ptp->num_lports = 8;
4801 ptp->ports_per_phy = 8;
4802 }
4803
4804 /* E810 functions
4805 *
4806 * The following functions operate on the E810 series devices which use
4807 * a separate external PHY.
4808 */
4809
4810 /**
4811 * ice_read_phy_reg_e810 - Read register from external PHY on E810
4812 * @hw: pointer to the HW struct
4813 * @addr: the address to read from
4814 * @val: On return, the value read from the PHY
4815 *
4816 * Read a register from the external PHY on the E810 device.
4817 */
ice_read_phy_reg_e810(struct ice_hw * hw,u32 addr,u32 * val)4818 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)
4819 {
4820 struct ice_sbq_msg_input msg = {0};
4821 int err;
4822
4823 msg.msg_addr_low = lower_16_bits(addr);
4824 msg.msg_addr_high = upper_16_bits(addr);
4825 msg.opcode = ice_sbq_msg_rd;
4826 msg.dest_dev = rmn_0;
4827
4828 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
4829 if (err) {
4830 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
4831 err);
4832 return err;
4833 }
4834
4835 *val = msg.data;
4836
4837 return 0;
4838 }
4839
4840 /**
4841 * ice_write_phy_reg_e810 - Write register on external PHY on E810
4842 * @hw: pointer to the HW struct
4843 * @addr: the address to writem to
4844 * @val: the value to write to the PHY
4845 *
4846 * Write a value to a register of the external PHY on the E810 device.
4847 */
ice_write_phy_reg_e810(struct ice_hw * hw,u32 addr,u32 val)4848 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)
4849 {
4850 struct ice_sbq_msg_input msg = {0};
4851 int err;
4852
4853 msg.msg_addr_low = lower_16_bits(addr);
4854 msg.msg_addr_high = upper_16_bits(addr);
4855 msg.opcode = ice_sbq_msg_wr;
4856 msg.dest_dev = rmn_0;
4857 msg.data = val;
4858
4859 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
4860 if (err) {
4861 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
4862 err);
4863 return err;
4864 }
4865
4866 return 0;
4867 }
4868
4869 /**
4870 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW
4871 * @hw: pointer to the HW struct
4872 * @idx: the timestamp index to read
4873 * @hi: 8 bit timestamp high value
4874 * @lo: 32 bit timestamp low value
4875 *
4876 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
4877 * timestamp block of the external PHY on the E810 device using the low latency
4878 * timestamp read.
4879 */
4880 static int
ice_read_phy_tstamp_ll_e810(struct ice_hw * hw,u8 idx,u8 * hi,u32 * lo)4881 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo)
4882 {
4883 struct ice_e810_params *params = &hw->ptp.phy.e810;
4884 unsigned long flags;
4885 u32 val;
4886 int err;
4887
4888 spin_lock_irqsave(¶ms->atqbal_wq.lock, flags);
4889
4890 /* Wait for any pending in-progress low latency interrupt */
4891 err = wait_event_interruptible_locked_irq(params->atqbal_wq,
4892 !(params->atqbal_flags &
4893 ATQBAL_FLAGS_INTR_IN_PROGRESS));
4894 if (err) {
4895 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags);
4896 return err;
4897 }
4898
4899 /* Write TS index to read to the PF register so the FW can read it */
4900 val = FIELD_PREP(REG_LL_PROXY_H_TS_IDX, idx) | REG_LL_PROXY_H_EXEC;
4901 wr32(hw, REG_LL_PROXY_H, val);
4902
4903 /* Read the register repeatedly until the FW provides us the TS */
4904 err = read_poll_timeout_atomic(rd32, val,
4905 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 10,
4906 REG_LL_PROXY_H_TIMEOUT_US, false, hw,
4907 REG_LL_PROXY_H);
4908 if (err) {
4909 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n");
4910 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags);
4911 return err;
4912 }
4913
4914 /* High 8 bit value of the TS is on the bits 16:23 */
4915 *hi = FIELD_GET(REG_LL_PROXY_H_TS_HIGH, val);
4916
4917 /* Read the low 32 bit value and set the TS valid bit */
4918 *lo = rd32(hw, REG_LL_PROXY_L) | TS_VALID;
4919
4920 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags);
4921
4922 return 0;
4923 }
4924
4925 /**
4926 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq
4927 * @hw: pointer to the HW struct
4928 * @lport: the lport to read from
4929 * @idx: the timestamp index to read
4930 * @hi: 8 bit timestamp high value
4931 * @lo: 32 bit timestamp low value
4932 *
4933 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
4934 * timestamp block of the external PHY on the E810 device using sideband queue.
4935 */
4936 static int
ice_read_phy_tstamp_sbq_e810(struct ice_hw * hw,u8 lport,u8 idx,u8 * hi,u32 * lo)4937 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi,
4938 u32 *lo)
4939 {
4940 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
4941 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
4942 u32 lo_val, hi_val;
4943 int err;
4944
4945 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);
4946 if (err) {
4947 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
4948 err);
4949 return err;
4950 }
4951
4952 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val);
4953 if (err) {
4954 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
4955 err);
4956 return err;
4957 }
4958
4959 *lo = lo_val;
4960 *hi = (u8)hi_val;
4961
4962 return 0;
4963 }
4964
4965 /**
4966 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
4967 * @hw: pointer to the HW struct
4968 * @lport: the lport to read from
4969 * @idx: the timestamp index to read
4970 * @tstamp: on return, the 40bit timestamp value
4971 *
4972 * Read a 40bit timestamp value out of the timestamp block of the external PHY
4973 * on the E810 device.
4974 */
4975 static int
ice_read_phy_tstamp_e810(struct ice_hw * hw,u8 lport,u8 idx,u64 * tstamp)4976 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
4977 {
4978 u32 lo = 0;
4979 u8 hi = 0;
4980 int err;
4981
4982 if (hw->dev_caps.ts_dev_info.ts_ll_read)
4983 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo);
4984 else
4985 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo);
4986
4987 if (err)
4988 return err;
4989
4990 /* For E810 devices, the timestamp is reported with the lower 32 bits
4991 * in the low register, and the upper 8 bits in the high register.
4992 */
4993 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
4994 FIELD_PREP(PHY_EXT_40B_LOW_M, lo);
4995
4996 return 0;
4997 }
4998
4999 /**
5000 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
5001 * @hw: pointer to the HW struct
5002 * @lport: the lport to read from
5003 * @idx: the timestamp index to reset
5004 *
5005 * Read the timestamp and then forcibly overwrite its value to clear the valid
5006 * bit from the timestamp block of the external PHY on the E810 device.
5007 *
5008 * This function should only be called on an idx whose bit is set according to
5009 * ice_get_phy_tx_tstamp_ready().
5010 */
ice_clear_phy_tstamp_e810(struct ice_hw * hw,u8 lport,u8 idx)5011 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
5012 {
5013 u32 lo_addr, hi_addr;
5014 u64 unused_tstamp;
5015 int err;
5016
5017 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp);
5018 if (err) {
5019 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n",
5020 lport, idx, err);
5021 return err;
5022 }
5023
5024 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
5025 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
5026
5027 err = ice_write_phy_reg_e810(hw, lo_addr, 0);
5028 if (err) {
5029 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n",
5030 lport, idx, err);
5031 return err;
5032 }
5033
5034 err = ice_write_phy_reg_e810(hw, hi_addr, 0);
5035 if (err) {
5036 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n",
5037 lport, idx, err);
5038 return err;
5039 }
5040
5041 return 0;
5042 }
5043
5044 /**
5045 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
5046 * @hw: pointer to HW struct
5047 *
5048 * Perform E810-specific PTP hardware clock initialization steps.
5049 *
5050 * Return: 0 on success, other error codes when failed to initialize TimeSync
5051 */
ice_ptp_init_phc_e810(struct ice_hw * hw)5052 static int ice_ptp_init_phc_e810(struct ice_hw *hw)
5053 {
5054 u8 tmr_idx;
5055 int err;
5056
5057 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY);
5058
5059 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5060 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
5061 GLTSYN_ENA_TSYN_ENA_M);
5062 if (err)
5063 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
5064 err);
5065
5066 return err;
5067 }
5068
5069 /**
5070 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
5071 * @hw: Board private structure
5072 * @time: Time to initialize the PHY port clock to
5073 *
5074 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
5075 * initial clock time. The time will not actually be programmed until the
5076 * driver issues an ICE_PTP_INIT_TIME command.
5077 *
5078 * The time value is the upper 32 bits of the PHY timer, usually in units of
5079 * nominal nanoseconds.
5080 */
ice_ptp_prep_phy_time_e810(struct ice_hw * hw,u32 time)5081 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
5082 {
5083 u8 tmr_idx;
5084 int err;
5085
5086 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5087 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
5088 if (err) {
5089 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n",
5090 err);
5091 return err;
5092 }
5093
5094 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
5095 if (err) {
5096 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n",
5097 err);
5098 return err;
5099 }
5100
5101 return 0;
5102 }
5103
5104 /**
5105 * ice_ptp_prep_phy_adj_ll_e810 - Prep PHY ports for a time adjustment
5106 * @hw: pointer to HW struct
5107 * @adj: adjustment value to program
5108 *
5109 * Use the low latency firmware interface to program PHY time adjustment to
5110 * all PHY ports.
5111 *
5112 * Return: 0 on success, -EBUSY on timeout
5113 */
ice_ptp_prep_phy_adj_ll_e810(struct ice_hw * hw,s32 adj)5114 static int ice_ptp_prep_phy_adj_ll_e810(struct ice_hw *hw, s32 adj)
5115 {
5116 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5117 struct ice_e810_params *params = &hw->ptp.phy.e810;
5118 u32 val;
5119 int err;
5120
5121 spin_lock_irq(¶ms->atqbal_wq.lock);
5122
5123 /* Wait for any pending in-progress low latency interrupt */
5124 err = wait_event_interruptible_locked_irq(params->atqbal_wq,
5125 !(params->atqbal_flags &
5126 ATQBAL_FLAGS_INTR_IN_PROGRESS));
5127 if (err) {
5128 spin_unlock_irq(¶ms->atqbal_wq.lock);
5129 return err;
5130 }
5131
5132 wr32(hw, REG_LL_PROXY_L, adj);
5133 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_ADJ) |
5134 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC;
5135 wr32(hw, REG_LL_PROXY_H, val);
5136
5137 /* Read the register repeatedly until the FW indicates completion */
5138 err = read_poll_timeout_atomic(rd32, val,
5139 !FIELD_GET(REG_LL_PROXY_H_EXEC, val),
5140 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw,
5141 REG_LL_PROXY_H);
5142 if (err) {
5143 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n");
5144 spin_unlock_irq(¶ms->atqbal_wq.lock);
5145 return err;
5146 }
5147
5148 spin_unlock_irq(¶ms->atqbal_wq.lock);
5149
5150 return 0;
5151 }
5152
5153 /**
5154 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
5155 * @hw: pointer to HW struct
5156 * @adj: adjustment value to program
5157 *
5158 * Prepare the PHY port for an atomic adjustment by programming the PHY
5159 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment
5160 * is completed by issuing an ICE_PTP_ADJ_TIME sync command.
5161 *
5162 * The adjustment value only contains the portion used for the upper 32bits of
5163 * the PHY timer, usually in units of nominal nanoseconds. Negative
5164 * adjustments are supported using 2s complement arithmetic.
5165 */
ice_ptp_prep_phy_adj_e810(struct ice_hw * hw,s32 adj)5166 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj)
5167 {
5168 u8 tmr_idx;
5169 int err;
5170
5171 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update)
5172 return ice_ptp_prep_phy_adj_ll_e810(hw, adj);
5173
5174 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5175
5176 /* Adjustments are represented as signed 2's complement values in
5177 * nanoseconds. Sub-nanosecond adjustment is not supported.
5178 */
5179 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0);
5180 if (err) {
5181 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n",
5182 err);
5183 return err;
5184 }
5185
5186 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj);
5187 if (err) {
5188 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n",
5189 err);
5190 return err;
5191 }
5192
5193 return 0;
5194 }
5195
5196 /**
5197 * ice_ptp_prep_phy_incval_ll_e810 - Prep PHY ports increment value change
5198 * @hw: pointer to HW struct
5199 * @incval: The new 40bit increment value to prepare
5200 *
5201 * Use the low latency firmware interface to program PHY time increment value
5202 * for all PHY ports.
5203 *
5204 * Return: 0 on success, -EBUSY on timeout
5205 */
ice_ptp_prep_phy_incval_ll_e810(struct ice_hw * hw,u64 incval)5206 static int ice_ptp_prep_phy_incval_ll_e810(struct ice_hw *hw, u64 incval)
5207 {
5208 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5209 struct ice_e810_params *params = &hw->ptp.phy.e810;
5210 u32 val;
5211 int err;
5212
5213 spin_lock_irq(¶ms->atqbal_wq.lock);
5214
5215 /* Wait for any pending in-progress low latency interrupt */
5216 err = wait_event_interruptible_locked_irq(params->atqbal_wq,
5217 !(params->atqbal_flags &
5218 ATQBAL_FLAGS_INTR_IN_PROGRESS));
5219 if (err) {
5220 spin_unlock_irq(¶ms->atqbal_wq.lock);
5221 return err;
5222 }
5223
5224 wr32(hw, REG_LL_PROXY_L, lower_32_bits(incval));
5225 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_FREQ) |
5226 FIELD_PREP(REG_LL_PROXY_H_TS_HIGH, (u8)upper_32_bits(incval)) |
5227 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC;
5228 wr32(hw, REG_LL_PROXY_H, val);
5229
5230 /* Read the register repeatedly until the FW indicates completion */
5231 err = read_poll_timeout_atomic(rd32, val,
5232 !FIELD_GET(REG_LL_PROXY_H_EXEC, val),
5233 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw,
5234 REG_LL_PROXY_H);
5235 if (err) {
5236 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n");
5237 spin_unlock_irq(¶ms->atqbal_wq.lock);
5238 return err;
5239 }
5240
5241 spin_unlock_irq(¶ms->atqbal_wq.lock);
5242
5243 return 0;
5244 }
5245
5246 /**
5247 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
5248 * @hw: pointer to HW struct
5249 * @incval: The new 40bit increment value to prepare
5250 *
5251 * Prepare the PHY port for a new increment value by programming the PHY
5252 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is
5253 * completed by issuing an ICE_PTP_INIT_INCVAL command.
5254 */
ice_ptp_prep_phy_incval_e810(struct ice_hw * hw,u64 incval)5255 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
5256 {
5257 u32 high, low;
5258 u8 tmr_idx;
5259 int err;
5260
5261 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update)
5262 return ice_ptp_prep_phy_incval_ll_e810(hw, incval);
5263
5264 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5265 low = lower_32_bits(incval);
5266 high = upper_32_bits(incval);
5267
5268 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
5269 if (err) {
5270 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n",
5271 err);
5272 return err;
5273 }
5274
5275 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
5276 if (err) {
5277 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n",
5278 err);
5279 return err;
5280 }
5281
5282 return 0;
5283 }
5284
5285 /**
5286 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
5287 * @hw: pointer to HW struct
5288 * @cmd: Command to be sent to the port
5289 *
5290 * Prepare the external PHYs connected to this device for a timer sync
5291 * command.
5292 */
ice_ptp_port_cmd_e810(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5293 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5294 {
5295 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
5296
5297 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val);
5298 }
5299
5300 /**
5301 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
5302 * @hw: pointer to the HW struct
5303 * @port: the PHY port to read
5304 * @tstamp_ready: contents of the Tx memory status register
5305 *
5306 * E810 devices do not use a Tx memory status register. Instead simply
5307 * indicate that all timestamps are currently ready.
5308 */
5309 static int
ice_get_phy_tx_tstamp_ready_e810(struct ice_hw * hw,u8 port,u64 * tstamp_ready)5310 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)
5311 {
5312 *tstamp_ready = 0xFFFFFFFFFFFFFFFF;
5313 return 0;
5314 }
5315
5316 /* E810 SMA functions
5317 *
5318 * The following functions operate specifically on E810 hardware and are used
5319 * to access the extended GPIOs available.
5320 */
5321
5322 /**
5323 * ice_read_sma_ctrl
5324 * @hw: pointer to the hw struct
5325 * @data: pointer to data to be read from the GPIO controller
5326 *
5327 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
5328 * PCA9575 expander, so only bits 3-7 in data are valid.
5329 */
ice_read_sma_ctrl(struct ice_hw * hw,u8 * data)5330 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data)
5331 {
5332 int status;
5333 u16 handle;
5334 u8 i;
5335
5336 status = ice_get_pca9575_handle(hw, &handle);
5337 if (status)
5338 return status;
5339
5340 *data = 0;
5341
5342 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) {
5343 bool pin;
5344
5345 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
5346 &pin, NULL);
5347 if (status)
5348 break;
5349 *data |= (u8)(!pin) << i;
5350 }
5351
5352 return status;
5353 }
5354
5355 /**
5356 * ice_write_sma_ctrl
5357 * @hw: pointer to the hw struct
5358 * @data: data to be written to the GPIO controller
5359 *
5360 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
5361 * of the PCA9575 expander, so only bits 3-7 in data are valid.
5362 */
ice_write_sma_ctrl(struct ice_hw * hw,u8 data)5363 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data)
5364 {
5365 int status;
5366 u16 handle;
5367 u8 i;
5368
5369 status = ice_get_pca9575_handle(hw, &handle);
5370 if (status)
5371 return status;
5372
5373 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) {
5374 bool pin;
5375
5376 pin = !(data & (1 << i));
5377 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
5378 pin, NULL);
5379 if (status)
5380 break;
5381 }
5382
5383 return status;
5384 }
5385
5386 /**
5387 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM
5388 * @hw: pointer to the HW struct
5389 * @entries: returns the SDP available connections section from NVM
5390 * @num_entries: returns the number of valid entries
5391 *
5392 * Return: 0 on success, negative error code if NVM read failed or section does
5393 * not exist or is corrupted
5394 */
ice_ptp_read_sdp_ac(struct ice_hw * hw,__le16 * entries,uint * num_entries)5395 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries)
5396 {
5397 __le16 data;
5398 u32 offset;
5399 int err;
5400
5401 err = ice_acquire_nvm(hw, ICE_RES_READ);
5402 if (err)
5403 goto exit;
5404
5405 /* Read the offset of SDP_AC */
5406 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET;
5407 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true,
5408 NULL);
5409 if (err)
5410 goto exit;
5411
5412 /* Check if section exist */
5413 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data));
5414 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) {
5415 err = -EINVAL;
5416 goto exit;
5417 }
5418
5419 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) {
5420 offset &= ICE_AQC_NVM_SDP_AC_PTR_M;
5421 offset *= ICE_AQC_NVM_SECTOR_UNIT;
5422 } else {
5423 offset *= sizeof(data);
5424 }
5425
5426 /* Skip reading section length and read the number of valid entries */
5427 offset += sizeof(data);
5428 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true,
5429 NULL);
5430 if (err)
5431 goto exit;
5432 *num_entries = le16_to_cpu(data);
5433
5434 /* Read SDP configuration section */
5435 offset += sizeof(data);
5436 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data),
5437 entries, false, true, NULL);
5438
5439 exit:
5440 if (err)
5441 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n");
5442 ice_release_nvm(hw);
5443 return err;
5444 }
5445
5446 /**
5447 * ice_ptp_init_phy_e810 - initialize PHY parameters
5448 * @ptp: pointer to the PTP HW struct
5449 */
ice_ptp_init_phy_e810(struct ice_ptp_hw * ptp)5450 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp)
5451 {
5452 ptp->num_lports = 8;
5453 ptp->ports_per_phy = 4;
5454
5455 init_waitqueue_head(&ptp->phy.e810.atqbal_wq);
5456 }
5457
5458 /* E830 functions
5459 *
5460 * The following functions operate on the E830 series devices.
5461 *
5462 */
5463
5464 /**
5465 * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization
5466 * @hw: pointer to HW struct
5467 *
5468 * Perform E830-specific PTP hardware clock initialization steps.
5469 */
ice_ptp_init_phc_e830(const struct ice_hw * hw)5470 static void ice_ptp_init_phc_e830(const struct ice_hw *hw)
5471 {
5472 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY);
5473 }
5474
5475 /**
5476 * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change
5477 * @hw: pointer to HW struct
5478 * @incval: The new 40bit increment value to prepare
5479 *
5480 * Prepare the PHY port for a new increment value by programming the PHC
5481 * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is
5482 * completed by FW automatically.
5483 */
ice_ptp_write_direct_incval_e830(const struct ice_hw * hw,u64 incval)5484 static void ice_ptp_write_direct_incval_e830(const struct ice_hw *hw,
5485 u64 incval)
5486 {
5487 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5488
5489 wr32(hw, GLTSYN_INCVAL_L(tmr_idx), lower_32_bits(incval));
5490 wr32(hw, GLTSYN_INCVAL_H(tmr_idx), upper_32_bits(incval));
5491 }
5492
5493 /**
5494 * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time
5495 * @hw: Board private structure
5496 * @time: Time to initialize the PHY port clock to
5497 *
5498 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
5499 * initial clock time. The time will not actually be programmed until the
5500 * driver issues an ICE_PTP_INIT_TIME command.
5501 *
5502 * The time value is the upper 32 bits of the PHY timer, usually in units of
5503 * nominal nanoseconds.
5504 */
ice_ptp_write_direct_phc_time_e830(const struct ice_hw * hw,u64 time)5505 static void ice_ptp_write_direct_phc_time_e830(const struct ice_hw *hw,
5506 u64 time)
5507 {
5508 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5509
5510 wr32(hw, GLTSYN_TIME_0(tmr_idx), 0);
5511 wr32(hw, GLTSYN_TIME_L(tmr_idx), lower_32_bits(time));
5512 wr32(hw, GLTSYN_TIME_H(tmr_idx), upper_32_bits(time));
5513 }
5514
5515 /**
5516 * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command
5517 * @hw: pointer to HW struct
5518 * @cmd: Command to be sent to the port
5519 *
5520 * Prepare the external PHYs connected to this device for a timer sync
5521 * command.
5522 *
5523 * Return: 0 on success, negative error code when PHY write failed
5524 */
ice_ptp_port_cmd_e830(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5525 static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5526 {
5527 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
5528
5529 return ice_write_phy_reg_e810(hw, E830_ETH_GLTSYN_CMD, val);
5530 }
5531
5532 /**
5533 * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY
5534 * @hw: pointer to the HW struct
5535 * @idx: the timestamp index to read
5536 * @tstamp: on return, the 40bit timestamp value
5537 *
5538 * Read a 40bit timestamp value out of the timestamp block of the external PHY
5539 * on the E830 device.
5540 */
ice_read_phy_tstamp_e830(const struct ice_hw * hw,u8 idx,u64 * tstamp)5541 static void ice_read_phy_tstamp_e830(const struct ice_hw *hw, u8 idx,
5542 u64 *tstamp)
5543 {
5544 u32 hi, lo;
5545
5546 hi = rd32(hw, E830_PRTTSYN_TXTIME_H(idx));
5547 lo = rd32(hw, E830_PRTTSYN_TXTIME_L(idx));
5548
5549 /* For E830 devices, the timestamp is reported with the lower 32 bits
5550 * in the low register, and the upper 8 bits in the high register.
5551 */
5552 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
5553 FIELD_PREP(PHY_EXT_40B_LOW_M, lo);
5554 }
5555
5556 /**
5557 * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register
5558 * @hw: pointer to the HW struct
5559 * @port: the PHY port to read
5560 * @tstamp_ready: contents of the Tx memory status register
5561 */
ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw * hw,u8 port,u64 * tstamp_ready)5562 static void ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw *hw, u8 port,
5563 u64 *tstamp_ready)
5564 {
5565 *tstamp_ready = rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_H);
5566 *tstamp_ready <<= 32;
5567 *tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L);
5568 }
5569
5570 /**
5571 * ice_ptp_init_phy_e830 - initialize PHY parameters
5572 * @ptp: pointer to the PTP HW struct
5573 */
ice_ptp_init_phy_e830(struct ice_ptp_hw * ptp)5574 static void ice_ptp_init_phy_e830(struct ice_ptp_hw *ptp)
5575 {
5576 ptp->num_lports = 8;
5577 ptp->ports_per_phy = 4;
5578 }
5579
5580 /* Device agnostic functions
5581 *
5582 * The following functions implement shared behavior common to all devices,
5583 * possibly calling a device specific implementation where necessary.
5584 */
5585
5586 /**
5587 * ice_ptp_lock - Acquire PTP global semaphore register lock
5588 * @hw: pointer to the HW struct
5589 *
5590 * Acquire the global PTP hardware semaphore lock. Returns true if the lock
5591 * was acquired, false otherwise.
5592 *
5593 * The PFTSYN_SEM register sets the busy bit on read, returning the previous
5594 * value. If software sees the busy bit cleared, this means that this function
5595 * acquired the lock (and the busy bit is now set). If software sees the busy
5596 * bit set, it means that another function acquired the lock.
5597 *
5598 * Software must clear the busy bit with a write to release the lock for other
5599 * functions when done.
5600 */
ice_ptp_lock(struct ice_hw * hw)5601 bool ice_ptp_lock(struct ice_hw *hw)
5602 {
5603 u32 hw_lock;
5604 int i;
5605
5606 #define MAX_TRIES 15
5607
5608 for (i = 0; i < MAX_TRIES; i++) {
5609 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
5610 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M;
5611 if (hw_lock) {
5612 /* Somebody is holding the lock */
5613 usleep_range(5000, 6000);
5614 continue;
5615 }
5616
5617 break;
5618 }
5619
5620 return !hw_lock;
5621 }
5622
5623 /**
5624 * ice_ptp_unlock - Release PTP global semaphore register lock
5625 * @hw: pointer to the HW struct
5626 *
5627 * Release the global PTP hardware semaphore lock. This is done by writing to
5628 * the PFTSYN_SEM register.
5629 */
ice_ptp_unlock(struct ice_hw * hw)5630 void ice_ptp_unlock(struct ice_hw *hw)
5631 {
5632 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
5633 }
5634
5635 /**
5636 * ice_ptp_init_hw - Initialize hw based on device type
5637 * @hw: pointer to the HW structure
5638 *
5639 * Determine the PHY model for the device, and initialize hw
5640 * for use by other functions.
5641 */
ice_ptp_init_hw(struct ice_hw * hw)5642 void ice_ptp_init_hw(struct ice_hw *hw)
5643 {
5644 struct ice_ptp_hw *ptp = &hw->ptp;
5645
5646 switch (hw->mac_type) {
5647 case ICE_MAC_E810:
5648 ice_ptp_init_phy_e810(ptp);
5649 break;
5650 case ICE_MAC_E830:
5651 ice_ptp_init_phy_e830(ptp);
5652 break;
5653 case ICE_MAC_GENERIC:
5654 ice_ptp_init_phy_e82x(ptp);
5655 break;
5656 case ICE_MAC_GENERIC_3K_E825:
5657 ice_ptp_init_phy_e825(hw);
5658 break;
5659 default:
5660 return;
5661 }
5662 }
5663
5664 /**
5665 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command
5666 * @hw: pointer to HW struct
5667 * @port: Port to which cmd has to be sent
5668 * @cmd: Command to be sent to the port
5669 *
5670 * Prepare one port for the upcoming timer sync command. Do not use this for
5671 * programming only a single port, instead use ice_ptp_one_port_cmd() to
5672 * ensure non-modified ports get properly initialized to ICE_PTP_NOP.
5673 *
5674 * Return:
5675 * * %0 - success
5676 * %-EBUSY - PHY type not supported
5677 * * %other - failed to write port command
5678 */
ice_ptp_write_port_cmd(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)5679 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port,
5680 enum ice_ptp_tmr_cmd cmd)
5681 {
5682 switch (hw->mac_type) {
5683 case ICE_MAC_GENERIC:
5684 return ice_ptp_write_port_cmd_e82x(hw, port, cmd);
5685 case ICE_MAC_GENERIC_3K_E825:
5686 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd);
5687 default:
5688 return -EOPNOTSUPP;
5689 }
5690 }
5691
5692 /**
5693 * ice_ptp_one_port_cmd - Program one PHY port for a timer command
5694 * @hw: pointer to HW struct
5695 * @configured_port: the port that should execute the command
5696 * @configured_cmd: the command to be executed on the configured port
5697 *
5698 * Prepare one port for executing a timer command, while preparing all other
5699 * ports to ICE_PTP_NOP. This allows executing a command on a single port
5700 * while ensuring all other ports do not execute stale commands.
5701 *
5702 * Return:
5703 * * %0 - success
5704 * * %other - failed to write port command
5705 */
ice_ptp_one_port_cmd(struct ice_hw * hw,u8 configured_port,enum ice_ptp_tmr_cmd configured_cmd)5706 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
5707 enum ice_ptp_tmr_cmd configured_cmd)
5708 {
5709 u32 port;
5710
5711 for (port = 0; port < hw->ptp.num_lports; port++) {
5712 int err;
5713
5714 /* Program the configured port with the configured command,
5715 * program all other ports with ICE_PTP_NOP.
5716 */
5717 if (port == configured_port)
5718 err = ice_ptp_write_port_cmd(hw, port, configured_cmd);
5719 else
5720 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP);
5721
5722 if (err)
5723 return err;
5724 }
5725
5726 return 0;
5727 }
5728
5729 /**
5730 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command
5731 * @hw: pointer to HW struct
5732 * @cmd: the timer command to setup
5733 *
5734 * Prepare all PHY ports on this device for the requested timer command. For
5735 * some families this can be done in one shot, but for other families each
5736 * port must be configured individually.
5737 *
5738 * Return:
5739 * * %0 - success
5740 * * %other - failed to write port command
5741 */
ice_ptp_port_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5742 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5743 {
5744 u32 port;
5745
5746 /* PHY models which can program all ports simultaneously */
5747 switch (hw->mac_type) {
5748 case ICE_MAC_E810:
5749 return ice_ptp_port_cmd_e810(hw, cmd);
5750 case ICE_MAC_E830:
5751 return ice_ptp_port_cmd_e830(hw, cmd);
5752 default:
5753 break;
5754 }
5755
5756 /* PHY models which require programming each port separately */
5757 for (port = 0; port < hw->ptp.num_lports; port++) {
5758 int err;
5759
5760 err = ice_ptp_write_port_cmd(hw, port, cmd);
5761 if (err)
5762 return err;
5763 }
5764
5765 return 0;
5766 }
5767
5768 /**
5769 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
5770 * @hw: pointer to HW struct
5771 * @cmd: the command to issue
5772 *
5773 * Prepare the source timer and PHY timers and then trigger the requested
5774 * command. This causes the shadow registers previously written in preparation
5775 * for the command to be synchronously applied to both the source and PHY
5776 * timers.
5777 */
ice_ptp_tmr_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5778 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5779 {
5780 int err;
5781
5782 /* First, prepare the source timer */
5783 ice_ptp_src_cmd(hw, cmd);
5784
5785 /* Next, prepare the ports */
5786 err = ice_ptp_port_cmd(hw, cmd);
5787 if (err) {
5788 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",
5789 cmd, err);
5790 return err;
5791 }
5792
5793 /* Write the sync command register to drive both source and PHY timer
5794 * commands synchronously
5795 */
5796 ice_ptp_exec_tmr_cmd(hw);
5797
5798 return 0;
5799 }
5800
5801 /**
5802 * ice_ptp_init_time - Initialize device time to provided value
5803 * @hw: pointer to HW struct
5804 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)
5805 *
5806 * Initialize the device to the specified time provided. This requires a three
5807 * step process:
5808 *
5809 * 1) write the new init time to the source timer shadow registers
5810 * 2) write the new init time to the PHY timer shadow registers
5811 * 3) issue an init_time timer command to synchronously switch both the source
5812 * and port timers to the new init time value at the next clock cycle.
5813 */
ice_ptp_init_time(struct ice_hw * hw,u64 time)5814 int ice_ptp_init_time(struct ice_hw *hw, u64 time)
5815 {
5816 u8 tmr_idx;
5817 int err;
5818
5819 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5820
5821 /* Source timers */
5822 /* For E830 we don't need to use shadow registers, its automatic */
5823 if (hw->mac_type == ICE_MAC_E830) {
5824 ice_ptp_write_direct_phc_time_e830(hw, time);
5825 return 0;
5826 }
5827
5828 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time));
5829 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time));
5830 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
5831
5832 /* PHY timers */
5833 /* Fill Rx and Tx ports and send msg to PHY */
5834 switch (hw->mac_type) {
5835 case ICE_MAC_E810:
5836 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
5837 break;
5838 case ICE_MAC_GENERIC:
5839 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF);
5840 break;
5841 case ICE_MAC_GENERIC_3K_E825:
5842 err = ice_ptp_prep_phy_time_eth56g(hw,
5843 (u32)(time & 0xFFFFFFFF));
5844 break;
5845 default:
5846 err = -EOPNOTSUPP;
5847 }
5848
5849 if (err)
5850 return err;
5851
5852 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME);
5853 }
5854
5855 /**
5856 * ice_ptp_write_incval - Program PHC with new increment value
5857 * @hw: pointer to HW struct
5858 * @incval: Source timer increment value per clock cycle
5859 *
5860 * Program the PHC with a new increment value. This requires a three-step
5861 * process:
5862 *
5863 * 1) Write the increment value to the source timer shadow registers
5864 * 2) Write the increment value to the PHY timer shadow registers
5865 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both
5866 * the source and port timers to the new increment value at the next clock
5867 * cycle.
5868 */
ice_ptp_write_incval(struct ice_hw * hw,u64 incval)5869 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
5870 {
5871 u8 tmr_idx;
5872 int err;
5873
5874 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5875
5876 /* For E830 we don't need to use shadow registers, its automatic */
5877 if (hw->mac_type == ICE_MAC_E830) {
5878 ice_ptp_write_direct_incval_e830(hw, incval);
5879 return 0;
5880 }
5881
5882 /* Shadow Adjust */
5883 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval));
5884 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval));
5885
5886 switch (hw->mac_type) {
5887 case ICE_MAC_E810:
5888 err = ice_ptp_prep_phy_incval_e810(hw, incval);
5889 break;
5890 case ICE_MAC_GENERIC:
5891 err = ice_ptp_prep_phy_incval_e82x(hw, incval);
5892 break;
5893 case ICE_MAC_GENERIC_3K_E825:
5894 err = ice_ptp_prep_phy_incval_eth56g(hw, incval);
5895 break;
5896 default:
5897 err = -EOPNOTSUPP;
5898 }
5899
5900 if (err)
5901 return err;
5902
5903 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL);
5904 }
5905
5906 /**
5907 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
5908 * @hw: pointer to HW struct
5909 * @incval: Source timer increment value per clock cycle
5910 *
5911 * Program a new PHC incval while holding the PTP semaphore.
5912 */
ice_ptp_write_incval_locked(struct ice_hw * hw,u64 incval)5913 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
5914 {
5915 int err;
5916
5917 if (!ice_ptp_lock(hw))
5918 return -EBUSY;
5919
5920 err = ice_ptp_write_incval(hw, incval);
5921
5922 ice_ptp_unlock(hw);
5923
5924 return err;
5925 }
5926
5927 /**
5928 * ice_ptp_adj_clock - Adjust PHC clock time atomically
5929 * @hw: pointer to HW struct
5930 * @adj: Adjustment in nanoseconds
5931 *
5932 * Perform an atomic adjustment of the PHC time by the specified number of
5933 * nanoseconds. This requires a three-step process:
5934 *
5935 * 1) Write the adjustment to the source timer shadow registers
5936 * 2) Write the adjustment to the PHY timer shadow registers
5937 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the
5938 * adjustment to both the source and port timers at the next clock cycle.
5939 */
ice_ptp_adj_clock(struct ice_hw * hw,s32 adj)5940 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)
5941 {
5942 u8 tmr_idx;
5943 int err;
5944
5945 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5946
5947 /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
5948 * For an ICE_PTP_ADJ_TIME command, this set of registers represents
5949 * the value to add to the clock time. It supports subtraction by
5950 * interpreting the value as a 2's complement integer.
5951 */
5952 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
5953 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
5954
5955 switch (hw->mac_type) {
5956 case ICE_MAC_E810:
5957 err = ice_ptp_prep_phy_adj_e810(hw, adj);
5958 break;
5959 case ICE_MAC_E830:
5960 /* E830 sync PHYs automatically after setting GLTSYN_SHADJ */
5961 return 0;
5962 case ICE_MAC_GENERIC:
5963 err = ice_ptp_prep_phy_adj_e82x(hw, adj);
5964 break;
5965 case ICE_MAC_GENERIC_3K_E825:
5966 err = ice_ptp_prep_phy_adj_eth56g(hw, adj);
5967 break;
5968 default:
5969 err = -EOPNOTSUPP;
5970 }
5971
5972 if (err)
5973 return err;
5974
5975 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME);
5976 }
5977
5978 /**
5979 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
5980 * @hw: pointer to the HW struct
5981 * @block: the block to read from
5982 * @idx: the timestamp index to read
5983 * @tstamp: on return, the 40bit timestamp value
5984 *
5985 * Read a 40bit timestamp value out of the timestamp block. For E822 devices,
5986 * the block is the quad to read from. For E810 devices, the block is the
5987 * logical port to read from.
5988 */
ice_read_phy_tstamp(struct ice_hw * hw,u8 block,u8 idx,u64 * tstamp)5989 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
5990 {
5991 switch (hw->mac_type) {
5992 case ICE_MAC_E810:
5993 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
5994 case ICE_MAC_E830:
5995 ice_read_phy_tstamp_e830(hw, idx, tstamp);
5996 return 0;
5997 case ICE_MAC_GENERIC:
5998 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp);
5999 case ICE_MAC_GENERIC_3K_E825:
6000 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp);
6001 default:
6002 return -EOPNOTSUPP;
6003 }
6004 }
6005
6006 /**
6007 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
6008 * @hw: pointer to the HW struct
6009 * @block: the block to read from
6010 * @idx: the timestamp index to reset
6011 *
6012 * Clear a timestamp from the timestamp block, discarding its value without
6013 * returning it. This resets the memory status bit for the timestamp index
6014 * allowing it to be reused for another timestamp in the future.
6015 *
6016 * For E822 devices, the block number is the PHY quad to clear from. For E810
6017 * devices, the block number is the logical port to clear from.
6018 *
6019 * This function must only be called on a timestamp index whose valid bit is
6020 * set according to ice_get_phy_tx_tstamp_ready().
6021 */
ice_clear_phy_tstamp(struct ice_hw * hw,u8 block,u8 idx)6022 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
6023 {
6024 switch (hw->mac_type) {
6025 case ICE_MAC_E810:
6026 return ice_clear_phy_tstamp_e810(hw, block, idx);
6027 case ICE_MAC_GENERIC:
6028 return ice_clear_phy_tstamp_e82x(hw, block, idx);
6029 case ICE_MAC_GENERIC_3K_E825:
6030 return ice_clear_ptp_tstamp_eth56g(hw, block, idx);
6031 default:
6032 return -EOPNOTSUPP;
6033 }
6034 }
6035
6036 /**
6037 * ice_get_pf_c827_idx - find and return the C827 index for the current pf
6038 * @hw: pointer to the hw struct
6039 * @idx: index of the found C827 PHY
6040 * Return:
6041 * * 0 - success
6042 * * negative - failure
6043 */
ice_get_pf_c827_idx(struct ice_hw * hw,u8 * idx)6044 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx)
6045 {
6046 struct ice_aqc_get_link_topo cmd;
6047 u8 node_part_number;
6048 u16 node_handle;
6049 int status;
6050 u8 ctx;
6051
6052 if (hw->mac_type != ICE_MAC_E810)
6053 return -ENODEV;
6054
6055 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) {
6056 *idx = C827_0;
6057 return 0;
6058 }
6059
6060 memset(&cmd, 0, sizeof(cmd));
6061
6062 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S;
6063 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S;
6064 cmd.addr.topo_params.node_type_ctx = ctx;
6065
6066 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number,
6067 &node_handle);
6068 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827)
6069 return -ENOENT;
6070
6071 if (node_handle == E810C_QSFP_C827_0_HANDLE)
6072 *idx = C827_0;
6073 else if (node_handle == E810C_QSFP_C827_1_HANDLE)
6074 *idx = C827_1;
6075 else
6076 return -EIO;
6077
6078 return 0;
6079 }
6080
6081 /**
6082 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
6083 * @hw: pointer to the HW struct
6084 */
ice_ptp_reset_ts_memory(struct ice_hw * hw)6085 void ice_ptp_reset_ts_memory(struct ice_hw *hw)
6086 {
6087 switch (hw->mac_type) {
6088 case ICE_MAC_GENERIC:
6089 ice_ptp_reset_ts_memory_e82x(hw);
6090 break;
6091 case ICE_MAC_GENERIC_3K_E825:
6092 ice_ptp_reset_ts_memory_eth56g(hw);
6093 break;
6094 case ICE_MAC_E810:
6095 default:
6096 return;
6097 }
6098 }
6099
6100 /**
6101 * ice_ptp_init_phc - Initialize PTP hardware clock
6102 * @hw: pointer to the HW struct
6103 *
6104 * Perform the steps required to initialize the PTP hardware clock.
6105 */
ice_ptp_init_phc(struct ice_hw * hw)6106 int ice_ptp_init_phc(struct ice_hw *hw)
6107 {
6108 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
6109
6110 /* Enable source clocks */
6111 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
6112
6113 /* Clear event err indications for auxiliary pins */
6114 (void)rd32(hw, GLTSYN_STAT(src_idx));
6115
6116 switch (hw->mac_type) {
6117 case ICE_MAC_E810:
6118 return ice_ptp_init_phc_e810(hw);
6119 case ICE_MAC_E830:
6120 ice_ptp_init_phc_e830(hw);
6121 return 0;
6122 case ICE_MAC_GENERIC:
6123 return ice_ptp_init_phc_e82x(hw);
6124 case ICE_MAC_GENERIC_3K_E825:
6125 return ice_ptp_init_phc_e825(hw);
6126 default:
6127 return -EOPNOTSUPP;
6128 }
6129 }
6130
6131 /**
6132 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
6133 * @hw: pointer to the HW struct
6134 * @block: the timestamp block to check
6135 * @tstamp_ready: storage for the PHY Tx memory status information
6136 *
6137 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value
6138 * which indicates which timestamps in the block may be captured. A set bit
6139 * means the timestamp can be read. An unset bit means the timestamp is not
6140 * ready and software should avoid reading the register.
6141 */
ice_get_phy_tx_tstamp_ready(struct ice_hw * hw,u8 block,u64 * tstamp_ready)6142 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
6143 {
6144 switch (hw->mac_type) {
6145 case ICE_MAC_E810:
6146 return ice_get_phy_tx_tstamp_ready_e810(hw, block,
6147 tstamp_ready);
6148 case ICE_MAC_E830:
6149 ice_get_phy_tx_tstamp_ready_e830(hw, block, tstamp_ready);
6150 return 0;
6151 case ICE_MAC_GENERIC:
6152 return ice_get_phy_tx_tstamp_ready_e82x(hw, block,
6153 tstamp_ready);
6154 case ICE_MAC_GENERIC_3K_E825:
6155 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block,
6156 tstamp_ready);
6157 default:
6158 return -EOPNOTSUPP;
6159 }
6160 }
6161
6162 /**
6163 * ice_cgu_get_pin_desc_e823 - get pin description array
6164 * @hw: pointer to the hw struct
6165 * @input: if request is done against input or output pin
6166 * @size: number of inputs/outputs
6167 *
6168 * Return: pointer to pin description array associated to given hw.
6169 */
6170 static const struct ice_cgu_pin_desc *
ice_cgu_get_pin_desc_e823(struct ice_hw * hw,bool input,int * size)6171 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size)
6172 {
6173 static const struct ice_cgu_pin_desc *t;
6174
6175 if (hw->cgu_part_number ==
6176 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) {
6177 if (input) {
6178 t = ice_e823_zl_cgu_inputs;
6179 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs);
6180 } else {
6181 t = ice_e823_zl_cgu_outputs;
6182 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs);
6183 }
6184 } else if (hw->cgu_part_number ==
6185 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) {
6186 if (input) {
6187 t = ice_e823_si_cgu_inputs;
6188 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs);
6189 } else {
6190 t = ice_e823_si_cgu_outputs;
6191 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs);
6192 }
6193 } else {
6194 t = NULL;
6195 *size = 0;
6196 }
6197
6198 return t;
6199 }
6200
6201 /**
6202 * ice_cgu_get_pin_desc - get pin description array
6203 * @hw: pointer to the hw struct
6204 * @input: if request is done against input or output pins
6205 * @size: size of array returned by function
6206 *
6207 * Return: pointer to pin description array associated to given hw.
6208 */
6209 static const struct ice_cgu_pin_desc *
ice_cgu_get_pin_desc(struct ice_hw * hw,bool input,int * size)6210 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size)
6211 {
6212 const struct ice_cgu_pin_desc *t = NULL;
6213
6214 switch (hw->device_id) {
6215 case ICE_DEV_ID_E810C_SFP:
6216 if (input) {
6217 t = ice_e810t_sfp_cgu_inputs;
6218 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs);
6219 } else {
6220 t = ice_e810t_sfp_cgu_outputs;
6221 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs);
6222 }
6223 break;
6224 case ICE_DEV_ID_E810C_QSFP:
6225 if (input) {
6226 t = ice_e810t_qsfp_cgu_inputs;
6227 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs);
6228 } else {
6229 t = ice_e810t_qsfp_cgu_outputs;
6230 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs);
6231 }
6232 break;
6233 case ICE_DEV_ID_E823L_10G_BASE_T:
6234 case ICE_DEV_ID_E823L_1GBE:
6235 case ICE_DEV_ID_E823L_BACKPLANE:
6236 case ICE_DEV_ID_E823L_QSFP:
6237 case ICE_DEV_ID_E823L_SFP:
6238 case ICE_DEV_ID_E823C_10G_BASE_T:
6239 case ICE_DEV_ID_E823C_BACKPLANE:
6240 case ICE_DEV_ID_E823C_QSFP:
6241 case ICE_DEV_ID_E823C_SFP:
6242 case ICE_DEV_ID_E823C_SGMII:
6243 t = ice_cgu_get_pin_desc_e823(hw, input, size);
6244 break;
6245 default:
6246 break;
6247 }
6248
6249 return t;
6250 }
6251
6252 /**
6253 * ice_cgu_get_num_pins - get pin description array size
6254 * @hw: pointer to the hw struct
6255 * @input: if request is done against input or output pins
6256 *
6257 * Return: size of pin description array for given hw.
6258 */
ice_cgu_get_num_pins(struct ice_hw * hw,bool input)6259 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input)
6260 {
6261 const struct ice_cgu_pin_desc *t;
6262 int size;
6263
6264 t = ice_cgu_get_pin_desc(hw, input, &size);
6265 if (t)
6266 return size;
6267
6268 return 0;
6269 }
6270
6271 /**
6272 * ice_cgu_get_pin_type - get pin's type
6273 * @hw: pointer to the hw struct
6274 * @pin: pin index
6275 * @input: if request is done against input or output pin
6276 *
6277 * Return: type of a pin.
6278 */
ice_cgu_get_pin_type(struct ice_hw * hw,u8 pin,bool input)6279 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input)
6280 {
6281 const struct ice_cgu_pin_desc *t;
6282 int t_size;
6283
6284 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6285
6286 if (!t)
6287 return 0;
6288
6289 if (pin >= t_size)
6290 return 0;
6291
6292 return t[pin].type;
6293 }
6294
6295 /**
6296 * ice_cgu_get_pin_freq_supp - get pin's supported frequency
6297 * @hw: pointer to the hw struct
6298 * @pin: pin index
6299 * @input: if request is done against input or output pin
6300 * @num: output number of supported frequencies
6301 *
6302 * Get frequency supported number and array of supported frequencies.
6303 *
6304 * Return: array of supported frequencies for given pin.
6305 */
6306 struct dpll_pin_frequency *
ice_cgu_get_pin_freq_supp(struct ice_hw * hw,u8 pin,bool input,u8 * num)6307 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num)
6308 {
6309 const struct ice_cgu_pin_desc *t;
6310 int t_size;
6311
6312 *num = 0;
6313 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6314 if (!t)
6315 return NULL;
6316 if (pin >= t_size)
6317 return NULL;
6318 *num = t[pin].freq_supp_num;
6319
6320 return t[pin].freq_supp;
6321 }
6322
6323 /**
6324 * ice_cgu_get_pin_name - get pin's name
6325 * @hw: pointer to the hw struct
6326 * @pin: pin index
6327 * @input: if request is done against input or output pin
6328 *
6329 * Return:
6330 * * null terminated char array with name
6331 * * NULL in case of failure
6332 */
ice_cgu_get_pin_name(struct ice_hw * hw,u8 pin,bool input)6333 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input)
6334 {
6335 const struct ice_cgu_pin_desc *t;
6336 int t_size;
6337
6338 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6339
6340 if (!t)
6341 return NULL;
6342
6343 if (pin >= t_size)
6344 return NULL;
6345
6346 return t[pin].name;
6347 }
6348
6349 /**
6350 * ice_get_cgu_state - get the state of the DPLL
6351 * @hw: pointer to the hw struct
6352 * @dpll_idx: Index of internal DPLL unit
6353 * @last_dpll_state: last known state of DPLL
6354 * @pin: pointer to a buffer for returning currently active pin
6355 * @ref_state: reference clock state
6356 * @eec_mode: eec mode of the DPLL
6357 * @phase_offset: pointer to a buffer for returning phase offset
6358 * @dpll_state: state of the DPLL (output)
6359 *
6360 * This function will read the state of the DPLL(dpll_idx). Non-null
6361 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to
6362 * retrieve currently active pin, state, mode and phase_offset respectively.
6363 *
6364 * Return: state of the DPLL
6365 */
ice_get_cgu_state(struct ice_hw * hw,u8 dpll_idx,enum dpll_lock_status last_dpll_state,u8 * pin,u8 * ref_state,u8 * eec_mode,s64 * phase_offset,enum dpll_lock_status * dpll_state)6366 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
6367 enum dpll_lock_status last_dpll_state, u8 *pin,
6368 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
6369 enum dpll_lock_status *dpll_state)
6370 {
6371 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config;
6372 s64 hw_phase_offset;
6373 int status;
6374
6375 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state,
6376 &hw_dpll_state, &hw_config,
6377 &hw_phase_offset, &hw_eec_mode);
6378 if (status)
6379 return status;
6380
6381 if (pin)
6382 /* current ref pin in dpll_state_refsel_status_X register */
6383 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL;
6384 if (phase_offset)
6385 *phase_offset = hw_phase_offset;
6386 if (ref_state)
6387 *ref_state = hw_ref_state;
6388 if (eec_mode)
6389 *eec_mode = hw_eec_mode;
6390 if (!dpll_state)
6391 return 0;
6392
6393 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ
6394 * it would never return to FREERUN. This aligns to ITU-T G.781
6395 * Recommendation. We cannot report HOLDOVER as HO memory is cleared
6396 * while switching to another reference.
6397 * Only for situations where previous state was either: "LOCKED without
6398 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN.
6399 */
6400 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) {
6401 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY)
6402 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ;
6403 else
6404 *dpll_state = DPLL_LOCK_STATUS_LOCKED;
6405 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ ||
6406 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) {
6407 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER;
6408 } else {
6409 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED;
6410 }
6411
6412 return 0;
6413 }
6414
6415 /**
6416 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins
6417 * @hw: pointer to the hw struct
6418 * @base_idx: returns index of first recovered clock pin on device
6419 * @pin_num: returns number of recovered clock pins available on device
6420 *
6421 * Based on hw provide caller info about recovery clock pins available on the
6422 * board.
6423 *
6424 * Return:
6425 * * 0 - success, information is valid
6426 * * negative - failure, information is not valid
6427 */
ice_get_cgu_rclk_pin_info(struct ice_hw * hw,u8 * base_idx,u8 * pin_num)6428 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num)
6429 {
6430 u8 phy_idx;
6431 int ret;
6432
6433 switch (hw->device_id) {
6434 case ICE_DEV_ID_E810C_SFP:
6435 case ICE_DEV_ID_E810C_QSFP:
6436
6437 ret = ice_get_pf_c827_idx(hw, &phy_idx);
6438 if (ret)
6439 return ret;
6440 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN);
6441 *pin_num = ICE_E810_RCLK_PINS_NUM;
6442 ret = 0;
6443 break;
6444 case ICE_DEV_ID_E823L_10G_BASE_T:
6445 case ICE_DEV_ID_E823L_1GBE:
6446 case ICE_DEV_ID_E823L_BACKPLANE:
6447 case ICE_DEV_ID_E823L_QSFP:
6448 case ICE_DEV_ID_E823L_SFP:
6449 case ICE_DEV_ID_E823C_10G_BASE_T:
6450 case ICE_DEV_ID_E823C_BACKPLANE:
6451 case ICE_DEV_ID_E823C_QSFP:
6452 case ICE_DEV_ID_E823C_SFP:
6453 case ICE_DEV_ID_E823C_SGMII:
6454 *pin_num = ICE_E82X_RCLK_PINS_NUM;
6455 ret = 0;
6456 if (hw->cgu_part_number ==
6457 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032)
6458 *base_idx = ZL_REF1P;
6459 else if (hw->cgu_part_number ==
6460 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384)
6461 *base_idx = SI_REF1P;
6462 else
6463 ret = -ENODEV;
6464
6465 break;
6466 default:
6467 ret = -ENODEV;
6468 break;
6469 }
6470
6471 return ret;
6472 }
6473
6474 /**
6475 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities
6476 * @hw: pointer to the hw struct
6477 * @pin_id: id of a pin
6478 * @caps: capabilities to modify
6479 *
6480 * Return:
6481 * * 0 - success, state capabilities were modified
6482 * * negative - failure, capabilities were not modified
6483 */
ice_cgu_get_output_pin_state_caps(struct ice_hw * hw,u8 pin_id,unsigned long * caps)6484 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
6485 unsigned long *caps)
6486 {
6487 bool can_change = true;
6488
6489 switch (hw->device_id) {
6490 case ICE_DEV_ID_E810C_SFP:
6491 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3)
6492 can_change = false;
6493 break;
6494 case ICE_DEV_ID_E810C_QSFP:
6495 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4)
6496 can_change = false;
6497 break;
6498 case ICE_DEV_ID_E823L_10G_BASE_T:
6499 case ICE_DEV_ID_E823L_1GBE:
6500 case ICE_DEV_ID_E823L_BACKPLANE:
6501 case ICE_DEV_ID_E823L_QSFP:
6502 case ICE_DEV_ID_E823L_SFP:
6503 case ICE_DEV_ID_E823C_10G_BASE_T:
6504 case ICE_DEV_ID_E823C_BACKPLANE:
6505 case ICE_DEV_ID_E823C_QSFP:
6506 case ICE_DEV_ID_E823C_SFP:
6507 case ICE_DEV_ID_E823C_SGMII:
6508 if (hw->cgu_part_number ==
6509 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 &&
6510 pin_id == ZL_OUT2)
6511 can_change = false;
6512 else if (hw->cgu_part_number ==
6513 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 &&
6514 pin_id == SI_OUT1)
6515 can_change = false;
6516 break;
6517 default:
6518 return -EINVAL;
6519 }
6520 if (can_change)
6521 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
6522 else
6523 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
6524
6525 return 0;
6526 }
6527