xref: /linux/drivers/dma/fsl-edma-common.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2013-2014 Freescale Semiconductor, Inc.
4  * Copyright 2018 Angelo Dureghello <angelo@sysam.it>
5  */
6 #ifndef _FSL_EDMA_COMMON_H_
7 #define _FSL_EDMA_COMMON_H_
8 
9 #include <linux/dma-direction.h>
10 #include <linux/platform_device.h>
11 #include "virt-dma.h"
12 
13 #define EDMA_CR_EDBG		BIT(1)
14 #define EDMA_CR_ERCA		BIT(2)
15 #define EDMA_CR_ERGA		BIT(3)
16 #define EDMA_CR_HOE		BIT(4)
17 #define EDMA_CR_HALT		BIT(5)
18 #define EDMA_CR_CLM		BIT(6)
19 #define EDMA_CR_EMLM		BIT(7)
20 #define EDMA_CR_ECX		BIT(16)
21 #define EDMA_CR_CX		BIT(17)
22 
23 #define EDMA_SEEI_SEEI(x)	((x) & GENMASK(4, 0))
24 #define EDMA_CEEI_CEEI(x)	((x) & GENMASK(4, 0))
25 #define EDMA_CINT_CINT(x)	((x) & GENMASK(4, 0))
26 #define EDMA_CERR_CERR(x)	((x) & GENMASK(4, 0))
27 
28 #define EDMA_TCD_ATTR_DSIZE(x)		(((x) & GENMASK(2, 0)))
29 #define EDMA_TCD_ATTR_DMOD(x)		(((x) & GENMASK(4, 0)) << 3)
30 #define EDMA_TCD_ATTR_SSIZE(x)		(((x) & GENMASK(2, 0)) << 8)
31 #define EDMA_TCD_ATTR_SMOD(x)		(((x) & GENMASK(4, 0)) << 11)
32 
33 #define EDMA_TCD_ITER_MASK		GENMASK(14, 0)
34 #define EDMA_TCD_CITER_CITER(x)		((x) & EDMA_TCD_ITER_MASK)
35 #define EDMA_TCD_BITER_BITER(x)		((x) & EDMA_TCD_ITER_MASK)
36 
37 #define EDMA_TCD_CSR_START		BIT(0)
38 #define EDMA_TCD_CSR_INT_MAJOR		BIT(1)
39 #define EDMA_TCD_CSR_INT_HALF		BIT(2)
40 #define EDMA_TCD_CSR_D_REQ		BIT(3)
41 #define EDMA_TCD_CSR_E_SG		BIT(4)
42 #define EDMA_TCD_CSR_E_LINK		BIT(5)
43 #define EDMA_TCD_CSR_ACTIVE		BIT(6)
44 #define EDMA_TCD_CSR_DONE		BIT(7)
45 
46 #define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))
47 #define EDMA_V3_TCD_NBYTES_MLOFF(x)        (x << 10)
48 #define EDMA_V3_TCD_NBYTES_DMLOE           (1 << 30)
49 #define EDMA_V3_TCD_NBYTES_SMLOE           (1 << 31)
50 
51 #define EDMAMUX_CHCFG_DIS		0x0
52 #define EDMAMUX_CHCFG_ENBL		0x80
53 #define EDMAMUX_CHCFG_SOURCE(n)		((n) & 0x3F)
54 
55 #define DMAMUX_NR	2
56 
57 #define EDMA_TCD                0x1000
58 
59 #define FSL_EDMA_BUSWIDTHS	(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
60 				 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
61 				 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
62 				 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
63 
64 #define EDMA_V3_CH_SBR_RD          BIT(22)
65 #define EDMA_V3_CH_SBR_WR          BIT(21)
66 #define EDMA_V3_CH_CSR_ERQ         BIT(0)
67 #define EDMA_V3_CH_CSR_EARQ        BIT(1)
68 #define EDMA_V3_CH_CSR_EEI         BIT(2)
69 #define EDMA_V3_CH_CSR_DONE        BIT(30)
70 #define EDMA_V3_CH_CSR_ACTIVE      BIT(31)
71 #define EDMA_V3_CH_ES_ERR          BIT(31)
72 #define EDMA_V3_MP_ES_VLD          BIT(31)
73 
74 enum fsl_edma_pm_state {
75 	RUNNING = 0,
76 	SUSPENDED,
77 };
78 
79 struct fsl_edma_hw_tcd {
80 	__le32	saddr;
81 	__le16	soff;
82 	__le16	attr;
83 	__le32	nbytes;
84 	__le32	slast;
85 	__le32	daddr;
86 	__le16	doff;
87 	__le16	citer;
88 	__le32	dlast_sga;
89 	__le16	csr;
90 	__le16	biter;
91 };
92 
93 struct fsl_edma_hw_tcd64 {
94 	__le64  saddr;
95 	__le16  soff;
96 	__le16  attr;
97 	__le32  nbytes;
98 	__le64  slast;
99 	__le64  daddr;
100 	__le64  dlast_sga;
101 	__le16  doff;
102 	__le16  citer;
103 	__le16  csr;
104 	__le16  biter;
105 } __packed;
106 
107 struct fsl_edma3_ch_reg {
108 	__le32	ch_csr;
109 	__le32	ch_es;
110 	__le32	ch_int;
111 	__le32	ch_sbr;
112 	__le32	ch_pri;
113 	__le32	ch_mux;
114 	__le32  ch_mattr; /* edma4, reserved for edma3 */
115 	__le32  ch_reserved;
116 	union {
117 		struct fsl_edma_hw_tcd tcd;
118 		struct fsl_edma_hw_tcd64 tcd64;
119 	};
120 } __packed;
121 
122 /*
123  * These are iomem pointers, for both v32 and v64.
124  */
125 struct edma_regs {
126 	void __iomem *cr;
127 	void __iomem *es;
128 	void __iomem *erqh;
129 	void __iomem *erql;	/* aka erq on v32 */
130 	void __iomem *eeih;
131 	void __iomem *eeil;	/* aka eei on v32 */
132 	void __iomem *seei;
133 	void __iomem *ceei;
134 	void __iomem *serq;
135 	void __iomem *cerq;
136 	void __iomem *cint;
137 	void __iomem *cerr;
138 	void __iomem *ssrt;
139 	void __iomem *cdne;
140 	void __iomem *inth;
141 	void __iomem *intl;
142 	void __iomem *errh;
143 	void __iomem *errl;
144 };
145 
146 struct fsl_edma_sw_tcd {
147 	dma_addr_t			ptcd;
148 	void				*vtcd;
149 };
150 
151 struct fsl_edma_chan {
152 	struct virt_dma_chan		vchan;
153 	enum dma_status			status;
154 	enum fsl_edma_pm_state		pm_state;
155 	struct fsl_edma_engine		*edma;
156 	struct fsl_edma_desc		*edesc;
157 	struct dma_slave_config		cfg;
158 	u32				attr;
159 	bool                            is_sw;
160 	struct dma_pool			*tcd_pool;
161 	dma_addr_t			dma_dev_addr;
162 	u32				dma_dev_size;
163 	enum dma_data_direction		dma_dir;
164 	char				chan_name[32];
165 	void __iomem			*tcd;
166 	void __iomem			*mux_addr;
167 	u32				real_count;
168 	struct work_struct		issue_worker;
169 	struct platform_device		*pdev;
170 	struct device			*pd_dev;
171 	struct device_link		*pd_dev_link;
172 	u32				srcid;
173 	struct clk			*clk;
174 	int                             priority;
175 	int				hw_chanid;
176 	int				txirq;
177 	irqreturn_t			(*irq_handler)(int irq, void *dev_id);
178 	bool				is_rxchan;
179 	bool				is_remote;
180 	bool				is_multi_fifo;
181 };
182 
183 struct fsl_edma_desc {
184 	struct virt_dma_desc		vdesc;
185 	struct fsl_edma_chan		*echan;
186 	bool				iscyclic;
187 	enum dma_transfer_direction	dirn;
188 	unsigned int			n_tcds;
189 	struct fsl_edma_sw_tcd		tcd[];
190 };
191 
192 #define FSL_EDMA_DRV_HAS_DMACLK		BIT(0)
193 #define FSL_EDMA_DRV_MUX_SWAP		BIT(1)
194 #define FSL_EDMA_DRV_CONFIG32		BIT(2)
195 #define FSL_EDMA_DRV_WRAP_IO		BIT(3)
196 #define FSL_EDMA_DRV_EDMA64		BIT(4)
197 #define FSL_EDMA_DRV_HAS_PD		BIT(5)
198 #define FSL_EDMA_DRV_HAS_CHCLK		BIT(6)
199 #define FSL_EDMA_DRV_HAS_CHMUX		BIT(7)
200 #define FSL_EDMA_DRV_MEM_REMOTE		BIT(8)
201 /* control and status register is in tcd address space, edma3 reg layout */
202 #define FSL_EDMA_DRV_SPLIT_REG		BIT(9)
203 #define FSL_EDMA_DRV_BUS_8BYTE		BIT(10)
204 #define FSL_EDMA_DRV_DEV_TO_DEV		BIT(11)
205 #define FSL_EDMA_DRV_ALIGN_64BYTE	BIT(12)
206 /* Need clean CHn_CSR DONE before enable TCD's ESG */
207 #define FSL_EDMA_DRV_CLEAR_DONE_E_SG	BIT(13)
208 /* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */
209 #define FSL_EDMA_DRV_CLEAR_DONE_E_LINK	BIT(14)
210 #define FSL_EDMA_DRV_TCD64		BIT(15)
211 
212 #define FSL_EDMA_DRV_EDMA3	(FSL_EDMA_DRV_SPLIT_REG |	\
213 				 FSL_EDMA_DRV_BUS_8BYTE |	\
214 				 FSL_EDMA_DRV_DEV_TO_DEV |	\
215 				 FSL_EDMA_DRV_ALIGN_64BYTE |	\
216 				 FSL_EDMA_DRV_CLEAR_DONE_E_SG |	\
217 				 FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
218 
219 #define FSL_EDMA_DRV_EDMA4	(FSL_EDMA_DRV_SPLIT_REG |	\
220 				 FSL_EDMA_DRV_BUS_8BYTE |	\
221 				 FSL_EDMA_DRV_DEV_TO_DEV |	\
222 				 FSL_EDMA_DRV_ALIGN_64BYTE |	\
223 				 FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
224 
225 struct fsl_edma_drvdata {
226 	u32			dmamuxs; /* only used before v3 */
227 	u32			chreg_off;
228 	u32			chreg_space_sz;
229 	u32			flags;
230 	u32			mux_off;	/* channel mux register offset */
231 	u32			mux_skip;	/* how much skip for each channel */
232 	int			(*setup_irq)(struct platform_device *pdev,
233 					     struct fsl_edma_engine *fsl_edma);
234 };
235 
236 struct fsl_edma_engine {
237 	struct dma_device	dma_dev;
238 	void __iomem		*membase;
239 	void __iomem		*muxbase[DMAMUX_NR];
240 	struct clk		*muxclk[DMAMUX_NR];
241 	struct clk		*dmaclk;
242 	struct mutex		fsl_edma_mutex;
243 	const struct fsl_edma_drvdata *drvdata;
244 	u32			n_chans;
245 	int			txirq;
246 	int			txirq_16_31;
247 	int			errirq;
248 	bool			big_endian;
249 	struct edma_regs	regs;
250 	u64			chan_masked;
251 	struct fsl_edma_chan	chans[] __counted_by(n_chans);
252 };
253 
fsl_edma_drvflags(struct fsl_edma_chan * fsl_chan)254 static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan)
255 {
256 	return fsl_chan->edma->drvdata->flags;
257 }
258 
259 #define edma_read_tcdreg_c(chan, _tcd,  __name)				\
260 _Generic(((_tcd)->__name),						\
261 	__iomem __le64 : edma_readq(chan->edma, &(_tcd)->__name),		\
262 	__iomem __le32 : edma_readl(chan->edma, &(_tcd)->__name),		\
263 	__iomem __le16 : edma_readw(chan->edma, &(_tcd)->__name)		\
264 	)
265 
266 #define edma_read_tcdreg(chan, __name)								\
267 ((fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) ?						\
268 	edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd64 __iomem *)chan->tcd), __name) :	\
269 	edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd __iomem *)chan->tcd), __name)		\
270 )
271 
272 #define edma_write_tcdreg_c(chan, _tcd, _val, __name)					\
273 _Generic((_tcd->__name),								\
274 	__iomem __le64 : edma_writeq(chan->edma, (u64 __force)(_val), &_tcd->__name),	\
275 	__iomem __le32 : edma_writel(chan->edma, (u32 __force)(_val), &_tcd->__name),	\
276 	__iomem __le16 : edma_writew(chan->edma, (u16 __force)(_val), &_tcd->__name),	\
277 	__iomem u8 : edma_writeb(chan->edma, _val, &_tcd->__name)			\
278 	)
279 
280 #define edma_write_tcdreg(chan, val, __name)							   \
281 do {												   \
282 	struct fsl_edma_hw_tcd64 __iomem *tcd64_r = (struct fsl_edma_hw_tcd64 __iomem *)chan->tcd; \
283 	struct fsl_edma_hw_tcd __iomem *tcd_r = (struct fsl_edma_hw_tcd __iomem *)chan->tcd;	   \
284 												   \
285 	if (fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64)					   \
286 		edma_write_tcdreg_c(chan, tcd64_r, val, __name);				   \
287 	else											   \
288 		edma_write_tcdreg_c(chan, tcd_r, val, __name);					   \
289 } while (0)
290 
291 #define edma_cp_tcd_to_reg(chan, __tcd, __name)							   \
292 do {	\
293 	struct fsl_edma_hw_tcd64 __iomem *tcd64_r = (struct fsl_edma_hw_tcd64 __iomem *)chan->tcd; \
294 	struct fsl_edma_hw_tcd __iomem *tcd_r = (struct fsl_edma_hw_tcd __iomem *)chan->tcd;	   \
295 	struct fsl_edma_hw_tcd64 *tcd64_m = (struct fsl_edma_hw_tcd64 *)__tcd;			   \
296 	struct fsl_edma_hw_tcd *tcd_m = (struct fsl_edma_hw_tcd *)__tcd;			   \
297 												   \
298 	if (fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64)					   \
299 		edma_write_tcdreg_c(chan, tcd64_r,  tcd64_m->__name, __name);			   \
300 	else											   \
301 		edma_write_tcdreg_c(chan, tcd_r, tcd_m->__name, __name);			   \
302 } while (0)
303 
304 #define edma_readl_chreg(chan, __name)				\
305 	edma_readl(chan->edma,					\
306 		   (void __iomem *)&(container_of(((__force void *)chan->tcd),\
307 						  struct fsl_edma3_ch_reg, tcd)->__name))
308 
309 #define edma_writel_chreg(chan, val,  __name)			\
310 	edma_writel(chan->edma, val,				\
311 		   (void __iomem *)&(container_of(((__force void *)chan->tcd),\
312 						  struct fsl_edma3_ch_reg, tcd)->__name))
313 
314 #define fsl_edma_get_tcd(_chan, _tcd, _field)			\
315 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? (((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
316 						 (((struct fsl_edma_hw_tcd *)_tcd)->_field))
317 
318 #define fsl_edma_le_to_cpu(x)						\
319 _Generic((x),								\
320 	__le64 : le64_to_cpu((x)),					\
321 	__le32 : le32_to_cpu((x)),					\
322 	__le16 : le16_to_cpu((x))					\
323 )
324 
325 #define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field)				\
326 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ?				\
327 	fsl_edma_le_to_cpu(((struct fsl_edma_hw_tcd64 *)_tcd)->_field) :	\
328 	fsl_edma_le_to_cpu(((struct fsl_edma_hw_tcd *)_tcd)->_field))
329 
330 #define fsl_edma_set_tcd_to_le_c(_tcd, _val, _field)					\
331 _Generic(((_tcd)->_field),								\
332 	__le64 : (_tcd)->_field = cpu_to_le64(_val),					\
333 	__le32 : (_tcd)->_field = cpu_to_le32(_val),					\
334 	__le16 : (_tcd)->_field = cpu_to_le16(_val)					\
335 )
336 
337 #define fsl_edma_set_tcd_to_le(_chan, _tcd, _val, _field)	\
338 do {								\
339 	if (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64)	\
340 		fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd64 *)_tcd, _val, _field);	\
341 	else											\
342 		fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd *)_tcd, _val, _field);		\
343 } while (0)
344 
345 /* Need after struct defination */
346 #include "fsl-edma-trace.h"
347 
348 /*
349  * R/W functions for big- or little-endian registers:
350  * The eDMA controller's endian is independent of the CPU core's endian.
351  * For the big-endian IP module, the offset for 8-bit or 16-bit registers
352  * should also be swapped opposite to that in little-endian IP.
353  */
edma_readq(struct fsl_edma_engine * edma,void __iomem * addr)354 static inline u64 edma_readq(struct fsl_edma_engine *edma, void __iomem *addr)
355 {
356 	u64 l, h;
357 
358 	if (edma->big_endian) {
359 		l = ioread32be(addr);
360 		h = ioread32be(addr + 4);
361 	} else {
362 		l = ioread32(addr);
363 		h = ioread32(addr + 4);
364 	}
365 
366 	trace_edma_readl(edma, addr, l);
367 	trace_edma_readl(edma, addr + 4, h);
368 
369 	return (h << 32) | l;
370 }
371 
edma_readl(struct fsl_edma_engine * edma,void __iomem * addr)372 static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
373 {
374 	u32 val;
375 
376 	if (edma->big_endian)
377 		val = ioread32be(addr);
378 	else
379 		val = ioread32(addr);
380 
381 	trace_edma_readl(edma, addr, val);
382 
383 	return val;
384 }
385 
edma_readw(struct fsl_edma_engine * edma,void __iomem * addr)386 static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
387 {
388 	u16 val;
389 
390 	if (edma->big_endian)
391 		val = ioread16be(addr);
392 	else
393 		val = ioread16(addr);
394 
395 	trace_edma_readw(edma, addr, val);
396 
397 	return val;
398 }
399 
edma_writeb(struct fsl_edma_engine * edma,u8 val,void __iomem * addr)400 static inline void edma_writeb(struct fsl_edma_engine *edma,
401 			       u8 val, void __iomem *addr)
402 {
403 	/* swap the reg offset for these in big-endian mode */
404 	if (edma->big_endian)
405 		iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
406 	else
407 		iowrite8(val, addr);
408 
409 	trace_edma_writeb(edma, addr, val);
410 }
411 
edma_writew(struct fsl_edma_engine * edma,u16 val,void __iomem * addr)412 static inline void edma_writew(struct fsl_edma_engine *edma,
413 			       u16 val, void __iomem *addr)
414 {
415 	/* swap the reg offset for these in big-endian mode */
416 	if (edma->big_endian)
417 		iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
418 	else
419 		iowrite16(val, addr);
420 
421 	trace_edma_writew(edma, addr, val);
422 }
423 
edma_writel(struct fsl_edma_engine * edma,u32 val,void __iomem * addr)424 static inline void edma_writel(struct fsl_edma_engine *edma,
425 			       u32 val, void __iomem *addr)
426 {
427 	if (edma->big_endian)
428 		iowrite32be(val, addr);
429 	else
430 		iowrite32(val, addr);
431 
432 	trace_edma_writel(edma, addr, val);
433 }
434 
edma_writeq(struct fsl_edma_engine * edma,u64 val,void __iomem * addr)435 static inline void edma_writeq(struct fsl_edma_engine *edma,
436 			       u64 val, void __iomem *addr)
437 {
438 	if (edma->big_endian) {
439 		iowrite32be(val & 0xFFFFFFFF, addr);
440 		iowrite32be(val >> 32, addr + 4);
441 	} else {
442 		iowrite32(val & 0xFFFFFFFF, addr);
443 		iowrite32(val >> 32, addr + 4);
444 	}
445 
446 	trace_edma_writel(edma, addr, val & 0xFFFFFFFF);
447 	trace_edma_writel(edma, addr + 4, val >> 32);
448 }
449 
to_fsl_edma_chan(struct dma_chan * chan)450 static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
451 {
452 	return container_of(chan, struct fsl_edma_chan, vchan.chan);
453 }
454 
to_fsl_edma_desc(struct virt_dma_desc * vd)455 static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
456 {
457 	return container_of(vd, struct fsl_edma_desc, vdesc);
458 }
459 
fsl_edma_err_chan_handler(struct fsl_edma_chan * fsl_chan)460 static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
461 {
462 	fsl_chan->status = DMA_ERROR;
463 }
464 
465 void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
466 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
467 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
468 			unsigned int slot, bool enable);
469 void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
470 int fsl_edma_terminate_all(struct dma_chan *chan);
471 int fsl_edma_pause(struct dma_chan *chan);
472 int fsl_edma_resume(struct dma_chan *chan);
473 int fsl_edma_slave_config(struct dma_chan *chan,
474 				 struct dma_slave_config *cfg);
475 enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
476 		dma_cookie_t cookie, struct dma_tx_state *txstate);
477 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
478 		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
479 		size_t period_len, enum dma_transfer_direction direction,
480 		unsigned long flags);
481 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
482 		struct dma_chan *chan, struct scatterlist *sgl,
483 		unsigned int sg_len, enum dma_transfer_direction direction,
484 		unsigned long flags, void *context);
485 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(
486 		struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src,
487 		size_t len, unsigned long flags);
488 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
489 void fsl_edma_issue_pending(struct dma_chan *chan);
490 int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
491 void fsl_edma_free_chan_resources(struct dma_chan *chan);
492 void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
493 void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
494 
495 #endif /* _FSL_EDMA_COMMON_H_ */
496