1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "basics/conversion.h"
35 #include "dcn316_resource.h"
36
37 #include "dcn20/dcn20_resource.h"
38 #include "dcn30/dcn30_resource.h"
39 #include "dcn31/dcn31_resource.h"
40
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn30/dcn30_hubbub.h"
43 #include "dcn31/dcn31_hubbub.h"
44 #include "dcn30/dcn30_mpc.h"
45 #include "dcn31/dcn31_hubp.h"
46 #include "irq/dcn31/irq_service_dcn31.h"
47 #include "dcn30/dcn30_dpp.h"
48 #include "dcn31/dcn31_optc.h"
49 #include "dcn20/dcn20_hwseq.h"
50 #include "dcn30/dcn30_hwseq.h"
51 #include "dce110/dce110_hwseq.h"
52 #include "dcn30/dcn30_opp.h"
53 #include "dcn20/dcn20_dsc.h"
54 #include "dcn30/dcn30_vpg.h"
55 #include "dcn30/dcn30_afmt.h"
56 #include "dcn30/dcn30_dio_stream_encoder.h"
57 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
58 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
59 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
61 #include "dcn31/dcn31_apg.h"
62 #include "dcn31/dcn31_dio_link_encoder.h"
63 #include "dcn31/dcn31_vpg.h"
64 #include "dcn31/dcn31_afmt.h"
65 #include "dce/dce_clock_source.h"
66 #include "dce/dce_audio.h"
67 #include "dce/dce_hwseq.h"
68 #include "clk_mgr.h"
69 #include "dio/dcn10/dcn10_dio.h"
70 #include "dio/virtual/virtual_stream_encoder.h"
71 #include "dce110/dce110_resource.h"
72 #include "dml/display_mode_vba.h"
73 #include "dml/dcn31/dcn31_fpu.h"
74 #include "dcn31/dcn31_dccg.h"
75 #include "dcn10/dcn10_resource.h"
76 #include "dcn31/dcn31_panel_cntl.h"
77
78 #include "dcn30/dcn30_dwb.h"
79 #include "dcn30/dcn30_mmhubbub.h"
80
81 #include "dcn/dcn_3_1_6_offset.h"
82 #include "dcn/dcn_3_1_6_sh_mask.h"
83 #include "dpcs/dpcs_4_2_3_offset.h"
84 #include "dpcs/dpcs_4_2_3_sh_mask.h"
85
86 #define regBIF_BX1_BIOS_SCRATCH_2 0x003a
87 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 1
88 #define regBIF_BX1_BIOS_SCRATCH_3 0x003b
89 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 1
90 #define regBIF_BX1_BIOS_SCRATCH_6 0x003e
91 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 1
92
93 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
94 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
95 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
96 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
97
98 #define DCN_BASE__INST0_SEG0 0x00000012
99 #define DCN_BASE__INST0_SEG1 0x000000C0
100 #define DCN_BASE__INST0_SEG2 0x000034C0
101 #define DCN_BASE__INST0_SEG3 0x00009000
102 #define DCN_BASE__INST0_SEG4 0x02403C00
103 #define DCN_BASE__INST0_SEG5 0
104
105 #define DPCS_BASE__INST0_SEG0 0x00000012
106 #define DPCS_BASE__INST0_SEG1 0x000000C0
107 #define DPCS_BASE__INST0_SEG2 0x000034C0
108 #define DPCS_BASE__INST0_SEG3 0x00009000
109 #define DPCS_BASE__INST0_SEG4 0x02403C00
110 #define DPCS_BASE__INST0_SEG5 0
111
112 #define NBIO_BASE__INST0_SEG0 0x00000000
113 #define NBIO_BASE__INST0_SEG1 0x00000014
114 #define NBIO_BASE__INST0_SEG2 0x00000D20
115 #define NBIO_BASE__INST0_SEG3 0x00010400
116 #define NBIO_BASE__INST0_SEG4 0x0241B000
117 #define NBIO_BASE__INST0_SEG5 0x04040000
118
119 #include "reg_helper.h"
120 #include "dce/dmub_abm.h"
121 #include "dce/dmub_psr.h"
122 #include "dce/dce_aux.h"
123 #include "dce/dce_i2c.h"
124
125 #include "dml/dcn30/display_mode_vba_30.h"
126 #include "vm_helper.h"
127 #include "dcn20/dcn20_vmid.h"
128
129 #include "link_enc_cfg.h"
130
131 #define DCN3_16_MAX_DET_SIZE 384
132 #define DCN3_16_CRB_SEGMENT_SIZE_KB 64
133
134 enum dcn31_clk_src_array_id {
135 DCN31_CLK_SRC_PLL0,
136 DCN31_CLK_SRC_PLL1,
137 DCN31_CLK_SRC_PLL2,
138 DCN31_CLK_SRC_PLL3,
139 DCN31_CLK_SRC_PLL4,
140 DCN30_CLK_SRC_TOTAL
141 };
142
143 /* begin *********************
144 * macros to expend register list macro defined in HW object header file
145 */
146
147 /* DCN */
148 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
149
150 #define BASE(seg) BASE_INNER(seg)
151
152 #define SR(reg_name)\
153 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
154 reg ## reg_name
155
156 #define SRI(reg_name, block, id)\
157 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
159
160 #define SRI2(reg_name, block, id)\
161 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
162 reg ## reg_name
163
164 #define SRIR(var_name, reg_name, block, id)\
165 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
166 reg ## block ## id ## _ ## reg_name
167
168 #define SRII(reg_name, block, id)\
169 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 reg ## block ## id ## _ ## reg_name
171
172 #define SRII_MPC_RMU(reg_name, block, id)\
173 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
174 reg ## block ## id ## _ ## reg_name
175
176 #define SRII_DWB(reg_name, temp_name, block, id)\
177 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
178 reg ## block ## id ## _ ## temp_name
179
180 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
181 .field_name = reg_name ## __ ## field_name ## post_fix
182
183 #define DCCG_SRII(reg_name, block, id)\
184 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
185 reg ## block ## id ## _ ## reg_name
186
187 #define VUPDATE_SRII(reg_name, block, id)\
188 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
189 reg ## reg_name ## _ ## block ## id
190
191 /* NBIO */
192 #define NBIO_BASE_INNER(seg) \
193 NBIO_BASE__INST0_SEG ## seg
194
195 #define NBIO_BASE(seg) \
196 NBIO_BASE_INNER(seg)
197
198 #define NBIO_SR(reg_name)\
199 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
200 regBIF_BX1_ ## reg_name
201
202 static const struct bios_registers bios_regs = {
203 NBIO_SR(BIOS_SCRATCH_3),
204 NBIO_SR(BIOS_SCRATCH_6)
205 };
206
207 #define clk_src_regs(index, pllid)\
208 [index] = {\
209 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
210 }
211
212 static const struct dce110_clk_src_regs clk_src_regs[] = {
213 clk_src_regs(0, A),
214 clk_src_regs(1, B),
215 clk_src_regs(2, C),
216 clk_src_regs(3, D),
217 clk_src_regs(4, E)
218 };
219
220 static const struct dce110_clk_src_shift cs_shift = {
221 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
222 };
223
224 static const struct dce110_clk_src_mask cs_mask = {
225 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
226 };
227
228 #define abm_regs(id)\
229 [id] = {\
230 ABM_DCN302_REG_LIST(id)\
231 }
232
233 static const struct dce_abm_registers abm_regs[] = {
234 abm_regs(0),
235 abm_regs(1),
236 abm_regs(2),
237 abm_regs(3),
238 };
239
240 static const struct dce_abm_shift abm_shift = {
241 ABM_MASK_SH_LIST_DCN30(__SHIFT)
242 };
243
244 static const struct dce_abm_mask abm_mask = {
245 ABM_MASK_SH_LIST_DCN30(_MASK)
246 };
247
248 #define audio_regs(id)\
249 [id] = {\
250 AUD_COMMON_REG_LIST(id)\
251 }
252
253 static const struct dce_audio_registers audio_regs[] = {
254 audio_regs(0),
255 audio_regs(1),
256 audio_regs(2),
257 audio_regs(3),
258 audio_regs(4),
259 audio_regs(5),
260 audio_regs(6)
261 };
262
263 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
264 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
265 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
266 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
267
268 static const struct dce_audio_shift audio_shift = {
269 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
270 };
271
272 static const struct dce_audio_mask audio_mask = {
273 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
274 };
275
276 #define vpg_regs(id)\
277 [id] = {\
278 VPG_DCN31_REG_LIST(id)\
279 }
280
281 static const struct dcn31_vpg_registers vpg_regs[] = {
282 vpg_regs(0),
283 vpg_regs(1),
284 vpg_regs(2),
285 vpg_regs(3),
286 vpg_regs(4),
287 vpg_regs(5),
288 vpg_regs(6),
289 vpg_regs(7),
290 vpg_regs(8),
291 vpg_regs(9),
292 };
293
294 static const struct dcn31_vpg_shift vpg_shift = {
295 DCN31_VPG_MASK_SH_LIST(__SHIFT)
296 };
297
298 static const struct dcn31_vpg_mask vpg_mask = {
299 DCN31_VPG_MASK_SH_LIST(_MASK)
300 };
301
302 #define afmt_regs(id)\
303 [id] = {\
304 AFMT_DCN31_REG_LIST(id)\
305 }
306
307 static const struct dcn31_afmt_registers afmt_regs[] = {
308 afmt_regs(0),
309 afmt_regs(1),
310 afmt_regs(2),
311 afmt_regs(3),
312 afmt_regs(4),
313 afmt_regs(5)
314 };
315
316 static const struct dcn31_afmt_shift afmt_shift = {
317 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
318 };
319
320 static const struct dcn31_afmt_mask afmt_mask = {
321 DCN31_AFMT_MASK_SH_LIST(_MASK)
322 };
323
324
325 #define apg_regs(id)\
326 [id] = {\
327 APG_DCN31_REG_LIST(id)\
328 }
329
330 static const struct dcn31_apg_registers apg_regs[] = {
331 apg_regs(0),
332 apg_regs(1),
333 apg_regs(2),
334 apg_regs(3)
335 };
336
337 static const struct dcn31_apg_shift apg_shift = {
338 DCN31_APG_MASK_SH_LIST(__SHIFT)
339 };
340
341 static const struct dcn31_apg_mask apg_mask = {
342 DCN31_APG_MASK_SH_LIST(_MASK)
343 };
344
345
346 #define stream_enc_regs(id)\
347 [id] = {\
348 SE_DCN3_REG_LIST(id)\
349 }
350
351 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
352 stream_enc_regs(0),
353 stream_enc_regs(1),
354 stream_enc_regs(2),
355 stream_enc_regs(3),
356 stream_enc_regs(4)
357 };
358
359 static const struct dcn10_stream_encoder_shift se_shift = {
360 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
361 };
362
363 static const struct dcn10_stream_encoder_mask se_mask = {
364 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
365 };
366
367
368 #define aux_regs(id)\
369 [id] = {\
370 DCN2_AUX_REG_LIST(id)\
371 }
372
373 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
374 aux_regs(0),
375 aux_regs(1),
376 aux_regs(2),
377 aux_regs(3),
378 aux_regs(4)
379 };
380
381 #define hpd_regs(id)\
382 [id] = {\
383 HPD_REG_LIST(id)\
384 }
385
386 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
387 hpd_regs(0),
388 hpd_regs(1),
389 hpd_regs(2),
390 hpd_regs(3),
391 hpd_regs(4)
392 };
393
394 #define link_regs(id, phyid)\
395 [id] = {\
396 LE_DCN31_REG_LIST(id), \
397 UNIPHY_DCN2_REG_LIST(phyid), \
398 DPCS_DCN31_REG_LIST(id), \
399 }
400
401 static const struct dce110_aux_registers_shift aux_shift = {
402 DCN_AUX_MASK_SH_LIST(__SHIFT)
403 };
404
405 static const struct dce110_aux_registers_mask aux_mask = {
406 DCN_AUX_MASK_SH_LIST(_MASK)
407 };
408
409 static const struct dcn10_link_enc_registers link_enc_regs[] = {
410 link_regs(0, A),
411 link_regs(1, B),
412 link_regs(2, C),
413 link_regs(3, D),
414 link_regs(4, E)
415 };
416
417 static const struct dcn10_link_enc_shift le_shift = {
418 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
419 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
420 };
421
422 static const struct dcn10_link_enc_mask le_mask = {
423 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
424 DPCS_DCN31_MASK_SH_LIST(_MASK)
425 };
426
427 #define hpo_frl_stream_encoder_reg_list(id)\
428 [id] = {\
429 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST(id)\
430 }
431
432 #define hpo_frl_stream_encoder_dme_reg_list(id)\
433 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST(id, 6)
434
435
436 static const struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[] = {
437 hpo_frl_stream_encoder_reg_list(0),
438 hpo_frl_stream_encoder_dme_reg_list(6),
439 };
440
441 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
442 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
443 };
444
445 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
446 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
447 };
448
449 #define hpo_frl_link_encoder_reg_list(id)\
450 [id] = {\
451 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST(id)\
452 }
453
454 static const struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[] = {
455 hpo_frl_link_encoder_reg_list(0),
456 };
457
458 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
459 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
460 };
461
462 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
463 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
464 };
465
466
467
468 #define hpo_dp_stream_encoder_reg_list(id)\
469 [id] = {\
470 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
471 }
472
473 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
474 hpo_dp_stream_encoder_reg_list(0),
475 hpo_dp_stream_encoder_reg_list(1),
476 hpo_dp_stream_encoder_reg_list(2),
477 hpo_dp_stream_encoder_reg_list(3),
478 };
479
480 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
481 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
482 };
483
484 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
485 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
486 };
487
488
489 #define hpo_dp_link_encoder_reg_list(id)\
490 [id] = {\
491 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
492 DCN3_1_RDPCSTX_REG_LIST(0),\
493 DCN3_1_RDPCSTX_REG_LIST(1),\
494 DCN3_1_RDPCSTX_REG_LIST(2),\
495 DCN3_1_RDPCSTX_REG_LIST(3),\
496 DCN3_1_RDPCSTX_REG_LIST(4)\
497 }
498
499 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
500 hpo_dp_link_encoder_reg_list(0),
501 hpo_dp_link_encoder_reg_list(1),
502 };
503
504 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
505 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
506 };
507
508 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
509 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
510 };
511
512
513 #define dpp_regs(id)\
514 [id] = {\
515 DPP_REG_LIST_DCN30(id),\
516 }
517
518 static const struct dcn3_dpp_registers dpp_regs[] = {
519 dpp_regs(0),
520 dpp_regs(1),
521 dpp_regs(2),
522 dpp_regs(3)
523 };
524
525 static const struct dcn3_dpp_shift tf_shift = {
526 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
527 };
528
529 static const struct dcn3_dpp_mask tf_mask = {
530 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
531 };
532
533 #define opp_regs(id)\
534 [id] = {\
535 OPP_REG_LIST_DCN30(id),\
536 }
537
538 static const struct dcn20_opp_registers opp_regs[] = {
539 opp_regs(0),
540 opp_regs(1),
541 opp_regs(2),
542 opp_regs(3)
543 };
544
545 static const struct dcn20_opp_shift opp_shift = {
546 OPP_MASK_SH_LIST_DCN20(__SHIFT)
547 };
548
549 static const struct dcn20_opp_mask opp_mask = {
550 OPP_MASK_SH_LIST_DCN20(_MASK)
551 };
552
553 #define aux_engine_regs(id)\
554 [id] = {\
555 AUX_COMMON_REG_LIST0(id), \
556 .AUXN_IMPCAL = 0, \
557 .AUXP_IMPCAL = 0, \
558 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
559 }
560
561 static const struct dce110_aux_registers aux_engine_regs[] = {
562 aux_engine_regs(0),
563 aux_engine_regs(1),
564 aux_engine_regs(2),
565 aux_engine_regs(3),
566 aux_engine_regs(4)
567 };
568
569 #define dwbc_regs_dcn3(id)\
570 [id] = {\
571 DWBC_COMMON_REG_LIST_DCN30(id),\
572 }
573
574 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
575 dwbc_regs_dcn3(0),
576 };
577
578 static const struct dcn30_dwbc_shift dwbc30_shift = {
579 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
580 };
581
582 static const struct dcn30_dwbc_mask dwbc30_mask = {
583 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
584 };
585
586 #define mcif_wb_regs_dcn3(id)\
587 [id] = {\
588 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
589 }
590
591 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
592 mcif_wb_regs_dcn3(0)
593 };
594
595 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
596 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
597 };
598
599 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
600 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
601 };
602
603 #define dsc_regsDCN20(id)\
604 [id] = {\
605 DSC_REG_LIST_DCN20(id)\
606 }
607
608 static const struct dcn20_dsc_registers dsc_regs[] = {
609 dsc_regsDCN20(0),
610 dsc_regsDCN20(1),
611 dsc_regsDCN20(2)
612 };
613
614 static const struct dcn20_dsc_shift dsc_shift = {
615 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
616 };
617
618 static const struct dcn20_dsc_mask dsc_mask = {
619 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
620 };
621
622 static const struct dcn30_mpc_registers mpc_regs = {
623 MPC_REG_LIST_DCN3_0(0),
624 MPC_REG_LIST_DCN3_0(1),
625 MPC_REG_LIST_DCN3_0(2),
626 MPC_REG_LIST_DCN3_0(3),
627 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
628 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
629 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
630 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
631 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
632 MPC_RMU_REG_LIST_DCN3AG(0),
633 MPC_RMU_REG_LIST_DCN3AG(1),
634 //MPC_RMU_REG_LIST_DCN3AG(2),
635 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
636 };
637
638 static const struct dcn30_mpc_shift mpc_shift = {
639 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
640 };
641
642 static const struct dcn30_mpc_mask mpc_mask = {
643 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
644 };
645
646 #define optc_regs(id)\
647 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
648
649 static const struct dcn_optc_registers optc_regs[] = {
650 optc_regs(0),
651 optc_regs(1),
652 optc_regs(2),
653 optc_regs(3)
654 };
655
656 static const struct dcn_optc_shift optc_shift = {
657 OPTC_COMMON_MASK_SH_LIST_DCN31X(__SHIFT)
658 };
659
660 static const struct dcn_optc_mask optc_mask = {
661 OPTC_COMMON_MASK_SH_LIST_DCN31X(_MASK)
662 };
663
664 #define hubp_regs(id)\
665 [id] = {\
666 HUBP_REG_LIST_DCN30(id)\
667 }
668
669 static const struct dcn_hubp2_registers hubp_regs[] = {
670 hubp_regs(0),
671 hubp_regs(1),
672 hubp_regs(2),
673 hubp_regs(3)
674 };
675
676
677 static const struct dcn_hubp2_shift hubp_shift = {
678 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
679 };
680
681 static const struct dcn_hubp2_mask hubp_mask = {
682 HUBP_MASK_SH_LIST_DCN31(_MASK)
683 };
684 static const struct dcn_hubbub_registers hubbub_reg = {
685 HUBBUB_REG_LIST_DCN31(0)
686 };
687
688 static const struct dcn_hubbub_shift hubbub_shift = {
689 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
690 };
691
692 static const struct dcn_hubbub_mask hubbub_mask = {
693 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
694 };
695
696 static const struct dccg_registers dccg_regs = {
697 DCCG_REG_LIST_DCN31()
698 };
699
700 static const struct dccg_shift dccg_shift = {
701 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
702 };
703
704 static const struct dccg_mask dccg_mask = {
705 DCCG_MASK_SH_LIST_DCN31(_MASK)
706 };
707
708
709 #define SRII2(reg_name_pre, reg_name_post, id)\
710 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
711 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
712 reg ## reg_name_pre ## id ## _ ## reg_name_post
713
714
715 #define HWSEQ_DCN31_REG_LIST()\
716 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
717 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
718 SR(DIO_MEM_PWR_CTRL), \
719 SR(ODM_MEM_PWR_CTRL3), \
720 SR(DMU_MEM_PWR_CNTL), \
721 SR(MMHUBBUB_MEM_PWR_CNTL), \
722 SR(DCCG_GATE_DISABLE_CNTL), \
723 SR(DCCG_GATE_DISABLE_CNTL2), \
724 SR(DCFCLK_CNTL),\
725 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
726 SRII(PIXEL_RATE_CNTL, OTG, 0), \
727 SRII(PIXEL_RATE_CNTL, OTG, 1),\
728 SRII(PIXEL_RATE_CNTL, OTG, 2),\
729 SRII(PIXEL_RATE_CNTL, OTG, 3),\
730 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
731 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
732 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
733 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
734 SR(MICROSECOND_TIME_BASE_DIV), \
735 SR(MILLISECOND_TIME_BASE_DIV), \
736 SR(DISPCLK_FREQ_CHANGE_CNTL), \
737 SR(RBBMIF_TIMEOUT_DIS), \
738 SR(RBBMIF_TIMEOUT_DIS_2), \
739 SR(DCHUBBUB_CRC_CTRL), \
740 SR(DPP_TOP0_DPP_CRC_CTRL), \
741 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
742 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
743 SR(MPC_CRC_CTRL), \
744 SR(MPC_CRC_RESULT_GB), \
745 SR(MPC_CRC_RESULT_C), \
746 SR(MPC_CRC_RESULT_AR), \
747 SR(DOMAIN0_PG_CONFIG), \
748 SR(DOMAIN1_PG_CONFIG), \
749 SR(DOMAIN2_PG_CONFIG), \
750 SR(DOMAIN3_PG_CONFIG), \
751 SR(DOMAIN16_PG_CONFIG), \
752 SR(DOMAIN17_PG_CONFIG), \
753 SR(DOMAIN18_PG_CONFIG), \
754 SR(DOMAIN0_PG_STATUS), \
755 SR(DOMAIN1_PG_STATUS), \
756 SR(DOMAIN2_PG_STATUS), \
757 SR(DOMAIN3_PG_STATUS), \
758 SR(DOMAIN16_PG_STATUS), \
759 SR(DOMAIN17_PG_STATUS), \
760 SR(DOMAIN18_PG_STATUS), \
761 SR(D1VGA_CONTROL), \
762 SR(D2VGA_CONTROL), \
763 SR(D3VGA_CONTROL), \
764 SR(D4VGA_CONTROL), \
765 SR(D5VGA_CONTROL), \
766 SR(D6VGA_CONTROL), \
767 SR(DC_IP_REQUEST_CNTL), \
768 SR(AZALIA_AUDIO_DTO), \
769 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
770 SR(HPO_TOP_HW_CONTROL)
771
772 static const struct dce_hwseq_registers hwseq_reg = {
773 HWSEQ_DCN31_REG_LIST()
774 };
775
776 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
777 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
778 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
779 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
780 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
781 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
782 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
783 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
784 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
785 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
786 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
787 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
788 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
789 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
790 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
791 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
792 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
793 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
794 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
795 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
796 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
797 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
798 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
799 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
800 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
801 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
802 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
803 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
804 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
805 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
806 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
807 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
808 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
809 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
810
811 static const struct dce_hwseq_shift hwseq_shift = {
812 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
813 };
814
815 static const struct dce_hwseq_mask hwseq_mask = {
816 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
817 };
818 #define vmid_regs(id)\
819 [id] = {\
820 DCN20_VMID_REG_LIST(id)\
821 }
822
823 static const struct dcn_vmid_registers vmid_regs[] = {
824 vmid_regs(0),
825 vmid_regs(1),
826 vmid_regs(2),
827 vmid_regs(3),
828 vmid_regs(4),
829 vmid_regs(5),
830 vmid_regs(6),
831 vmid_regs(7),
832 vmid_regs(8),
833 vmid_regs(9),
834 vmid_regs(10),
835 vmid_regs(11),
836 vmid_regs(12),
837 vmid_regs(13),
838 vmid_regs(14),
839 vmid_regs(15)
840 };
841
842 static const struct dcn20_vmid_shift vmid_shifts = {
843 DCN20_VMID_MASK_SH_LIST(__SHIFT)
844 };
845
846 static const struct dcn20_vmid_mask vmid_masks = {
847 DCN20_VMID_MASK_SH_LIST(_MASK)
848 };
849
850 static const struct dcn_dio_registers dio_regs = {
851 DIO_REG_LIST_DCN10()
852 };
853
854 #define DIO_MASK_SH_LIST(mask_sh)\
855 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
856
857 static const struct dcn_dio_shift dio_shift = {
858 DIO_MASK_SH_LIST(__SHIFT)
859 };
860
861 static const struct dcn_dio_mask dio_mask = {
862 DIO_MASK_SH_LIST(_MASK)
863 };
864
865 static const struct resource_caps res_cap_dcn31 = {
866 .num_timing_generator = 4,
867 .num_opp = 4,
868 .num_video_plane = 4,
869 .num_audio = 5,
870 .num_stream_encoder = 5,
871 .num_dig_link_enc = 5,
872 .num_hpo_frl = 1,
873 .num_hpo_dp_stream_encoder = 4,
874 .num_hpo_dp_link_encoder = 2,
875 .num_pll = 5,
876 .num_dwb = 1,
877 .num_ddc = 5,
878 .num_vmid = 16,
879 .num_mpc_3dlut = 2,
880 .num_dsc = 3,
881 };
882
883 static const struct dc_plane_cap plane_cap = {
884 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
885 .per_pixel_alpha = true,
886
887 .pixel_format_support = {
888 .argb8888 = true,
889 .nv12 = true,
890 .fp16 = true,
891 .p010 = true,
892 .ayuv = false,
893 },
894
895 .max_upscale_factor = {
896 .argb8888 = 16000,
897 .nv12 = 16000,
898 .fp16 = 16000
899 },
900
901 // 6:1 downscaling ratio: 1000/6 = 166.666
902 .max_downscale_factor = {
903 .argb8888 = 167,
904 .nv12 = 167,
905 .fp16 = 167
906 },
907 64,
908 64
909 };
910
911 static const struct dc_debug_options debug_defaults_drv = {
912 .limit_ffe = 3,
913 .disable_z10 = true, /*hw not support it*/
914 .disable_dmcu = true,
915 .force_abm_enable = false,
916 .clock_trace = true,
917 .disable_pplib_clock_request = false,
918 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
919 .force_single_disp_pipe_split = false,
920 .disable_dcc = DCC_ENABLE,
921 .vsr_support = true,
922 .performance_trace = false,
923 .max_downscale_src_width = 4096,/*upto true 4k*/
924 .disable_pplib_wm_range = false,
925 .scl_reset_length10 = true,
926 .sanity_checks = false,
927 .underflow_assert_delay_us = 0xFFFFFFFF,
928 .dwb_fi_phase = -1, // -1 = disable,
929 .dmub_command_table = true,
930 .pstate_enabled = true,
931 .use_max_lb = true,
932 .enable_mem_low_power = {
933 .bits = {
934 .vga = true,
935 .i2c = true,
936 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
937 .dscl = true,
938 .cm = true,
939 .mpc = true,
940 .optc = true,
941 .vpg = true,
942 .afmt = true,
943 }
944 },
945 .max_frl_rate = HDMI_FRL_LINK_RATE_10GBPS, /*same as dcn3.1 for now*/
946 .using_dml2 = false,
947 };
948
949 static const struct dc_check_config config_defaults = {
950 .enable_legacy_fast_update = true,
951 };
952
953 static const struct dc_panel_config panel_config_defaults = {
954 .psr = {
955 .disable_psr = false,
956 .disallow_psrsu = false,
957 .disallow_replay = false,
958 },
959 .ilr = {
960 .optimize_edp_link_rate = true,
961 },
962 };
963
dcn31_dpp_destroy(struct dpp ** dpp)964 static void dcn31_dpp_destroy(struct dpp **dpp)
965 {
966 kfree(TO_DCN20_DPP(*dpp));
967 *dpp = NULL;
968 }
969
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)970 static struct dpp *dcn31_dpp_create(
971 struct dc_context *ctx,
972 uint32_t inst)
973 {
974 struct dcn3_dpp *dpp =
975 kzalloc_obj(struct dcn3_dpp);
976
977 if (!dpp)
978 return NULL;
979
980 if (dpp3_construct(dpp, ctx, inst,
981 &dpp_regs[inst], &tf_shift, &tf_mask))
982 return &dpp->base;
983
984 BREAK_TO_DEBUGGER();
985 kfree(dpp);
986 return NULL;
987 }
988
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)989 static struct output_pixel_processor *dcn31_opp_create(
990 struct dc_context *ctx, uint32_t inst)
991 {
992 struct dcn20_opp *opp =
993 kzalloc_obj(struct dcn20_opp);
994
995 if (!opp) {
996 BREAK_TO_DEBUGGER();
997 return NULL;
998 }
999
1000 dcn20_opp_construct(opp, ctx, inst,
1001 &opp_regs[inst], &opp_shift, &opp_mask);
1002 return &opp->base;
1003 }
1004
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)1005 static struct dce_aux *dcn31_aux_engine_create(
1006 struct dc_context *ctx,
1007 uint32_t inst)
1008 {
1009 struct aux_engine_dce110 *aux_engine =
1010 kzalloc_obj(struct aux_engine_dce110);
1011
1012 if (!aux_engine)
1013 return NULL;
1014
1015 dce110_aux_engine_construct(aux_engine, ctx, inst,
1016 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1017 &aux_engine_regs[inst],
1018 &aux_mask,
1019 &aux_shift,
1020 ctx->dc->caps.extended_aux_timeout_support);
1021
1022 return &aux_engine->base;
1023 }
1024 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1025
1026 static const struct dce_i2c_registers i2c_hw_regs[] = {
1027 i2c_inst_regs(1),
1028 i2c_inst_regs(2),
1029 i2c_inst_regs(3),
1030 i2c_inst_regs(4),
1031 i2c_inst_regs(5),
1032 };
1033
1034 static const struct dce_i2c_shift i2c_shifts = {
1035 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1036 };
1037
1038 static const struct dce_i2c_mask i2c_masks = {
1039 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1040 };
1041
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1042 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1043 struct dc_context *ctx,
1044 uint32_t inst)
1045 {
1046 struct dce_i2c_hw *dce_i2c_hw =
1047 kzalloc_obj(struct dce_i2c_hw);
1048
1049 if (!dce_i2c_hw)
1050 return NULL;
1051
1052 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1053 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1054
1055 return dce_i2c_hw;
1056 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1057 static struct mpc *dcn31_mpc_create(
1058 struct dc_context *ctx,
1059 int num_mpcc,
1060 int num_rmu)
1061 {
1062 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
1063
1064 if (!mpc30)
1065 return NULL;
1066
1067 dcn30_mpc_construct(mpc30, ctx,
1068 &mpc_regs,
1069 &mpc_shift,
1070 &mpc_mask,
1071 num_mpcc,
1072 num_rmu);
1073
1074 return &mpc30->base;
1075 }
1076
dcn316_dio_create(struct dc_context * ctx)1077 static struct dio *dcn316_dio_create(struct dc_context *ctx)
1078 {
1079 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
1080
1081 if (!dio10)
1082 return NULL;
1083
1084 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1085
1086 return &dio10->base;
1087 }
1088
dcn31_hubbub_create(struct dc_context * ctx)1089 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1090 {
1091 int i;
1092
1093 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1094
1095 if (!hubbub3)
1096 return NULL;
1097
1098 hubbub31_construct(hubbub3, ctx,
1099 &hubbub_reg,
1100 &hubbub_shift,
1101 &hubbub_mask,
1102 dcn3_16_ip.det_buffer_size_kbytes,
1103 dcn3_16_ip.pixel_chunk_size_kbytes,
1104 dcn3_16_ip.config_return_buffer_size_in_kbytes);
1105
1106
1107 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1108 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1109
1110 vmid->ctx = ctx;
1111
1112 vmid->regs = &vmid_regs[i];
1113 vmid->shifts = &vmid_shifts;
1114 vmid->masks = &vmid_masks;
1115 }
1116
1117 return &hubbub3->base;
1118 }
1119
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1120 static struct timing_generator *dcn31_timing_generator_create(
1121 struct dc_context *ctx,
1122 uint32_t instance)
1123 {
1124 struct optc *tgn10 =
1125 kzalloc_obj(struct optc);
1126
1127 if (!tgn10)
1128 return NULL;
1129
1130 tgn10->base.inst = instance;
1131 tgn10->base.ctx = ctx;
1132
1133 tgn10->tg_regs = &optc_regs[instance];
1134 tgn10->tg_shift = &optc_shift;
1135 tgn10->tg_mask = &optc_mask;
1136
1137 dcn31_timing_generator_init(tgn10);
1138
1139 return &tgn10->base;
1140 }
1141
1142 static const struct encoder_feature_support link_enc_feature = {
1143 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1144 .max_hdmi_pixel_clock = 600000,
1145 .hdmi_ycbcr420_supported = true,
1146 .dp_ycbcr420_supported = true,
1147 .fec_supported = true,
1148 .flags.bits.IS_HBR2_CAPABLE = true,
1149 .flags.bits.IS_HBR3_CAPABLE = true,
1150 .flags.bits.IS_TPS3_CAPABLE = true,
1151 .flags.bits.IS_TPS4_CAPABLE = true
1152 };
1153
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1154 static struct link_encoder *dcn31_link_encoder_create(
1155 struct dc_context *ctx,
1156 const struct encoder_init_data *enc_init_data)
1157 {
1158 (void)ctx;
1159 struct dcn20_link_encoder *enc20 =
1160 kzalloc_obj(struct dcn20_link_encoder);
1161
1162 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1163 return NULL;
1164
1165 dcn31_link_encoder_construct(enc20,
1166 enc_init_data,
1167 &link_enc_feature,
1168 &link_enc_regs[enc_init_data->transmitter],
1169 &link_enc_aux_regs[enc_init_data->channel - 1],
1170 &link_enc_hpd_regs[enc_init_data->hpd_source],
1171 &le_shift,
1172 &le_mask);
1173
1174 return &enc20->enc10.base;
1175 }
1176
1177 /* Create a minimal link encoder object not associated with a particular
1178 * physical connector.
1179 * resource_funcs.link_enc_create_minimal
1180 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1181 static struct link_encoder *dcn31_link_enc_create_minimal(
1182 struct dc_context *ctx, enum engine_id eng_id)
1183 {
1184 struct dcn20_link_encoder *enc20;
1185
1186 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc)
1187 return NULL;
1188
1189 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1190 if (!enc20)
1191 return NULL;
1192
1193 dcn31_link_encoder_construct_minimal(
1194 enc20,
1195 ctx,
1196 &link_enc_feature,
1197 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1198 &le_shift,
1199 &le_mask,
1200 eng_id);
1201
1202 return &enc20->enc10.base;
1203 }
1204
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1205 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1206 {
1207 struct dcn31_panel_cntl *panel_cntl =
1208 kzalloc_obj(struct dcn31_panel_cntl);
1209
1210 if (!panel_cntl)
1211 return NULL;
1212
1213 dcn31_panel_cntl_construct(panel_cntl, init_data);
1214
1215 return &panel_cntl->base;
1216 }
1217
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1218 static void read_dce_straps(
1219 struct dc_context *ctx,
1220 struct resource_straps *straps)
1221 {
1222 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1223 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1224
1225 }
1226
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1227 static struct audio *dcn31_create_audio(
1228 struct dc_context *ctx, unsigned int inst)
1229 {
1230 return dce_audio_create(ctx, inst,
1231 &audio_regs[inst], &audio_shift, &audio_mask);
1232 }
1233
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1234 static struct vpg *dcn31_vpg_create(
1235 struct dc_context *ctx,
1236 uint32_t inst)
1237 {
1238 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1239
1240 if (!vpg31)
1241 return NULL;
1242
1243 vpg31_construct(vpg31, ctx, inst,
1244 &vpg_regs[inst],
1245 &vpg_shift,
1246 &vpg_mask);
1247
1248 return &vpg31->base;
1249 }
1250
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1251 static struct afmt *dcn31_afmt_create(
1252 struct dc_context *ctx,
1253 uint32_t inst)
1254 {
1255 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1256
1257 if (!afmt31)
1258 return NULL;
1259
1260 afmt31_construct(afmt31, ctx, inst,
1261 &afmt_regs[inst],
1262 &afmt_shift,
1263 &afmt_mask);
1264
1265 // Light sleep by default, no need to power down here
1266
1267 return &afmt31->base;
1268 }
1269
1270
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1271 static struct apg *dcn31_apg_create(
1272 struct dc_context *ctx,
1273 uint32_t inst)
1274 {
1275 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1276
1277 if (!apg31)
1278 return NULL;
1279
1280 apg31_construct(apg31, ctx, inst,
1281 &apg_regs[inst],
1282 &apg_shift,
1283 &apg_mask);
1284
1285 return &apg31->base;
1286 }
1287
1288
dcn316_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1289 static struct stream_encoder *dcn316_stream_encoder_create(
1290 enum engine_id eng_id,
1291 struct dc_context *ctx)
1292 {
1293 struct dcn10_stream_encoder *enc1;
1294 struct vpg *vpg;
1295 struct afmt *afmt;
1296 int vpg_inst;
1297 int afmt_inst;
1298
1299 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1300 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1301 return NULL;
1302
1303 vpg_inst = eng_id;
1304 afmt_inst = eng_id;
1305
1306 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1307 vpg = dcn31_vpg_create(ctx, vpg_inst);
1308 afmt = dcn31_afmt_create(ctx, afmt_inst);
1309
1310 if (!enc1 || !vpg || !afmt) {
1311 kfree(enc1);
1312 kfree(vpg);
1313 kfree(afmt);
1314 return NULL;
1315 }
1316
1317 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1318 eng_id, vpg, afmt,
1319 &stream_enc_regs[eng_id],
1320 &se_shift, &se_mask);
1321
1322 return &enc1->base;
1323 }
1324
dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1325 static struct hpo_frl_stream_encoder *dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,
1326 struct dc_context *ctx)
1327 {
1328 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1329 struct afmt *afmt;
1330 struct vpg *vpg;
1331 int afmt_inst;
1332 int vpg_inst;
1333
1334 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1335 if (eng_id == ENGINE_ID_HPO_0) {
1336 vpg_inst = 5;
1337 afmt_inst = 5;
1338 } else {
1339 return NULL;
1340 }
1341
1342 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1343 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1344 vpg = dcn31_vpg_create(ctx, vpg_inst);
1345 afmt = dcn31_afmt_create(ctx, afmt_inst);
1346
1347 if (!hpo_enc3 || !vpg || !afmt) {
1348 kfree(hpo_enc3);
1349 kfree(vpg);
1350 kfree(afmt);
1351 return NULL;
1352 }
1353
1354 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3,
1355 ctx,
1356 ctx->dc_bios,
1357 eng_id,
1358 vpg,
1359 afmt,
1360 &hpo_frl_stream_enc_regs[eng_id - ENGINE_ID_HPO_0],
1361 &hpo_se_shift,
1362 &hpo_se_mask);
1363
1364 return &hpo_enc3->base;
1365 }
1366
dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1367 static struct hpo_frl_link_encoder *dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,
1368 struct dc_context *ctx)
1369 {
1370 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1371
1372 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1373
1374 /* allocate HPO link encoder */
1375 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1376 if (!hpo_enc3)
1377 return NULL; /* out of memory */
1378
1379 hpo_frl_link_encoder3_construct(hpo_enc3,
1380 ctx,
1381 eng_id - ENGINE_ID_HPO_0,
1382 &hpo_frl_link_enc_regs[eng_id - ENGINE_ID_HPO_0],
1383 &hpo_le_shift,
1384 &hpo_le_mask);
1385
1386 return &hpo_enc3->base;
1387 }
1388
1389
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1390 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1391 enum engine_id eng_id,
1392 struct dc_context *ctx)
1393 {
1394 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1395 struct vpg *vpg;
1396 struct apg *apg;
1397 uint32_t hpo_dp_inst;
1398 uint32_t vpg_inst;
1399 uint32_t apg_inst;
1400
1401 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1402 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1403
1404 /* Mapping of VPG register blocks to HPO DP block instance:
1405 * VPG[6] -> HPO_DP[0]
1406 * VPG[7] -> HPO_DP[1]
1407 * VPG[8] -> HPO_DP[2]
1408 * VPG[9] -> HPO_DP[3]
1409 */
1410 vpg_inst = hpo_dp_inst + 6;
1411
1412 /* Mapping of APG register blocks to HPO DP block instance:
1413 * APG[0] -> HPO_DP[0]
1414 * APG[1] -> HPO_DP[1]
1415 * APG[2] -> HPO_DP[2]
1416 * APG[3] -> HPO_DP[3]
1417 */
1418 apg_inst = hpo_dp_inst;
1419
1420 /* allocate HPO stream encoder and create VPG sub-block */
1421 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1422 vpg = dcn31_vpg_create(ctx, vpg_inst);
1423 apg = dcn31_apg_create(ctx, apg_inst);
1424
1425 if (!hpo_dp_enc31 || !vpg || !apg) {
1426 kfree(hpo_dp_enc31);
1427 kfree(vpg);
1428 kfree(apg);
1429 return NULL;
1430 }
1431
1432 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1433 hpo_dp_inst, eng_id, vpg, apg,
1434 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1435 &hpo_dp_se_shift, &hpo_dp_se_mask);
1436
1437 return &hpo_dp_enc31->base;
1438 }
1439
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1440 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1441 uint8_t inst,
1442 struct dc_context *ctx)
1443 {
1444 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1445
1446 /* allocate HPO link encoder */
1447 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1448 if (!hpo_dp_enc31)
1449 return NULL; /* out of memory */
1450
1451 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1452 &hpo_dp_link_enc_regs[inst],
1453 &hpo_dp_le_shift, &hpo_dp_le_mask);
1454
1455 return &hpo_dp_enc31->base;
1456 }
1457
1458
dcn31_hwseq_create(struct dc_context * ctx)1459 static struct dce_hwseq *dcn31_hwseq_create(
1460 struct dc_context *ctx)
1461 {
1462 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1463
1464 if (hws) {
1465 hws->ctx = ctx;
1466 hws->regs = &hwseq_reg;
1467 hws->shifts = &hwseq_shift;
1468 hws->masks = &hwseq_mask;
1469 }
1470 return hws;
1471 }
1472 static const struct resource_create_funcs res_create_funcs = {
1473 .read_dce_straps = read_dce_straps,
1474 .create_audio = dcn31_create_audio,
1475 .create_stream_encoder = dcn316_stream_encoder_create,
1476 .create_hpo_frl_stream_encoder = dcn31_hpo_frl_stream_encoder_create,
1477 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1478 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1479 .create_hwseq = dcn31_hwseq_create,
1480 };
1481
dcn316_resource_destruct(struct dcn316_resource_pool * pool)1482 static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
1483 {
1484 unsigned int i;
1485
1486 for (i = 0; i < pool->base.stream_enc_count; i++) {
1487 if (pool->base.stream_enc[i] != NULL) {
1488 if (pool->base.stream_enc[i]->vpg != NULL) {
1489 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1490 pool->base.stream_enc[i]->vpg = NULL;
1491 }
1492 if (pool->base.stream_enc[i]->afmt != NULL) {
1493 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1494 pool->base.stream_enc[i]->afmt = NULL;
1495 }
1496 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1497 pool->base.stream_enc[i] = NULL;
1498 }
1499 }
1500
1501 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1502 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1503 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1504 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1505 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1506 }
1507 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1508 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1509 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1510 }
1511 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1512 pool->base.hpo_frl_stream_enc[i] = NULL;
1513 }
1514 }
1515
1516 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1517 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1518 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1519 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1520 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1521 }
1522 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1523 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1524 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1525 }
1526 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1527 pool->base.hpo_dp_stream_enc[i] = NULL;
1528 }
1529 }
1530
1531 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1532 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1533 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1534 pool->base.hpo_dp_link_enc[i] = NULL;
1535 }
1536 }
1537
1538 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1539 if (pool->base.dscs[i] != NULL)
1540 dcn20_dsc_destroy(&pool->base.dscs[i]);
1541 }
1542
1543 if (pool->base.mpc != NULL) {
1544 kfree(TO_DCN20_MPC(pool->base.mpc));
1545 pool->base.mpc = NULL;
1546 }
1547 if (pool->base.hubbub != NULL) {
1548 kfree(pool->base.hubbub);
1549 pool->base.hubbub = NULL;
1550 }
1551 if (pool->base.dio != NULL) {
1552 kfree(TO_DCN10_DIO(pool->base.dio));
1553 pool->base.dio = NULL;
1554 }
1555 for (i = 0; i < pool->base.pipe_count; i++) {
1556 if (pool->base.dpps[i] != NULL)
1557 dcn31_dpp_destroy(&pool->base.dpps[i]);
1558
1559 if (pool->base.ipps[i] != NULL)
1560 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1561
1562 if (pool->base.hubps[i] != NULL) {
1563 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1564 pool->base.hubps[i] = NULL;
1565 }
1566
1567 if (pool->base.irqs != NULL) {
1568 dal_irq_service_destroy(&pool->base.irqs);
1569 }
1570 }
1571
1572 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1573 if (pool->base.engines[i] != NULL)
1574 dce110_engine_destroy(&pool->base.engines[i]);
1575 if (pool->base.hw_i2cs[i] != NULL) {
1576 kfree(pool->base.hw_i2cs[i]);
1577 pool->base.hw_i2cs[i] = NULL;
1578 }
1579 if (pool->base.sw_i2cs[i] != NULL) {
1580 kfree(pool->base.sw_i2cs[i]);
1581 pool->base.sw_i2cs[i] = NULL;
1582 }
1583 }
1584
1585 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1586 if (pool->base.opps[i] != NULL)
1587 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1588 }
1589
1590 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1591 if (pool->base.timing_generators[i] != NULL) {
1592 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1593 pool->base.timing_generators[i] = NULL;
1594 }
1595 }
1596
1597 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1598 if (pool->base.dwbc[i] != NULL) {
1599 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1600 pool->base.dwbc[i] = NULL;
1601 }
1602 if (pool->base.mcif_wb[i] != NULL) {
1603 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1604 pool->base.mcif_wb[i] = NULL;
1605 }
1606 }
1607
1608 for (i = 0; i < pool->base.audio_count; i++) {
1609 if (pool->base.audios[i])
1610 dce_aud_destroy(&pool->base.audios[i]);
1611 }
1612
1613 for (i = 0; i < pool->base.clk_src_count; i++) {
1614 if (pool->base.clock_sources[i] != NULL) {
1615 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1616 pool->base.clock_sources[i] = NULL;
1617 }
1618 }
1619
1620 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1621 if (pool->base.mpc_lut[i] != NULL) {
1622 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1623 pool->base.mpc_lut[i] = NULL;
1624 }
1625 if (pool->base.mpc_shaper[i] != NULL) {
1626 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1627 pool->base.mpc_shaper[i] = NULL;
1628 }
1629 }
1630
1631 if (pool->base.dp_clock_source != NULL) {
1632 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1633 pool->base.dp_clock_source = NULL;
1634 }
1635
1636 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1637 if (pool->base.multiple_abms[i] != NULL)
1638 dce_abm_destroy(&pool->base.multiple_abms[i]);
1639 }
1640
1641 if (pool->base.psr != NULL)
1642 dmub_psr_destroy(&pool->base.psr);
1643
1644 if (pool->base.dccg != NULL)
1645 dcn_dccg_destroy(&pool->base.dccg);
1646 }
1647
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1648 static struct hubp *dcn31_hubp_create(
1649 struct dc_context *ctx,
1650 uint32_t inst)
1651 {
1652 struct dcn20_hubp *hubp2 =
1653 kzalloc_obj(struct dcn20_hubp);
1654
1655 if (!hubp2)
1656 return NULL;
1657
1658 if (hubp31_construct(hubp2, ctx, inst,
1659 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1660 return &hubp2->base;
1661
1662 BREAK_TO_DEBUGGER();
1663 kfree(hubp2);
1664 return NULL;
1665 }
1666
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1667 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1668 {
1669 unsigned int i;
1670 uint32_t pipe_count = pool->res_cap->num_dwb;
1671
1672 for (i = 0; i < pipe_count; i++) {
1673 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1674
1675 if (!dwbc30) {
1676 dm_error("DC: failed to create dwbc30!\n");
1677 return false;
1678 }
1679
1680 dcn30_dwbc_construct(dwbc30, ctx,
1681 &dwbc30_regs[i],
1682 &dwbc30_shift,
1683 &dwbc30_mask,
1684 i);
1685
1686 pool->dwbc[i] = &dwbc30->base;
1687 }
1688 return true;
1689 }
1690
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1691 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1692 {
1693 unsigned int i;
1694 uint32_t pipe_count = pool->res_cap->num_dwb;
1695
1696 for (i = 0; i < pipe_count; i++) {
1697 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1698
1699 if (!mcif_wb30) {
1700 dm_error("DC: failed to create mcif_wb30!\n");
1701 return false;
1702 }
1703
1704 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1705 &mcif_wb30_regs[i],
1706 &mcif_wb30_shift,
1707 &mcif_wb30_mask,
1708 i);
1709
1710 pool->mcif_wb[i] = &mcif_wb30->base;
1711 }
1712 return true;
1713 }
1714
dcn31_dsc_create(struct dc_context * ctx,uint32_t inst)1715 static struct display_stream_compressor *dcn31_dsc_create(
1716 struct dc_context *ctx, uint32_t inst)
1717 {
1718 struct dcn20_dsc *dsc =
1719 kzalloc_obj(struct dcn20_dsc);
1720
1721 if (!dsc) {
1722 BREAK_TO_DEBUGGER();
1723 return NULL;
1724 }
1725
1726 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1727 return &dsc->base;
1728 }
1729
dcn316_destroy_resource_pool(struct resource_pool ** pool)1730 static void dcn316_destroy_resource_pool(struct resource_pool **pool)
1731 {
1732 struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool);
1733
1734 dcn316_resource_destruct(dcn31_pool);
1735 kfree(dcn31_pool);
1736 *pool = NULL;
1737 }
1738
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1739 static struct clock_source *dcn31_clock_source_create(
1740 struct dc_context *ctx,
1741 struct dc_bios *bios,
1742 enum clock_source_id id,
1743 const struct dce110_clk_src_regs *regs,
1744 bool dp_clk_src)
1745 {
1746 struct dce110_clk_src *clk_src =
1747 kzalloc_obj(struct dce110_clk_src);
1748
1749 if (!clk_src)
1750 return NULL;
1751
1752 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1753 regs, &cs_shift, &cs_mask)) {
1754 clk_src->base.dp_clk_src = dp_clk_src;
1755 return &clk_src->base;
1756 }
1757
1758 kfree(clk_src);
1759
1760 BREAK_TO_DEBUGGER();
1761 return NULL;
1762 }
1763
is_dual_plane(enum surface_pixel_format format)1764 static bool is_dual_plane(enum surface_pixel_format format)
1765 {
1766 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1767 }
1768
dcn316_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1769 static int dcn316_populate_dml_pipes_from_context(
1770 struct dc *dc, struct dc_state *context,
1771 display_e2e_pipe_params_st *pipes,
1772 enum dc_validate_mode validate_mode)
1773 {
1774 unsigned int i;
1775 int pipe_cnt;
1776 struct resource_context *res_ctx = &context->res_ctx;
1777 struct pipe_ctx *pipe = 0;
1778 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
1779
1780 DC_FP_START();
1781 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1782 DC_FP_END();
1783
1784 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1785 struct dc_crtc_timing *timing;
1786
1787 if (!res_ctx->pipe_ctx[i].stream)
1788 continue;
1789 pipe = &res_ctx->pipe_ctx[i];
1790 timing = &pipe->stream->timing;
1791
1792 /*
1793 * Immediate flip can be set dynamically after enabling the plane.
1794 * We need to require support for immediate flip or underflow can be
1795 * intermittently experienced depending on peak b/w requirements.
1796 */
1797 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1798
1799 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1800 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1801 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1802 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1803 DC_FP_START();
1804 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1805 DC_FP_END();
1806
1807 if (pipes[pipe_cnt].dout.dsc_enable) {
1808 switch (timing->display_color_depth) {
1809 case COLOR_DEPTH_888:
1810 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1811 break;
1812 case COLOR_DEPTH_101010:
1813 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1814 break;
1815 case COLOR_DEPTH_121212:
1816 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1817 break;
1818 default:
1819 ASSERT(0);
1820 break;
1821 }
1822 }
1823
1824 pipe_cnt++;
1825 }
1826
1827 if (pipe_cnt)
1828 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1829 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1830 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE)
1831 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE;
1832 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE);
1833 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1834 if (is_dual_plane(pipe->plane_state->format)
1835 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1836 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1837 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1838 } else if (!is_dual_plane(pipe->plane_state->format)) {
1839 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1840 pipes[0].pipe.src.unbounded_req_mode = true;
1841 }
1842 }
1843
1844 return pipe_cnt;
1845 }
1846
dcn316_get_panel_config_defaults(struct dc_panel_config * panel_config)1847 static void dcn316_get_panel_config_defaults(struct dc_panel_config *panel_config)
1848 {
1849 *panel_config = panel_config_defaults;
1850 }
1851
1852 static struct dc_cap_funcs cap_funcs = {
1853 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1854 };
1855
dcn316_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1856 static void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1857 {
1858 DC_FP_START();
1859 dcn316_update_bw_bounding_box_fpu(dc, bw_params);
1860 DC_FP_END();
1861 }
1862
1863 static struct resource_funcs dcn316_res_pool_funcs = {
1864 .destroy = dcn316_destroy_resource_pool,
1865 .link_enc_create = dcn31_link_encoder_create,
1866 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1867 .link_encs_assign = link_enc_cfg_link_encs_assign,
1868 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1869 .hpo_frl_link_enc_create = dcn31_hpo_frl_link_encoder_create,
1870 .panel_cntl_create = dcn31_panel_cntl_create,
1871 .validate_bandwidth = dcn31_validate_bandwidth,
1872 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1873 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1874 .populate_dml_pipes = dcn316_populate_dml_pipes_from_context,
1875 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1876 .release_pipe = dcn20_release_pipe,
1877 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1878 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1879 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1880 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1881 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1882 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1883 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1884 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1885 .update_bw_bounding_box = dcn316_update_bw_bounding_box,
1886 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1887 .get_panel_config_defaults = dcn316_get_panel_config_defaults,
1888 .get_det_buffer_size = dcn31_get_det_buffer_size,
1889 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1890 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1891 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
1892 .get_default_tiling_info = dcn10_get_default_tiling_info
1893 };
1894
dcn316_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn316_resource_pool * pool)1895 static bool dcn316_resource_construct(
1896 uint8_t num_virtual_links,
1897 struct dc *dc,
1898 struct dcn316_resource_pool *pool)
1899 {
1900 int i;
1901 struct dc_context *ctx = dc->ctx;
1902 struct irq_service_init_data init_data;
1903
1904 ctx->dc_bios->regs = &bios_regs;
1905
1906 pool->base.res_cap = &res_cap_dcn31;
1907
1908 pool->base.funcs = &dcn316_res_pool_funcs;
1909
1910 /*************************************************
1911 * Resource + asic cap harcoding *
1912 *************************************************/
1913 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1914 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1915 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1916
1917 /* Enable 4to1MPC by default */
1918 dc->config.allow_4to1MPC = true;
1919
1920 dc->caps.max_downscale_ratio = 600;
1921 dc->caps.i2c_speed_in_khz = 100;
1922 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1923 dc->caps.max_cursor_size = 256;
1924 dc->caps.min_horizontal_blanking_period = 80;
1925 dc->caps.dmdata_alloc_size = 2048;
1926 dc->caps.max_slave_planes = 2;
1927 dc->caps.max_slave_yuv_planes = 2;
1928 dc->caps.max_slave_rgb_planes = 2;
1929 dc->caps.post_blend_color_processing = true;
1930 dc->caps.force_dp_tps4_for_cp2520 = true;
1931 if (dc->config.forceHBR2CP2520)
1932 dc->caps.force_dp_tps4_for_cp2520 = false;
1933 dc->caps.hdmi_hpo = true;
1934 dc->caps.dp_hpo = true;
1935 dc->caps.dp_hdmi21_pcon_support = true;
1936 dc->caps.edp_dsc_support = true;
1937 dc->caps.extended_aux_timeout_support = true;
1938 dc->caps.dmcub_support = true;
1939 dc->caps.is_apu = true;
1940
1941 /* Color pipeline capabilities */
1942 dc->caps.color.dpp.dcn_arch = 1;
1943 dc->caps.color.dpp.input_lut_shared = 0;
1944 dc->caps.color.dpp.icsc = 1;
1945 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1946 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1947 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1948 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1949 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1950 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1951 dc->caps.color.dpp.post_csc = 1;
1952 dc->caps.color.dpp.gamma_corr = 1;
1953 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1954
1955 dc->caps.color.dpp.hw_3d_lut = 1;
1956 dc->caps.color.dpp.ogam_ram = 1;
1957 // no OGAM ROM on DCN301
1958 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1959 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1960 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1961 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1962 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1963 dc->caps.color.dpp.ocsc = 0;
1964
1965 dc->caps.color.mpc.gamut_remap = 1;
1966 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
1967 dc->caps.color.mpc.ogam_ram = 1;
1968 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1969 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1970 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1971 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1972 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1973 dc->caps.color.mpc.ocsc = 1;
1974 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
1975
1976 /* read VBIOS LTTPR caps */
1977 {
1978 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1979 enum bp_result bp_query_result;
1980 uint8_t is_vbios_lttpr_enable = 0;
1981
1982 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1983 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1984 }
1985
1986 /* interop bit is implicit */
1987 {
1988 dc->caps.vbios_lttpr_aware = true;
1989 }
1990 }
1991 dc->check_config = config_defaults;
1992
1993 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1994 dc->debug = debug_defaults_drv;
1995
1996 // Init the vm_helper
1997 if (dc->vm_helper)
1998 vm_helper_init(dc->vm_helper, 16);
1999
2000 /*************************************************
2001 * Create resources *
2002 *************************************************/
2003
2004 /* Clock Sources for Pixel Clock*/
2005 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2006 dcn31_clock_source_create(ctx, ctx->dc_bios,
2007 CLOCK_SOURCE_COMBO_PHY_PLL0,
2008 &clk_src_regs[0], false);
2009 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2010 dcn31_clock_source_create(ctx, ctx->dc_bios,
2011 CLOCK_SOURCE_COMBO_PHY_PLL1,
2012 &clk_src_regs[1], false);
2013 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2014 dcn31_clock_source_create(ctx, ctx->dc_bios,
2015 CLOCK_SOURCE_COMBO_PHY_PLL2,
2016 &clk_src_regs[2], false);
2017 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2018 dcn31_clock_source_create(ctx, ctx->dc_bios,
2019 CLOCK_SOURCE_COMBO_PHY_PLL3,
2020 &clk_src_regs[3], false);
2021 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2022 dcn31_clock_source_create(ctx, ctx->dc_bios,
2023 CLOCK_SOURCE_COMBO_PHY_PLL4,
2024 &clk_src_regs[4], false);
2025
2026 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2027
2028 /* todo: not reuse phy_pll registers */
2029 pool->base.dp_clock_source =
2030 dcn31_clock_source_create(ctx, ctx->dc_bios,
2031 CLOCK_SOURCE_ID_DP_DTO,
2032 &clk_src_regs[0], true);
2033
2034 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2035 if (pool->base.clock_sources[i] == NULL) {
2036 dm_error("DC: failed to create clock sources!\n");
2037 BREAK_TO_DEBUGGER();
2038 goto create_fail;
2039 }
2040 }
2041
2042 /* TODO: DCCG */
2043 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2044 if (pool->base.dccg == NULL) {
2045 dm_error("DC: failed to create dccg!\n");
2046 BREAK_TO_DEBUGGER();
2047 goto create_fail;
2048 }
2049
2050 /* TODO: IRQ */
2051 init_data.ctx = dc->ctx;
2052 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2053 if (!pool->base.irqs)
2054 goto create_fail;
2055
2056 /* HUBBUB */
2057 pool->base.hubbub = dcn31_hubbub_create(ctx);
2058 if (pool->base.hubbub == NULL) {
2059 BREAK_TO_DEBUGGER();
2060 dm_error("DC: failed to create hubbub!\n");
2061 goto create_fail;
2062 }
2063
2064 /* DIO */
2065 pool->base.dio = dcn316_dio_create(ctx);
2066 if (pool->base.dio == NULL) {
2067 BREAK_TO_DEBUGGER();
2068 dm_error("DC: failed to create dio!\n");
2069 goto create_fail;
2070 }
2071
2072 /* HUBPs, DPPs, OPPs and TGs */
2073 for (i = 0; i < (int)pool->base.pipe_count; i++) {
2074 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2075 if (pool->base.hubps[i] == NULL) {
2076 BREAK_TO_DEBUGGER();
2077 dm_error(
2078 "DC: failed to create hubps!\n");
2079 goto create_fail;
2080 }
2081
2082 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2083 if (pool->base.dpps[i] == NULL) {
2084 BREAK_TO_DEBUGGER();
2085 dm_error(
2086 "DC: failed to create dpps!\n");
2087 goto create_fail;
2088 }
2089 }
2090
2091 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2092 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2093 if (pool->base.opps[i] == NULL) {
2094 BREAK_TO_DEBUGGER();
2095 dm_error(
2096 "DC: failed to create output pixel processor!\n");
2097 goto create_fail;
2098 }
2099 }
2100
2101 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2102 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2103 ctx, i);
2104 if (pool->base.timing_generators[i] == NULL) {
2105 BREAK_TO_DEBUGGER();
2106 dm_error("DC: failed to create tg!\n");
2107 goto create_fail;
2108 }
2109 }
2110 pool->base.timing_generator_count = i;
2111
2112 /* PSR */
2113 pool->base.psr = dmub_psr_create(ctx);
2114 if (pool->base.psr == NULL) {
2115 dm_error("DC: failed to create psr obj!\n");
2116 BREAK_TO_DEBUGGER();
2117 goto create_fail;
2118 }
2119
2120 /* ABM */
2121 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2122 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2123 &abm_regs[i],
2124 &abm_shift,
2125 &abm_mask);
2126 if (pool->base.multiple_abms[i] == NULL) {
2127 dm_error("DC: failed to create abm for pipe %d!\n", i);
2128 BREAK_TO_DEBUGGER();
2129 goto create_fail;
2130 }
2131 }
2132
2133 /* MPC and DSC */
2134 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2135 if (pool->base.mpc == NULL) {
2136 BREAK_TO_DEBUGGER();
2137 dm_error("DC: failed to create mpc!\n");
2138 goto create_fail;
2139 }
2140
2141 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2142 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2143 if (pool->base.dscs[i] == NULL) {
2144 BREAK_TO_DEBUGGER();
2145 dm_error("DC: failed to create display stream compressor %d!\n", i);
2146 goto create_fail;
2147 }
2148 }
2149
2150 /* DWB and MMHUBBUB */
2151 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2152 BREAK_TO_DEBUGGER();
2153 dm_error("DC: failed to create dwbc!\n");
2154 goto create_fail;
2155 }
2156
2157 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2158 BREAK_TO_DEBUGGER();
2159 dm_error("DC: failed to create mcif_wb!\n");
2160 goto create_fail;
2161 }
2162
2163 /* AUX and I2C */
2164 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2165 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2166 if (pool->base.engines[i] == NULL) {
2167 BREAK_TO_DEBUGGER();
2168 dm_error(
2169 "DC:failed to create aux engine!!\n");
2170 goto create_fail;
2171 }
2172 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2173 if (pool->base.hw_i2cs[i] == NULL) {
2174 BREAK_TO_DEBUGGER();
2175 dm_error(
2176 "DC:failed to create hw i2c!!\n");
2177 goto create_fail;
2178 }
2179 pool->base.sw_i2cs[i] = NULL;
2180 }
2181
2182 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2183 if (!resource_construct(num_virtual_links, dc, &pool->base,
2184 &res_create_funcs))
2185 goto create_fail;
2186
2187 /* HW Sequencer and Plane caps */
2188 dcn31_hw_sequencer_construct(dc);
2189
2190 dc->caps.max_planes = pool->base.pipe_count;
2191
2192 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2193 dc->caps.planes[i] = plane_cap;
2194
2195 dc->caps.max_odm_combine_factor = 4;
2196
2197 dc->cap_funcs = cap_funcs;
2198
2199 dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp;
2200
2201 return true;
2202
2203 create_fail:
2204
2205 dcn316_resource_destruct(pool);
2206
2207 return false;
2208 }
2209
dcn316_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2210 struct resource_pool *dcn316_create_resource_pool(
2211 const struct dc_init_data *init_data,
2212 struct dc *dc)
2213 {
2214 struct dcn316_resource_pool *pool =
2215 kzalloc_obj(struct dcn316_resource_pool);
2216
2217 if (!pool)
2218 return NULL;
2219
2220 if (dcn316_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2221 return &pool->base;
2222
2223 BREAK_TO_DEBUGGER();
2224 kfree(pool);
2225 return NULL;
2226 }
2227