1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce_ipp.h" 27 #include "reg_helper.h" 28 #include "dm_services.h" 29 30 #define REG(reg) \ 31 (ipp_dce->regs->reg) 32 33 #undef FN 34 #define FN(reg_name, field_name) \ 35 ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name 36 37 #define CTX \ 38 ipp_dce->base.ctx 39 40 41 static void dce_ipp_cursor_set_position( 42 struct input_pixel_processor *ipp, 43 const struct dc_cursor_position *position, 44 const struct dc_cursor_mi_param *param) 45 { 46 (void)param; 47 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 48 49 /* lock cursor registers */ 50 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); 51 52 /* Flag passed in structure differentiates cursor enable/disable. */ 53 /* Update if it differs from cached state. */ 54 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); 55 56 REG_SET_2(CUR_POSITION, 0, 57 CURSOR_X_POSITION, position->x, 58 CURSOR_Y_POSITION, position->y); 59 60 REG_SET_2(CUR_HOT_SPOT, 0, 61 CURSOR_HOT_SPOT_X, position->x_hotspot, 62 CURSOR_HOT_SPOT_Y, position->y_hotspot); 63 64 /* unlock cursor registers */ 65 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); 66 } 67 68 static void dce_ipp_cursor_set_attributes( 69 struct input_pixel_processor *ipp, 70 const struct dc_cursor_attributes *attributes) 71 { 72 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 73 int mode; 74 75 /* Lock cursor registers */ 76 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); 77 78 /* Program cursor control */ 79 switch (attributes->color_format) { 80 case CURSOR_MODE_MONO: 81 mode = 0; 82 break; 83 case CURSOR_MODE_COLOR_1BIT_AND: 84 mode = 1; 85 break; 86 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 87 mode = 2; 88 break; 89 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 90 mode = 3; 91 break; 92 default: 93 BREAK_TO_DEBUGGER(); /* unsupported */ 94 mode = 0; 95 } 96 97 REG_UPDATE_3(CUR_CONTROL, 98 CURSOR_MODE, mode, 99 CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, 100 CUR_INV_TRANS_CLAMP, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); 101 102 if (attributes->color_format == CURSOR_MODE_MONO) { 103 REG_SET_3(CUR_COLOR1, 0, 104 CUR_COLOR1_BLUE, 0, 105 CUR_COLOR1_GREEN, 0, 106 CUR_COLOR1_RED, 0); 107 108 REG_SET_3(CUR_COLOR2, 0, 109 CUR_COLOR2_BLUE, 0xff, 110 CUR_COLOR2_GREEN, 0xff, 111 CUR_COLOR2_RED, 0xff); 112 } 113 114 /* 115 * Program cursor size -- NOTE: HW spec specifies that HW register 116 * stores size as (height - 1, width - 1) 117 */ 118 REG_SET_2(CUR_SIZE, 0, 119 CURSOR_WIDTH, attributes->width-1, 120 CURSOR_HEIGHT, attributes->height-1); 121 122 /* Program cursor surface address */ 123 /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor 124 * surface base address in byte. It is 4K byte aligned. 125 * The correct way to program cursor surface address is to first write 126 * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS 127 */ 128 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, 129 CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part); 130 131 REG_SET(CUR_SURFACE_ADDRESS, 0, 132 CURSOR_SURFACE_ADDRESS, attributes->address.low_part); 133 134 /* Unlock Cursor registers. */ 135 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); 136 } 137 138 139 static void dce_ipp_program_prescale(struct input_pixel_processor *ipp, 140 struct ipp_prescale_params *params) 141 { 142 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 143 144 /* set to bypass mode first before change */ 145 REG_UPDATE(PRESCALE_GRPH_CONTROL, 146 GRPH_PRESCALE_BYPASS, 1); 147 148 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, 149 GRPH_PRESCALE_SCALE_R, params->scale, 150 GRPH_PRESCALE_BIAS_R, params->bias); 151 152 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, 153 GRPH_PRESCALE_SCALE_G, params->scale, 154 GRPH_PRESCALE_BIAS_G, params->bias); 155 156 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, 157 GRPH_PRESCALE_SCALE_B, params->scale, 158 GRPH_PRESCALE_BIAS_B, params->bias); 159 160 if (params->mode != IPP_PRESCALE_MODE_BYPASS) { 161 REG_UPDATE(PRESCALE_GRPH_CONTROL, 162 GRPH_PRESCALE_BYPASS, 0); 163 164 /* If prescale is in use, then legacy lut should be bypassed */ 165 REG_UPDATE(INPUT_GAMMA_CONTROL, 166 GRPH_INPUT_GAMMA_MODE, 1); 167 } 168 } 169 170 static void dce_ipp_program_input_lut( 171 struct input_pixel_processor *ipp, 172 const struct dc_gamma *gamma) 173 { 174 int i; 175 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 176 177 /* power on LUT memory */ 178 if (REG(DCFE_MEM_PWR_CTRL)) 179 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); 180 181 /* enable all */ 182 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); 183 184 /* 256 entry mode */ 185 REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); 186 187 /* LUT-256, unsigned, integer, new u0.12 format */ 188 REG_SET_3(DC_LUT_CONTROL, 0, 189 DC_LUT_DATA_R_FORMAT, 3, 190 DC_LUT_DATA_G_FORMAT, 3, 191 DC_LUT_DATA_B_FORMAT, 3); 192 193 /* start from index 0 */ 194 REG_SET(DC_LUT_RW_INDEX, 0, 195 DC_LUT_RW_INDEX, 0); 196 197 for (i = 0; i < gamma->num_entries; i++) { 198 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, 199 dc_fixpt_round( 200 gamma->entries.red[i])); 201 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, 202 dc_fixpt_round( 203 gamma->entries.green[i])); 204 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, 205 dc_fixpt_round( 206 gamma->entries.blue[i])); 207 } 208 209 /* power off LUT memory */ 210 if (REG(DCFE_MEM_PWR_CTRL)) 211 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); 212 213 /* bypass prescale, enable legacy LUT */ 214 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 215 REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 216 } 217 218 static void dce_ipp_set_degamma( 219 struct input_pixel_processor *ipp, 220 enum ipp_degamma_mode mode) 221 { 222 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 223 uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; 224 225 ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB); 226 227 REG_SET_3(DEGAMMA_CONTROL, 0, 228 GRPH_DEGAMMA_MODE, degamma_type, 229 CURSOR_DEGAMMA_MODE, degamma_type, 230 CURSOR2_DEGAMMA_MODE, degamma_type); 231 } 232 233 #if defined(CONFIG_DRM_AMD_DC_SI) 234 static void dce60_ipp_set_degamma( 235 struct input_pixel_processor *ipp, 236 enum ipp_degamma_mode mode) 237 { 238 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 239 uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; 240 241 ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB); 242 /* DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL reg */ 243 REG_SET_2(DEGAMMA_CONTROL, 0, 244 GRPH_DEGAMMA_MODE, degamma_type, 245 CURSOR_DEGAMMA_MODE, degamma_type); 246 } 247 #endif 248 249 static const struct ipp_funcs dce_ipp_funcs = { 250 .ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes, 251 .ipp_cursor_set_position = dce_ipp_cursor_set_position, 252 .ipp_program_prescale = dce_ipp_program_prescale, 253 .ipp_program_input_lut = dce_ipp_program_input_lut, 254 .ipp_set_degamma = dce_ipp_set_degamma 255 }; 256 257 #if defined(CONFIG_DRM_AMD_DC_SI) 258 static const struct ipp_funcs dce60_ipp_funcs = { 259 .ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes, 260 .ipp_cursor_set_position = dce_ipp_cursor_set_position, 261 .ipp_program_prescale = dce_ipp_program_prescale, 262 .ipp_program_input_lut = dce_ipp_program_input_lut, 263 .ipp_set_degamma = dce60_ipp_set_degamma 264 }; 265 #endif 266 267 268 /*****************************************/ 269 /* Constructor, Destructor */ 270 /*****************************************/ 271 272 void dce_ipp_construct( 273 struct dce_ipp *ipp_dce, 274 struct dc_context *ctx, 275 int inst, 276 const struct dce_ipp_registers *regs, 277 const struct dce_ipp_shift *ipp_shift, 278 const struct dce_ipp_mask *ipp_mask) 279 { 280 ipp_dce->base.ctx = ctx; 281 ipp_dce->base.inst = inst; 282 ipp_dce->base.funcs = &dce_ipp_funcs; 283 284 ipp_dce->regs = regs; 285 ipp_dce->ipp_shift = ipp_shift; 286 ipp_dce->ipp_mask = ipp_mask; 287 } 288 289 #if defined(CONFIG_DRM_AMD_DC_SI) 290 void dce60_ipp_construct( 291 struct dce_ipp *ipp_dce, 292 struct dc_context *ctx, 293 int inst, 294 const struct dce_ipp_registers *regs, 295 const struct dce_ipp_shift *ipp_shift, 296 const struct dce_ipp_mask *ipp_mask) 297 { 298 ipp_dce->base.ctx = ctx; 299 ipp_dce->base.inst = inst; 300 ipp_dce->base.funcs = &dce60_ipp_funcs; 301 302 ipp_dce->regs = regs; 303 ipp_dce->ipp_shift = ipp_shift; 304 ipp_dce->ipp_mask = ipp_mask; 305 } 306 #endif 307 308 void dce_ipp_destroy(struct input_pixel_processor **ipp) 309 { 310 kfree(TO_DCE_IPP(*ipp)); 311 *ipp = NULL; 312 } 313