xref: /linux/arch/mips/kernel/traps.c (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7  * Copyright (C) 1995, 1996 Paul M. Antoine
8  * Copyright (C) 1998 Ulf Carlsson
9  * Copyright (C) 1999 Silicon Graphics, Inc.
10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11  * Copyright (C) 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
12  * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc.  All rights reserved.
13  * Copyright (C) 2014, Imagination Technologies Ltd.
14  */
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/extable.h>
25 #include <linux/mm.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/debug.h>
28 #include <linux/smp.h>
29 #include <linux/spinlock.h>
30 #include <linux/kallsyms.h>
31 #include <linux/memblock.h>
32 #include <linux/interrupt.h>
33 #include <linux/ptrace.h>
34 #include <linux/kgdb.h>
35 #include <linux/kdebug.h>
36 #include <linux/kprobes.h>
37 #include <linux/notifier.h>
38 #include <linux/kdb.h>
39 #include <linux/irq.h>
40 #include <linux/perf_event.h>
41 
42 #include <asm/addrspace.h>
43 #include <asm/bootinfo.h>
44 #include <asm/branch.h>
45 #include <asm/break.h>
46 #include <asm/cop2.h>
47 #include <asm/cpu.h>
48 #include <asm/cpu-type.h>
49 #include <asm/dsp.h>
50 #include <asm/fpu.h>
51 #include <asm/fpu_emulator.h>
52 #include <asm/idle.h>
53 #include <asm/isa-rev.h>
54 #include <asm/mips-cps.h>
55 #include <asm/mips-r2-to-r6-emul.h>
56 #include <asm/mipsregs.h>
57 #include <asm/mipsmtregs.h>
58 #include <asm/module.h>
59 #include <asm/msa.h>
60 #include <asm/ptrace.h>
61 #include <asm/regdef.h>
62 #include <asm/sections.h>
63 #include <asm/siginfo.h>
64 #include <asm/tlbdebug.h>
65 #include <asm/traps.h>
66 #include <linux/uaccess.h>
67 #include <asm/watch.h>
68 #include <asm/mmu_context.h>
69 #include <asm/types.h>
70 #include <asm/stacktrace.h>
71 #include <asm/tlbex.h>
72 #include <asm/uasm.h>
73 
74 #include <asm/mach-loongson64/cpucfg-emul.h>
75 
76 #include "access-helper.h"
77 
78 extern void check_wait(void);
79 extern asmlinkage void rollback_handle_int(void);
80 extern asmlinkage void handle_int(void);
81 extern asmlinkage void handle_adel(void);
82 extern asmlinkage void handle_ades(void);
83 extern asmlinkage void handle_ibe(void);
84 extern asmlinkage void handle_dbe(void);
85 extern asmlinkage void handle_sys(void);
86 extern asmlinkage void handle_bp(void);
87 extern asmlinkage void handle_ri(void);
88 extern asmlinkage void handle_ri_rdhwr_tlbp(void);
89 extern asmlinkage void handle_ri_rdhwr(void);
90 extern asmlinkage void handle_cpu(void);
91 extern asmlinkage void handle_ov(void);
92 extern asmlinkage void handle_tr(void);
93 extern asmlinkage void handle_msa_fpe(void);
94 extern asmlinkage void handle_fpe(void);
95 extern asmlinkage void handle_ftlb(void);
96 extern asmlinkage void handle_gsexc(void);
97 extern asmlinkage void handle_msa(void);
98 extern asmlinkage void handle_mdmx(void);
99 extern asmlinkage void handle_watch(void);
100 extern asmlinkage void handle_mt(void);
101 extern asmlinkage void handle_dsp(void);
102 extern asmlinkage void handle_mcheck(void);
103 extern asmlinkage void handle_reserved(void);
104 extern void tlb_do_page_fault_0(void);
105 
106 void (*board_be_init)(void);
107 static int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
108 void (*board_nmi_handler_setup)(void);
109 void (*board_ejtag_handler_setup)(void);
110 void (*board_bind_eic_interrupt)(int irq, int regset);
111 void (*board_ebase_setup)(void);
112 void(*board_cache_error_setup)(void);
113 
mips_set_be_handler(int (* handler)(struct pt_regs * regs,int is_fixup))114 void mips_set_be_handler(int (*handler)(struct pt_regs *regs, int is_fixup))
115 {
116 	board_be_handler = handler;
117 }
118 EXPORT_SYMBOL_GPL(mips_set_be_handler);
119 
show_raw_backtrace(unsigned long reg29,const char * loglvl,bool user)120 static void show_raw_backtrace(unsigned long reg29, const char *loglvl,
121 			       bool user)
122 {
123 	unsigned long *sp = (unsigned long *)(reg29 & ~3);
124 	unsigned long addr;
125 
126 	printk("%sCall Trace:", loglvl);
127 #ifdef CONFIG_KALLSYMS
128 	printk("%s\n", loglvl);
129 #endif
130 	while (!kstack_end(sp)) {
131 		if (__get_addr(&addr, sp++, user)) {
132 			printk("%s (Bad stack address)", loglvl);
133 			break;
134 		}
135 		if (__kernel_text_address(addr))
136 			print_ip_sym(loglvl, addr);
137 	}
138 	printk("%s\n", loglvl);
139 }
140 
141 #ifdef CONFIG_KALLSYMS
142 int raw_show_trace;
set_raw_show_trace(char * str)143 static int __init set_raw_show_trace(char *str)
144 {
145 	raw_show_trace = 1;
146 	return 1;
147 }
148 __setup("raw_show_trace", set_raw_show_trace);
149 #endif
150 
show_backtrace(struct task_struct * task,const struct pt_regs * regs,const char * loglvl,bool user)151 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
152 			   const char *loglvl, bool user)
153 {
154 	unsigned long sp = regs->regs[29];
155 	unsigned long ra = regs->regs[31];
156 	unsigned long pc = regs->cp0_epc;
157 
158 	if (!task)
159 		task = current;
160 
161 	if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
162 		show_raw_backtrace(sp, loglvl, user);
163 		return;
164 	}
165 	printk("%sCall Trace:\n", loglvl);
166 	do {
167 		print_ip_sym(loglvl, pc);
168 		pc = unwind_stack(task, &sp, pc, &ra);
169 	} while (pc);
170 	pr_cont("\n");
171 }
172 
173 /*
174  * This routine abuses get_user()/put_user() to reference pointers
175  * with at least a bit of error checking ...
176  */
show_stacktrace(struct task_struct * task,const struct pt_regs * regs,const char * loglvl,bool user)177 static void show_stacktrace(struct task_struct *task,
178 	const struct pt_regs *regs, const char *loglvl, bool user)
179 {
180 	const int field = 2 * sizeof(unsigned long);
181 	unsigned long stackdata;
182 	int i;
183 	unsigned long *sp = (unsigned long *)regs->regs[29];
184 
185 	printk("%sStack :", loglvl);
186 	i = 0;
187 	while ((unsigned long) sp & (PAGE_SIZE - 1)) {
188 		if (i && ((i % (64 / field)) == 0)) {
189 			pr_cont("\n");
190 			printk("%s       ", loglvl);
191 		}
192 		if (i > 39) {
193 			pr_cont(" ...");
194 			break;
195 		}
196 
197 		if (__get_addr(&stackdata, sp++, user)) {
198 			pr_cont(" (Bad stack address)");
199 			break;
200 		}
201 
202 		pr_cont(" %0*lx", field, stackdata);
203 		i++;
204 	}
205 	pr_cont("\n");
206 	show_backtrace(task, regs, loglvl, user);
207 }
208 
show_stack(struct task_struct * task,unsigned long * sp,const char * loglvl)209 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
210 {
211 	struct pt_regs regs;
212 
213 	regs.cp0_status = KSU_KERNEL;
214 	if (sp) {
215 		regs.regs[29] = (unsigned long)sp;
216 		regs.regs[31] = 0;
217 		regs.cp0_epc = 0;
218 	} else {
219 		if (task && task != current) {
220 			regs.regs[29] = task->thread.reg29;
221 			regs.regs[31] = 0;
222 			regs.cp0_epc = task->thread.reg31;
223 		} else {
224 			prepare_frametrace(&regs);
225 		}
226 	}
227 	show_stacktrace(task, &regs, loglvl, false);
228 }
229 
show_code(void * pc,bool user)230 static void show_code(void *pc, bool user)
231 {
232 	long i;
233 	unsigned short *pc16 = NULL;
234 
235 	printk("Code:");
236 
237 	if ((unsigned long)pc & 1)
238 		pc16 = (u16 *)((unsigned long)pc & ~1);
239 
240 	for(i = -3 ; i < 6 ; i++) {
241 		if (pc16) {
242 			u16 insn16;
243 
244 			if (__get_inst16(&insn16, pc16 + i, user))
245 				goto bad_address;
246 
247 			pr_cont("%c%04x%c", (i?' ':'<'), insn16, (i?' ':'>'));
248 		} else {
249 			u32 insn32;
250 
251 			if (__get_inst32(&insn32, (u32 *)pc + i, user))
252 				goto bad_address;
253 
254 			pr_cont("%c%08x%c", (i?' ':'<'), insn32, (i?' ':'>'));
255 		}
256 	}
257 	pr_cont("\n");
258 	return;
259 
260 bad_address:
261 	pr_cont(" (Bad address in epc)\n\n");
262 }
263 
__show_regs(const struct pt_regs * regs)264 static void __show_regs(const struct pt_regs *regs)
265 {
266 	const int field = 2 * sizeof(unsigned long);
267 	unsigned int cause = regs->cp0_cause;
268 	unsigned int exccode;
269 	int i;
270 
271 	show_regs_print_info(KERN_DEFAULT);
272 
273 	/*
274 	 * Saved main processor registers
275 	 */
276 	for (i = 0; i < 32; ) {
277 		if ((i % 4) == 0)
278 			printk("$%2d   :", i);
279 		if (i == 0)
280 			pr_cont(" %0*lx", field, 0UL);
281 		else if (i == 26 || i == 27)
282 			pr_cont(" %*s", field, "");
283 		else
284 			pr_cont(" %0*lx", field, regs->regs[i]);
285 
286 		i++;
287 		if ((i % 4) == 0)
288 			pr_cont("\n");
289 	}
290 
291 #ifdef CONFIG_CPU_HAS_SMARTMIPS
292 	printk("Acx    : %0*lx\n", field, regs->acx);
293 #endif
294 	if (MIPS_ISA_REV < 6) {
295 		printk("Hi    : %0*lx\n", field, regs->hi);
296 		printk("Lo    : %0*lx\n", field, regs->lo);
297 	}
298 
299 	/*
300 	 * Saved cp0 registers
301 	 */
302 	printk("epc   : %0*lx %pS\n", field, regs->cp0_epc,
303 	       (void *) regs->cp0_epc);
304 	printk("ra    : %0*lx %pS\n", field, regs->regs[31],
305 	       (void *) regs->regs[31]);
306 
307 	printk("Status: %08x	", (uint32_t) regs->cp0_status);
308 
309 	if (cpu_has_3kex) {
310 		if (regs->cp0_status & ST0_KUO)
311 			pr_cont("KUo ");
312 		if (regs->cp0_status & ST0_IEO)
313 			pr_cont("IEo ");
314 		if (regs->cp0_status & ST0_KUP)
315 			pr_cont("KUp ");
316 		if (regs->cp0_status & ST0_IEP)
317 			pr_cont("IEp ");
318 		if (regs->cp0_status & ST0_KUC)
319 			pr_cont("KUc ");
320 		if (regs->cp0_status & ST0_IEC)
321 			pr_cont("IEc ");
322 	} else if (cpu_has_4kex) {
323 		if (regs->cp0_status & ST0_KX)
324 			pr_cont("KX ");
325 		if (regs->cp0_status & ST0_SX)
326 			pr_cont("SX ");
327 		if (regs->cp0_status & ST0_UX)
328 			pr_cont("UX ");
329 		switch (regs->cp0_status & ST0_KSU) {
330 		case KSU_USER:
331 			pr_cont("USER ");
332 			break;
333 		case KSU_SUPERVISOR:
334 			pr_cont("SUPERVISOR ");
335 			break;
336 		case KSU_KERNEL:
337 			pr_cont("KERNEL ");
338 			break;
339 		default:
340 			pr_cont("BAD_MODE ");
341 			break;
342 		}
343 		if (regs->cp0_status & ST0_ERL)
344 			pr_cont("ERL ");
345 		if (regs->cp0_status & ST0_EXL)
346 			pr_cont("EXL ");
347 		if (regs->cp0_status & ST0_IE)
348 			pr_cont("IE ");
349 	}
350 	pr_cont("\n");
351 
352 	exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
353 	printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
354 
355 	if (1 <= exccode && exccode <= 5)
356 		printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
357 
358 	printk("PrId  : %08x (%s)\n", read_c0_prid(),
359 	       cpu_name_string());
360 }
361 
362 /*
363  * FIXME: really the generic show_regs should take a const pointer argument.
364  */
show_regs(struct pt_regs * regs)365 void show_regs(struct pt_regs *regs)
366 {
367 	__show_regs(regs);
368 	dump_stack();
369 }
370 
show_registers(struct pt_regs * regs)371 void show_registers(struct pt_regs *regs)
372 {
373 	const int field = 2 * sizeof(unsigned long);
374 
375 	__show_regs(regs);
376 	print_modules();
377 	printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
378 	       current->comm, current->pid, current_thread_info(), current,
379 	      field, current_thread_info()->tp_value);
380 	if (cpu_has_userlocal) {
381 		unsigned long tls;
382 
383 		tls = read_c0_userlocal();
384 		if (tls != current_thread_info()->tp_value)
385 			printk("*HwTLS: %0*lx\n", field, tls);
386 	}
387 
388 	show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs));
389 	show_code((void *)regs->cp0_epc, user_mode(regs));
390 	printk("\n");
391 }
392 
393 static DEFINE_RAW_SPINLOCK(die_lock);
394 
die(const char * str,struct pt_regs * regs)395 void __noreturn die(const char *str, struct pt_regs *regs)
396 {
397 	static int die_counter;
398 	int sig = SIGSEGV;
399 
400 	oops_enter();
401 
402 	if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
403 		       SIGSEGV) == NOTIFY_STOP)
404 		sig = 0;
405 
406 	console_verbose();
407 	raw_spin_lock_irq(&die_lock);
408 	bust_spinlocks(1);
409 
410 	printk("%s[#%d]:\n", str, ++die_counter);
411 	show_registers(regs);
412 	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
413 	raw_spin_unlock_irq(&die_lock);
414 
415 	oops_exit();
416 
417 	if (in_interrupt())
418 		panic("Fatal exception in interrupt");
419 
420 	if (panic_on_oops)
421 		panic("Fatal exception");
422 
423 	if (regs && kexec_should_crash(current))
424 		crash_kexec(regs);
425 
426 	make_task_dead(sig);
427 }
428 
429 extern struct exception_table_entry __start___dbe_table[];
430 extern struct exception_table_entry __stop___dbe_table[];
431 
432 __asm__(
433 "	.section	__dbe_table, \"a\"\n"
434 "	.previous			\n");
435 
436 /* Given an address, look for it in the exception tables. */
search_dbe_tables(unsigned long addr)437 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
438 {
439 	const struct exception_table_entry *e;
440 
441 	e = search_extable(__start___dbe_table,
442 			   __stop___dbe_table - __start___dbe_table, addr);
443 	if (!e)
444 		e = search_module_dbetables(addr);
445 	return e;
446 }
447 
do_be(struct pt_regs * regs)448 asmlinkage void do_be(struct pt_regs *regs)
449 {
450 	const int field = 2 * sizeof(unsigned long);
451 	const struct exception_table_entry *fixup = NULL;
452 	int data = regs->cp0_cause & 4;
453 	int action = MIPS_BE_FATAL;
454 	enum ctx_state prev_state;
455 
456 	prev_state = exception_enter();
457 	/* XXX For now.	 Fixme, this searches the wrong table ...  */
458 	if (data && !user_mode(regs))
459 		fixup = search_dbe_tables(exception_epc(regs));
460 
461 	if (fixup)
462 		action = MIPS_BE_FIXUP;
463 
464 	if (board_be_handler)
465 		action = board_be_handler(regs, fixup != NULL);
466 	else
467 		mips_cm_error_report();
468 
469 	switch (action) {
470 	case MIPS_BE_DISCARD:
471 		goto out;
472 	case MIPS_BE_FIXUP:
473 		if (fixup) {
474 			regs->cp0_epc = fixup->nextinsn;
475 			goto out;
476 		}
477 		break;
478 	default:
479 		break;
480 	}
481 
482 	/*
483 	 * Assume it would be too dangerous to continue ...
484 	 */
485 	printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
486 	       data ? "Data" : "Instruction",
487 	       field, regs->cp0_epc, field, regs->regs[31]);
488 	if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
489 		       SIGBUS) == NOTIFY_STOP)
490 		goto out;
491 
492 	die_if_kernel("Oops", regs);
493 	force_sig(SIGBUS);
494 
495 out:
496 	exception_exit(prev_state);
497 }
498 
499 /*
500  * ll/sc, rdhwr, sync emulation
501  */
502 
503 #define OPCODE 0xfc000000
504 #define BASE   0x03e00000
505 #define RT     0x001f0000
506 #define OFFSET 0x0000ffff
507 #define LL     0xc0000000
508 #define SC     0xe0000000
509 #define SPEC0  0x00000000
510 #define SPEC3  0x7c000000
511 #define RD     0x0000f800
512 #define FUNC   0x0000003f
513 #define SYNC   0x0000000f
514 #define RDHWR  0x0000003b
515 
516 /*  microMIPS definitions   */
517 #define MM_POOL32A_FUNC 0xfc00ffff
518 #define MM_RDHWR        0x00006b3c
519 #define MM_RS           0x001f0000
520 #define MM_RT           0x03e00000
521 
522 /*
523  * The ll_bit is cleared by r*_switch.S
524  */
525 
526 unsigned int ll_bit;
527 struct task_struct *ll_task;
528 
simulate_ll(struct pt_regs * regs,unsigned int opcode)529 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
530 {
531 	unsigned long value, __user *vaddr;
532 	long offset;
533 
534 	/*
535 	 * analyse the ll instruction that just caused a ri exception
536 	 * and put the referenced address to addr.
537 	 */
538 
539 	/* sign extend offset */
540 	offset = opcode & OFFSET;
541 	offset <<= 16;
542 	offset >>= 16;
543 
544 	vaddr = (unsigned long __user *)
545 		((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
546 
547 	if ((unsigned long)vaddr & 3)
548 		return SIGBUS;
549 	if (get_user(value, vaddr))
550 		return SIGSEGV;
551 
552 	preempt_disable();
553 
554 	if (ll_task == NULL || ll_task == current) {
555 		ll_bit = 1;
556 	} else {
557 		ll_bit = 0;
558 	}
559 	ll_task = current;
560 
561 	preempt_enable();
562 
563 	regs->regs[(opcode & RT) >> 16] = value;
564 
565 	return 0;
566 }
567 
simulate_sc(struct pt_regs * regs,unsigned int opcode)568 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
569 {
570 	unsigned long __user *vaddr;
571 	unsigned long reg;
572 	long offset;
573 
574 	/*
575 	 * analyse the sc instruction that just caused a ri exception
576 	 * and put the referenced address to addr.
577 	 */
578 
579 	/* sign extend offset */
580 	offset = opcode & OFFSET;
581 	offset <<= 16;
582 	offset >>= 16;
583 
584 	vaddr = (unsigned long __user *)
585 		((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
586 	reg = (opcode & RT) >> 16;
587 
588 	if ((unsigned long)vaddr & 3)
589 		return SIGBUS;
590 
591 	preempt_disable();
592 
593 	if (ll_bit == 0 || ll_task != current) {
594 		regs->regs[reg] = 0;
595 		preempt_enable();
596 		return 0;
597 	}
598 
599 	preempt_enable();
600 
601 	if (put_user(regs->regs[reg], vaddr))
602 		return SIGSEGV;
603 
604 	regs->regs[reg] = 1;
605 
606 	return 0;
607 }
608 
609 /*
610  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
611  * opcodes are supposed to result in coprocessor unusable exceptions if
612  * executed on ll/sc-less processors.  That's the theory.  In practice a
613  * few processors such as NEC's VR4100 throw reserved instruction exceptions
614  * instead, so we're doing the emulation thing in both exception handlers.
615  */
simulate_llsc(struct pt_regs * regs,unsigned int opcode)616 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
617 {
618 	if ((opcode & OPCODE) == LL) {
619 		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
620 				1, regs, 0);
621 		return simulate_ll(regs, opcode);
622 	}
623 	if ((opcode & OPCODE) == SC) {
624 		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
625 				1, regs, 0);
626 		return simulate_sc(regs, opcode);
627 	}
628 
629 	return -1;			/* Must be something else ... */
630 }
631 
632 /*
633  * Simulate trapping 'rdhwr' instructions to provide user accessible
634  * registers not implemented in hardware.
635  */
simulate_rdhwr(struct pt_regs * regs,int rd,int rt)636 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
637 {
638 	struct thread_info *ti = task_thread_info(current);
639 
640 	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
641 			1, regs, 0);
642 	switch (rd) {
643 	case MIPS_HWR_CPUNUM:		/* CPU number */
644 		regs->regs[rt] = smp_processor_id();
645 		return 0;
646 	case MIPS_HWR_SYNCISTEP:	/* SYNCI length */
647 		regs->regs[rt] = min(current_cpu_data.dcache.linesz,
648 				     current_cpu_data.icache.linesz);
649 		return 0;
650 	case MIPS_HWR_CC:		/* Read count register */
651 		regs->regs[rt] = read_c0_count();
652 		return 0;
653 	case MIPS_HWR_CCRES:		/* Count register resolution */
654 		switch (current_cpu_type()) {
655 		case CPU_20KC:
656 		case CPU_25KF:
657 			regs->regs[rt] = 1;
658 			break;
659 		default:
660 			regs->regs[rt] = 2;
661 		}
662 		return 0;
663 	case MIPS_HWR_ULR:		/* Read UserLocal register */
664 		regs->regs[rt] = ti->tp_value;
665 		return 0;
666 	default:
667 		return -1;
668 	}
669 }
670 
simulate_rdhwr_normal(struct pt_regs * regs,unsigned int opcode)671 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
672 {
673 	if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
674 		int rd = (opcode & RD) >> 11;
675 		int rt = (opcode & RT) >> 16;
676 
677 		simulate_rdhwr(regs, rd, rt);
678 		return 0;
679 	}
680 
681 	/* Not ours.  */
682 	return -1;
683 }
684 
simulate_rdhwr_mm(struct pt_regs * regs,unsigned int opcode)685 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
686 {
687 	if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
688 		int rd = (opcode & MM_RS) >> 16;
689 		int rt = (opcode & MM_RT) >> 21;
690 		simulate_rdhwr(regs, rd, rt);
691 		return 0;
692 	}
693 
694 	/* Not ours.  */
695 	return -1;
696 }
697 
simulate_sync(struct pt_regs * regs,unsigned int opcode)698 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
699 {
700 	if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
701 		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
702 				1, regs, 0);
703 		return 0;
704 	}
705 
706 	return -1;			/* Must be something else ... */
707 }
708 
709 /*
710  * Loongson-3 CSR instructions emulation
711  */
712 
713 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
714 
715 #define LWC2             0xc8000000
716 #define RS               BASE
717 #define CSR_OPCODE2      0x00000118
718 #define CSR_OPCODE2_MASK 0x000007ff
719 #define CSR_FUNC_MASK    RT
720 #define CSR_FUNC_CPUCFG  0x8
721 
simulate_loongson3_cpucfg(struct pt_regs * regs,unsigned int opcode)722 static int simulate_loongson3_cpucfg(struct pt_regs *regs,
723 				     unsigned int opcode)
724 {
725 	int op = opcode & OPCODE;
726 	int op2 = opcode & CSR_OPCODE2_MASK;
727 	int csr_func = (opcode & CSR_FUNC_MASK) >> 16;
728 
729 	if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) {
730 		int rd = (opcode & RD) >> 11;
731 		int rs = (opcode & RS) >> 21;
732 		__u64 sel = regs->regs[rs];
733 
734 		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
735 
736 		/* Do not emulate on unsupported core models. */
737 		preempt_disable();
738 		if (!loongson3_cpucfg_emulation_enabled(&current_cpu_data)) {
739 			preempt_enable();
740 			return -1;
741 		}
742 		regs->regs[rd] = loongson3_cpucfg_read_synthesized(
743 			&current_cpu_data, sel);
744 		preempt_enable();
745 		return 0;
746 	}
747 
748 	/* Not ours.  */
749 	return -1;
750 }
751 #endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */
752 
do_ov(struct pt_regs * regs)753 asmlinkage void do_ov(struct pt_regs *regs)
754 {
755 	enum ctx_state prev_state;
756 
757 	prev_state = exception_enter();
758 	die_if_kernel("Integer overflow", regs);
759 
760 	force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc);
761 	exception_exit(prev_state);
762 }
763 
764 #ifdef CONFIG_MIPS_FP_SUPPORT
765 
766 /*
767  * Send SIGFPE according to FCSR Cause bits, which must have already
768  * been masked against Enable bits.  This is impotant as Inexact can
769  * happen together with Overflow or Underflow, and `ptrace' can set
770  * any bits.
771  */
force_fcr31_sig(unsigned long fcr31,void __user * fault_addr,struct task_struct * tsk)772 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
773 		     struct task_struct *tsk)
774 {
775 	int si_code = FPE_FLTUNK;
776 
777 	if (fcr31 & FPU_CSR_INV_X)
778 		si_code = FPE_FLTINV;
779 	else if (fcr31 & FPU_CSR_DIV_X)
780 		si_code = FPE_FLTDIV;
781 	else if (fcr31 & FPU_CSR_OVF_X)
782 		si_code = FPE_FLTOVF;
783 	else if (fcr31 & FPU_CSR_UDF_X)
784 		si_code = FPE_FLTUND;
785 	else if (fcr31 & FPU_CSR_INE_X)
786 		si_code = FPE_FLTRES;
787 
788 	force_sig_fault_to_task(SIGFPE, si_code, fault_addr, tsk);
789 }
790 
process_fpemu_return(int sig,void __user * fault_addr,unsigned long fcr31)791 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
792 {
793 	int si_code;
794 
795 	switch (sig) {
796 	case 0:
797 		return 0;
798 
799 	case SIGFPE:
800 		force_fcr31_sig(fcr31, fault_addr, current);
801 		return 1;
802 
803 	case SIGBUS:
804 		force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
805 		return 1;
806 
807 	case SIGSEGV:
808 		mmap_read_lock(current->mm);
809 		if (vma_lookup(current->mm, (unsigned long)fault_addr))
810 			si_code = SEGV_ACCERR;
811 		else
812 			si_code = SEGV_MAPERR;
813 		mmap_read_unlock(current->mm);
814 		force_sig_fault(SIGSEGV, si_code, fault_addr);
815 		return 1;
816 
817 	default:
818 		force_sig(sig);
819 		return 1;
820 	}
821 }
822 
simulate_fp(struct pt_regs * regs,unsigned int opcode,unsigned long old_epc,unsigned long old_ra)823 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
824 		       unsigned long old_epc, unsigned long old_ra)
825 {
826 	union mips_instruction inst = { .word = opcode };
827 	void __user *fault_addr;
828 	unsigned long fcr31;
829 	int sig;
830 
831 	/* If it's obviously not an FP instruction, skip it */
832 	switch (inst.i_format.opcode) {
833 	case cop1_op:
834 	case cop1x_op:
835 	case lwc1_op:
836 	case ldc1_op:
837 	case swc1_op:
838 	case sdc1_op:
839 		break;
840 
841 	default:
842 		return -1;
843 	}
844 
845 	/*
846 	 * do_ri skipped over the instruction via compute_return_epc, undo
847 	 * that for the FPU emulator.
848 	 */
849 	regs->cp0_epc = old_epc;
850 	regs->regs[31] = old_ra;
851 
852 	/* Run the emulator */
853 	sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
854 				       &fault_addr);
855 
856 	/*
857 	 * We can't allow the emulated instruction to leave any
858 	 * enabled Cause bits set in $fcr31.
859 	 */
860 	fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
861 	current->thread.fpu.fcr31 &= ~fcr31;
862 
863 	/* Restore the hardware register state */
864 	own_fpu(1);
865 
866 	/* Send a signal if required.  */
867 	process_fpemu_return(sig, fault_addr, fcr31);
868 
869 	return 0;
870 }
871 
872 /*
873  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
874  */
do_fpe(struct pt_regs * regs,unsigned long fcr31)875 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
876 {
877 	enum ctx_state prev_state;
878 	void __user *fault_addr;
879 	int sig;
880 
881 	prev_state = exception_enter();
882 	if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
883 		       SIGFPE) == NOTIFY_STOP)
884 		goto out;
885 
886 	/* Clear FCSR.Cause before enabling interrupts */
887 	write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
888 	local_irq_enable();
889 
890 	die_if_kernel("FP exception in kernel code", regs);
891 
892 	if (fcr31 & FPU_CSR_UNI_X) {
893 		/*
894 		 * Unimplemented operation exception.  If we've got the full
895 		 * software emulator on-board, let's use it...
896 		 *
897 		 * Force FPU to dump state into task/thread context.  We're
898 		 * moving a lot of data here for what is probably a single
899 		 * instruction, but the alternative is to pre-decode the FP
900 		 * register operands before invoking the emulator, which seems
901 		 * a bit extreme for what should be an infrequent event.
902 		 */
903 
904 		/* Run the emulator */
905 		sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
906 					       &fault_addr);
907 
908 		/*
909 		 * We can't allow the emulated instruction to leave any
910 		 * enabled Cause bits set in $fcr31.
911 		 */
912 		fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
913 		current->thread.fpu.fcr31 &= ~fcr31;
914 
915 		/* Restore the hardware register state */
916 		own_fpu(1);	/* Using the FPU again.	 */
917 	} else {
918 		sig = SIGFPE;
919 		fault_addr = (void __user *) regs->cp0_epc;
920 	}
921 
922 	/* Send a signal if required.  */
923 	process_fpemu_return(sig, fault_addr, fcr31);
924 
925 out:
926 	exception_exit(prev_state);
927 }
928 
929 /*
930  * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
931  * emulated more than some threshold number of instructions, force migration to
932  * a "CPU" that has FP support.
933  */
mt_ase_fp_affinity(void)934 static void mt_ase_fp_affinity(void)
935 {
936 #ifdef CONFIG_MIPS_MT_FPAFF
937 	if (mt_fpemul_threshold > 0 &&
938 	     ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
939 		/*
940 		 * If there's no FPU present, or if the application has already
941 		 * restricted the allowed set to exclude any CPUs with FPUs,
942 		 * we'll skip the procedure.
943 		 */
944 		if (cpumask_intersects(&current->cpus_mask, &mt_fpu_cpumask)) {
945 			cpumask_t tmask;
946 
947 			current->thread.user_cpus_allowed
948 				= current->cpus_mask;
949 			cpumask_and(&tmask, &current->cpus_mask,
950 				    &mt_fpu_cpumask);
951 			set_cpus_allowed_ptr(current, &tmask);
952 			set_thread_flag(TIF_FPUBOUND);
953 		}
954 	}
955 #endif /* CONFIG_MIPS_MT_FPAFF */
956 }
957 
958 #else /* !CONFIG_MIPS_FP_SUPPORT */
959 
simulate_fp(struct pt_regs * regs,unsigned int opcode,unsigned long old_epc,unsigned long old_ra)960 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
961 		       unsigned long old_epc, unsigned long old_ra)
962 {
963 	return -1;
964 }
965 
966 #endif /* !CONFIG_MIPS_FP_SUPPORT */
967 
do_trap_or_bp(struct pt_regs * regs,unsigned int code,int si_code,const char * str)968 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
969 	const char *str)
970 {
971 	char b[40];
972 
973 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
974 	if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
975 			 SIGTRAP) == NOTIFY_STOP)
976 		return;
977 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
978 
979 	if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
980 		       SIGTRAP) == NOTIFY_STOP)
981 		return;
982 
983 	/*
984 	 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
985 	 * insns, even for trap and break codes that indicate arithmetic
986 	 * failures.  Weird ...
987 	 * But should we continue the brokenness???  --macro
988 	 */
989 	switch (code) {
990 	case BRK_OVERFLOW:
991 	case BRK_DIVZERO:
992 		scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
993 		die_if_kernel(b, regs);
994 		force_sig_fault(SIGFPE,
995 				code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF,
996 				(void __user *) regs->cp0_epc);
997 		break;
998 	case BRK_BUG:
999 		die_if_kernel("Kernel bug detected", regs);
1000 		force_sig(SIGTRAP);
1001 		break;
1002 	case BRK_MEMU:
1003 		/*
1004 		 * This breakpoint code is used by the FPU emulator to retake
1005 		 * control of the CPU after executing the instruction from the
1006 		 * delay slot of an emulated branch.
1007 		 *
1008 		 * Terminate if exception was recognized as a delay slot return
1009 		 * otherwise handle as normal.
1010 		 */
1011 		if (do_dsemulret(regs))
1012 			return;
1013 
1014 		die_if_kernel("Math emu break/trap", regs);
1015 		force_sig(SIGTRAP);
1016 		break;
1017 	default:
1018 		scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
1019 		die_if_kernel(b, regs);
1020 		if (si_code) {
1021 			force_sig_fault(SIGTRAP, si_code, NULL);
1022 		} else {
1023 			force_sig(SIGTRAP);
1024 		}
1025 	}
1026 }
1027 
do_bp(struct pt_regs * regs)1028 asmlinkage void do_bp(struct pt_regs *regs)
1029 {
1030 	unsigned long epc = msk_isa16_mode(exception_epc(regs));
1031 	unsigned int opcode, bcode;
1032 	enum ctx_state prev_state;
1033 	bool user = user_mode(regs);
1034 
1035 	prev_state = exception_enter();
1036 	current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1037 	if (get_isa16_mode(regs->cp0_epc)) {
1038 		u16 instr[2];
1039 
1040 		if (__get_inst16(&instr[0], (u16 *)epc, user))
1041 			goto out_sigsegv;
1042 
1043 		if (!cpu_has_mmips) {
1044 			/* MIPS16e mode */
1045 			bcode = (instr[0] >> 5) & 0x3f;
1046 		} else if (mm_insn_16bit(instr[0])) {
1047 			/* 16-bit microMIPS BREAK */
1048 			bcode = instr[0] & 0xf;
1049 		} else {
1050 			/* 32-bit microMIPS BREAK */
1051 			if (__get_inst16(&instr[1], (u16 *)(epc + 2), user))
1052 				goto out_sigsegv;
1053 			opcode = (instr[0] << 16) | instr[1];
1054 			bcode = (opcode >> 6) & ((1 << 20) - 1);
1055 		}
1056 	} else {
1057 		if (__get_inst32(&opcode, (u32 *)epc, user))
1058 			goto out_sigsegv;
1059 		bcode = (opcode >> 6) & ((1 << 20) - 1);
1060 	}
1061 
1062 	/*
1063 	 * There is the ancient bug in the MIPS assemblers that the break
1064 	 * code starts left to bit 16 instead to bit 6 in the opcode.
1065 	 * Gas is bug-compatible, but not always, grrr...
1066 	 * We handle both cases with a simple heuristics.  --macro
1067 	 */
1068 	if (bcode >= (1 << 10))
1069 		bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
1070 
1071 	/*
1072 	 * notify the kprobe handlers, if instruction is likely to
1073 	 * pertain to them.
1074 	 */
1075 	switch (bcode) {
1076 	case BRK_UPROBE:
1077 		if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
1078 			       current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1079 			goto out;
1080 		else
1081 			break;
1082 	case BRK_UPROBE_XOL:
1083 		if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1084 			       current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1085 			goto out;
1086 		else
1087 			break;
1088 	case BRK_KPROBE_BP:
1089 		if (notify_die(DIE_BREAK, "debug", regs, bcode,
1090 			       current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1091 			goto out;
1092 		else
1093 			break;
1094 	case BRK_KPROBE_SSTEPBP:
1095 		if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1096 			       current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1097 			goto out;
1098 		else
1099 			break;
1100 	default:
1101 		break;
1102 	}
1103 
1104 	do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1105 
1106 out:
1107 	exception_exit(prev_state);
1108 	return;
1109 
1110 out_sigsegv:
1111 	force_sig(SIGSEGV);
1112 	goto out;
1113 }
1114 
do_tr(struct pt_regs * regs)1115 asmlinkage void do_tr(struct pt_regs *regs)
1116 {
1117 	u32 opcode, tcode = 0;
1118 	enum ctx_state prev_state;
1119 	u16 instr[2];
1120 	bool user = user_mode(regs);
1121 	unsigned long epc = msk_isa16_mode(exception_epc(regs));
1122 
1123 	prev_state = exception_enter();
1124 	current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1125 	if (get_isa16_mode(regs->cp0_epc)) {
1126 		if (__get_inst16(&instr[0], (u16 *)(epc + 0), user) ||
1127 		    __get_inst16(&instr[1], (u16 *)(epc + 2), user))
1128 			goto out_sigsegv;
1129 		opcode = (instr[0] << 16) | instr[1];
1130 		/* Immediate versions don't provide a code.  */
1131 		if (!(opcode & OPCODE))
1132 			tcode = (opcode >> 12) & ((1 << 4) - 1);
1133 	} else {
1134 		if (__get_inst32(&opcode, (u32 *)epc, user))
1135 			goto out_sigsegv;
1136 		/* Immediate versions don't provide a code.  */
1137 		if (!(opcode & OPCODE))
1138 			tcode = (opcode >> 6) & ((1 << 10) - 1);
1139 	}
1140 
1141 	do_trap_or_bp(regs, tcode, 0, "Trap");
1142 
1143 out:
1144 	exception_exit(prev_state);
1145 	return;
1146 
1147 out_sigsegv:
1148 	force_sig(SIGSEGV);
1149 	goto out;
1150 }
1151 
do_ri(struct pt_regs * regs)1152 asmlinkage void do_ri(struct pt_regs *regs)
1153 {
1154 	unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1155 	unsigned long old_epc = regs->cp0_epc;
1156 	unsigned long old31 = regs->regs[31];
1157 	enum ctx_state prev_state;
1158 	unsigned int opcode = 0;
1159 	int status = -1;
1160 
1161 	/*
1162 	 * Avoid any kernel code. Just emulate the R2 instruction
1163 	 * as quickly as possible.
1164 	 */
1165 	if (mipsr2_emulation && cpu_has_mips_r6 &&
1166 	    likely(user_mode(regs)) &&
1167 	    likely(get_user(opcode, epc) >= 0)) {
1168 		unsigned long fcr31 = 0;
1169 
1170 		status = mipsr2_decoder(regs, opcode, &fcr31);
1171 		switch (status) {
1172 		case 0:
1173 		case SIGEMT:
1174 			return;
1175 		case SIGILL:
1176 			goto no_r2_instr;
1177 		default:
1178 			process_fpemu_return(status,
1179 					     &current->thread.cp0_baduaddr,
1180 					     fcr31);
1181 			return;
1182 		}
1183 	}
1184 
1185 no_r2_instr:
1186 
1187 	prev_state = exception_enter();
1188 	current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1189 
1190 	if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1191 		       SIGILL) == NOTIFY_STOP)
1192 		goto out;
1193 
1194 	die_if_kernel("Reserved instruction in kernel code", regs);
1195 
1196 	if (unlikely(compute_return_epc(regs) < 0))
1197 		goto out;
1198 
1199 	if (!get_isa16_mode(regs->cp0_epc)) {
1200 		if (unlikely(get_user(opcode, epc) < 0))
1201 			status = SIGSEGV;
1202 
1203 		if (!cpu_has_llsc && status < 0)
1204 			status = simulate_llsc(regs, opcode);
1205 
1206 		if (status < 0)
1207 			status = simulate_rdhwr_normal(regs, opcode);
1208 
1209 		if (status < 0)
1210 			status = simulate_sync(regs, opcode);
1211 
1212 		if (status < 0)
1213 			status = simulate_fp(regs, opcode, old_epc, old31);
1214 
1215 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
1216 		if (status < 0)
1217 			status = simulate_loongson3_cpucfg(regs, opcode);
1218 #endif
1219 	} else if (cpu_has_mmips) {
1220 		unsigned short mmop[2] = { 0 };
1221 
1222 		if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1223 			status = SIGSEGV;
1224 		if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1225 			status = SIGSEGV;
1226 		opcode = mmop[0];
1227 		opcode = (opcode << 16) | mmop[1];
1228 
1229 		if (status < 0)
1230 			status = simulate_rdhwr_mm(regs, opcode);
1231 	}
1232 
1233 	if (status < 0)
1234 		status = SIGILL;
1235 
1236 	if (unlikely(status > 0)) {
1237 		regs->cp0_epc = old_epc;		/* Undo skip-over.  */
1238 		regs->regs[31] = old31;
1239 		force_sig(status);
1240 	}
1241 
1242 out:
1243 	exception_exit(prev_state);
1244 }
1245 
1246 /*
1247  * No lock; only written during early bootup by CPU 0.
1248  */
1249 static RAW_NOTIFIER_HEAD(cu2_chain);
1250 
register_cu2_notifier(struct notifier_block * nb)1251 int __ref register_cu2_notifier(struct notifier_block *nb)
1252 {
1253 	return raw_notifier_chain_register(&cu2_chain, nb);
1254 }
1255 
cu2_notifier_call_chain(unsigned long val,void * v)1256 int cu2_notifier_call_chain(unsigned long val, void *v)
1257 {
1258 	return raw_notifier_call_chain(&cu2_chain, val, v);
1259 }
1260 
default_cu2_call(struct notifier_block * nfb,unsigned long action,void * data)1261 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1262 	void *data)
1263 {
1264 	struct pt_regs *regs = data;
1265 
1266 	die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1267 			      "instruction", regs);
1268 	force_sig(SIGILL);
1269 
1270 	return NOTIFY_OK;
1271 }
1272 
1273 #ifdef CONFIG_MIPS_FP_SUPPORT
1274 
enable_restore_fp_context(int msa)1275 static int enable_restore_fp_context(int msa)
1276 {
1277 	int err, was_fpu_owner, prior_msa;
1278 	bool first_fp;
1279 
1280 	/* Initialize context if it hasn't been used already */
1281 	first_fp = init_fp_ctx(current);
1282 
1283 	if (first_fp) {
1284 		preempt_disable();
1285 		err = own_fpu_inatomic(1);
1286 		if (msa && !err) {
1287 			enable_msa();
1288 			/*
1289 			 * with MSA enabled, userspace can see MSACSR
1290 			 * and MSA regs, but the values in them are from
1291 			 * other task before current task, restore them
1292 			 * from saved fp/msa context
1293 			 */
1294 			write_msa_csr(current->thread.fpu.msacsr);
1295 			/*
1296 			 * own_fpu_inatomic(1) just restore low 64bit,
1297 			 * fix the high 64bit
1298 			 */
1299 			init_msa_upper();
1300 			set_thread_flag(TIF_USEDMSA);
1301 			set_thread_flag(TIF_MSA_CTX_LIVE);
1302 		}
1303 		preempt_enable();
1304 		return err;
1305 	}
1306 
1307 	/*
1308 	 * This task has formerly used the FP context.
1309 	 *
1310 	 * If this thread has no live MSA vector context then we can simply
1311 	 * restore the scalar FP context. If it has live MSA vector context
1312 	 * (that is, it has or may have used MSA since last performing a
1313 	 * function call) then we'll need to restore the vector context. This
1314 	 * applies even if we're currently only executing a scalar FP
1315 	 * instruction. This is because if we were to later execute an MSA
1316 	 * instruction then we'd either have to:
1317 	 *
1318 	 *  - Restore the vector context & clobber any registers modified by
1319 	 *    scalar FP instructions between now & then.
1320 	 *
1321 	 * or
1322 	 *
1323 	 *  - Not restore the vector context & lose the most significant bits
1324 	 *    of all vector registers.
1325 	 *
1326 	 * Neither of those options is acceptable. We cannot restore the least
1327 	 * significant bits of the registers now & only restore the most
1328 	 * significant bits later because the most significant bits of any
1329 	 * vector registers whose aliased FP register is modified now will have
1330 	 * been zeroed. We'd have no way to know that when restoring the vector
1331 	 * context & thus may load an outdated value for the most significant
1332 	 * bits of a vector register.
1333 	 */
1334 	if (!msa && !thread_msa_context_live())
1335 		return own_fpu(1);
1336 
1337 	/*
1338 	 * This task is using or has previously used MSA. Thus we require
1339 	 * that Status.FR == 1.
1340 	 */
1341 	preempt_disable();
1342 	was_fpu_owner = is_fpu_owner();
1343 	err = own_fpu_inatomic(0);
1344 	if (err)
1345 		goto out;
1346 
1347 	enable_msa();
1348 	write_msa_csr(current->thread.fpu.msacsr);
1349 	set_thread_flag(TIF_USEDMSA);
1350 
1351 	/*
1352 	 * If this is the first time that the task is using MSA and it has
1353 	 * previously used scalar FP in this time slice then we already nave
1354 	 * FP context which we shouldn't clobber. We do however need to clear
1355 	 * the upper 64b of each vector register so that this task has no
1356 	 * opportunity to see data left behind by another.
1357 	 */
1358 	prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1359 	if (!prior_msa && was_fpu_owner) {
1360 		init_msa_upper();
1361 
1362 		goto out;
1363 	}
1364 
1365 	if (!prior_msa) {
1366 		/*
1367 		 * Restore the least significant 64b of each vector register
1368 		 * from the existing scalar FP context.
1369 		 */
1370 		_restore_fp(current);
1371 
1372 		/*
1373 		 * The task has not formerly used MSA, so clear the upper 64b
1374 		 * of each vector register such that it cannot see data left
1375 		 * behind by another task.
1376 		 */
1377 		init_msa_upper();
1378 	} else {
1379 		/* We need to restore the vector context. */
1380 		restore_msa(current);
1381 
1382 		/* Restore the scalar FP control & status register */
1383 		if (!was_fpu_owner)
1384 			write_32bit_cp1_register(CP1_STATUS,
1385 						 current->thread.fpu.fcr31);
1386 	}
1387 
1388 out:
1389 	preempt_enable();
1390 
1391 	return 0;
1392 }
1393 
1394 #else /* !CONFIG_MIPS_FP_SUPPORT */
1395 
enable_restore_fp_context(int msa)1396 static int enable_restore_fp_context(int msa)
1397 {
1398 	return SIGILL;
1399 }
1400 
1401 #endif /* CONFIG_MIPS_FP_SUPPORT */
1402 
do_cpu(struct pt_regs * regs)1403 asmlinkage void do_cpu(struct pt_regs *regs)
1404 {
1405 	enum ctx_state prev_state;
1406 	unsigned int __user *epc;
1407 	unsigned long old_epc, old31;
1408 	unsigned int opcode;
1409 	unsigned int cpid;
1410 	int status;
1411 
1412 	prev_state = exception_enter();
1413 	cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1414 
1415 	if (cpid != 2)
1416 		die_if_kernel("do_cpu invoked from kernel context!", regs);
1417 
1418 	switch (cpid) {
1419 	case 0:
1420 		epc = (unsigned int __user *)exception_epc(regs);
1421 		old_epc = regs->cp0_epc;
1422 		old31 = regs->regs[31];
1423 		opcode = 0;
1424 		status = -1;
1425 
1426 		if (unlikely(compute_return_epc(regs) < 0))
1427 			break;
1428 
1429 		if (!get_isa16_mode(regs->cp0_epc)) {
1430 			if (unlikely(get_user(opcode, epc) < 0))
1431 				status = SIGSEGV;
1432 
1433 			if (!cpu_has_llsc && status < 0)
1434 				status = simulate_llsc(regs, opcode);
1435 		}
1436 
1437 		if (status < 0)
1438 			status = SIGILL;
1439 
1440 		if (unlikely(status > 0)) {
1441 			regs->cp0_epc = old_epc;	/* Undo skip-over.  */
1442 			regs->regs[31] = old31;
1443 			force_sig(status);
1444 		}
1445 
1446 		break;
1447 
1448 #ifdef CONFIG_MIPS_FP_SUPPORT
1449 	case 3:
1450 		/*
1451 		 * The COP3 opcode space and consequently the CP0.Status.CU3
1452 		 * bit and the CP0.Cause.CE=3 encoding have been removed as
1453 		 * of the MIPS III ISA.  From the MIPS IV and MIPS32r2 ISAs
1454 		 * up the space has been reused for COP1X instructions, that
1455 		 * are enabled by the CP0.Status.CU1 bit and consequently
1456 		 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1457 		 * exceptions.  Some FPU-less processors that implement one
1458 		 * of these ISAs however use this code erroneously for COP1X
1459 		 * instructions.  Therefore we redirect this trap to the FP
1460 		 * emulator too.
1461 		 */
1462 		if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1463 			force_sig(SIGILL);
1464 			break;
1465 		}
1466 		fallthrough;
1467 	case 1: {
1468 		void __user *fault_addr;
1469 		unsigned long fcr31;
1470 		int err, sig;
1471 
1472 		err = enable_restore_fp_context(0);
1473 
1474 		if (raw_cpu_has_fpu && !err)
1475 			break;
1476 
1477 		sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1478 					       &fault_addr);
1479 
1480 		/*
1481 		 * We can't allow the emulated instruction to leave
1482 		 * any enabled Cause bits set in $fcr31.
1483 		 */
1484 		fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1485 		current->thread.fpu.fcr31 &= ~fcr31;
1486 
1487 		/* Send a signal if required.  */
1488 		if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1489 			mt_ase_fp_affinity();
1490 
1491 		break;
1492 	}
1493 #else /* CONFIG_MIPS_FP_SUPPORT */
1494 	case 1:
1495 	case 3:
1496 		force_sig(SIGILL);
1497 		break;
1498 #endif /* CONFIG_MIPS_FP_SUPPORT */
1499 
1500 	case 2:
1501 		raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1502 		break;
1503 	}
1504 
1505 	exception_exit(prev_state);
1506 }
1507 
do_msa_fpe(struct pt_regs * regs,unsigned int msacsr)1508 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1509 {
1510 	enum ctx_state prev_state;
1511 
1512 	prev_state = exception_enter();
1513 	current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1514 	if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1515 		       current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1516 		goto out;
1517 
1518 	/* Clear MSACSR.Cause before enabling interrupts */
1519 	write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1520 	local_irq_enable();
1521 
1522 	die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1523 	force_sig(SIGFPE);
1524 out:
1525 	exception_exit(prev_state);
1526 }
1527 
do_msa(struct pt_regs * regs)1528 asmlinkage void do_msa(struct pt_regs *regs)
1529 {
1530 	enum ctx_state prev_state;
1531 	int err;
1532 
1533 	prev_state = exception_enter();
1534 
1535 	if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1536 		force_sig(SIGILL);
1537 		goto out;
1538 	}
1539 
1540 	die_if_kernel("do_msa invoked from kernel context!", regs);
1541 
1542 	err = enable_restore_fp_context(1);
1543 	if (err)
1544 		force_sig(SIGILL);
1545 out:
1546 	exception_exit(prev_state);
1547 }
1548 
do_mdmx(struct pt_regs * regs)1549 asmlinkage void do_mdmx(struct pt_regs *regs)
1550 {
1551 	enum ctx_state prev_state;
1552 
1553 	prev_state = exception_enter();
1554 	force_sig(SIGILL);
1555 	exception_exit(prev_state);
1556 }
1557 
1558 /*
1559  * Called with interrupts disabled.
1560  */
do_watch(struct pt_regs * regs)1561 asmlinkage void do_watch(struct pt_regs *regs)
1562 {
1563 	enum ctx_state prev_state;
1564 
1565 	prev_state = exception_enter();
1566 	/*
1567 	 * Clear WP (bit 22) bit of cause register so we don't loop
1568 	 * forever.
1569 	 */
1570 	clear_c0_cause(CAUSEF_WP);
1571 
1572 	/*
1573 	 * If the current thread has the watch registers loaded, save
1574 	 * their values and send SIGTRAP.  Otherwise another thread
1575 	 * left the registers set, clear them and continue.
1576 	 */
1577 	if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1578 		mips_read_watch_registers();
1579 		local_irq_enable();
1580 		force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL);
1581 	} else {
1582 		mips_clear_watch_registers();
1583 		local_irq_enable();
1584 	}
1585 	exception_exit(prev_state);
1586 }
1587 
do_mcheck(struct pt_regs * regs)1588 asmlinkage void do_mcheck(struct pt_regs *regs)
1589 {
1590 	int multi_match = regs->cp0_status & ST0_TS;
1591 	enum ctx_state prev_state;
1592 
1593 	prev_state = exception_enter();
1594 	show_regs(regs);
1595 
1596 	if (multi_match) {
1597 		dump_tlb_regs();
1598 		pr_info("\n");
1599 		dump_tlb_all();
1600 	}
1601 
1602 	show_code((void *)regs->cp0_epc, user_mode(regs));
1603 
1604 	/*
1605 	 * Some chips may have other causes of machine check (e.g. SB1
1606 	 * graduation timer)
1607 	 */
1608 	panic("Caught Machine Check exception - %scaused by multiple "
1609 	      "matching entries in the TLB.",
1610 	      (multi_match) ? "" : "not ");
1611 }
1612 
do_mt(struct pt_regs * regs)1613 asmlinkage void do_mt(struct pt_regs *regs)
1614 {
1615 	int subcode;
1616 
1617 	subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1618 			>> VPECONTROL_EXCPT_SHIFT;
1619 	switch (subcode) {
1620 	case 0:
1621 		printk(KERN_DEBUG "Thread Underflow\n");
1622 		break;
1623 	case 1:
1624 		printk(KERN_DEBUG "Thread Overflow\n");
1625 		break;
1626 	case 2:
1627 		printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1628 		break;
1629 	case 3:
1630 		printk(KERN_DEBUG "Gating Storage Exception\n");
1631 		break;
1632 	case 4:
1633 		printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1634 		break;
1635 	case 5:
1636 		printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1637 		break;
1638 	default:
1639 		printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1640 			subcode);
1641 		break;
1642 	}
1643 	die_if_kernel("MIPS MT Thread exception in kernel", regs);
1644 
1645 	force_sig(SIGILL);
1646 }
1647 
1648 
do_dsp(struct pt_regs * regs)1649 asmlinkage void do_dsp(struct pt_regs *regs)
1650 {
1651 	if (cpu_has_dsp)
1652 		panic("Unexpected DSP exception");
1653 
1654 	force_sig(SIGILL);
1655 }
1656 
do_reserved(struct pt_regs * regs)1657 asmlinkage void do_reserved(struct pt_regs *regs)
1658 {
1659 	/*
1660 	 * Game over - no way to handle this if it ever occurs.	 Most probably
1661 	 * caused by a new unknown cpu type or after another deadly
1662 	 * hard/software error.
1663 	 */
1664 	show_regs(regs);
1665 	panic("Caught reserved exception %ld - should not happen.",
1666 	      (regs->cp0_cause & 0x7f) >> 2);
1667 }
1668 
1669 static int __initdata l1parity = 1;
nol1parity(char * s)1670 static int __init nol1parity(char *s)
1671 {
1672 	l1parity = 0;
1673 	return 1;
1674 }
1675 __setup("nol1par", nol1parity);
1676 static int __initdata l2parity = 1;
nol2parity(char * s)1677 static int __init nol2parity(char *s)
1678 {
1679 	l2parity = 0;
1680 	return 1;
1681 }
1682 __setup("nol2par", nol2parity);
1683 
1684 /*
1685  * Some MIPS CPUs can enable/disable for cache parity detection, but do
1686  * it different ways.
1687  */
parity_protection_init(void)1688 static inline __init void parity_protection_init(void)
1689 {
1690 #define ERRCTL_PE	0x80000000
1691 #define ERRCTL_L2P	0x00800000
1692 
1693 	if (mips_cm_revision() >= CM_REV_CM3) {
1694 		ulong gcr_ectl, cp0_ectl;
1695 
1696 		/*
1697 		 * With CM3 systems we need to ensure that the L1 & L2
1698 		 * parity enables are set to the same value, since this
1699 		 * is presumed by the hardware engineers.
1700 		 *
1701 		 * If the user disabled either of L1 or L2 ECC checking,
1702 		 * disable both.
1703 		 */
1704 		l1parity &= l2parity;
1705 		l2parity &= l1parity;
1706 
1707 		/* Probe L1 ECC support */
1708 		cp0_ectl = read_c0_ecc();
1709 		write_c0_ecc(cp0_ectl | ERRCTL_PE);
1710 		back_to_back_c0_hazard();
1711 		cp0_ectl = read_c0_ecc();
1712 
1713 		/* Probe L2 ECC support */
1714 		gcr_ectl = read_gcr_err_control();
1715 
1716 		if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
1717 		    !(cp0_ectl & ERRCTL_PE)) {
1718 			/*
1719 			 * One of L1 or L2 ECC checking isn't supported,
1720 			 * so we cannot enable either.
1721 			 */
1722 			l1parity = l2parity = 0;
1723 		}
1724 
1725 		/* Configure L1 ECC checking */
1726 		if (l1parity)
1727 			cp0_ectl |= ERRCTL_PE;
1728 		else
1729 			cp0_ectl &= ~ERRCTL_PE;
1730 		write_c0_ecc(cp0_ectl);
1731 		back_to_back_c0_hazard();
1732 		WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1733 
1734 		/* Configure L2 ECC checking */
1735 		if (l2parity)
1736 			gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1737 		else
1738 			gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
1739 		write_gcr_err_control(gcr_ectl);
1740 		gcr_ectl = read_gcr_err_control();
1741 		gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1742 		WARN_ON(!!gcr_ectl != l2parity);
1743 
1744 		pr_info("Cache parity protection %sabled\n",
1745 			l1parity ? "en" : "dis");
1746 		return;
1747 	}
1748 
1749 	switch (current_cpu_type()) {
1750 	case CPU_24K:
1751 	case CPU_34K:
1752 	case CPU_74K:
1753 	case CPU_1004K:
1754 	case CPU_1074K:
1755 	case CPU_INTERAPTIV:
1756 	case CPU_PROAPTIV:
1757 	case CPU_P5600:
1758 	case CPU_QEMU_GENERIC:
1759 	case CPU_P6600:
1760 		{
1761 			unsigned long errctl;
1762 			unsigned int l1parity_present, l2parity_present;
1763 
1764 			errctl = read_c0_ecc();
1765 			errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1766 
1767 			/* probe L1 parity support */
1768 			write_c0_ecc(errctl | ERRCTL_PE);
1769 			back_to_back_c0_hazard();
1770 			l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1771 
1772 			/* probe L2 parity support */
1773 			write_c0_ecc(errctl|ERRCTL_L2P);
1774 			back_to_back_c0_hazard();
1775 			l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1776 
1777 			if (l1parity_present && l2parity_present) {
1778 				if (l1parity)
1779 					errctl |= ERRCTL_PE;
1780 				if (l1parity ^ l2parity)
1781 					errctl |= ERRCTL_L2P;
1782 			} else if (l1parity_present) {
1783 				if (l1parity)
1784 					errctl |= ERRCTL_PE;
1785 			} else if (l2parity_present) {
1786 				if (l2parity)
1787 					errctl |= ERRCTL_L2P;
1788 			} else {
1789 				/* No parity available */
1790 			}
1791 
1792 			printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1793 
1794 			write_c0_ecc(errctl);
1795 			back_to_back_c0_hazard();
1796 			errctl = read_c0_ecc();
1797 			printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1798 
1799 			if (l1parity_present)
1800 				printk(KERN_INFO "Cache parity protection %sabled\n",
1801 				       (errctl & ERRCTL_PE) ? "en" : "dis");
1802 
1803 			if (l2parity_present) {
1804 				if (l1parity_present && l1parity)
1805 					errctl ^= ERRCTL_L2P;
1806 				printk(KERN_INFO "L2 cache parity protection %sabled\n",
1807 				       (errctl & ERRCTL_L2P) ? "en" : "dis");
1808 			}
1809 		}
1810 		break;
1811 
1812 	case CPU_5KC:
1813 	case CPU_5KE:
1814 	case CPU_LOONGSON32:
1815 		write_c0_ecc(0x80000000);
1816 		back_to_back_c0_hazard();
1817 		/* Set the PE bit (bit 31) in the c0_errctl register. */
1818 		printk(KERN_INFO "Cache parity protection %sabled\n",
1819 		       (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1820 		break;
1821 	case CPU_20KC:
1822 	case CPU_25KF:
1823 		/* Clear the DE bit (bit 16) in the c0_status register. */
1824 		printk(KERN_INFO "Enable cache parity protection for "
1825 		       "MIPS 20KC/25KF CPUs.\n");
1826 		clear_c0_status(ST0_DE);
1827 		break;
1828 	default:
1829 		break;
1830 	}
1831 }
1832 
cache_parity_error(void)1833 asmlinkage void cache_parity_error(void)
1834 {
1835 	const int field = 2 * sizeof(unsigned long);
1836 	unsigned int reg_val;
1837 
1838 	/* For the moment, report the problem and hang. */
1839 	printk("Cache error exception:\n");
1840 	printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1841 	reg_val = read_c0_cacheerr();
1842 	printk("c0_cacheerr == %08x\n", reg_val);
1843 
1844 	printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1845 	       reg_val & (1<<30) ? "secondary" : "primary",
1846 	       reg_val & (1<<31) ? "data" : "insn");
1847 	if ((cpu_has_mips_r2_r6) &&
1848 	    ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1849 		pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1850 			reg_val & (1<<29) ? "ED " : "",
1851 			reg_val & (1<<28) ? "ET " : "",
1852 			reg_val & (1<<27) ? "ES " : "",
1853 			reg_val & (1<<26) ? "EE " : "",
1854 			reg_val & (1<<25) ? "EB " : "",
1855 			reg_val & (1<<24) ? "EI " : "",
1856 			reg_val & (1<<23) ? "E1 " : "",
1857 			reg_val & (1<<22) ? "E0 " : "");
1858 	} else {
1859 		pr_err("Error bits: %s%s%s%s%s%s%s\n",
1860 			reg_val & (1<<29) ? "ED " : "",
1861 			reg_val & (1<<28) ? "ET " : "",
1862 			reg_val & (1<<26) ? "EE " : "",
1863 			reg_val & (1<<25) ? "EB " : "",
1864 			reg_val & (1<<24) ? "EI " : "",
1865 			reg_val & (1<<23) ? "E1 " : "",
1866 			reg_val & (1<<22) ? "E0 " : "");
1867 	}
1868 	printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1869 
1870 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1871 	if (reg_val & (1<<22))
1872 		printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1873 
1874 	if (reg_val & (1<<23))
1875 		printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1876 #endif
1877 
1878 	panic("Can't handle the cache error!");
1879 }
1880 
do_ftlb(void)1881 asmlinkage void do_ftlb(void)
1882 {
1883 	const int field = 2 * sizeof(unsigned long);
1884 	unsigned int reg_val;
1885 
1886 	/* For the moment, report the problem and hang. */
1887 	if ((cpu_has_mips_r2_r6) &&
1888 	    (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1889 	    ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1890 		pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1891 		       read_c0_ecc());
1892 		pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1893 		reg_val = read_c0_cacheerr();
1894 		pr_err("c0_cacheerr == %08x\n", reg_val);
1895 
1896 		if ((reg_val & 0xc0000000) == 0xc0000000) {
1897 			pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1898 		} else {
1899 			pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1900 			       reg_val & (1<<30) ? "secondary" : "primary",
1901 			       reg_val & (1<<31) ? "data" : "insn");
1902 		}
1903 	} else {
1904 		pr_err("FTLB error exception\n");
1905 	}
1906 	/* Just print the cacheerr bits for now */
1907 	cache_parity_error();
1908 }
1909 
do_gsexc(struct pt_regs * regs,u32 diag1)1910 asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1)
1911 {
1912 	u32 exccode = (diag1 & LOONGSON_DIAG1_EXCCODE) >>
1913 			LOONGSON_DIAG1_EXCCODE_SHIFT;
1914 	enum ctx_state prev_state;
1915 
1916 	prev_state = exception_enter();
1917 
1918 	switch (exccode) {
1919 	case 0x08:
1920 		/* Undocumented exception, will trigger on certain
1921 		 * also-undocumented instructions accessible from userspace.
1922 		 * Processor state is not otherwise corrupted, but currently
1923 		 * we don't know how to proceed. Maybe there is some
1924 		 * undocumented control flag to enable the instructions?
1925 		 */
1926 		force_sig(SIGILL);
1927 		break;
1928 
1929 	default:
1930 		/* None of the other exceptions, documented or not, have
1931 		 * further details given; none are encountered in the wild
1932 		 * either. Panic in case some of them turn out to be fatal.
1933 		 */
1934 		show_regs(regs);
1935 		panic("Unhandled Loongson exception - GSCause = %08x", diag1);
1936 	}
1937 
1938 	exception_exit(prev_state);
1939 }
1940 
1941 /*
1942  * SDBBP EJTAG debug exception handler.
1943  * We skip the instruction and return to the next instruction.
1944  */
ejtag_exception_handler(struct pt_regs * regs)1945 void ejtag_exception_handler(struct pt_regs *regs)
1946 {
1947 	const int field = 2 * sizeof(unsigned long);
1948 	unsigned long depc, old_epc, old_ra;
1949 	unsigned int debug;
1950 
1951 	printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1952 	depc = read_c0_depc();
1953 	debug = read_c0_debug();
1954 	printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1955 	if (debug & 0x80000000) {
1956 		/*
1957 		 * In branch delay slot.
1958 		 * We cheat a little bit here and use EPC to calculate the
1959 		 * debug return address (DEPC). EPC is restored after the
1960 		 * calculation.
1961 		 */
1962 		old_epc = regs->cp0_epc;
1963 		old_ra = regs->regs[31];
1964 		regs->cp0_epc = depc;
1965 		compute_return_epc(regs);
1966 		depc = regs->cp0_epc;
1967 		regs->cp0_epc = old_epc;
1968 		regs->regs[31] = old_ra;
1969 	} else
1970 		depc += 4;
1971 	write_c0_depc(depc);
1972 
1973 #if 0
1974 	printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1975 	write_c0_debug(debug | 0x100);
1976 #endif
1977 }
1978 
1979 /*
1980  * NMI exception handler.
1981  * No lock; only written during early bootup by CPU 0.
1982  */
1983 static RAW_NOTIFIER_HEAD(nmi_chain);
1984 
register_nmi_notifier(struct notifier_block * nb)1985 int register_nmi_notifier(struct notifier_block *nb)
1986 {
1987 	return raw_notifier_chain_register(&nmi_chain, nb);
1988 }
1989 
nmi_exception_handler(struct pt_regs * regs)1990 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1991 {
1992 	char str[100];
1993 
1994 	nmi_enter();
1995 	raw_notifier_call_chain(&nmi_chain, 0, regs);
1996 	bust_spinlocks(1);
1997 	snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1998 		 smp_processor_id(), regs->cp0_epc);
1999 	regs->cp0_epc = read_c0_errorepc();
2000 	die(str, regs);
2001 	nmi_exit();
2002 }
2003 
2004 unsigned long ebase;
2005 EXPORT_SYMBOL_GPL(ebase);
2006 unsigned long exception_handlers[32];
2007 unsigned long vi_handlers[64];
2008 
reserve_exception_space(phys_addr_t addr,unsigned long size)2009 void reserve_exception_space(phys_addr_t addr, unsigned long size)
2010 {
2011 	/*
2012 	 * reserve exception space on CPUs other than CPU0
2013 	 * is too late, since memblock is unavailable when APs
2014 	 * up
2015 	 */
2016 	if (smp_processor_id() == 0)
2017 		memblock_reserve(addr, size);
2018 }
2019 
set_except_vector(int n,void * addr)2020 void __init *set_except_vector(int n, void *addr)
2021 {
2022 	unsigned long handler = (unsigned long) addr;
2023 	unsigned long old_handler;
2024 
2025 #ifdef CONFIG_CPU_MICROMIPS
2026 	/*
2027 	 * Only the TLB handlers are cache aligned with an even
2028 	 * address. All other handlers are on an odd address and
2029 	 * require no modification. Otherwise, MIPS32 mode will
2030 	 * be entered when handling any TLB exceptions. That
2031 	 * would be bad...since we must stay in microMIPS mode.
2032 	 */
2033 	if (!(handler & 0x1))
2034 		handler |= 1;
2035 #endif
2036 	old_handler = xchg(&exception_handlers[n], handler);
2037 
2038 	if (n == 0 && cpu_has_divec) {
2039 #ifdef CONFIG_CPU_MICROMIPS
2040 		unsigned long jump_mask = ~((1 << 27) - 1);
2041 #else
2042 		unsigned long jump_mask = ~((1 << 28) - 1);
2043 #endif
2044 		u32 *buf = (u32 *)(ebase + 0x200);
2045 		if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
2046 			uasm_i_j(&buf, handler & ~jump_mask);
2047 			uasm_i_nop(&buf);
2048 		} else {
2049 			UASM_i_LA(&buf, GPR_K0, handler);
2050 			uasm_i_jr(&buf, GPR_K0);
2051 			uasm_i_nop(&buf);
2052 		}
2053 		local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
2054 	}
2055 	return (void *)old_handler;
2056 }
2057 
do_default_vi(void)2058 static void do_default_vi(void)
2059 {
2060 	show_regs(get_irq_regs());
2061 	panic("Caught unexpected vectored interrupt.");
2062 }
2063 
set_vi_handler(int n,vi_handler_t addr)2064 void *set_vi_handler(int n, vi_handler_t addr)
2065 {
2066 	extern const u8 except_vec_vi[];
2067 	extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
2068 	extern const u8 rollback_except_vec_vi[];
2069 	unsigned long handler;
2070 	unsigned long old_handler = vi_handlers[n];
2071 	int srssets = current_cpu_data.srsets;
2072 	u16 *h;
2073 	unsigned char *b;
2074 	const u8 *vec_start;
2075 	int ori_offset;
2076 	int handler_len;
2077 
2078 	BUG_ON(!cpu_has_veic && !cpu_has_vint);
2079 
2080 	if (addr == NULL) {
2081 		handler = (unsigned long) do_default_vi;
2082 	} else
2083 		handler = (unsigned long) addr;
2084 	vi_handlers[n] = handler;
2085 
2086 	b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
2087 
2088 	if (cpu_has_veic) {
2089 		if (board_bind_eic_interrupt)
2090 			board_bind_eic_interrupt(n, 0);
2091 	} else if (cpu_has_vint) {
2092 		/* SRSMap is only defined if shadow sets are implemented */
2093 		if (srssets > 1)
2094 			change_c0_srsmap(0xf << n*4, 0 << n*4);
2095 	}
2096 
2097 	vec_start = using_rollback_handler() ? rollback_except_vec_vi :
2098 					       except_vec_vi;
2099 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
2100 	ori_offset = except_vec_vi_ori - vec_start + 2;
2101 #else
2102 	ori_offset = except_vec_vi_ori - vec_start;
2103 #endif
2104 	handler_len = except_vec_vi_end - vec_start;
2105 
2106 	if (handler_len > VECTORSPACING) {
2107 		/*
2108 		 * Sigh... panicing won't help as the console
2109 		 * is probably not configured :(
2110 		 */
2111 		panic("VECTORSPACING too small");
2112 	}
2113 
2114 	set_handler(((unsigned long)b - ebase), vec_start,
2115 #ifdef CONFIG_CPU_MICROMIPS
2116 			(handler_len - 1));
2117 #else
2118 			handler_len);
2119 #endif
2120 	/* insert offset into vi_handlers[] */
2121 	h = (u16 *)(b + ori_offset);
2122 	*h = n * sizeof(handler);
2123 	local_flush_icache_range((unsigned long)b,
2124 				 (unsigned long)(b+handler_len));
2125 
2126 	return (void *)old_handler;
2127 }
2128 
2129 /*
2130  * Timer interrupt
2131  */
2132 int cp0_compare_irq;
2133 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2134 int cp0_compare_irq_shift;
2135 
2136 /*
2137  * Performance counter IRQ or -1 if shared with timer
2138  */
2139 int cp0_perfcount_irq;
2140 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2141 
2142 /*
2143  * Fast debug channel IRQ or -1 if not present
2144  */
2145 int cp0_fdc_irq;
2146 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2147 
2148 static int noulri;
2149 
ulri_disable(char * s)2150 static int __init ulri_disable(char *s)
2151 {
2152 	pr_info("Disabling ulri\n");
2153 	noulri = 1;
2154 
2155 	return 1;
2156 }
2157 __setup("noulri", ulri_disable);
2158 
2159 /* configure STATUS register */
configure_status(void)2160 static void configure_status(void)
2161 {
2162 	/*
2163 	 * Disable coprocessors and select 32-bit or 64-bit addressing
2164 	 * and the 16/32 or 32/32 FPR register model.  Reset the BEV
2165 	 * flag that some firmware may have left set and the TS bit (for
2166 	 * IP27).  Set XX for ISA IV code to work.
2167 	 */
2168 	unsigned int status_set = ST0_KERNEL_CUMASK;
2169 #ifdef CONFIG_64BIT
2170 	status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2171 #endif
2172 	if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2173 		status_set |= ST0_XX;
2174 	if (cpu_has_dsp)
2175 		status_set |= ST0_MX;
2176 
2177 	change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2178 			 status_set);
2179 	back_to_back_c0_hazard();
2180 }
2181 
2182 unsigned int hwrena;
2183 EXPORT_SYMBOL_GPL(hwrena);
2184 
2185 /* configure HWRENA register */
configure_hwrena(void)2186 static void configure_hwrena(void)
2187 {
2188 	hwrena = cpu_hwrena_impl_bits;
2189 
2190 	if (cpu_has_mips_r2_r6)
2191 		hwrena |= MIPS_HWRENA_CPUNUM |
2192 			  MIPS_HWRENA_SYNCISTEP |
2193 			  MIPS_HWRENA_CC |
2194 			  MIPS_HWRENA_CCRES;
2195 
2196 	if (!noulri && cpu_has_userlocal)
2197 		hwrena |= MIPS_HWRENA_ULR;
2198 
2199 	if (hwrena)
2200 		write_c0_hwrena(hwrena);
2201 }
2202 
configure_exception_vector(void)2203 static void configure_exception_vector(void)
2204 {
2205 	if (cpu_has_mips_r2_r6) {
2206 		unsigned long sr = set_c0_status(ST0_BEV);
2207 		/* If available, use WG to set top bits of EBASE */
2208 		if (cpu_has_ebase_wg) {
2209 #ifdef CONFIG_64BIT
2210 			write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2211 #else
2212 			write_c0_ebase(ebase | MIPS_EBASE_WG);
2213 #endif
2214 		}
2215 		write_c0_ebase(ebase);
2216 		write_c0_status(sr);
2217 	}
2218 	if (cpu_has_veic || cpu_has_vint) {
2219 		/* Setting vector spacing enables EI/VI mode  */
2220 		change_c0_intctl(0x3e0, VECTORSPACING);
2221 	}
2222 	if (cpu_has_divec) {
2223 		if (cpu_has_mipsmt) {
2224 			unsigned int vpflags = dvpe();
2225 			set_c0_cause(CAUSEF_IV);
2226 			evpe(vpflags);
2227 		} else
2228 			set_c0_cause(CAUSEF_IV);
2229 	}
2230 }
2231 
per_cpu_trap_init(bool is_boot_cpu)2232 void per_cpu_trap_init(bool is_boot_cpu)
2233 {
2234 	unsigned int cpu = smp_processor_id();
2235 
2236 	configure_status();
2237 	configure_hwrena();
2238 
2239 	configure_exception_vector();
2240 
2241 	/*
2242 	 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2243 	 *
2244 	 *  o read IntCtl.IPTI to determine the timer interrupt
2245 	 *  o read IntCtl.IPPCI to determine the performance counter interrupt
2246 	 *  o read IntCtl.IPFDC to determine the fast debug channel interrupt
2247 	 */
2248 	if (cpu_has_mips_r2_r6) {
2249 		cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2250 		cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2251 		cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2252 		cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2253 		if (!cp0_fdc_irq)
2254 			cp0_fdc_irq = -1;
2255 
2256 	} else {
2257 		cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2258 		cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2259 		cp0_perfcount_irq = -1;
2260 		cp0_fdc_irq = -1;
2261 	}
2262 
2263 	if (cpu_has_mmid)
2264 		cpu_data[cpu].asid_cache = 0;
2265 	else if (!cpu_data[cpu].asid_cache)
2266 		cpu_data[cpu].asid_cache = asid_first_version(cpu);
2267 
2268 	mmgrab(&init_mm);
2269 	current->active_mm = &init_mm;
2270 	BUG_ON(current->mm);
2271 	enter_lazy_tlb(&init_mm, current);
2272 
2273 	/* Boot CPU's cache setup in setup_arch(). */
2274 	if (!is_boot_cpu)
2275 		cpu_cache_init();
2276 	tlb_init();
2277 	TLBMISS_HANDLER_SETUP();
2278 }
2279 
2280 /* Install CPU exception handler */
set_handler(unsigned long offset,const void * addr,unsigned long size)2281 void set_handler(unsigned long offset, const void *addr, unsigned long size)
2282 {
2283 #ifdef CONFIG_CPU_MICROMIPS
2284 	memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2285 #else
2286 	memcpy((void *)(ebase + offset), addr, size);
2287 #endif
2288 	local_flush_icache_range(ebase + offset, ebase + offset + size);
2289 }
2290 
2291 static const char panic_null_cerr[] =
2292 	"Trying to set NULL cache error exception handler\n";
2293 
2294 /*
2295  * Install uncached CPU exception handler.
2296  * This is suitable only for the cache error exception which is the only
2297  * exception handler that is being run uncached.
2298  */
set_uncached_handler(unsigned long offset,void * addr,unsigned long size)2299 void set_uncached_handler(unsigned long offset, void *addr,
2300 	unsigned long size)
2301 {
2302 	unsigned long uncached_ebase = CKSEG1ADDR_OR_64BIT(__pa(ebase));
2303 
2304 	if (!addr)
2305 		panic(panic_null_cerr);
2306 
2307 	memcpy((void *)(uncached_ebase + offset), addr, size);
2308 }
2309 
2310 static int __initdata rdhwr_noopt;
set_rdhwr_noopt(char * str)2311 static int __init set_rdhwr_noopt(char *str)
2312 {
2313 	rdhwr_noopt = 1;
2314 	return 1;
2315 }
2316 
2317 __setup("rdhwr_noopt", set_rdhwr_noopt);
2318 
trap_init(void)2319 void __init trap_init(void)
2320 {
2321 	extern char except_vec3_generic;
2322 	extern char except_vec4;
2323 	extern char except_vec3_r4000;
2324 	unsigned long i, vec_size;
2325 	phys_addr_t ebase_pa;
2326 
2327 	check_wait();
2328 
2329 	if (!cpu_has_mips_r2_r6) {
2330 		ebase = CAC_BASE;
2331 		vec_size = 0x400;
2332 	} else {
2333 		if (cpu_has_veic || cpu_has_vint)
2334 			vec_size = 0x200 + VECTORSPACING*64;
2335 		else
2336 			vec_size = PAGE_SIZE;
2337 
2338 		ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
2339 		if (!ebase_pa)
2340 			panic("%s: Failed to allocate %lu bytes align=0x%x\n",
2341 			      __func__, vec_size, 1 << fls(vec_size));
2342 
2343 		/*
2344 		 * Try to ensure ebase resides in KSeg0 if possible.
2345 		 *
2346 		 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2347 		 * hitting a poorly defined exception base for Cache Errors.
2348 		 * The allocation is likely to be in the low 512MB of physical,
2349 		 * in which case we should be able to convert to KSeg0.
2350 		 *
2351 		 * EVA is special though as it allows segments to be rearranged
2352 		 * and to become uncached during cache error handling.
2353 		 */
2354 		if (!IS_ENABLED(CONFIG_EVA) && ebase_pa < 0x20000000)
2355 			ebase = CKSEG0ADDR(ebase_pa);
2356 		else
2357 			ebase = (unsigned long)phys_to_virt(ebase_pa);
2358 		if (ebase_pa >= 0x20000000)
2359 			pr_warn("ebase(%pa) should better be in KSeg0",
2360 				&ebase_pa);
2361 	}
2362 
2363 	if (cpu_has_mmips) {
2364 		unsigned int config3 = read_c0_config3();
2365 
2366 		if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2367 			write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2368 		else
2369 			write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2370 	}
2371 
2372 	if (board_ebase_setup)
2373 		board_ebase_setup();
2374 	per_cpu_trap_init(true);
2375 	memblock_set_bottom_up(false);
2376 
2377 	/*
2378 	 * Copy the generic exception handlers to their final destination.
2379 	 * This will be overridden later as suitable for a particular
2380 	 * configuration.
2381 	 */
2382 	set_handler(0x180, &except_vec3_generic, 0x80);
2383 
2384 	/*
2385 	 * Setup default vectors
2386 	 */
2387 	for (i = 0; i <= 31; i++)
2388 		set_except_vector(i, handle_reserved);
2389 
2390 	/*
2391 	 * Copy the EJTAG debug exception vector handler code to its final
2392 	 * destination.
2393 	 */
2394 	if (cpu_has_ejtag && board_ejtag_handler_setup)
2395 		board_ejtag_handler_setup();
2396 
2397 	/*
2398 	 * Only some CPUs have the watch exceptions.
2399 	 */
2400 	if (cpu_has_watch)
2401 		set_except_vector(EXCCODE_WATCH, handle_watch);
2402 
2403 	/*
2404 	 * Initialise interrupt handlers
2405 	 */
2406 	if (cpu_has_veic || cpu_has_vint) {
2407 		int nvec = cpu_has_veic ? 64 : 8;
2408 		for (i = 0; i < nvec; i++)
2409 			set_vi_handler(i, NULL);
2410 	}
2411 	else if (cpu_has_divec)
2412 		set_handler(0x200, &except_vec4, 0x8);
2413 
2414 	/*
2415 	 * Some CPUs can enable/disable for cache parity detection, but does
2416 	 * it different ways.
2417 	 */
2418 	parity_protection_init();
2419 
2420 	/*
2421 	 * The Data Bus Errors / Instruction Bus Errors are signaled
2422 	 * by external hardware.  Therefore these two exceptions
2423 	 * may have board specific handlers.
2424 	 */
2425 	if (board_be_init)
2426 		board_be_init();
2427 
2428 	set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2429 					rollback_handle_int : handle_int);
2430 	set_except_vector(EXCCODE_MOD, handle_tlbm);
2431 	set_except_vector(EXCCODE_TLBL, handle_tlbl);
2432 	set_except_vector(EXCCODE_TLBS, handle_tlbs);
2433 
2434 	set_except_vector(EXCCODE_ADEL, handle_adel);
2435 	set_except_vector(EXCCODE_ADES, handle_ades);
2436 
2437 	set_except_vector(EXCCODE_IBE, handle_ibe);
2438 	set_except_vector(EXCCODE_DBE, handle_dbe);
2439 
2440 	set_except_vector(EXCCODE_SYS, handle_sys);
2441 	set_except_vector(EXCCODE_BP, handle_bp);
2442 
2443 	if (rdhwr_noopt)
2444 		set_except_vector(EXCCODE_RI, handle_ri);
2445 	else {
2446 		if (cpu_has_vtag_icache)
2447 			set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2448 		else if (current_cpu_type() == CPU_LOONGSON64)
2449 			set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2450 		else
2451 			set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2452 	}
2453 
2454 	set_except_vector(EXCCODE_CPU, handle_cpu);
2455 	set_except_vector(EXCCODE_OV, handle_ov);
2456 	set_except_vector(EXCCODE_TR, handle_tr);
2457 	set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2458 
2459 	if (board_nmi_handler_setup)
2460 		board_nmi_handler_setup();
2461 
2462 	if (cpu_has_fpu && !cpu_has_nofpuex)
2463 		set_except_vector(EXCCODE_FPE, handle_fpe);
2464 
2465 	if (cpu_has_ftlbparex)
2466 		set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2467 
2468 	if (cpu_has_gsexcex)
2469 		set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc);
2470 
2471 	if (cpu_has_rixiex) {
2472 		set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2473 		set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2474 	}
2475 
2476 	set_except_vector(EXCCODE_MSADIS, handle_msa);
2477 	set_except_vector(EXCCODE_MDMX, handle_mdmx);
2478 
2479 	if (cpu_has_mcheck)
2480 		set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2481 
2482 	if (cpu_has_mipsmt)
2483 		set_except_vector(EXCCODE_THREAD, handle_mt);
2484 
2485 	set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2486 
2487 	if (board_cache_error_setup)
2488 		board_cache_error_setup();
2489 
2490 	if (cpu_has_vce)
2491 		/* Special exception: R4[04]00 uses also the divec space. */
2492 		set_handler(0x180, &except_vec3_r4000, 0x100);
2493 	else if (cpu_has_4kex)
2494 		set_handler(0x180, &except_vec3_generic, 0x80);
2495 	else
2496 		set_handler(0x080, &except_vec3_generic, 0x80);
2497 
2498 	local_flush_icache_range(ebase, ebase + vec_size);
2499 
2500 	sort_extable(__start___dbe_table, __stop___dbe_table);
2501 
2502 	cu2_notifier(default_cu2_call, 0x80000000);	/* Run last  */
2503 }
2504 
trap_pm_notifier(struct notifier_block * self,unsigned long cmd,void * v)2505 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2506 			    void *v)
2507 {
2508 	switch (cmd) {
2509 	case CPU_PM_ENTER_FAILED:
2510 	case CPU_PM_EXIT:
2511 		configure_status();
2512 		configure_hwrena();
2513 		configure_exception_vector();
2514 
2515 		/* Restore register with CPU number for TLB handlers */
2516 		TLBMISS_HANDLER_RESTORE();
2517 
2518 		break;
2519 	}
2520 
2521 	return NOTIFY_OK;
2522 }
2523 
2524 static struct notifier_block trap_pm_notifier_block = {
2525 	.notifier_call = trap_pm_notifier,
2526 };
2527 
trap_pm_init(void)2528 static int __init trap_pm_init(void)
2529 {
2530 	return cpu_pm_register_notifier(&trap_pm_notifier_block);
2531 }
2532 arch_initcall(trap_pm_init);
2533