1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 4 #include <linux/component.h> 5 #include <linux/delay.h> 6 #include <linux/device.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/slab.h> 16 #include <sound/jack.h> 17 #include <sound/pcm_params.h> 18 #include <sound/pcm.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #include "wcd-clsh-v2.h" 24 #include "wcd-common.h" 25 #include "wcd-mbhc-v2.h" 26 #include "wcd937x.h" 27 28 #define CHIPID_WCD9370 0x0 29 #define CHIPID_WCD9375 0x5 30 31 /* Z value defined in milliohm */ 32 #define WCD937X_ZDET_VAL_32 (32000) 33 #define WCD937X_ZDET_VAL_400 (400000) 34 #define WCD937X_ZDET_VAL_1200 (1200000) 35 #define WCD937X_ZDET_VAL_100K (100000000) 36 /* Z floating defined in ohms */ 37 #define WCD937X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 38 #define WCD937X_ZDET_NUM_MEASUREMENTS (900) 39 #define WCD937X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14) 40 #define WCD937X_MBHC_GET_X1(x) ((x) & 0x3FFF) 41 /* Z value compared in milliOhm */ 42 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z) (((z) > 400000) || ((z) < 32000)) 43 #define WCD937X_MBHC_ZDET_CONST (86 * 16384) 44 #define WCD937X_MBHC_MOISTURE_RREF R_24_KOHM 45 #define WCD_MBHC_HS_V_MAX 1600 46 #define EAR_RX_PATH_AUX 1 47 #define WCD937X_MBHC_MAX_BUTTONS 8 48 49 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 50 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 51 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 52 SNDRV_PCM_RATE_384000) 53 54 /* Fractional Rates */ 55 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 56 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 57 58 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 59 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 60 61 enum { 62 ALLOW_BUCK_DISABLE, 63 HPH_COMP_DELAY, 64 HPH_PA_DELAY, 65 AMIC2_BCS_ENABLE, 66 }; 67 68 enum { 69 AIF1_PB = 0, 70 AIF1_CAP, 71 NUM_CODEC_DAIS, 72 }; 73 74 struct wcd937x_priv { 75 struct sdw_slave *tx_sdw_dev; 76 struct wcd937x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 77 struct device *txdev; 78 struct device *rxdev; 79 struct device_node *rxnode; 80 struct device_node *txnode; 81 struct regmap *regmap; 82 /* micb setup lock */ 83 struct mutex micb_lock; 84 /* mbhc module */ 85 struct wcd_mbhc *wcd_mbhc; 86 struct wcd_mbhc_config mbhc_cfg; 87 struct wcd_mbhc_intr intr_ids; 88 struct wcd_clsh_ctrl *clsh_info; 89 struct wcd_common common; 90 struct irq_domain *virq; 91 struct regmap_irq_chip_data *irq_chip; 92 struct snd_soc_jack *jack; 93 unsigned long status_mask; 94 s32 micb_ref[WCD937X_MAX_MICBIAS]; 95 s32 pullup_ref[WCD937X_MAX_MICBIAS]; 96 u32 hph_mode; 97 int ear_rx_path; 98 int hphr_pdm_wd_int; 99 int hphl_pdm_wd_int; 100 int aux_pdm_wd_int; 101 bool comp1_enable; 102 bool comp2_enable; 103 104 struct gpio_desc *us_euro_gpio; 105 struct gpio_desc *reset_gpio; 106 107 atomic_t rx_clk_cnt; 108 atomic_t ana_clk_count; 109 }; 110 111 static const char * const wcd937x_supplies[] = { 112 "vdd-rxtx", "vdd-px", "vdd-mic-bias", "vdd-buck", 113 }; 114 115 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 116 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 117 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 118 119 struct wcd937x_mbhc_zdet_param { 120 u16 ldo_ctl; 121 u16 noff; 122 u16 nshift; 123 u16 btn5; 124 u16 btn6; 125 u16 btn7; 126 }; 127 128 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 129 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD937X_ANA_MBHC_MECH, 0x80), 130 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD937X_ANA_MBHC_MECH, 0x40), 131 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD937X_ANA_MBHC_MECH, 0x20), 132 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 133 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD937X_ANA_MBHC_ELECT, 0x08), 134 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 135 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD937X_ANA_MBHC_MECH, 0x04), 136 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x10), 137 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x08), 138 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD937X_ANA_MBHC_MECH, 0x01), 139 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD937X_ANA_MBHC_ELECT, 0x06), 140 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937X_ANA_MBHC_ELECT, 0x80), 141 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 142 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD937X_MBHC_NEW_CTL_1, 0x03), 143 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD937X_MBHC_NEW_CTL_2, 0x03), 144 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x08), 145 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 146 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x20), 147 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x80), 148 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x40), 149 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD937X_HPH_OCP_CTL, 0x10), 150 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x07), 151 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD937X_ANA_MBHC_ELECT, 0x70), 152 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0xFF), 153 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD937X_ANA_MICB2, 0xC0), 154 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD937X_HPH_CNP_WG_TIME, 0xFF), 155 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD937X_ANA_HPH, 0x40), 156 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD937X_ANA_HPH, 0x80), 157 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD937X_ANA_HPH, 0xC0), 158 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 159 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD937X_MBHC_CTL_BCS, 0x02), 160 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x01), 161 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD937X_MBHC_NEW_CTL_2, 0x70), 162 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x20), 163 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD937X_HPH_PA_CTL2, 0x40), 164 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD937X_HPH_PA_CTL2, 0x10), 165 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD937X_HPH_L_TEST, 0x01), 166 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD937X_HPH_R_TEST, 0x01), 167 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x80), 168 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x20), 169 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937X_MBHC_NEW_CTL_1, 0x08), 170 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD937X_MBHC_NEW_FSM_STATUS, 0x40), 171 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD937X_MBHC_NEW_FSM_STATUS, 0x80), 172 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD937X_MBHC_NEW_ADC_RESULT, 0xFF), 173 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD937X_ANA_MICB2, 0x3F), 174 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD937X_MBHC_NEW_CTL_1, 0x10), 175 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD937X_MBHC_NEW_CTL_1, 0x04), 176 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD937X_ANA_MBHC_ZDET, 0x02), 177 }; 178 179 static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = { 180 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, BIT(0)), 181 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, BIT(1)), 182 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, BIT(2)), 183 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, BIT(3)), 184 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, BIT(4)), 185 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, BIT(5)), 186 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, BIT(6)), 187 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, BIT(7)), 188 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, BIT(0)), 189 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, BIT(1)), 190 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, BIT(2)), 191 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, BIT(3)), 192 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, BIT(4)), 193 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, BIT(5)), 194 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, BIT(6)), 195 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, BIT(7)), 196 REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, BIT(0)), 197 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, BIT(1)), 198 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, BIT(2)), 199 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, BIT(3)), 200 }; 201 202 static int wcd937x_handle_post_irq(void *data) 203 { 204 struct wcd937x_priv *wcd937x; 205 206 if (data) 207 wcd937x = (struct wcd937x_priv *)data; 208 else 209 return IRQ_HANDLED; 210 211 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0); 212 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0); 213 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0); 214 215 return IRQ_HANDLED; 216 } 217 218 static const u32 wcd937x_config_regs[] = { 219 WCD937X_DIGITAL_INTR_LEVEL_0, 220 }; 221 222 static const struct regmap_irq_chip wcd937x_regmap_irq_chip = { 223 .name = "wcd937x", 224 .irqs = wcd937x_irqs, 225 .num_irqs = ARRAY_SIZE(wcd937x_irqs), 226 .num_regs = 3, 227 .status_base = WCD937X_DIGITAL_INTR_STATUS_0, 228 .mask_base = WCD937X_DIGITAL_INTR_MASK_0, 229 .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0, 230 .use_ack = 1, 231 .clear_ack = 1, 232 .config_base = wcd937x_config_regs, 233 .num_config_bases = ARRAY_SIZE(wcd937x_config_regs), 234 .num_config_regs = 1, 235 .runtime_pm = true, 236 .handle_post_irq = wcd937x_handle_post_irq, 237 .irq_drv_data = NULL, 238 }; 239 240 static void wcd937x_reset(struct wcd937x_priv *wcd937x) 241 { 242 gpiod_set_value(wcd937x->reset_gpio, 1); 243 usleep_range(20, 30); 244 gpiod_set_value(wcd937x->reset_gpio, 0); 245 usleep_range(20, 30); 246 } 247 248 static void wcd937x_io_init(struct regmap *regmap) 249 { 250 u32 val = 0, temp = 0, temp1 = 0; 251 252 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_29, &val); 253 254 val = val & 0x0F; 255 256 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &temp); 257 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_17, &temp1); 258 259 if (temp == 0x02 || temp1 > 0x09) 260 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0E, val); 261 else 262 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0e, 0x0e); 263 264 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x80, 0x80); 265 usleep_range(1000, 1010); 266 267 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x40, 0x40); 268 usleep_range(1000, 1010); 269 270 regmap_update_bits(regmap, WCD937X_LDORXTX_CONFIG, BIT(4), 0x00); 271 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xf0, BIT(7)); 272 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(7), BIT(7)); 273 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), BIT(6)); 274 usleep_range(10000, 10010); 275 276 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), 0x00); 277 regmap_update_bits(regmap, WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xff, 0xd9); 278 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_1, 0xff, 0xfa); 279 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_1, 0xff, 0xfa); 280 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_1, 0xff, 0xfa); 281 282 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_2, 0x38, 0x00); 283 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_2, 0x38, 0x00); 284 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_2, 0x38, 0x00); 285 286 /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ 287 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &val); 288 if (val == 0x01) { 289 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 290 } else if (val == 0x02) { 291 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); 292 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); 293 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 294 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50); 295 } 296 } 297 298 static int wcd937x_rx_clk_enable(struct snd_soc_component *component) 299 { 300 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 301 302 if (atomic_read(&wcd937x->rx_clk_cnt)) 303 return 0; 304 305 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(3), BIT(3)); 306 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), BIT(0)); 307 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), BIT(0)); 308 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX0_CTL, BIT(6), 0x00); 309 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX1_CTL, BIT(6), 0x00); 310 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX2_CTL, BIT(6), 0x00); 311 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), BIT(1)); 312 313 atomic_inc(&wcd937x->rx_clk_cnt); 314 315 return 0; 316 } 317 318 static int wcd937x_rx_clk_disable(struct snd_soc_component *component) 319 { 320 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 321 322 if (!atomic_read(&wcd937x->rx_clk_cnt)) { 323 dev_err(component->dev, "clk already disabled\n"); 324 return 0; 325 } 326 327 atomic_dec(&wcd937x->rx_clk_cnt); 328 329 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), 0x00); 330 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), 0x00); 331 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), 0x00); 332 333 return 0; 334 } 335 336 static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 337 struct snd_kcontrol *kcontrol, 338 int event) 339 { 340 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 341 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 342 int hph_mode = wcd937x->hph_mode; 343 344 switch (event) { 345 case SND_SOC_DAPM_PRE_PMU: 346 wcd937x_rx_clk_enable(component); 347 snd_soc_component_update_bits(component, 348 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 349 BIT(0), BIT(0)); 350 snd_soc_component_update_bits(component, 351 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 352 BIT(2), BIT(2)); 353 snd_soc_component_update_bits(component, 354 WCD937X_HPH_RDAC_CLK_CTL1, 355 BIT(7), 0x00); 356 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 357 break; 358 case SND_SOC_DAPM_POST_PMU: 359 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 360 snd_soc_component_update_bits(component, 361 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 362 0x0f, BIT(1)); 363 else if (hph_mode == CLS_H_LOHIFI) 364 snd_soc_component_update_bits(component, 365 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 366 0x0f, 0x06); 367 368 if (wcd937x->comp1_enable) { 369 snd_soc_component_update_bits(component, 370 WCD937X_DIGITAL_CDC_COMP_CTL_0, 371 BIT(1), BIT(1)); 372 snd_soc_component_update_bits(component, 373 WCD937X_HPH_L_EN, 374 BIT(5), 0x00); 375 376 if (wcd937x->comp2_enable) { 377 snd_soc_component_update_bits(component, 378 WCD937X_DIGITAL_CDC_COMP_CTL_0, 379 BIT(0), BIT(0)); 380 snd_soc_component_update_bits(component, 381 WCD937X_HPH_R_EN, BIT(5), 0x00); 382 } 383 384 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 385 usleep_range(5000, 5110); 386 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 387 } 388 } else { 389 snd_soc_component_update_bits(component, 390 WCD937X_DIGITAL_CDC_COMP_CTL_0, 391 BIT(1), 0x00); 392 snd_soc_component_update_bits(component, 393 WCD937X_HPH_L_EN, 394 BIT(5), BIT(5)); 395 } 396 397 snd_soc_component_update_bits(component, 398 WCD937X_HPH_NEW_INT_HPH_TIMER1, 399 BIT(1), 0x00); 400 break; 401 case SND_SOC_DAPM_POST_PMD: 402 snd_soc_component_update_bits(component, 403 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 404 0x0f, BIT(0)); 405 break; 406 } 407 408 return 0; 409 } 410 411 static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 412 struct snd_kcontrol *kcontrol, 413 int event) 414 { 415 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 416 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 417 int hph_mode = wcd937x->hph_mode; 418 419 switch (event) { 420 case SND_SOC_DAPM_PRE_PMU: 421 wcd937x_rx_clk_enable(component); 422 snd_soc_component_update_bits(component, 423 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(1), BIT(1)); 424 snd_soc_component_update_bits(component, 425 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, BIT(3), BIT(3)); 426 snd_soc_component_update_bits(component, 427 WCD937X_HPH_RDAC_CLK_CTL1, BIT(7), 0x00); 428 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 429 break; 430 case SND_SOC_DAPM_POST_PMU: 431 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 432 snd_soc_component_update_bits(component, 433 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 434 0x0f, BIT(1)); 435 else if (hph_mode == CLS_H_LOHIFI) 436 snd_soc_component_update_bits(component, 437 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 438 0x0f, 0x06); 439 if (wcd937x->comp2_enable) { 440 snd_soc_component_update_bits(component, 441 WCD937X_DIGITAL_CDC_COMP_CTL_0, 442 BIT(0), BIT(0)); 443 snd_soc_component_update_bits(component, 444 WCD937X_HPH_R_EN, BIT(5), 0x00); 445 if (wcd937x->comp1_enable) { 446 snd_soc_component_update_bits(component, 447 WCD937X_DIGITAL_CDC_COMP_CTL_0, 448 BIT(1), BIT(1)); 449 snd_soc_component_update_bits(component, 450 WCD937X_HPH_L_EN, 451 BIT(5), 0x00); 452 } 453 454 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 455 usleep_range(5000, 5110); 456 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 457 } 458 } else { 459 snd_soc_component_update_bits(component, 460 WCD937X_DIGITAL_CDC_COMP_CTL_0, 461 BIT(0), 0x00); 462 snd_soc_component_update_bits(component, 463 WCD937X_HPH_R_EN, 464 BIT(5), BIT(5)); 465 } 466 snd_soc_component_update_bits(component, 467 WCD937X_HPH_NEW_INT_HPH_TIMER1, 468 BIT(1), 0x00); 469 break; 470 case SND_SOC_DAPM_POST_PMD: 471 snd_soc_component_update_bits(component, 472 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 473 0x0f, BIT(0)); 474 break; 475 } 476 477 return 0; 478 } 479 480 static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 481 struct snd_kcontrol *kcontrol, 482 int event) 483 { 484 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 485 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 486 int hph_mode = wcd937x->hph_mode; 487 488 switch (event) { 489 case SND_SOC_DAPM_PRE_PMU: 490 wcd937x_rx_clk_enable(component); 491 snd_soc_component_update_bits(component, 492 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 493 BIT(2), BIT(2)); 494 snd_soc_component_update_bits(component, 495 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 496 BIT(0), BIT(0)); 497 498 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 499 snd_soc_component_update_bits(component, 500 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 501 0x0f, BIT(1)); 502 else if (hph_mode == CLS_H_LOHIFI) 503 snd_soc_component_update_bits(component, 504 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 505 0x0f, 0x06); 506 if (wcd937x->comp1_enable) 507 snd_soc_component_update_bits(component, 508 WCD937X_DIGITAL_CDC_COMP_CTL_0, 509 BIT(1), BIT(1)); 510 usleep_range(5000, 5010); 511 512 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, BIT(2), 0x00); 513 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 514 WCD_CLSH_EVENT_PRE_DAC, 515 WCD_CLSH_STATE_EAR, 516 hph_mode); 517 518 break; 519 case SND_SOC_DAPM_POST_PMD: 520 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI || 521 hph_mode == CLS_H_HIFI) 522 snd_soc_component_update_bits(component, 523 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 524 0x0f, BIT(0)); 525 if (wcd937x->comp1_enable) 526 snd_soc_component_update_bits(component, 527 WCD937X_DIGITAL_CDC_COMP_CTL_0, 528 BIT(1), 0x00); 529 break; 530 } 531 532 return 0; 533 } 534 535 static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 536 struct snd_kcontrol *kcontrol, 537 int event) 538 { 539 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 540 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 541 int hph_mode = wcd937x->hph_mode; 542 543 switch (event) { 544 case SND_SOC_DAPM_PRE_PMU: 545 wcd937x_rx_clk_enable(component); 546 snd_soc_component_update_bits(component, 547 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 548 BIT(2), BIT(2)); 549 snd_soc_component_update_bits(component, 550 WCD937X_AUX_AUXPA, 551 BIT(4), BIT(4)); 552 snd_soc_component_update_bits(component, 553 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 554 BIT(2), BIT(2)); 555 snd_soc_component_update_bits(component, 556 WCD937X_DIGITAL_CDC_AUX_GAIN_CTL, 557 BIT(0), BIT(0)); 558 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 559 WCD_CLSH_EVENT_PRE_DAC, 560 WCD_CLSH_STATE_AUX, 561 hph_mode); 562 563 break; 564 case SND_SOC_DAPM_POST_PMD: 565 snd_soc_component_update_bits(component, 566 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 567 BIT(2), 0x00); 568 snd_soc_component_update_bits(component, 569 WCD937X_AUX_AUXPA, 570 BIT(4), 0x00); 571 break; 572 } 573 574 return 0; 575 } 576 577 static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 578 struct snd_kcontrol *kcontrol, 579 int event) 580 { 581 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 582 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 583 int hph_mode = wcd937x->hph_mode; 584 585 switch (event) { 586 case SND_SOC_DAPM_PRE_PMU: 587 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 588 WCD_CLSH_EVENT_PRE_DAC, 589 WCD_CLSH_STATE_HPHR, 590 hph_mode); 591 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 592 BIT(4), BIT(4)); 593 usleep_range(100, 110); 594 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 595 snd_soc_component_update_bits(component, 596 WCD937X_DIGITAL_PDM_WD_CTL1, 597 0x07, 0x03); 598 break; 599 case SND_SOC_DAPM_POST_PMU: 600 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 601 if (wcd937x->comp2_enable) 602 usleep_range(7000, 7100); 603 else 604 usleep_range(20000, 20100); 605 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 606 } 607 608 snd_soc_component_update_bits(component, 609 WCD937X_HPH_NEW_INT_HPH_TIMER1, 610 BIT(1), BIT(1)); 611 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 612 snd_soc_component_update_bits(component, 613 WCD937X_ANA_RX_SUPPLIES, 614 BIT(1), BIT(1)); 615 enable_irq(wcd937x->hphr_pdm_wd_int); 616 break; 617 case SND_SOC_DAPM_PRE_PMD: 618 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 619 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 620 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 621 break; 622 case SND_SOC_DAPM_POST_PMD: 623 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 624 if (wcd937x->comp2_enable) 625 usleep_range(7000, 7100); 626 else 627 usleep_range(20000, 20100); 628 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 629 } 630 631 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 632 snd_soc_component_update_bits(component, 633 WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00); 634 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 635 BIT(4), 0x00); 636 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 637 WCD_CLSH_EVENT_POST_PA, 638 WCD_CLSH_STATE_HPHR, 639 hph_mode); 640 break; 641 } 642 643 return 0; 644 } 645 646 static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 647 struct snd_kcontrol *kcontrol, 648 int event) 649 { 650 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 651 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 652 int hph_mode = wcd937x->hph_mode; 653 654 switch (event) { 655 case SND_SOC_DAPM_PRE_PMU: 656 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 657 WCD_CLSH_EVENT_PRE_DAC, 658 WCD_CLSH_STATE_HPHL, 659 hph_mode); 660 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 661 BIT(5), BIT(5)); 662 usleep_range(100, 110); 663 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 664 snd_soc_component_update_bits(component, 665 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03); 666 break; 667 case SND_SOC_DAPM_POST_PMU: 668 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 669 if (!wcd937x->comp1_enable) 670 usleep_range(20000, 20100); 671 else 672 usleep_range(7000, 7100); 673 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 674 } 675 676 snd_soc_component_update_bits(component, 677 WCD937X_HPH_NEW_INT_HPH_TIMER1, 678 BIT(1), BIT(1)); 679 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 680 snd_soc_component_update_bits(component, 681 WCD937X_ANA_RX_SUPPLIES, 682 BIT(1), BIT(1)); 683 enable_irq(wcd937x->hphl_pdm_wd_int); 684 break; 685 case SND_SOC_DAPM_PRE_PMD: 686 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 687 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 688 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 689 break; 690 case SND_SOC_DAPM_POST_PMD: 691 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 692 if (!wcd937x->comp1_enable) 693 usleep_range(20000, 20100); 694 else 695 usleep_range(7000, 7100); 696 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 697 } 698 699 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 700 snd_soc_component_update_bits(component, 701 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00); 702 snd_soc_component_update_bits(component, 703 WCD937X_ANA_HPH, BIT(5), 0x00); 704 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 705 WCD_CLSH_EVENT_POST_PA, 706 WCD_CLSH_STATE_HPHL, 707 hph_mode); 708 break; 709 } 710 711 return 0; 712 } 713 714 static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 715 struct snd_kcontrol *kcontrol, 716 int event) 717 { 718 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 719 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 720 int hph_mode = wcd937x->hph_mode; 721 u8 val; 722 723 switch (event) { 724 case SND_SOC_DAPM_PRE_PMU: 725 val = WCD937X_DIGITAL_PDM_WD_CTL2_EN | 726 WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL | 727 WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF; 728 snd_soc_component_update_bits(component, 729 WCD937X_DIGITAL_PDM_WD_CTL2, 730 WCD937X_DIGITAL_PDM_WD_CTL2_MASK, 731 val); 732 break; 733 case SND_SOC_DAPM_POST_PMU: 734 usleep_range(1000, 1010); 735 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 736 snd_soc_component_update_bits(component, 737 WCD937X_ANA_RX_SUPPLIES, 738 BIT(1), BIT(1)); 739 /* Enable AUX PA related RX supplies */ 740 snd_soc_component_update_bits(component, 741 WCD937X_ANA_RX_SUPPLIES, 742 BIT(6), BIT(6)); 743 snd_soc_component_update_bits(component, 744 WCD937X_ANA_RX_SUPPLIES, 745 BIT(7), BIT(7)); 746 enable_irq(wcd937x->aux_pdm_wd_int); 747 break; 748 case SND_SOC_DAPM_PRE_PMD: 749 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 750 snd_soc_component_update_bits(component, 751 WCD937X_ANA_RX_SUPPLIES, 752 BIT(6), 0x00); 753 snd_soc_component_update_bits(component, 754 WCD937X_ANA_RX_SUPPLIES, 755 BIT(7), 0x00); 756 break; 757 case SND_SOC_DAPM_POST_PMD: 758 usleep_range(2000, 2010); 759 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 760 WCD_CLSH_EVENT_POST_PA, 761 WCD_CLSH_STATE_AUX, 762 hph_mode); 763 snd_soc_component_update_bits(component, 764 WCD937X_DIGITAL_PDM_WD_CTL2, 765 WCD937X_DIGITAL_PDM_WD_CTL2_MASK, 766 0x00); 767 break; 768 } 769 770 return 0; 771 } 772 773 static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 774 struct snd_kcontrol *kcontrol, 775 int event) 776 { 777 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 778 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 779 int hph_mode = wcd937x->hph_mode; 780 781 switch (event) { 782 case SND_SOC_DAPM_PRE_PMU: 783 /* Enable watchdog interrupt for HPHL or AUX depending on mux value */ 784 wcd937x->ear_rx_path = snd_soc_component_read(component, 785 WCD937X_DIGITAL_CDC_EAR_PATH_CTL); 786 787 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 788 snd_soc_component_update_bits(component, 789 WCD937X_DIGITAL_PDM_WD_CTL2, 790 BIT(0), BIT(0)); 791 else 792 snd_soc_component_update_bits(component, 793 WCD937X_DIGITAL_PDM_WD_CTL0, 794 0x07, 0x03); 795 if (!wcd937x->comp1_enable) 796 snd_soc_component_update_bits(component, 797 WCD937X_ANA_EAR_COMPANDER_CTL, 798 BIT(7), BIT(7)); 799 break; 800 case SND_SOC_DAPM_POST_PMU: 801 usleep_range(6000, 6010); 802 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 803 snd_soc_component_update_bits(component, 804 WCD937X_ANA_RX_SUPPLIES, 805 BIT(1), BIT(1)); 806 807 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 808 enable_irq(wcd937x->aux_pdm_wd_int); 809 else 810 enable_irq(wcd937x->hphl_pdm_wd_int); 811 break; 812 case SND_SOC_DAPM_PRE_PMD: 813 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 814 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 815 else 816 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 817 break; 818 case SND_SOC_DAPM_POST_PMD: 819 if (!wcd937x->comp1_enable) 820 snd_soc_component_update_bits(component, 821 WCD937X_ANA_EAR_COMPANDER_CTL, 822 BIT(7), 0x00); 823 usleep_range(7000, 7010); 824 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 825 WCD_CLSH_EVENT_POST_PA, 826 WCD_CLSH_STATE_EAR, 827 hph_mode); 828 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, 829 BIT(2), BIT(2)); 830 831 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 832 snd_soc_component_update_bits(component, 833 WCD937X_DIGITAL_PDM_WD_CTL2, 834 BIT(0), 0x00); 835 else 836 snd_soc_component_update_bits(component, 837 WCD937X_DIGITAL_PDM_WD_CTL0, 838 0x07, 0x00); 839 break; 840 } 841 842 return 0; 843 } 844 845 static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w, 846 struct snd_kcontrol *kcontrol, 847 int event) 848 { 849 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 850 851 if (event == SND_SOC_DAPM_POST_PMD) { 852 wcd937x_rx_clk_disable(component); 853 snd_soc_component_update_bits(component, 854 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 855 BIT(0), 0x00); 856 } 857 858 return 0; 859 } 860 861 static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w, 862 struct snd_kcontrol *kcontrol, int event) 863 { 864 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 865 866 if (event == SND_SOC_DAPM_POST_PMD) { 867 wcd937x_rx_clk_disable(component); 868 snd_soc_component_update_bits(component, 869 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 870 BIT(1), 0x00); 871 } 872 873 return 0; 874 } 875 876 static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w, 877 struct snd_kcontrol *kcontrol, 878 int event) 879 { 880 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 881 882 if (event == SND_SOC_DAPM_POST_PMD) { 883 usleep_range(6000, 6010); 884 wcd937x_rx_clk_disable(component); 885 snd_soc_component_update_bits(component, 886 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 887 BIT(2), 0x00); 888 } 889 890 return 0; 891 } 892 893 894 static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 895 struct snd_kcontrol *kcontrol, int event) 896 { 897 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 898 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 899 bool use_amic3 = snd_soc_component_read(component, WCD937X_TX_NEW_TX_CH2_SEL) & BIT(7); 900 901 /* Enable BCS for Headset mic */ 902 if (event == SND_SOC_DAPM_PRE_PMU && strnstr(w->name, "ADC", sizeof("ADC"))) 903 if (w->shift == 1 && !use_amic3) 904 set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 905 906 return 0; 907 } 908 909 static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w, 910 struct snd_kcontrol *kcontrol, int event) 911 { 912 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 913 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 914 915 switch (event) { 916 case SND_SOC_DAPM_PRE_PMU: 917 atomic_inc(&wcd937x->ana_clk_count); 918 snd_soc_component_update_bits(component, 919 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(7), BIT(7)); 920 snd_soc_component_update_bits(component, 921 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), BIT(3)); 922 snd_soc_component_update_bits(component, 923 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(4), BIT(4)); 924 break; 925 case SND_SOC_DAPM_POST_PMD: 926 if (w->shift == 1 && test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) 927 clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 928 929 snd_soc_component_update_bits(component, 930 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), 0x00); 931 break; 932 } 933 934 return 0; 935 } 936 937 static int wcd937x_enable_req(struct snd_soc_dapm_widget *w, 938 struct snd_kcontrol *kcontrol, int event) 939 { 940 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 941 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 942 943 switch (event) { 944 case SND_SOC_DAPM_PRE_PMU: 945 snd_soc_component_update_bits(component, 946 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(1), BIT(1)); 947 snd_soc_component_update_bits(component, 948 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(0), 0x00); 949 snd_soc_component_update_bits(component, 950 WCD937X_ANA_TX_CH2, BIT(6), BIT(6)); 951 snd_soc_component_update_bits(component, 952 WCD937X_ANA_TX_CH3_HPF, BIT(6), BIT(6)); 953 snd_soc_component_update_bits(component, 954 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70); 955 snd_soc_component_update_bits(component, 956 WCD937X_ANA_TX_CH1, BIT(7), BIT(7)); 957 snd_soc_component_update_bits(component, 958 WCD937X_ANA_TX_CH2, BIT(6), 0x00); 959 snd_soc_component_update_bits(component, 960 WCD937X_ANA_TX_CH2, BIT(7), BIT(7)); 961 snd_soc_component_update_bits(component, 962 WCD937X_ANA_TX_CH3, BIT(7), BIT(7)); 963 break; 964 case SND_SOC_DAPM_POST_PMD: 965 snd_soc_component_update_bits(component, 966 WCD937X_ANA_TX_CH1, BIT(7), 0x00); 967 snd_soc_component_update_bits(component, 968 WCD937X_ANA_TX_CH2, BIT(7), 0x00); 969 snd_soc_component_update_bits(component, 970 WCD937X_ANA_TX_CH3, BIT(7), 0x00); 971 snd_soc_component_update_bits(component, 972 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(4), 0x00); 973 974 atomic_dec(&wcd937x->ana_clk_count); 975 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 976 snd_soc_component_update_bits(component, 977 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 978 BIT(4), 0x00); 979 atomic_set(&wcd937x->ana_clk_count, 0); 980 } 981 982 snd_soc_component_update_bits(component, 983 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 984 BIT(7), 0x00); 985 break; 986 } 987 988 return 0; 989 } 990 991 static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 992 struct snd_kcontrol *kcontrol, 993 int event) 994 { 995 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 996 u16 dmic_clk_reg; 997 998 switch (w->shift) { 999 case 0: 1000 case 1: 1001 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL; 1002 break; 1003 case 2: 1004 case 3: 1005 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL; 1006 break; 1007 case 4: 1008 case 5: 1009 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL; 1010 break; 1011 default: 1012 dev_err(component->dev, "Invalid DMIC Selection\n"); 1013 return -EINVAL; 1014 } 1015 1016 switch (event) { 1017 case SND_SOC_DAPM_PRE_PMU: 1018 snd_soc_component_update_bits(component, 1019 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1020 BIT(7), BIT(7)); 1021 snd_soc_component_update_bits(component, 1022 dmic_clk_reg, 0x07, BIT(1)); 1023 snd_soc_component_update_bits(component, 1024 dmic_clk_reg, BIT(3), BIT(3)); 1025 snd_soc_component_update_bits(component, 1026 dmic_clk_reg, 0x70, BIT(5)); 1027 break; 1028 } 1029 1030 return 0; 1031 } 1032 1033 static int wcd937x_micbias_control(struct snd_soc_component *component, 1034 int micb_num, int req, bool is_dapm) 1035 { 1036 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1037 int micb_index = micb_num - 1; 1038 u16 micb_reg; 1039 1040 if (micb_index < 0 || (micb_index > WCD937X_MAX_MICBIAS - 1)) { 1041 dev_err(component->dev, "Invalid micbias index, micb_ind:%d\n", micb_index); 1042 return -EINVAL; 1043 } 1044 switch (micb_num) { 1045 case MIC_BIAS_1: 1046 micb_reg = WCD937X_ANA_MICB1; 1047 break; 1048 case MIC_BIAS_2: 1049 micb_reg = WCD937X_ANA_MICB2; 1050 break; 1051 case MIC_BIAS_3: 1052 micb_reg = WCD937X_ANA_MICB3; 1053 break; 1054 default: 1055 dev_err(component->dev, "Invalid micbias number: %d\n", micb_num); 1056 return -EINVAL; 1057 } 1058 1059 mutex_lock(&wcd937x->micb_lock); 1060 switch (req) { 1061 case MICB_PULLUP_ENABLE: 1062 wcd937x->pullup_ref[micb_index]++; 1063 if (wcd937x->pullup_ref[micb_index] == 1 && 1064 wcd937x->micb_ref[micb_index] == 0) 1065 snd_soc_component_update_bits(component, micb_reg, 1066 0xc0, BIT(7)); 1067 break; 1068 case MICB_PULLUP_DISABLE: 1069 if (wcd937x->pullup_ref[micb_index] > 0) 1070 wcd937x->pullup_ref[micb_index]++; 1071 if (wcd937x->pullup_ref[micb_index] == 0 && 1072 wcd937x->micb_ref[micb_index] == 0) 1073 snd_soc_component_update_bits(component, micb_reg, 1074 0xc0, 0x00); 1075 break; 1076 case MICB_ENABLE: 1077 wcd937x->micb_ref[micb_index]++; 1078 atomic_inc(&wcd937x->ana_clk_count); 1079 if (wcd937x->micb_ref[micb_index] == 1) { 1080 snd_soc_component_update_bits(component, 1081 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1082 0xf0, 0xf0); 1083 snd_soc_component_update_bits(component, 1084 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1085 BIT(4), BIT(4)); 1086 snd_soc_component_update_bits(component, 1087 WCD937X_MICB1_TEST_CTL_2, 1088 BIT(0), BIT(0)); 1089 snd_soc_component_update_bits(component, 1090 WCD937X_MICB2_TEST_CTL_2, 1091 BIT(0), BIT(0)); 1092 snd_soc_component_update_bits(component, 1093 WCD937X_MICB3_TEST_CTL_2, 1094 BIT(0), BIT(0)); 1095 snd_soc_component_update_bits(component, 1096 micb_reg, 0xc0, BIT(6)); 1097 1098 if (micb_num == MIC_BIAS_2) 1099 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1100 WCD_EVENT_POST_MICBIAS_2_ON); 1101 1102 if (micb_num == MIC_BIAS_2 && is_dapm) 1103 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1104 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1105 } 1106 break; 1107 case MICB_DISABLE: 1108 atomic_dec(&wcd937x->ana_clk_count); 1109 if (wcd937x->micb_ref[micb_index] > 0) 1110 wcd937x->micb_ref[micb_index]--; 1111 if (wcd937x->micb_ref[micb_index] == 0 && 1112 wcd937x->pullup_ref[micb_index] > 0) 1113 snd_soc_component_update_bits(component, micb_reg, 1114 0xc0, BIT(7)); 1115 else if (wcd937x->micb_ref[micb_index] == 0 && 1116 wcd937x->pullup_ref[micb_index] == 0) { 1117 if (micb_num == MIC_BIAS_2) 1118 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1119 WCD_EVENT_PRE_MICBIAS_2_OFF); 1120 1121 snd_soc_component_update_bits(component, micb_reg, 1122 0xc0, 0x00); 1123 if (micb_num == MIC_BIAS_2) 1124 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1125 WCD_EVENT_POST_MICBIAS_2_OFF); 1126 } 1127 1128 if (is_dapm && micb_num == MIC_BIAS_2) 1129 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1130 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1131 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 1132 snd_soc_component_update_bits(component, 1133 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1134 BIT(4), 0x00); 1135 atomic_set(&wcd937x->ana_clk_count, 0); 1136 } 1137 break; 1138 } 1139 mutex_unlock(&wcd937x->micb_lock); 1140 1141 return 0; 1142 } 1143 1144 static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1145 int event) 1146 { 1147 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1148 int micb_num = w->shift; 1149 1150 switch (event) { 1151 case SND_SOC_DAPM_PRE_PMU: 1152 wcd937x_micbias_control(component, micb_num, 1153 MICB_ENABLE, true); 1154 break; 1155 case SND_SOC_DAPM_POST_PMU: 1156 usleep_range(1000, 1100); 1157 break; 1158 case SND_SOC_DAPM_POST_PMD: 1159 wcd937x_micbias_control(component, micb_num, 1160 MICB_DISABLE, true); 1161 break; 1162 } 1163 1164 return 0; 1165 } 1166 1167 static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1168 struct snd_kcontrol *kcontrol, 1169 int event) 1170 { 1171 return __wcd937x_codec_enable_micbias(w, event); 1172 } 1173 1174 static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1175 int event) 1176 { 1177 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1178 int micb_num = w->shift; 1179 1180 switch (event) { 1181 case SND_SOC_DAPM_PRE_PMU: 1182 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_ENABLE, true); 1183 break; 1184 case SND_SOC_DAPM_POST_PMU: 1185 usleep_range(1000, 1100); 1186 break; 1187 case SND_SOC_DAPM_POST_PMD: 1188 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_DISABLE, true); 1189 break; 1190 } 1191 1192 return 0; 1193 } 1194 1195 static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1196 struct snd_kcontrol *kcontrol, 1197 int event) 1198 { 1199 return __wcd937x_codec_enable_micbias_pullup(w, event); 1200 } 1201 1202 static int wcd937x_connect_port(struct wcd937x_sdw_priv *wcd, u8 port_idx, u8 ch_id, bool enable) 1203 { 1204 struct sdw_port_config *port_config = &wcd->port_config[port_idx - 1]; 1205 const struct wcd_sdw_ch_info *ch_info = &wcd->ch_info[ch_id]; 1206 u8 port_num = ch_info->port_num; 1207 u8 ch_mask = ch_info->ch_mask; 1208 u8 mstr_port_num, mstr_ch_mask; 1209 struct sdw_slave *sdev = wcd->sdev; 1210 1211 port_config->num = port_num; 1212 1213 mstr_port_num = sdev->m_port_map[port_num]; 1214 mstr_ch_mask = ch_info->master_ch_mask; 1215 1216 if (enable) { 1217 port_config->ch_mask |= ch_mask; 1218 wcd->master_channel_map[mstr_port_num] |= mstr_ch_mask; 1219 } else { 1220 port_config->ch_mask &= ~ch_mask; 1221 wcd->master_channel_map[mstr_port_num] &= ~mstr_ch_mask; 1222 } 1223 1224 return 0; 1225 } 1226 1227 static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1228 struct snd_ctl_elem_value *ucontrol) 1229 { 1230 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1231 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1232 1233 ucontrol->value.integer.value[0] = wcd937x->hph_mode; 1234 return 0; 1235 } 1236 1237 static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1238 struct snd_ctl_elem_value *ucontrol) 1239 { 1240 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1241 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1242 u32 mode_val; 1243 1244 mode_val = ucontrol->value.enumerated.item[0]; 1245 1246 if (!mode_val) 1247 mode_val = CLS_AB; 1248 1249 if (mode_val == wcd937x->hph_mode) 1250 return 0; 1251 1252 switch (mode_val) { 1253 case CLS_H_NORMAL: 1254 case CLS_H_HIFI: 1255 case CLS_H_LP: 1256 case CLS_AB: 1257 case CLS_H_LOHIFI: 1258 case CLS_H_ULP: 1259 case CLS_AB_LP: 1260 case CLS_AB_HIFI: 1261 wcd937x->hph_mode = mode_val; 1262 return 1; 1263 } 1264 1265 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__); 1266 return -EINVAL; 1267 } 1268 1269 static int wcd937x_get_compander(struct snd_kcontrol *kcontrol, 1270 struct snd_ctl_elem_value *ucontrol) 1271 { 1272 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1273 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1274 struct soc_mixer_control *mc; 1275 bool hphr; 1276 1277 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1278 hphr = mc->shift; 1279 1280 ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable : 1281 wcd937x->comp1_enable; 1282 return 0; 1283 } 1284 1285 static int wcd937x_set_compander(struct snd_kcontrol *kcontrol, 1286 struct snd_ctl_elem_value *ucontrol) 1287 { 1288 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1289 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1290 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[AIF1_PB]; 1291 int value = ucontrol->value.integer.value[0]; 1292 struct soc_mixer_control *mc; 1293 int portidx; 1294 bool hphr; 1295 1296 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1297 hphr = mc->shift; 1298 1299 if (hphr) { 1300 if (value == wcd937x->comp2_enable) 1301 return 0; 1302 1303 wcd937x->comp2_enable = value; 1304 } else { 1305 if (value == wcd937x->comp1_enable) 1306 return 0; 1307 1308 wcd937x->comp1_enable = value; 1309 } 1310 1311 portidx = wcd->ch_info[mc->reg].port_num; 1312 1313 if (value) 1314 wcd937x_connect_port(wcd, portidx, mc->reg, true); 1315 else 1316 wcd937x_connect_port(wcd, portidx, mc->reg, false); 1317 1318 return 1; 1319 } 1320 1321 static int wcd937x_get_swr_port(struct snd_kcontrol *kcontrol, 1322 struct snd_ctl_elem_value *ucontrol) 1323 { 1324 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1325 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1326 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1327 struct wcd937x_sdw_priv *wcd; 1328 int dai_id = mixer->shift; 1329 int ch_idx = mixer->reg; 1330 int portidx; 1331 1332 wcd = wcd937x->sdw_priv[dai_id]; 1333 portidx = wcd->ch_info[ch_idx].port_num; 1334 1335 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1336 1337 return 0; 1338 } 1339 1340 static int wcd937x_set_swr_port(struct snd_kcontrol *kcontrol, 1341 struct snd_ctl_elem_value *ucontrol) 1342 { 1343 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1344 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1345 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1346 struct wcd937x_sdw_priv *wcd; 1347 int dai_id = mixer->shift; 1348 int ch_idx = mixer->reg; 1349 int portidx; 1350 bool enable; 1351 1352 wcd = wcd937x->sdw_priv[dai_id]; 1353 1354 portidx = wcd->ch_info[ch_idx].port_num; 1355 1356 enable = ucontrol->value.integer.value[0]; 1357 1358 if (enable == wcd->port_enable[portidx]) { 1359 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1360 return 0; 1361 } 1362 1363 wcd->port_enable[portidx] = enable; 1364 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1365 1366 return 1; 1367 } 1368 1369 static const char * const rx_hph_mode_mux_text[] = { 1370 "CLS_H_NORMAL", "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", 1371 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_LP", "CLS_AB_HIFI", 1372 }; 1373 1374 static const struct soc_enum rx_hph_mode_mux_enum = 1375 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), rx_hph_mode_mux_text); 1376 1377 /* MBHC related */ 1378 static void wcd937x_mbhc_clk_setup(struct snd_soc_component *component, 1379 bool enable) 1380 { 1381 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_1, 1382 WCD937X_MBHC_CTL_RCO_EN_MASK, enable); 1383 } 1384 1385 static void wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1386 bool enable) 1387 { 1388 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_ELECT, 1389 WCD937X_ANA_MBHC_BIAS_EN, enable); 1390 } 1391 1392 static void wcd937x_mbhc_program_btn_thr(struct snd_soc_component *component, 1393 int *btn_low, int *btn_high, 1394 int num_btn, bool is_micbias) 1395 { 1396 int i, vth; 1397 1398 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1399 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1400 __func__, num_btn); 1401 return; 1402 } 1403 1404 for (i = 0; i < num_btn; i++) { 1405 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1406 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_BTN0 + i, 1407 WCD937X_MBHC_BTN_VTH_MASK, vth); 1408 } 1409 } 1410 1411 static bool wcd937x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1412 { 1413 u8 val; 1414 1415 if (micb_num == MIC_BIAS_2) { 1416 val = snd_soc_component_read_field(component, 1417 WCD937X_ANA_MICB2, 1418 WCD937X_ANA_MICB2_ENABLE_MASK); 1419 if (val == WCD937X_MICB_ENABLE) 1420 return true; 1421 } 1422 return false; 1423 } 1424 1425 static void wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1426 int pull_up_cur) 1427 { 1428 /* Default pull up current to 2uA */ 1429 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1430 pull_up_cur = HS_PULLUP_I_2P0_UA; 1431 1432 snd_soc_component_write_field(component, 1433 WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 1434 WCD937X_HSDET_PULLUP_C_MASK, pull_up_cur); 1435 } 1436 1437 static int wcd937x_mbhc_request_micbias(struct snd_soc_component *component, 1438 int micb_num, int req) 1439 { 1440 return wcd937x_micbias_control(component, micb_num, req, false); 1441 } 1442 1443 static void wcd937x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1444 bool enable) 1445 { 1446 if (enable) { 1447 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1448 WCD937X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1449 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1450 WCD937X_RAMP_EN_MASK, 1); 1451 } else { 1452 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1453 WCD937X_RAMP_EN_MASK, 0); 1454 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1455 WCD937X_RAMP_SHIFT_CTRL_MASK, 0); 1456 } 1457 } 1458 1459 static int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1460 int req_volt, int micb_num) 1461 { 1462 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1463 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 1464 1465 switch (micb_num) { 1466 case MIC_BIAS_1: 1467 micb_reg = WCD937X_ANA_MICB1; 1468 break; 1469 case MIC_BIAS_2: 1470 micb_reg = WCD937X_ANA_MICB2; 1471 break; 1472 case MIC_BIAS_3: 1473 micb_reg = WCD937X_ANA_MICB3; 1474 break; 1475 default: 1476 return -EINVAL; 1477 } 1478 mutex_lock(&wcd937x->micb_lock); 1479 /* 1480 * If requested micbias voltage is same as current micbias 1481 * voltage, then just return. Otherwise, adjust voltage as 1482 * per requested value. If micbias is already enabled, then 1483 * to avoid slow micbias ramp-up or down enable pull-up 1484 * momentarily, change the micbias value and then re-enable 1485 * micbias. 1486 */ 1487 micb_en = snd_soc_component_read_field(component, micb_reg, 1488 WCD937X_MICB_EN_MASK); 1489 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 1490 WCD937X_MICB_VOUT_MASK); 1491 1492 req_vout_ctl = wcd_get_micb_vout_ctl_val(component->dev, req_volt); 1493 if (req_vout_ctl < 0) { 1494 ret = -EINVAL; 1495 goto exit; 1496 } 1497 1498 if (cur_vout_ctl == req_vout_ctl) { 1499 ret = 0; 1500 goto exit; 1501 } 1502 1503 if (micb_en == WCD937X_MICB_ENABLE) 1504 snd_soc_component_write_field(component, micb_reg, 1505 WCD937X_MICB_EN_MASK, 1506 WCD937X_MICB_PULL_UP); 1507 1508 snd_soc_component_write_field(component, micb_reg, 1509 WCD937X_MICB_VOUT_MASK, 1510 req_vout_ctl); 1511 1512 if (micb_en == WCD937X_MICB_ENABLE) { 1513 snd_soc_component_write_field(component, micb_reg, 1514 WCD937X_MICB_EN_MASK, 1515 WCD937X_MICB_ENABLE); 1516 /* 1517 * Add 2ms delay as per HW requirement after enabling 1518 * micbias 1519 */ 1520 usleep_range(2000, 2100); 1521 } 1522 exit: 1523 mutex_unlock(&wcd937x->micb_lock); 1524 return ret; 1525 } 1526 1527 static int wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 1528 int micb_num, bool req_en) 1529 { 1530 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1531 int micb_mv; 1532 1533 if (micb_num != MIC_BIAS_2) 1534 return -EINVAL; 1535 /* 1536 * If device tree micbias level is already above the minimum 1537 * voltage needed to detect threshold microphone, then do 1538 * not change the micbias, just return. 1539 */ 1540 if (wcd937x->common.micb_mv[2] >= WCD_MBHC_THR_HS_MICB_MV) 1541 return 0; 1542 1543 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd937x->common.micb_mv[2]; 1544 1545 return wcd937x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 1546 } 1547 1548 static void wcd937x_mbhc_get_result_params(struct snd_soc_component *component, 1549 s16 *d1_a, u16 noff, 1550 int32_t *zdet) 1551 { 1552 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1553 int i; 1554 int val, val1; 1555 s16 c1; 1556 s32 x1, d1; 1557 s32 denom; 1558 static const int minCode_param[] = { 1559 3277, 1639, 820, 410, 205, 103, 52, 26 1560 }; 1561 1562 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x20); 1563 for (i = 0; i < WCD937X_ZDET_NUM_MEASUREMENTS; i++) { 1564 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_2, &val); 1565 if (val & 0x80) 1566 break; 1567 } 1568 val = val << 0x8; 1569 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_1, &val1); 1570 val |= val1; 1571 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x00); 1572 x1 = WCD937X_MBHC_GET_X1(val); 1573 c1 = WCD937X_MBHC_GET_C1(val); 1574 /* If ramp is not complete, give additional 5ms */ 1575 if (c1 < 2 && x1) 1576 usleep_range(5000, 5050); 1577 1578 if (!c1 || !x1) { 1579 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 1580 c1, x1); 1581 goto ramp_down; 1582 } 1583 d1 = d1_a[c1]; 1584 denom = (x1 * d1) - (1 << (14 - noff)); 1585 if (denom > 0) 1586 *zdet = (WCD937X_MBHC_ZDET_CONST * 1000) / denom; 1587 else if (x1 < minCode_param[noff]) 1588 *zdet = WCD937X_ZDET_FLOATING_IMPEDANCE; 1589 1590 dev_err(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 1591 __func__, d1, c1, x1, *zdet); 1592 ramp_down: 1593 i = 0; 1594 while (x1) { 1595 regmap_read(wcd937x->regmap, 1596 WCD937X_ANA_MBHC_RESULT_1, &val); 1597 regmap_read(wcd937x->regmap, 1598 WCD937X_ANA_MBHC_RESULT_2, &val1); 1599 val = val << 0x08; 1600 val |= val1; 1601 x1 = WCD937X_MBHC_GET_X1(val); 1602 i++; 1603 if (i == WCD937X_ZDET_NUM_MEASUREMENTS) 1604 break; 1605 } 1606 } 1607 1608 static void wcd937x_mbhc_zdet_ramp(struct snd_soc_component *component, 1609 struct wcd937x_mbhc_zdet_param *zdet_param, 1610 s32 *zl, s32 *zr, s16 *d1_a) 1611 { 1612 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1613 s32 zdet = 0; 1614 1615 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1616 WCD937X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 1617 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN5, 1618 WCD937X_VTH_MASK, zdet_param->btn5); 1619 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN6, 1620 WCD937X_VTH_MASK, zdet_param->btn6); 1621 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN7, 1622 WCD937X_VTH_MASK, zdet_param->btn7); 1623 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1624 WCD937X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 1625 snd_soc_component_update_bits(component, WCD937X_MBHC_NEW_ZDET_RAMP_CTL, 1626 0x0F, zdet_param->nshift); 1627 1628 if (!zl) 1629 goto z_right; 1630 /* Start impedance measurement for HPH_L */ 1631 regmap_update_bits(wcd937x->regmap, 1632 WCD937X_ANA_MBHC_ZDET, 0x80, 0x80); 1633 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1634 regmap_update_bits(wcd937x->regmap, 1635 WCD937X_ANA_MBHC_ZDET, 0x80, 0x00); 1636 1637 *zl = zdet; 1638 1639 z_right: 1640 if (!zr) 1641 return; 1642 /* Start impedance measurement for HPH_R */ 1643 regmap_update_bits(wcd937x->regmap, 1644 WCD937X_ANA_MBHC_ZDET, 0x40, 0x40); 1645 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1646 regmap_update_bits(wcd937x->regmap, 1647 WCD937X_ANA_MBHC_ZDET, 0x40, 0x00); 1648 1649 *zr = zdet; 1650 } 1651 1652 static void wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 1653 s32 *z_val, int flag_l_r) 1654 { 1655 s16 q1; 1656 int q1_cal; 1657 1658 if (*z_val < (WCD937X_ZDET_VAL_400 / 1000)) 1659 q1 = snd_soc_component_read(component, 1660 WCD937X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 1661 else 1662 q1 = snd_soc_component_read(component, 1663 WCD937X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 1664 if (q1 & 0x80) 1665 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 1666 else 1667 q1_cal = (10000 + (q1 * 25)); 1668 if (q1_cal > 0) 1669 *z_val = ((*z_val) * 10000) / q1_cal; 1670 } 1671 1672 static void wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 1673 u32 *zl, u32 *zr) 1674 { 1675 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1676 s16 reg0, reg1, reg2, reg3, reg4; 1677 s32 z1l, z1r, z1ls; 1678 int zMono, z_diff1, z_diff2; 1679 bool is_fsm_disable = false; 1680 struct wcd937x_mbhc_zdet_param zdet_param[] = { 1681 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 1682 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 1683 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 1684 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 1685 }; 1686 struct wcd937x_mbhc_zdet_param *zdet_param_ptr = NULL; 1687 s16 d1_a[][4] = { 1688 {0, 30, 90, 30}, 1689 {0, 30, 30, 5}, 1690 {0, 30, 30, 5}, 1691 {0, 30, 30, 5}, 1692 }; 1693 s16 *d1 = NULL; 1694 1695 reg0 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN5); 1696 reg1 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN6); 1697 reg2 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN7); 1698 reg3 = snd_soc_component_read(component, WCD937X_MBHC_CTL_CLK); 1699 reg4 = snd_soc_component_read(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL); 1700 1701 if (snd_soc_component_read(component, WCD937X_ANA_MBHC_ELECT) & 0x80) { 1702 is_fsm_disable = true; 1703 regmap_update_bits(wcd937x->regmap, 1704 WCD937X_ANA_MBHC_ELECT, 0x80, 0x00); 1705 } 1706 1707 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 1708 if (wcd937x->mbhc_cfg.hphl_swh) 1709 regmap_update_bits(wcd937x->regmap, 1710 WCD937X_ANA_MBHC_MECH, 0x80, 0x00); 1711 1712 /* Turn off 100k pull down on HPHL */ 1713 regmap_update_bits(wcd937x->regmap, 1714 WCD937X_ANA_MBHC_MECH, 0x01, 0x00); 1715 1716 /* Disable surge protection before impedance detection. 1717 * This is done to give correct value for high impedance. 1718 */ 1719 regmap_update_bits(wcd937x->regmap, 1720 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 1721 /* 1ms delay needed after disable surge protection */ 1722 usleep_range(1000, 1010); 1723 1724 /* First get impedance on Left */ 1725 d1 = d1_a[1]; 1726 zdet_param_ptr = &zdet_param[1]; 1727 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1728 1729 if (!WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1l)) 1730 goto left_ch_impedance; 1731 1732 /* Second ramp for left ch */ 1733 if (z1l < WCD937X_ZDET_VAL_32) { 1734 zdet_param_ptr = &zdet_param[0]; 1735 d1 = d1_a[0]; 1736 } else if ((z1l > WCD937X_ZDET_VAL_400) && 1737 (z1l <= WCD937X_ZDET_VAL_1200)) { 1738 zdet_param_ptr = &zdet_param[2]; 1739 d1 = d1_a[2]; 1740 } else if (z1l > WCD937X_ZDET_VAL_1200) { 1741 zdet_param_ptr = &zdet_param[3]; 1742 d1 = d1_a[3]; 1743 } 1744 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1745 1746 left_ch_impedance: 1747 if (z1l == WCD937X_ZDET_FLOATING_IMPEDANCE || 1748 z1l > WCD937X_ZDET_VAL_100K) { 1749 *zl = WCD937X_ZDET_FLOATING_IMPEDANCE; 1750 zdet_param_ptr = &zdet_param[1]; 1751 d1 = d1_a[1]; 1752 } else { 1753 *zl = z1l / 1000; 1754 wcd937x_wcd_mbhc_qfuse_cal(component, zl, 0); 1755 } 1756 1757 /* Start of right impedance ramp and calculation */ 1758 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1759 if (WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1r)) { 1760 if ((z1r > WCD937X_ZDET_VAL_1200 && 1761 zdet_param_ptr->noff == 0x6) || 1762 ((*zl) != WCD937X_ZDET_FLOATING_IMPEDANCE)) 1763 goto right_ch_impedance; 1764 /* Second ramp for right ch */ 1765 if (z1r < WCD937X_ZDET_VAL_32) { 1766 zdet_param_ptr = &zdet_param[0]; 1767 d1 = d1_a[0]; 1768 } else if ((z1r > WCD937X_ZDET_VAL_400) && 1769 (z1r <= WCD937X_ZDET_VAL_1200)) { 1770 zdet_param_ptr = &zdet_param[2]; 1771 d1 = d1_a[2]; 1772 } else if (z1r > WCD937X_ZDET_VAL_1200) { 1773 zdet_param_ptr = &zdet_param[3]; 1774 d1 = d1_a[3]; 1775 } 1776 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1777 } 1778 right_ch_impedance: 1779 if (z1r == WCD937X_ZDET_FLOATING_IMPEDANCE || 1780 z1r > WCD937X_ZDET_VAL_100K) { 1781 *zr = WCD937X_ZDET_FLOATING_IMPEDANCE; 1782 } else { 1783 *zr = z1r / 1000; 1784 wcd937x_wcd_mbhc_qfuse_cal(component, zr, 1); 1785 } 1786 1787 /* Mono/stereo detection */ 1788 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) && 1789 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE)) { 1790 dev_err(component->dev, 1791 "%s: plug type is invalid or extension cable\n", 1792 __func__); 1793 goto zdet_complete; 1794 } 1795 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1796 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1797 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 1798 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 1799 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1800 goto zdet_complete; 1801 } 1802 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1803 WCD937X_HPHPA_GND_OVR_MASK, 1); 1804 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1805 WCD937X_HPHPA_GND_R_MASK, 1); 1806 if (*zl < (WCD937X_ZDET_VAL_32 / 1000)) 1807 wcd937x_mbhc_zdet_ramp(component, &zdet_param[0], &z1ls, NULL, d1); 1808 else 1809 wcd937x_mbhc_zdet_ramp(component, &zdet_param[1], &z1ls, NULL, d1); 1810 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1811 WCD937X_HPHPA_GND_R_MASK, 0); 1812 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1813 WCD937X_HPHPA_GND_OVR_MASK, 0); 1814 z1ls /= 1000; 1815 wcd937x_wcd_mbhc_qfuse_cal(component, &z1ls, 0); 1816 /* Parallel of left Z and 9 ohm pull down resistor */ 1817 zMono = ((*zl) * 9) / ((*zl) + 9); 1818 z_diff1 = (z1ls > zMono) ? (z1ls - zMono) : (zMono - z1ls); 1819 z_diff2 = ((*zl) > z1ls) ? ((*zl) - z1ls) : (z1ls - (*zl)); 1820 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + zMono))) 1821 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 1822 else 1823 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1824 1825 /* Enable surge protection again after impedance detection */ 1826 regmap_update_bits(wcd937x->regmap, 1827 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1828 zdet_complete: 1829 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN5, reg0); 1830 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN6, reg1); 1831 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN7, reg2); 1832 /* Turn on 100k pull down on HPHL */ 1833 regmap_update_bits(wcd937x->regmap, 1834 WCD937X_ANA_MBHC_MECH, 0x01, 0x01); 1835 1836 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 1837 if (wcd937x->mbhc_cfg.hphl_swh) 1838 regmap_update_bits(wcd937x->regmap, 1839 WCD937X_ANA_MBHC_MECH, 0x80, 0x80); 1840 1841 snd_soc_component_write(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, reg4); 1842 snd_soc_component_write(component, WCD937X_MBHC_CTL_CLK, reg3); 1843 if (is_fsm_disable) 1844 regmap_update_bits(wcd937x->regmap, 1845 WCD937X_ANA_MBHC_ELECT, 0x80, 0x80); 1846 } 1847 1848 static void wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 1849 bool enable) 1850 { 1851 if (enable) { 1852 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1853 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 1); 1854 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1855 WCD937X_MBHC_GND_DET_EN_MASK, 1); 1856 } else { 1857 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1858 WCD937X_MBHC_GND_DET_EN_MASK, 0); 1859 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1860 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 0); 1861 } 1862 } 1863 1864 static void wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 1865 bool enable) 1866 { 1867 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1868 WCD937X_HPHPA_GND_R_MASK, enable); 1869 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1870 WCD937X_HPHPA_GND_L_MASK, enable); 1871 } 1872 1873 static void wcd937x_mbhc_moisture_config(struct snd_soc_component *component) 1874 { 1875 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1876 1877 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1878 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1879 WCD937X_M_RTH_CTL_MASK, R_OFF); 1880 return; 1881 } 1882 1883 /* Do not enable moisture detection if jack type is NC */ 1884 if (!wcd937x->mbhc_cfg.hphl_swh) { 1885 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1886 __func__); 1887 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1888 WCD937X_M_RTH_CTL_MASK, R_OFF); 1889 return; 1890 } 1891 1892 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1893 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1894 } 1895 1896 static void wcd937x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 1897 { 1898 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1899 1900 if (enable) 1901 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1902 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1903 else 1904 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1905 WCD937X_M_RTH_CTL_MASK, R_OFF); 1906 } 1907 1908 static bool wcd937x_mbhc_get_moisture_status(struct snd_soc_component *component) 1909 { 1910 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1911 bool ret = false; 1912 1913 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1914 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1915 WCD937X_M_RTH_CTL_MASK, R_OFF); 1916 goto done; 1917 } 1918 1919 /* Do not enable moisture detection if jack type is NC */ 1920 if (!wcd937x->mbhc_cfg.hphl_swh) { 1921 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1922 __func__); 1923 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1924 WCD937X_M_RTH_CTL_MASK, R_OFF); 1925 goto done; 1926 } 1927 1928 /* 1929 * If moisture_en is already enabled, then skip to plug type 1930 * detection. 1931 */ 1932 if (snd_soc_component_read_field(component, WCD937X_MBHC_NEW_CTL_2, WCD937X_M_RTH_CTL_MASK)) 1933 goto done; 1934 1935 wcd937x_mbhc_moisture_detect_en(component, true); 1936 /* Read moisture comparator status */ 1937 ret = ((snd_soc_component_read(component, WCD937X_MBHC_NEW_FSM_STATUS) 1938 & 0x20) ? 0 : 1); 1939 done: 1940 return ret; 1941 } 1942 1943 static void wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 1944 bool enable) 1945 { 1946 snd_soc_component_write_field(component, 1947 WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 1948 WCD937X_MOISTURE_EN_POLLING_MASK, enable); 1949 } 1950 1951 static const struct wcd_mbhc_cb mbhc_cb = { 1952 .clk_setup = wcd937x_mbhc_clk_setup, 1953 .mbhc_bias = wcd937x_mbhc_mbhc_bias_control, 1954 .set_btn_thr = wcd937x_mbhc_program_btn_thr, 1955 .micbias_enable_status = wcd937x_mbhc_micb_en_status, 1956 .hph_pull_up_control_v2 = wcd937x_mbhc_hph_l_pull_up_control, 1957 .mbhc_micbias_control = wcd937x_mbhc_request_micbias, 1958 .mbhc_micb_ramp_control = wcd937x_mbhc_micb_ramp_control, 1959 .mbhc_micb_ctrl_thr_mic = wcd937x_mbhc_micb_ctrl_threshold_mic, 1960 .compute_impedance = wcd937x_wcd_mbhc_calc_impedance, 1961 .mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd_det_ctrl, 1962 .hph_pull_down_ctrl = wcd937x_mbhc_hph_pull_down_ctrl, 1963 .mbhc_moisture_config = wcd937x_mbhc_moisture_config, 1964 .mbhc_get_moisture_status = wcd937x_mbhc_get_moisture_status, 1965 .mbhc_moisture_polling_ctrl = wcd937x_mbhc_moisture_polling_ctrl, 1966 .mbhc_moisture_detect_en = wcd937x_mbhc_moisture_detect_en, 1967 }; 1968 1969 static int wcd937x_get_hph_type(struct snd_kcontrol *kcontrol, 1970 struct snd_ctl_elem_value *ucontrol) 1971 { 1972 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1973 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1974 1975 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd937x->wcd_mbhc); 1976 1977 return 0; 1978 } 1979 1980 static int wcd937x_hph_impedance_get(struct snd_kcontrol *kcontrol, 1981 struct snd_ctl_elem_value *ucontrol) 1982 { 1983 u32 zl, zr; 1984 bool hphr; 1985 struct soc_mixer_control *mc; 1986 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1987 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1988 1989 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1990 hphr = mc->shift; 1991 wcd_mbhc_get_impedance(wcd937x->wcd_mbhc, &zl, &zr); 1992 ucontrol->value.integer.value[0] = hphr ? zr : zl; 1993 1994 return 0; 1995 } 1996 1997 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 1998 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 1999 wcd937x_get_hph_type, NULL), 2000 }; 2001 2002 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2003 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2004 wcd937x_hph_impedance_get, NULL), 2005 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2006 wcd937x_hph_impedance_get, NULL), 2007 }; 2008 2009 static int wcd937x_mbhc_init(struct snd_soc_component *component) 2010 { 2011 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2012 struct wcd_mbhc_intr *intr_ids = &wcd937x->intr_ids; 2013 2014 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2015 WCD937X_IRQ_MBHC_SW_DET); 2016 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2017 WCD937X_IRQ_MBHC_BUTTON_PRESS_DET); 2018 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2019 WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET); 2020 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2021 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2022 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2023 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET); 2024 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2025 WCD937X_IRQ_HPHL_OCP_INT); 2026 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2027 WCD937X_IRQ_HPHR_OCP_INT); 2028 2029 wcd937x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2030 if (IS_ERR(wcd937x->wcd_mbhc)) 2031 return PTR_ERR(wcd937x->wcd_mbhc); 2032 2033 snd_soc_add_component_controls(component, impedance_detect_controls, 2034 ARRAY_SIZE(impedance_detect_controls)); 2035 snd_soc_add_component_controls(component, hph_type_detect_controls, 2036 ARRAY_SIZE(hph_type_detect_controls)); 2037 2038 return 0; 2039 } 2040 2041 static void wcd937x_mbhc_deinit(struct snd_soc_component *component) 2042 { 2043 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2044 2045 wcd_mbhc_deinit(wcd937x->wcd_mbhc); 2046 } 2047 2048 /* END MBHC */ 2049 2050 static const struct snd_kcontrol_new wcd937x_snd_controls[] = { 2051 SOC_SINGLE_TLV("EAR_PA Volume", WCD937X_ANA_EAR_COMPANDER_CTL, 2052 2, 0x10, 0, ear_pa_gain), 2053 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2054 wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put), 2055 2056 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD937X_COMP_L, 0, 1, 0, 2057 wcd937x_get_compander, wcd937x_set_compander), 2058 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD937X_COMP_R, 1, 1, 0, 2059 wcd937x_get_compander, wcd937x_set_compander), 2060 2061 SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain), 2062 SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain), 2063 SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2064 SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2065 SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2066 2067 SOC_SINGLE_EXT("HPHL Switch", WCD937X_HPH_L, 0, 1, 0, 2068 wcd937x_get_swr_port, wcd937x_set_swr_port), 2069 SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0, 2070 wcd937x_get_swr_port, wcd937x_set_swr_port), 2071 SOC_SINGLE_EXT("LO Switch", WCD937X_LO, 0, 1, 0, 2072 wcd937x_get_swr_port, wcd937x_set_swr_port), 2073 SOC_SINGLE_EXT("CLSH PA Switch", WCD937X_CLSH, 0, 1, 0, 2074 wcd937x_get_swr_port, wcd937x_set_swr_port), 2075 SOC_SINGLE_EXT("DSD_L Switch", WCD937X_DSD_L, 0, 1, 0, 2076 wcd937x_get_swr_port, wcd937x_set_swr_port), 2077 SOC_SINGLE_EXT("DSD_R Switch", WCD937X_DSD_R, 0, 1, 0, 2078 wcd937x_get_swr_port, wcd937x_set_swr_port), 2079 SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0, 2080 wcd937x_get_swr_port, wcd937x_set_swr_port), 2081 SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0, 2082 wcd937x_get_swr_port, wcd937x_set_swr_port), 2083 SOC_SINGLE_EXT("ADC3 Switch", WCD937X_ADC3, 1, 1, 0, 2084 wcd937x_get_swr_port, wcd937x_set_swr_port), 2085 SOC_SINGLE_EXT("DMIC0 Switch", WCD937X_DMIC0, 1, 1, 0, 2086 wcd937x_get_swr_port, wcd937x_set_swr_port), 2087 SOC_SINGLE_EXT("DMIC1 Switch", WCD937X_DMIC1, 1, 1, 0, 2088 wcd937x_get_swr_port, wcd937x_set_swr_port), 2089 SOC_SINGLE_EXT("MBHC Switch", WCD937X_MBHC, 1, 1, 0, 2090 wcd937x_get_swr_port, wcd937x_set_swr_port), 2091 SOC_SINGLE_EXT("DMIC2 Switch", WCD937X_DMIC2, 1, 1, 0, 2092 wcd937x_get_swr_port, wcd937x_set_swr_port), 2093 SOC_SINGLE_EXT("DMIC3 Switch", WCD937X_DMIC3, 1, 1, 0, 2094 wcd937x_get_swr_port, wcd937x_set_swr_port), 2095 SOC_SINGLE_EXT("DMIC4 Switch", WCD937X_DMIC4, 1, 1, 0, 2096 wcd937x_get_swr_port, wcd937x_set_swr_port), 2097 SOC_SINGLE_EXT("DMIC5 Switch", WCD937X_DMIC5, 1, 1, 0, 2098 wcd937x_get_swr_port, wcd937x_set_swr_port), 2099 }; 2100 2101 static const struct snd_kcontrol_new adc1_switch[] = { 2102 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2103 }; 2104 2105 static const struct snd_kcontrol_new adc2_switch[] = { 2106 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2107 }; 2108 2109 static const struct snd_kcontrol_new adc3_switch[] = { 2110 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2111 }; 2112 2113 static const struct snd_kcontrol_new dmic1_switch[] = { 2114 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2115 }; 2116 2117 static const struct snd_kcontrol_new dmic2_switch[] = { 2118 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2119 }; 2120 2121 static const struct snd_kcontrol_new dmic3_switch[] = { 2122 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2123 }; 2124 2125 static const struct snd_kcontrol_new dmic4_switch[] = { 2126 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2127 }; 2128 2129 static const struct snd_kcontrol_new dmic5_switch[] = { 2130 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2131 }; 2132 2133 static const struct snd_kcontrol_new dmic6_switch[] = { 2134 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2135 }; 2136 2137 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2138 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2139 }; 2140 2141 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2142 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2143 }; 2144 2145 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2146 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2147 }; 2148 2149 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2150 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2151 }; 2152 2153 static const char * const adc2_mux_text[] = { 2154 "INP2", "INP3" 2155 }; 2156 2157 static const char * const rdac3_mux_text[] = { 2158 "RX1", "RX3" 2159 }; 2160 2161 static const struct soc_enum adc2_enum = 2162 SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7, 2163 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2164 2165 static const struct soc_enum rdac3_enum = 2166 SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2167 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2168 2169 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2170 2171 static const struct snd_kcontrol_new rx_rdac3_mux = SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2172 2173 static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = { 2174 /* Input widgets */ 2175 SND_SOC_DAPM_INPUT("AMIC1"), 2176 SND_SOC_DAPM_INPUT("AMIC2"), 2177 SND_SOC_DAPM_INPUT("AMIC3"), 2178 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2179 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2180 SND_SOC_DAPM_INPUT("IN3_AUX"), 2181 2182 /* TX widgets */ 2183 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2184 wcd937x_codec_enable_adc, 2185 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2186 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2187 wcd937x_codec_enable_adc, 2188 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2189 2190 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2191 NULL, 0, wcd937x_enable_req, 2192 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2193 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0, 2194 NULL, 0, wcd937x_enable_req, 2195 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2196 2197 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2198 2199 /* TX mixers */ 2200 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, 2201 adc1_switch, ARRAY_SIZE(adc1_switch), 2202 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2203 SND_SOC_DAPM_POST_PMD), 2204 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0, 2205 adc2_switch, ARRAY_SIZE(adc2_switch), 2206 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2207 SND_SOC_DAPM_POST_PMD), 2208 2209 /* MIC_BIAS widgets */ 2210 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2211 wcd937x_codec_enable_micbias, 2212 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2213 SND_SOC_DAPM_POST_PMD), 2214 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2215 wcd937x_codec_enable_micbias, 2216 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2217 SND_SOC_DAPM_POST_PMD), 2218 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2219 wcd937x_codec_enable_micbias, 2220 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2221 SND_SOC_DAPM_POST_PMD), 2222 2223 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2224 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2225 2226 /* RX widgets */ 2227 SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0, 2228 wcd937x_codec_enable_ear_pa, 2229 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2230 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2231 SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0, 2232 wcd937x_codec_enable_aux_pa, 2233 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2234 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2235 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0, 2236 wcd937x_codec_enable_hphl_pa, 2237 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2238 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2239 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0, 2240 wcd937x_codec_enable_hphr_pa, 2241 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2242 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2243 2244 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2245 wcd937x_codec_hphl_dac_event, 2246 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2247 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2248 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2249 wcd937x_codec_hphr_dac_event, 2250 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2251 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2252 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2253 wcd937x_codec_ear_dac_event, 2254 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2255 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2256 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2257 wcd937x_codec_aux_dac_event, 2258 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2259 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2260 2261 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2262 2263 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, 2264 wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU | 2265 SND_SOC_DAPM_POST_PMD), 2266 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, 2267 wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU | 2268 SND_SOC_DAPM_POST_PMD), 2269 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, 2270 wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU | 2271 SND_SOC_DAPM_POST_PMD), 2272 2273 /* RX mixer widgets*/ 2274 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2275 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2276 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2277 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2278 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2279 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2280 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2281 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2282 2283 /* TX output widgets */ 2284 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2285 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2286 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2287 SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"), 2288 2289 /* RX output widgets */ 2290 SND_SOC_DAPM_OUTPUT("EAR"), 2291 SND_SOC_DAPM_OUTPUT("AUX"), 2292 SND_SOC_DAPM_OUTPUT("HPHL"), 2293 SND_SOC_DAPM_OUTPUT("HPHR"), 2294 2295 /* MIC_BIAS pull up widgets */ 2296 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2297 wcd937x_codec_enable_micbias_pullup, 2298 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2299 SND_SOC_DAPM_POST_PMD), 2300 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2301 wcd937x_codec_enable_micbias_pullup, 2302 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2303 SND_SOC_DAPM_POST_PMD), 2304 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2305 wcd937x_codec_enable_micbias_pullup, 2306 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2307 SND_SOC_DAPM_POST_PMD), 2308 }; 2309 2310 static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = { 2311 /* Input widgets */ 2312 SND_SOC_DAPM_INPUT("AMIC4"), 2313 2314 /* TX widgets */ 2315 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2316 wcd937x_codec_enable_adc, 2317 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2318 2319 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0, 2320 NULL, 0, wcd937x_enable_req, 2321 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2322 2323 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2324 wcd937x_codec_enable_dmic, 2325 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2326 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2327 wcd937x_codec_enable_dmic, 2328 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2329 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2330 wcd937x_codec_enable_dmic, 2331 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2332 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2333 wcd937x_codec_enable_dmic, 2334 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2335 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2336 wcd937x_codec_enable_dmic, 2337 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2338 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2339 wcd937x_codec_enable_dmic, 2340 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2341 2342 /* TX mixer widgets */ 2343 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 2344 0, dmic1_switch, ARRAY_SIZE(dmic1_switch), 2345 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2346 SND_SOC_DAPM_POST_PMD), 2347 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1, 2348 0, dmic2_switch, ARRAY_SIZE(dmic2_switch), 2349 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2350 SND_SOC_DAPM_POST_PMD), 2351 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2, 2352 0, dmic3_switch, ARRAY_SIZE(dmic3_switch), 2353 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2354 SND_SOC_DAPM_POST_PMD), 2355 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3, 2356 0, dmic4_switch, ARRAY_SIZE(dmic4_switch), 2357 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2358 SND_SOC_DAPM_POST_PMD), 2359 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4, 2360 0, dmic5_switch, ARRAY_SIZE(dmic5_switch), 2361 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2362 SND_SOC_DAPM_POST_PMD), 2363 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5, 2364 0, dmic6_switch, ARRAY_SIZE(dmic6_switch), 2365 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2366 SND_SOC_DAPM_POST_PMD), 2367 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch, 2368 ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl, 2369 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2370 2371 /* Output widgets */ 2372 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2373 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2374 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2375 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2376 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2377 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2378 }; 2379 2380 static const struct snd_soc_dapm_route wcd937x_audio_map[] = { 2381 { "ADC1_OUTPUT", NULL, "ADC1_MIXER" }, 2382 { "ADC1_MIXER", "Switch", "ADC1 REQ" }, 2383 { "ADC1 REQ", NULL, "ADC1" }, 2384 { "ADC1", NULL, "AMIC1" }, 2385 2386 { "ADC2_OUTPUT", NULL, "ADC2_MIXER" }, 2387 { "ADC2_MIXER", "Switch", "ADC2 REQ" }, 2388 { "ADC2 REQ", NULL, "ADC2" }, 2389 { "ADC2", NULL, "ADC2 MUX" }, 2390 { "ADC2 MUX", "INP3", "AMIC3" }, 2391 { "ADC2 MUX", "INP2", "AMIC2" }, 2392 2393 { "IN1_HPHL", NULL, "VDD_BUCK" }, 2394 { "IN1_HPHL", NULL, "CLS_H_PORT" }, 2395 { "RX1", NULL, "IN1_HPHL" }, 2396 { "RDAC1", NULL, "RX1" }, 2397 { "HPHL_RDAC", "Switch", "RDAC1" }, 2398 { "HPHL PGA", NULL, "HPHL_RDAC" }, 2399 { "HPHL", NULL, "HPHL PGA" }, 2400 2401 { "IN2_HPHR", NULL, "VDD_BUCK" }, 2402 { "IN2_HPHR", NULL, "CLS_H_PORT" }, 2403 { "RX2", NULL, "IN2_HPHR" }, 2404 { "RDAC2", NULL, "RX2" }, 2405 { "HPHR_RDAC", "Switch", "RDAC2" }, 2406 { "HPHR PGA", NULL, "HPHR_RDAC" }, 2407 { "HPHR", NULL, "HPHR PGA" }, 2408 2409 { "IN3_AUX", NULL, "VDD_BUCK" }, 2410 { "IN3_AUX", NULL, "CLS_H_PORT" }, 2411 { "RX3", NULL, "IN3_AUX" }, 2412 { "RDAC4", NULL, "RX3" }, 2413 { "AUX_RDAC", "Switch", "RDAC4" }, 2414 { "AUX PGA", NULL, "AUX_RDAC" }, 2415 { "AUX", NULL, "AUX PGA" }, 2416 2417 { "RDAC3_MUX", "RX3", "RX3" }, 2418 { "RDAC3_MUX", "RX1", "RX1" }, 2419 { "RDAC3", NULL, "RDAC3_MUX" }, 2420 { "EAR_RDAC", "Switch", "RDAC3" }, 2421 { "EAR PGA", NULL, "EAR_RDAC" }, 2422 { "EAR", NULL, "EAR PGA" }, 2423 }; 2424 2425 static const struct snd_soc_dapm_route wcd9375_audio_map[] = { 2426 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2427 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2428 { "ADC3_MIXER", "Switch", "ADC3 REQ" }, 2429 { "ADC3 REQ", NULL, "ADC3" }, 2430 { "ADC3", NULL, "AMIC4" }, 2431 2432 { "DMIC1_OUTPUT", NULL, "DMIC1_MIXER" }, 2433 { "DMIC1_MIXER", "Switch", "DMIC1" }, 2434 2435 { "DMIC2_OUTPUT", NULL, "DMIC2_MIXER" }, 2436 { "DMIC2_MIXER", "Switch", "DMIC2" }, 2437 2438 { "DMIC3_OUTPUT", NULL, "DMIC3_MIXER" }, 2439 { "DMIC3_MIXER", "Switch", "DMIC3" }, 2440 2441 { "DMIC4_OUTPUT", NULL, "DMIC4_MIXER" }, 2442 { "DMIC4_MIXER", "Switch", "DMIC4" }, 2443 2444 { "DMIC5_OUTPUT", NULL, "DMIC5_MIXER" }, 2445 { "DMIC5_MIXER", "Switch", "DMIC5" }, 2446 2447 { "DMIC6_OUTPUT", NULL, "DMIC6_MIXER" }, 2448 { "DMIC6_MIXER", "Switch", "DMIC6" }, 2449 }; 2450 2451 static void wcd937x_set_micbias_data(struct device *dev, struct wcd937x_priv *wcd937x) 2452 { 2453 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, WCD937X_ANA_MICB_VOUT, 2454 wcd937x->common.micb_vout[0]); 2455 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, WCD937X_ANA_MICB_VOUT, 2456 wcd937x->common.micb_vout[1]); 2457 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, WCD937X_ANA_MICB_VOUT, 2458 wcd937x->common.micb_vout[2]); 2459 } 2460 2461 static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data) 2462 { 2463 return IRQ_HANDLED; 2464 } 2465 2466 static const struct irq_chip wcd_irq_chip = { 2467 .name = "WCD937x", 2468 }; 2469 2470 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2471 irq_hw_number_t hw) 2472 { 2473 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2474 irq_set_nested_thread(virq, 1); 2475 irq_set_noprobe(virq); 2476 2477 return 0; 2478 } 2479 2480 static const struct irq_domain_ops wcd_domain_ops = { 2481 .map = wcd_irq_chip_map, 2482 }; 2483 2484 static int wcd937x_irq_init(struct wcd937x_priv *wcd, struct device *dev) 2485 { 2486 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 2487 if (!(wcd->virq)) { 2488 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 2489 return -EINVAL; 2490 } 2491 2492 return devm_regmap_add_irq_chip(dev, wcd->regmap, 2493 irq_create_mapping(wcd->virq, 0), 2494 IRQF_ONESHOT, 0, &wcd937x_regmap_irq_chip, 2495 &wcd->irq_chip); 2496 } 2497 2498 static int wcd937x_soc_codec_probe(struct snd_soc_component *component) 2499 { 2500 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2501 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2502 struct sdw_slave *tx_sdw_dev = wcd937x->tx_sdw_dev; 2503 struct device *dev = component->dev; 2504 unsigned long time_left; 2505 int i, ret; 2506 u32 chipid; 2507 2508 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 2509 msecs_to_jiffies(5000)); 2510 if (!time_left) { 2511 dev_err(dev, "soundwire device init timeout\n"); 2512 return -ETIMEDOUT; 2513 } 2514 2515 snd_soc_component_init_regmap(component, wcd937x->regmap); 2516 ret = pm_runtime_resume_and_get(dev); 2517 if (ret < 0) 2518 return ret; 2519 2520 chipid = (snd_soc_component_read(component, 2521 WCD937X_DIGITAL_EFUSE_REG_0) & 0x1e) >> 1; 2522 if (chipid != CHIPID_WCD9370 && chipid != CHIPID_WCD9375) { 2523 dev_err(dev, "Got unknown chip id: 0x%x\n", chipid); 2524 pm_runtime_put(dev); 2525 return -EINVAL; 2526 } 2527 2528 wcd937x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD937X); 2529 if (IS_ERR(wcd937x->clsh_info)) { 2530 pm_runtime_put(dev); 2531 return PTR_ERR(wcd937x->clsh_info); 2532 } 2533 2534 wcd937x_io_init(wcd937x->regmap); 2535 /* Set all interrupts as edge triggered */ 2536 for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++) 2537 regmap_write(wcd937x->regmap, (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0); 2538 2539 pm_runtime_put(dev); 2540 2541 wcd937x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2542 WCD937X_IRQ_HPHR_PDM_WD_INT); 2543 wcd937x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2544 WCD937X_IRQ_HPHL_PDM_WD_INT); 2545 wcd937x->aux_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2546 WCD937X_IRQ_AUX_PDM_WD_INT); 2547 2548 /* Request for watchdog interrupt */ 2549 ret = devm_request_threaded_irq(dev, wcd937x->hphr_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2550 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2551 "HPHR PDM WDOG INT", wcd937x); 2552 if (ret) 2553 dev_err(dev, "Failed to request HPHR watchdog interrupt (%d)\n", ret); 2554 2555 ret = devm_request_threaded_irq(dev, wcd937x->hphl_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2556 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2557 "HPHL PDM WDOG INT", wcd937x); 2558 if (ret) 2559 dev_err(dev, "Failed to request HPHL watchdog interrupt (%d)\n", ret); 2560 2561 ret = devm_request_threaded_irq(dev, wcd937x->aux_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2562 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2563 "AUX PDM WDOG INT", wcd937x); 2564 if (ret) 2565 dev_err(dev, "Failed to request Aux watchdog interrupt (%d)\n", ret); 2566 2567 /* Disable watchdog interrupt for HPH and AUX */ 2568 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 2569 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 2570 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 2571 2572 if (chipid == CHIPID_WCD9375) { 2573 ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets, 2574 ARRAY_SIZE(wcd9375_dapm_widgets)); 2575 if (ret < 0) { 2576 dev_err(component->dev, "Failed to add snd_ctls\n"); 2577 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2578 return ret; 2579 } 2580 2581 ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map, 2582 ARRAY_SIZE(wcd9375_audio_map)); 2583 if (ret < 0) { 2584 dev_err(component->dev, "Failed to add routes\n"); 2585 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2586 return ret; 2587 } 2588 } 2589 2590 ret = wcd937x_mbhc_init(component); 2591 if (ret) 2592 dev_err(component->dev, "mbhc initialization failed\n"); 2593 2594 return ret; 2595 } 2596 2597 static void wcd937x_soc_codec_remove(struct snd_soc_component *component) 2598 { 2599 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2600 2601 wcd937x_mbhc_deinit(component); 2602 free_irq(wcd937x->aux_pdm_wd_int, wcd937x); 2603 free_irq(wcd937x->hphl_pdm_wd_int, wcd937x); 2604 free_irq(wcd937x->hphr_pdm_wd_int, wcd937x); 2605 2606 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2607 } 2608 2609 static int wcd937x_codec_set_jack(struct snd_soc_component *comp, 2610 struct snd_soc_jack *jack, void *data) 2611 { 2612 struct wcd937x_priv *wcd = dev_get_drvdata(comp->dev); 2613 int ret = 0; 2614 2615 if (jack) 2616 ret = wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 2617 else 2618 wcd_mbhc_stop(wcd->wcd_mbhc); 2619 2620 return ret; 2621 } 2622 2623 static const struct snd_soc_component_driver soc_codec_dev_wcd937x = { 2624 .name = "wcd937x_codec", 2625 .probe = wcd937x_soc_codec_probe, 2626 .remove = wcd937x_soc_codec_remove, 2627 .controls = wcd937x_snd_controls, 2628 .num_controls = ARRAY_SIZE(wcd937x_snd_controls), 2629 .dapm_widgets = wcd937x_dapm_widgets, 2630 .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets), 2631 .dapm_routes = wcd937x_audio_map, 2632 .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map), 2633 .set_jack = wcd937x_codec_set_jack, 2634 .endianness = 1, 2635 }; 2636 2637 static bool wcd937x_swap_gnd_mic(struct snd_soc_component *component) 2638 { 2639 int value; 2640 struct wcd937x_priv *wcd937x; 2641 2642 wcd937x = snd_soc_component_get_drvdata(component); 2643 2644 value = gpiod_get_value(wcd937x->us_euro_gpio); 2645 gpiod_set_value(wcd937x->us_euro_gpio, !value); 2646 2647 return true; 2648 } 2649 2650 static int wcd937x_codec_hw_params(struct snd_pcm_substream *substream, 2651 struct snd_pcm_hw_params *params, 2652 struct snd_soc_dai *dai) 2653 { 2654 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2655 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2656 2657 return wcd937x_sdw_hw_params(wcd, substream, params, dai); 2658 } 2659 2660 static int wcd937x_codec_free(struct snd_pcm_substream *substream, 2661 struct snd_soc_dai *dai) 2662 { 2663 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2664 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2665 2666 return sdw_stream_remove_slave(wcd->sdev, wcd->sruntime); 2667 } 2668 2669 static int wcd937x_codec_set_sdw_stream(struct snd_soc_dai *dai, 2670 void *stream, int direction) 2671 { 2672 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2673 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2674 2675 wcd->sruntime = stream; 2676 2677 return 0; 2678 } 2679 2680 static int wcd937x_get_channel_map(const struct snd_soc_dai *dai, 2681 unsigned int *tx_num, unsigned int *tx_slot, 2682 unsigned int *rx_num, unsigned int *rx_slot) 2683 { 2684 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2685 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2686 int i; 2687 2688 switch (dai->id) { 2689 case AIF1_PB: 2690 if (!rx_slot || !rx_num) { 2691 dev_err(dai->dev, "Invalid rx_slot %p or rx_num %p\n", 2692 rx_slot, rx_num); 2693 return -EINVAL; 2694 } 2695 2696 for (i = 0; i < SDW_MAX_PORTS; i++) 2697 rx_slot[i] = wcd->master_channel_map[i]; 2698 2699 *rx_num = i; 2700 break; 2701 case AIF1_CAP: 2702 if (!tx_slot || !tx_num) { 2703 dev_err(dai->dev, "Invalid tx_slot %p or tx_num %p\n", 2704 tx_slot, tx_num); 2705 return -EINVAL; 2706 } 2707 2708 for (i = 0; i < SDW_MAX_PORTS; i++) 2709 tx_slot[i] = wcd->master_channel_map[i]; 2710 2711 *tx_num = i; 2712 break; 2713 default: 2714 break; 2715 } 2716 2717 return 0; 2718 } 2719 2720 static const struct snd_soc_dai_ops wcd937x_sdw_dai_ops = { 2721 .hw_params = wcd937x_codec_hw_params, 2722 .hw_free = wcd937x_codec_free, 2723 .set_stream = wcd937x_codec_set_sdw_stream, 2724 .get_channel_map = wcd937x_get_channel_map, 2725 }; 2726 2727 static struct snd_soc_dai_driver wcd937x_dais[] = { 2728 [0] = { 2729 .name = "wcd937x-sdw-rx", 2730 .playback = { 2731 .stream_name = "WCD AIF Playback", 2732 .rates = WCD937X_RATES | WCD937X_FRAC_RATES, 2733 .formats = WCD937X_FORMATS, 2734 .rate_min = 8000, 2735 .rate_max = 384000, 2736 .channels_min = 1, 2737 .channels_max = 4, 2738 }, 2739 .ops = &wcd937x_sdw_dai_ops, 2740 }, 2741 [1] = { 2742 .name = "wcd937x-sdw-tx", 2743 .capture = { 2744 .stream_name = "WCD AIF Capture", 2745 .rates = WCD937X_RATES, 2746 .formats = WCD937X_FORMATS, 2747 .rate_min = 8000, 2748 .rate_max = 192000, 2749 .channels_min = 1, 2750 .channels_max = 4, 2751 }, 2752 .ops = &wcd937x_sdw_dai_ops, 2753 }, 2754 }; 2755 2756 static int wcd937x_bind(struct device *dev) 2757 { 2758 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2759 int ret; 2760 2761 /* Give the SDW subdevices some more time to settle */ 2762 usleep_range(5000, 5010); 2763 2764 ret = component_bind_all(dev, wcd937x); 2765 if (ret) { 2766 dev_err(dev, "Slave bind failed, ret = %d\n", ret); 2767 return ret; 2768 } 2769 2770 wcd937x->rxdev = of_sdw_find_device_by_node(wcd937x->rxnode); 2771 if (!wcd937x->rxdev) { 2772 dev_err(dev, "could not find slave with matching of node\n"); 2773 ret = -EINVAL; 2774 goto err_component_unbind; 2775 } 2776 2777 wcd937x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd937x->rxdev); 2778 wcd937x->sdw_priv[AIF1_PB]->wcd937x = wcd937x; 2779 2780 wcd937x->txdev = of_sdw_find_device_by_node(wcd937x->txnode); 2781 if (!wcd937x->txdev) { 2782 dev_err(dev, "could not find txslave with matching of node\n"); 2783 ret = -EINVAL; 2784 goto err_put_rxdev; 2785 } 2786 2787 wcd937x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd937x->txdev); 2788 wcd937x->sdw_priv[AIF1_CAP]->wcd937x = wcd937x; 2789 wcd937x->tx_sdw_dev = dev_to_sdw_dev(wcd937x->txdev); 2790 2791 /* 2792 * As TX is the main CSR reg interface, which should not be suspended first. 2793 * expicilty add the dependency link 2794 */ 2795 if (!device_link_add(wcd937x->rxdev, wcd937x->txdev, 2796 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2797 dev_err(dev, "Could not devlink TX and RX\n"); 2798 ret = -EINVAL; 2799 goto err_put_txdev; 2800 } 2801 2802 if (!device_link_add(dev, wcd937x->txdev, 2803 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2804 dev_err(dev, "Could not devlink WCD and TX\n"); 2805 ret = -EINVAL; 2806 goto err_remove_link1; 2807 } 2808 2809 if (!device_link_add(dev, wcd937x->rxdev, 2810 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2811 dev_err(dev, "Could not devlink WCD and RX\n"); 2812 ret = -EINVAL; 2813 goto err_remove_link2; 2814 } 2815 2816 wcd937x->regmap = wcd937x->sdw_priv[AIF1_CAP]->regmap; 2817 if (!wcd937x->regmap) { 2818 dev_err(dev, "could not get TX device regmap\n"); 2819 ret = -EINVAL; 2820 goto err_remove_link3; 2821 } 2822 2823 ret = wcd937x_irq_init(wcd937x, dev); 2824 if (ret) { 2825 dev_err(dev, "IRQ init failed: %d\n", ret); 2826 goto err_remove_link3; 2827 } 2828 2829 wcd937x->sdw_priv[AIF1_PB]->slave_irq = wcd937x->virq; 2830 wcd937x->sdw_priv[AIF1_CAP]->slave_irq = wcd937x->virq; 2831 2832 wcd937x_set_micbias_data(dev, wcd937x); 2833 2834 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x, 2835 wcd937x_dais, ARRAY_SIZE(wcd937x_dais)); 2836 if (ret) { 2837 dev_err(dev, "Codec registration failed\n"); 2838 goto err_remove_link3; 2839 } 2840 2841 return ret; 2842 2843 err_remove_link3: 2844 device_link_remove(dev, wcd937x->rxdev); 2845 err_remove_link2: 2846 device_link_remove(dev, wcd937x->txdev); 2847 err_remove_link1: 2848 device_link_remove(wcd937x->rxdev, wcd937x->txdev); 2849 err_put_txdev: 2850 put_device(wcd937x->txdev); 2851 err_put_rxdev: 2852 put_device(wcd937x->rxdev); 2853 err_component_unbind: 2854 component_unbind_all(dev, wcd937x); 2855 return ret; 2856 } 2857 2858 static void wcd937x_unbind(struct device *dev) 2859 { 2860 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2861 2862 snd_soc_unregister_component(dev); 2863 device_link_remove(dev, wcd937x->txdev); 2864 device_link_remove(dev, wcd937x->rxdev); 2865 device_link_remove(wcd937x->rxdev, wcd937x->txdev); 2866 component_unbind_all(dev, wcd937x); 2867 mutex_destroy(&wcd937x->micb_lock); 2868 put_device(wcd937x->txdev); 2869 put_device(wcd937x->rxdev); 2870 } 2871 2872 static const struct component_master_ops wcd937x_comp_ops = { 2873 .bind = wcd937x_bind, 2874 .unbind = wcd937x_unbind, 2875 }; 2876 2877 static int wcd937x_add_slave_components(struct wcd937x_priv *wcd937x, 2878 struct device *dev, 2879 struct component_match **matchptr) 2880 { 2881 struct device_node *np = dev->of_node; 2882 2883 wcd937x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 2884 if (!wcd937x->rxnode) { 2885 dev_err(dev, "Couldn't parse phandle to qcom,rx-device!\n"); 2886 return -ENODEV; 2887 } 2888 2889 component_match_add_release(dev, matchptr, component_release_of, 2890 component_compare_of, wcd937x->rxnode); 2891 2892 wcd937x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 2893 if (!wcd937x->txnode) { 2894 dev_err(dev, "Couldn't parse phandle to qcom,tx-device\n"); 2895 return -ENODEV; 2896 } 2897 2898 component_match_add_release(dev, matchptr, component_release_of, 2899 component_compare_of, wcd937x->txnode); 2900 2901 return 0; 2902 } 2903 2904 static int wcd937x_probe(struct platform_device *pdev) 2905 { 2906 struct component_match *match = NULL; 2907 struct device *dev = &pdev->dev; 2908 struct wcd937x_priv *wcd937x; 2909 struct wcd_mbhc_config *cfg; 2910 int ret; 2911 2912 wcd937x = devm_kzalloc(dev, sizeof(*wcd937x), GFP_KERNEL); 2913 if (!wcd937x) 2914 return -ENOMEM; 2915 2916 dev_set_drvdata(dev, wcd937x); 2917 mutex_init(&wcd937x->micb_lock); 2918 wcd937x->common.dev = dev; 2919 wcd937x->common.max_bias = 3; 2920 2921 wcd937x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 2922 if (IS_ERR(wcd937x->reset_gpio)) 2923 return dev_err_probe(dev, PTR_ERR(wcd937x->reset_gpio), 2924 "failed to reset wcd gpio\n"); 2925 2926 wcd937x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 2927 if (IS_ERR(wcd937x->us_euro_gpio)) 2928 return dev_err_probe(dev, PTR_ERR(wcd937x->us_euro_gpio), 2929 "us-euro swap Control GPIO not found\n"); 2930 2931 cfg = &wcd937x->mbhc_cfg; 2932 cfg->swap_gnd_mic = wcd937x_swap_gnd_mic; 2933 2934 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd937x_supplies), 2935 wcd937x_supplies); 2936 if (ret) 2937 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 2938 2939 ret = wcd_dt_parse_micbias_info(&wcd937x->common); 2940 if (ret) 2941 return dev_err_probe(dev, ret, "Failed to get micbias\n"); 2942 2943 cfg->mbhc_micbias = MIC_BIAS_2; 2944 cfg->anc_micbias = MIC_BIAS_2; 2945 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 2946 cfg->num_btn = WCD937X_MBHC_MAX_BUTTONS; 2947 cfg->micb_mv = wcd937x->common.micb_mv[2]; 2948 cfg->linein_th = 5000; 2949 cfg->hs_thr = 1700; 2950 cfg->hph_thr = 50; 2951 2952 wcd_dt_parse_mbhc_data(dev, &wcd937x->mbhc_cfg); 2953 2954 ret = wcd937x_add_slave_components(wcd937x, dev, &match); 2955 if (ret) 2956 return ret; 2957 2958 wcd937x_reset(wcd937x); 2959 2960 ret = component_master_add_with_match(dev, &wcd937x_comp_ops, match); 2961 if (ret) 2962 return ret; 2963 2964 pm_runtime_set_autosuspend_delay(dev, 1000); 2965 pm_runtime_use_autosuspend(dev); 2966 pm_runtime_mark_last_busy(dev); 2967 pm_runtime_set_active(dev); 2968 pm_runtime_enable(dev); 2969 pm_runtime_idle(dev); 2970 2971 return 0; 2972 } 2973 2974 static void wcd937x_remove(struct platform_device *pdev) 2975 { 2976 struct device *dev = &pdev->dev; 2977 2978 component_master_del(&pdev->dev, &wcd937x_comp_ops); 2979 2980 pm_runtime_disable(dev); 2981 pm_runtime_set_suspended(dev); 2982 pm_runtime_dont_use_autosuspend(dev); 2983 } 2984 2985 #if defined(CONFIG_OF) 2986 static const struct of_device_id wcd937x_of_match[] = { 2987 { .compatible = "qcom,wcd9370-codec" }, 2988 { .compatible = "qcom,wcd9375-codec" }, 2989 { } 2990 }; 2991 MODULE_DEVICE_TABLE(of, wcd937x_of_match); 2992 #endif 2993 2994 static struct platform_driver wcd937x_codec_driver = { 2995 .probe = wcd937x_probe, 2996 .remove = wcd937x_remove, 2997 .driver = { 2998 .name = "wcd937x_codec", 2999 .of_match_table = of_match_ptr(wcd937x_of_match), 3000 .suppress_bind_attrs = true, 3001 }, 3002 }; 3003 3004 module_platform_driver(wcd937x_codec_driver); 3005 MODULE_DESCRIPTION("WCD937X Codec driver"); 3006 MODULE_LICENSE("GPL"); 3007