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Searched defs:VT (Results 1 – 25 of 238) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DMatchContext.h41 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal()
111 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { in getNode()
119 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
127 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
136 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, in getNode()
145 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
154 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
163 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal()
H A DLegalizeVectorOps.cpp709 MVT VT = Node->getSimpleValueType(0); in Promote() local
750 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType(); in PromoteINT_TO_FP() local
788 MVT VT = Node->getSimpleValueType(0); in PromoteFP_TO_INT() local
1147 EVT VT = Node->getValueType(0); in ExpandSELECT() local
1200 EVT VT = Node->getValueType(0); in ExpandSEXTINREG() local
1222 EVT VT = Node->getValueType(0); in ExpandANY_EXTEND_VECTOR_INREG() local
1257 EVT VT = Node->getValueType(0); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1281 EVT VT = Node->getValueType(0); in ExpandZERO_EXTEND_VECTOR_INREG() local
1315 static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) { in createBSWAPShuffleMask()
1323 EVT VT = Node->getValueType(0); in ExpandBSWAP() local
[all …]
H A DResourcePriorityQueue.cpp93 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
131 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() local
326 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
335 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() local
474 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
485 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode() local
H A DSelectionDAG.cpp128 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
1123 EVT VT = N->getValueType(0); in VerifySDNode() local
1199 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1433 SDValue SelectionDAG::getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT) { in getFPExtendOrRound()
1442 const SDLoc &DL, EVT VT) { in getStrictFPExtendOrRound()
1454 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getAnyExtOrTrunc()
1460 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getSExtOrTrunc()
1466 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getZExtOrTrunc()
1473 EVT VT) { in getBitcastedAnyExtOrTrunc()
1488 EVT VT) { in getBitcastedSExtOrTrunc()
[all …]
H A DLegalizeTypes.h62 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { in getTypeAction() argument
67 bool isTypeLegal(EVT VT) const { in isTypeLegal() argument
72 bool isSimpleLegalType(EVT VT) const { in isSimpleLegalType() argument
76 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType() argument
282 EVT VT = Op.getValueType(); VPSExtPromotedInteger() local
[all...]
H A DDAGCombiner.cpp256 for (MVT VT : MVT::all_valuetypes()) in DAGCombiner() local
343 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
841 bool hasOperation(unsigned Opcode, EVT VT) { in hasOperation()
858 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
1112 EVT VT = LoadStore->getMemoryVT(); in reassociationCanBreakAddressingModePattern() local
1152 EVT VT = LoadStore->getMemoryVT(); in reassociationCanBreakAddressingModePattern() local
1179 EVT VT = LoadStore->getMemoryVT(); in reassociationCanBreakAddressingModePattern() local
1196 EVT VT = N0.getValueType(); in reassociateOpsCommutative() local
1314 const SDLoc &DL, EVT VT, SDValue N0, in reassociateReduction()
1415 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DVTEmitter.cpp32 static void VTtoGetLLVMTyString(raw_ostream &OS, const Record *VT) { in VTtoGetLLVMTyString()
84 for (auto *VT : ValueTypes) { in run() local
113 for (const auto *VT : VTsByNumber) { in run() local
166 for (const auto *VT : VTsByNumber) { in run() local
182 for (const auto *VT : VTsByNumber) { in run() local
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h261 SimpleValueType VT = EltTyTable[SimpleTy - FIRST_VALUETYPE]; in getVectorElementType() local
371 bool knownBitsGT(MVT VT) const { in knownBitsGT()
377 bool knownBitsGE(MVT VT) const { in knownBitsGE()
382 bool knownBitsLT(MVT VT) const { in knownBitsLT()
388 bool knownBitsLE(MVT VT) const { in knownBitsLE()
393 bool bitsGT(MVT VT) const { in bitsGT()
400 bool bitsGE(MVT VT) const { in bitsGE()
407 bool bitsLT(MVT VT) const { in bitsLT()
414 bool bitsLE(MVT VT) const { in bitsLE()
440 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h458 virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const { in shouldExpandGetActiveLaneMask()
469 virtual bool shouldExpandCttzElements(EVT VT) const { return true; } in shouldExpandCttzElements()
479 virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const { in shouldReassociateReduction()
501 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
543 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap()
546 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem()
706 virtual bool isCtpopFast(EVT VT) const { in isCtpopFast()
712 virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const { in getCustomCtpopCost()
756 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const { in convertSetCCLogicToBitwiseLogic()
765 MVT VT = MVT::getIntegerVT(NumBits); in hasFastEqualityCompare() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp49 for (EVT VT : VTs) { in computeLegalValueVTs() local
128 for (auto VT : MFI.getParams()) in WebAssemblyFunctionInfo() local
130 for (auto VT : MFI.getResults()) in WebAssemblyFunctionInfo() local
159 for (auto VT : YamlMFI.Params) in initializeBaseYamlFields() local
161 for (auto VT : YamlMFI.Results) in initializeBaseYamlFields() local
H A DWebAssemblyMachineFunctionInfo.h81 void addParam(MVT VT) { Params.push_back(VT); } in addParam()
84 void addResult(MVT VT) { Results.push_back(VT); } in addResult()
93 void setLocal(size_t i, MVT VT) { Locals[i] = VT; } in setLocal()
94 void addLocal(MVT VT) { Locals.push_back(VT); } in addLocal()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp103 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, in getFPLibCall()
447 MVT VT) { in getOUTLINE_ATOMIC()
488 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC()
689 for (MVT VT : MVT::fp_valuetypes()) { in initActions() local
698 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
1063 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT()
1379 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1518 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown()
1648 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1697 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, in allowsMemoryAccessForAlignment()
[all …]
H A DCallingConvLower.cpp103 MVT VT = Outs[i].VT; in CheckReturn() local
117 MVT VT = Outs[i].VT; in AnalyzeReturn() local
165 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
178 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
193 static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) { in isValueTypeInRegForCC()
202 MVT VT, CCAssignFn Fn) { in getRemainingRegParmsForType()
H A DValueTypes.cpp39 EVT VT; in getExtendedIntegerVT() local
45 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, in getExtendedVectorVT()
54 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, ElementCount EC) { in getExtendedVectorVT()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp229 static MVT scaleVectorType(MVT VT) { in scaleVectorType()
257 static void genShuffleBland(MVT VT, ArrayRef<int> Mask, in genShuffleBland()
287 static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix, in reorderSubVector()
327 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
367 MVT VT = MVT::getVectorVT(MVT::i8, NumOfElm); in interleave8bitStride4() local
436 static void createShuffleStride(MVT VT, int Stride, in createShuffleStride()
450 static void setGroupSize(MVT VT, SmallVectorImpl<int> &SizeInfo) { in setGroupSize()
473 static void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask()
558 MVT VT = MVT::getVT(Shuffles[0]->getType()); in deinterleave8bitStride3() local
606 static void group2Shuffle(MVT VT, SmallVectorImpl<int> &Mask, in group2Shuffle()
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H A DX86FastISel.cpp290 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { in isTypeLegal()
316 bool X86FastISel::X86FastEmitLoad(MVT VT, X86AddressMode &AM, in X86FastEmitLoad()
479 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM, in X86FastEmitStore()
652 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, in X86FastEmitStore()
1151 MVT VT; in X86SelectStore() local
1339 MVT VT; in X86SelectLoad() local
1358 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { in X86ChooseCmpOpcode()
1385 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { in X86ChooseCmpImmediateOpcode()
1403 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, EVT VT, in X86FastEmitCompare()
1439 MVT VT; in X86SelectCmp() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DNumericalStabilitySanitizer.cpp231 static Type *typeFromFTValueType(FTValueType VT, LLVMContext &Context) { in typeFromFTValueType()
246 static const char *typeNameFromFTValueType(FTValueType VT) { in typeNameFromFTValueType()
268 for (int VT = 0; VT < kNumValueTypes; ++VT) { in MappingConfig() local
312 if (const auto VT = ftValueTypeFromType(FT)) in getExtendedFPType() local
340 if (const auto VT = ftValueTypeFromType(FT)) in getMemoryExtentsOrDie() local
612 const FTValueType VT = static_cast<FTValueType>(I); in NumericalStabilitySanitizer() local
716 Type *VT = Arg.getType(); in createShadowArguments() local
815 Type *VT = Arg->getType(); in populateShadowStack() local
848 if (const auto VT = ftValueTypeFromType(Ty)) in emitCheckInternal() local
1049 Type *VT = Phi.getType(); in maybeCreateShadowPhi() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp165 auto addRegClassForRVV = [this](MVT VT) { in RISCVTargetLowering() argument
188 for (MVT VT : BoolVecVTs) in RISCVTargetLowering() local
190 for (MVT VT : IntVecVTs) { in RISCVTargetLowering() local
198 for (MVT VT in RISCVTargetLowering() local
202 for (MVT VT : BF16VecVTs) RISCVTargetLowering() local
206 for (MVT VT : F32VecVTs) RISCVTargetLowering() local
210 for (MVT VT : F64VecVTs) RISCVTargetLowering() local
214 __anon765c18b70202(MVT VT) RISCVTargetLowering() argument
220 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) RISCVTargetLowering() local
224 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) RISCVTargetLowering() local
745 for (MVT VT : BoolVecVTs) { RISCVTargetLowering() local
815 for (MVT VT : IntVecVTs) { RISCVTargetLowering() local
968 __anon765c18b70302(MVT VT) RISCVTargetLowering() argument
1046 __anon765c18b70402(MVT VT, ArrayRef<MVT::SimpleValueType> SmallerVTs) RISCVTargetLowering() argument
1054 for (MVT VT : F16VecVTs) { RISCVTargetLowering() local
1060 for (MVT VT : F16VecVTs) { RISCVTargetLowering() local
1096 for (MVT VT : BF16VecVTs) { RISCVTargetLowering() local
1117 for (MVT VT : F32VecVTs) { RISCVTargetLowering() local
1126 for (MVT VT : F64VecVTs) { RISCVTargetLowering() local
1136 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { RISCVTargetLowering() local
1285 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { RISCVTargetLowering() local
1962 EVT VT = Y.getValueType(); hasAndNotCompare() local
2253 isFPImmLegal(const APFloat & Imm,EVT VT,bool ForCodeSize) const isFPImmLegal() argument
2368 getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const getVectorTypeBreakdownForCallingConv() argument
2448 getLMUL(MVT VT) getLMUL() argument
2492 getSubregIndexByMVT(MVT VT,unsigned Index) getSubregIndexByMVT() argument
2515 getRegClassIDForVecVT(MVT VT) getRegClassIDForVecVT() argument
2605 useRVVForFixedLengthVectorVT(MVT VT,const RISCVSubtarget & Subtarget) useRVVForFixedLengthVectorVT() argument
2681 getContainerForFixedLengthVector(const TargetLowering & TLI,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2716 getContainerForFixedLengthVector(SelectionDAG & DAG,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2727 convertToScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertToScalableVector() argument
2739 convertFromScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertFromScalableVector() argument
2847 shouldExpandBuildVectorWithShuffles(EVT VT,unsigned DefinedValues) const shouldExpandBuildVectorWithShuffles() argument
3041 MVT VT = Op.getSimpleValueType(); lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local
3151 MVT VT = Op.getSimpleValueType(); lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() local
3251 MVT VT = Op.getSimpleValueType(); lowerFTRUNC_FCEIL_FFLOOR_FROUND() local
3279 MVT VT = Op.getSimpleValueType(); lowerVectorXRINT() local
3303 getVSlidedown(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlidedown() argument
3315 getVSlideup(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlideup() argument
3325 getLMUL1VT(MVT VT) getLMUL1VT() argument
3470 matchSplatAsGather(SDValue SplatVal,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) matchSplatAsGather() argument
3514 MVT VT = Op.getSimpleValueType(); lowerBuildVectorViaDominantValues() local
3621 MVT VT = Op.getSimpleValueType(); lowerBuildVectorOfConstants() local
3943 MVT VT = Op.getSimpleValueType(); lowerBuildVectorViaPacking() local
4000 MVT VT = Op.getSimpleValueType(); lowerBUILD_VECTORvXf16() local
4011 MVT VT = Op.getSimpleValueType(); lowerBUILD_VECTOR() local
4237 splatPartsI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Lo,SDValue Hi,SDValue VL,SelectionDAG & DAG) splatPartsI64WithVL() argument
4293 splatSplitI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Scalar,SDValue VL,SelectionDAG & DAG) splatSplitI64WithVL() argument
4306 lowerScalarSplat(SDValue Passthru,SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarSplat() argument
4343 lowerScalarInsert(SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarInsert() argument
4403 isDeinterleaveShuffle(MVT VT,MVT ContainerVT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget) isDeinterleaveShuffle() argument
4448 isInterleaveShuffle(ArrayRef<int> Mask,MVT VT,int & EvenSrc,int & OddSrc,const RISCVSubtarget & Subtarget) isInterleaveShuffle() argument
4558 getDeinterleaveViaVNSRL(const SDLoc & DL,MVT VT,SDValue Src,bool EvenElts,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) getDeinterleaveViaVNSRL() argument
4617 lowerVECTOR_SHUFFLEAsVSlidedown(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlidedown() argument
4694 lowerVECTOR_SHUFFLEAsVSlideup(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlideup() argument
4738 lowerVECTOR_SHUFFLEAsVSlide1(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlide1() argument
4896 MVT VT = SVN->getSimpleValueType(0); lowerBitreverseShuffle() local
4950 EVT VT = SVN->getValueType(0); isLegalBitRotate() local
4972 EVT VT = SVN->getValueType(0); lowerVECTOR_SHUFFLEAsRotate() local
4999 MVT VT = SVN->getSimpleValueType(0); lowerShuffleViaVRegSplitting() local
5083 MVT VT = Op.getSimpleValueType(); lowerVECTOR_SHUFFLE() local
5404 MVT VT = Op.getSimpleValueType(); lowerCTLZ_CTTZ_ZERO_UNDEF() local
5571 MVT VT = Op.getSimpleValueType(); expandUnalignedRVVLoad() local
5602 MVT VT = StoredVal.getSimpleValueType(); expandUnalignedRVVStore() local
5760 MVT VT = Op.getSimpleValueType(); LowerIS_FPCLASS() local
5862 MVT VT = Op.getSimpleValueType(); lowerFMAXIMUM_FMINIMUM() local
6297 EVT VT = Op.getValueType(); LowerOperation() local
6379 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6414 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6435 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6491 EVT VT = Op.getValueType(); LowerOperation() local
6508 EVT VT = Op.getValueType(); LowerOperation() local
6571 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6720 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6867 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6932 EVT VT = Op.getValueType(); LowerOperation() local
6945 MVT VT = Op.getSimpleValueType(); LowerOperation() local
7047 EVT VT = Op->getValueType(0); LowerOperation() local
7562 MVT VT = N->getSimpleValueType(0); combineSelectToBinOp() local
7665 EVT VT = BO->getValueType(0); foldBinOpIntoSelectIfProfitable() local
7696 MVT VT = Op.getSimpleValueType(); lowerSELECT() local
7916 EVT VT = Op.getValueType(); lowerFRAMEADDR() local
7942 EVT VT = Op.getValueType(); lowerRETURNADDR() local
7966 EVT VT = Lo.getValueType(); lowerShiftLeftParts() local
8005 EVT VT = Lo.getValueType(); lowerShiftRightParts() local
8056 MVT VT = Op.getSimpleValueType(); lowerVectorMaskSplat() local
8153 MVT VT = Op.getOperand(0).getSimpleValueType(); lowerFixedLengthVectorExtendToRVV() local
8234 MVT VT = Op.getSimpleValueType(); lowerVectorTruncLike() local
8297 MVT VT = Op.getSimpleValueType(); lowerStrictFPExtendOrRoundLike() local
8351 MVT VT = Op.getSimpleValueType(); lowerVectorFPExtendOrRoundLike() local
8815 MVT VT = Op.getOperand(SplatOp - 1).getSimpleValueType(); lowerVectorIntrinsicScalars() local
9070 isValidEGW(int EGS,EVT VT,const RISCVSubtarget & Subtarget) isValidEGW() argument
9246 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
9326 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
9363 MVT VT = Op.getSimpleValueType(); getVCIXISDNodeWCHAIN() local
9416 MVT VT = Op->getSimpleValueType(0); LowerINTRINSIC_W_CHAIN() local
9498 MVT VT = Op->getSimpleValueType(0); LowerINTRINSIC_W_CHAIN() local
9571 MVT VT = Val.getSimpleValueType(); LowerINTRINSIC_VOID() local
9619 MVT VT = Op->getOperand(2).getSimpleValueType(); LowerINTRINSIC_VOID() local
10422 MVT VT = N.getSimpleValueType(); widenVectorOpsToi8() local
10618 MVT VT = Op.getSimpleValueType(); lowerSTEP_VECTOR() local
10764 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorLoadToRVV() local
10814 MVT VT = StoreVal.getSimpleValueType(); lowerFixedLengthVectorStoreToRVV() local
10858 MVT VT = Op.getSimpleValueType(); lowerMaskedLoad() local
10946 MVT VT = Val.getSimpleValueType(); lowerMaskedStore() local
10991 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorSetccToRVV() local
11019 MVT VT = Op.getSimpleValueType(); lowerVectorStrictFSetcc() local
11101 MVT VT = Op.getSimpleValueType(); lowerABS() local
11139 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorFCOPYSIGNToRVV() local
11159 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorSelectToRVV() local
11187 MVT VT = Op.getSimpleValueType(); lowerToScalableOp() local
11240 MVT VT = Op.getSimpleValueType(); lowerVPOp() local
11293 MVT VT = Op.getSimpleValueType(); lowerVPExtMaskOp() local
11326 MVT VT = Op.getSimpleValueType(); lowerVPSetCCMaskOp() local
11530 MVT VT = Op.getSimpleValueType(); lowerVPFPIntConvOp() local
11549 MVT VT = Op.getSimpleValueType(); lowerVPSpliceExperimental() local
11626 MVT VT = Op.getSimpleValueType(); lowerVPSplatExperimental() local
11647 MVT VT = Op.getSimpleValueType(); lowerVPReverseExperimental() local
11766 MVT VT = Op.getSimpleValueType(); lowerLogicVPOp() local
11794 MVT VT = Op.getSimpleValueType(); lowerVPStridedLoad() local
11843 MVT VT = StoreVal.getSimpleValueType(); lowerVPStridedStore() local
11882 MVT VT = Op.getSimpleValueType(); lowerMaskedGather() local
12006 MVT VT = Val.getSimpleValueType(); lowerMaskedScatter() local
12440 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
12601 EVT VT = N->getValueType(0); ReplaceNodeResults() local
12642 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
12839 EVT VT = N->getValueType(0); ReplaceNodeResults() local
12959 const EVT VT = N->getValueType(0); combineBinOpOfExtractToReduceTree() local
13153 EVT VT = N->getValueType(0); transformAddShlImm() local
13204 EVT VT = N->getValueType(0); combineSelectAndUse() local
13299 EVT VT = N->getValueType(0); transformAddImmMulImm() local
13358 EVT VT = N->getValueType(0); combineBinOpOfZExt() local
13401 EVT VT = N->getValueType(0); combineAddOfBooleanXor() local
13449 EVT VT = N->getValueType(0); combineSubOfBoolean() local
13493 EVT VT = N->getValueType(0); combineSubShiftToOrcB() local
13520 EVT VT = N->getValueType(0); performSUBCombine() local
13575 EVT VT = N->getValueType(0); combineDeMorganOfBoolean() local
13599 EVT VT = N->getValueType(0); combineTruncSelectToSMaxUSat() local
13665 EVT VT = N->getValueType(0); performTRUNCATECombine() local
13751 EVT VT = N->getValueType(0); combineOrOfCZERO() local
13825 EVT VT = N0.getValueType(); performXORCombine() local
13866 EVT VT = N->getValueType(0); expandMul() local
14016 EVT VT = N->getValueType(0); combineVectorMulToSraBitcast() local
14054 EVT VT = N->getValueType(0); performMULCombine() local
14109 EVT VT = N.getValueType(); narrowIndex() local
14175 EVT VT = N->getValueType(0); performSETCCCombine() local
14221 EVT VT = N->getValueType(0); performSIGN_EXTEND_INREGCombine() local
14367 MVT VT = Root->getSimpleValueType(0); getNarrowType() local
14489 MVT VT = OrigOperand.getSimpleValueType(); fillUpExtensionSupportForSplat() local
14553 MVT VT = OrigOperand.getSimpleValueType(); fillUpExtensionSupport() local
14581 MVT VT = OrigOperand.getSimpleValueType(); fillUpExtensionSupport() local
14694 MVT VT = Root->getSimpleValueType(0); getMaskAndVL() local
15309 EVT VT = N->getValueType(0); performFP_TO_INTCombine() local
15455 EVT VT = N->getValueType(0); performBITREVERSECombine() local
15737 EVT VT = Cond.getValueType(); tryDemorganOfBooleanCondition() local
15896 EVT VT = N->getValueType(0); tryFoldSelectIntoOp() local
15980 EVT VT = N->getValueType(0); useInversedSetcc() local
16032 EVT VT = N->getValueType(0); performBUILD_VECTORCombine() local
16094 EVT VT = InVec.getValueType(); performINSERT_VECTOR_ELTCombine() local
16162 EVT VT = N->getValueType(0); performCONCAT_VECTORSCombine() local
16349 EVT VT = N->getValueType(0); combineToVWMACC() local
16388 matchIndexAsShuffle(EVT VT,SDValue Index,SDValue Mask,SmallVector<int> & ShuffleMask) matchIndexAsShuffle() argument
16423 matchIndexAsWiderOp(EVT VT,SDValue Index,SDValue Mask,Align BaseAlign,const RISCVSubtarget & ST) matchIndexAsWiderOp() argument
16528 MVT VT = N->getSimpleValueType(0); combineTruncToVnclip() local
16755 MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
16787 EVT VT = N->getValueType(0); PerformDAGCombine() local
16921 EVT VT = N->getValueType(0); PerformDAGCombine() local
17036 EVT VT = N->getValueType(0); PerformDAGCombine() local
17061 const EVT VT = N->getValueType(0); PerformDAGCombine() local
17183 EVT VT = MSN->getValue()->getValueType(0); PerformDAGCombine() local
17256 EVT VT = N->getValueType(0); PerformDAGCombine() local
17278 EVT VT = N->getValueType(0); PerformDAGCombine() local
17421 EVT VT = N->getValueType(0); PerformDAGCombine() local
17443 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17454 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17486 EVT VT = N->getValueType(0); PerformDAGCombine() local
17497 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17550 MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17598 EVT VT = N->getValueType(0); PerformDAGCombine() local
17609 EVT VT = N->getValueType(0); PerformDAGCombine() local
17709 EVT VT = Op.getValueType(); targetShrinkDemandedConstant() local
19883 getPrefTypeAlign(EVT VT,SelectionDAG & DAG) getPrefTypeAlign() argument
20200 MVT VT = Outs[i].VT; CanLowerReturn() local
21225 EVT VT; getPreIndexedAddressParts() local
21268 EVT VT; getPostIndexedAddressParts() local
21344 decomposeMulByConstant(LLVMContext & Context,EVT VT,SDValue C) const decomposeMulByConstant() argument
21386 EVT VT = AddNode.getValueType(); isMulAddWithConstProfitable() local
21407 allowsMisalignedMemoryAccesses(EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMisalignedMemoryAccesses() argument
21576 isIntDivCheap(EVT VT,AttributeList Attr) const isIntDivCheap() argument
21619 EVT VT = getValueType(DL, VTy); isLegalInterleavedAccessType() local
21901 getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const getRegisterByName() argument
21975 getCustomCtpopCost(EVT VT,ISD::CondCode Cond) const getCustomCtpopCost() argument
22018 EVT VT = N->getValueType(0); BuildSDIVPow2() local
22029 shouldFoldSelectWithSingleBitTest(EVT VT,const APInt & AndMask) const shouldFoldSelectWithSingleBitTest() argument
22108 EVT VT = TLI->getValueType(DL, ElemTy); constructArgInfos() local
22122 EVT VT = ValueVTs[Value]; constructArgInfos() local
[all...]
H A DRISCVISelDAGToDAG.cpp63 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
80 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
175 static SDValue selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, in selectImmSeq()
204 static SDValue selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, in selectImm()
343 MVT VT = Node->getSimpleValueType(0); in selectVLSEG() local
382 MVT VT = Node->getSimpleValueType(0); in selectVLSEGFF() local
425 MVT VT = Node->getSimpleValueType(0); in selectVLXSEG() local
480 MVT VT = Node->getOperand(2)->getSimpleValueType(0); in selectVSSEG() local
510 MVT VT = Node->getOperand(2)->getSimpleValueType(0); in selectVSXSEG() local
605 MVT VT = Node->getSimpleValueType(0); in tryShrinkShlLogicImm() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp167 EVT VT = N->getValueType(0); in SelectExtractHigh() local
181 EVT VT = Op.getValueType(); in SelectRoundingVLShr() local
728 EVT VT = N.getValueType(); in SelectShiftedRegisterFromAnd() local
1469 EVT VT = N->getValueType(0); in SelectTable() local
1581 EVT VT = LD->getMemoryVT(); in tryIndexedLoad() local
1681 EVT VT = N->getValueType(0); in SelectLoad() local
1710 EVT VT = N->getValueType(0); in SelectPostLoad() local
1774 static unsigned SelectOpcodeFromVT(EVT VT, ArrayRef<unsigned> Opcodes) { in SelectOpcodeFromVT()
1833 EVT VT = N->getValueType(0); in SelectPExtPair() local
1847 EVT VT = N->getValueType(0); in SelectWhilePair() local
[all …]
H A DAArch64ISelLowering.cpp172 static inline EVT getPackedSVEVectorVT(EVT VT) { in getPackedSVEVectorVT()
212 static inline EVT getPromotedVTForPredicate(EVT VT) { in getPromotedVTForPredicate()
234 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType()
453 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
457 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
633 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
685 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
1028 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
1035 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering() local
1323 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
183 for (MVT VT : MVT::integer_valuetypes()) in AMDGPUTargetLowering() local
187 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
199 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in AMDGPUTargetLowering() local
461 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering() local
507 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering() local
528 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering() local
703 static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) { in opMustUseVOP3Encoding()
764 MVT VT = N->getValueType(0).getScalarType().getSimpleVT(); in allUsesHaveSourceMods() local
782 EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, in getTypeForExtReturn()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp47 MVT VT = Node->getSimpleValueType(0); in INITIALIZE_PASS() local
209 MVT VT = Addr.getSimpleValueType(); in SelectAddrConstant() local
275 EVT VT = N.getValueType(); in selectShiftMask() local
302 MVT VT = N.getSimpleValueType(); in selectSExti32() local
319 MVT VT = N.getSimpleValueType(); in selectZExti32() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp391 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { in ARMMoveToFPReg()
401 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { in ARMMoveToIntReg()
414 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { in ARMMaterializeFP()
453 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { in ARMMaterializeInt()
522 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { in ARMMaterializeGV()
629 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
647 MVT VT; in fastMaterializeAlloca() local
671 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
683 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
800 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { in ARMSimplifyAddress()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/
H A DWebAssemblyAsmTypeCheck.cpp159 for (auto VT : llvm::reverse(LastSig.Returns)) { in checkEnd() local
174 for (auto VT : llvm::reverse(Sig.Params)) in checkSig() local
416 auto VT = WebAssembly::regClassToValType(Op.RegClass); in typeCheck() local
425 auto VT = WebAssembly::regClassToValType(Op.RegClass); in typeCheck() local

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