1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 3 4 #ifndef DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H 5 #define DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H 6 7 #define TEGRA264_SID(x) ((x) << 8) 8 9 /* 10 * SMMU stream IDs 11 */ 12 13 #define TEGRA264_SID_AON TEGRA264_SID(0x01) 14 #define TEGRA264_SID_APE TEGRA264_SID(0x02) 15 #define TEGRA264_SID_ETR TEGRA264_SID(0x03) 16 #define TEGRA264_SID_BPMP TEGRA264_SID(0x04) 17 #define TEGRA264_SID_DCE TEGRA264_SID(0x05) 18 #define TEGRA264_SID_EQOS TEGRA264_SID(0x06) 19 #define TEGRA264_SID_GPCDMA TEGRA264_SID(0x08) 20 #define TEGRA264_SID_DISP TEGRA264_SID(0x09) 21 #define TEGRA264_SID_HDA TEGRA264_SID(0x0a) 22 #define TEGRA264_SID_HOST1X TEGRA264_SID(0x0b) 23 #define TEGRA264_SID_ISP0 TEGRA264_SID(0x0c) 24 #define TEGRA264_SID_ISP1 TEGRA264_SID(0x0d) 25 #define TEGRA264_SID_PMA0 TEGRA264_SID(0x0e) 26 #define TEGRA264_SID_FSI0 TEGRA264_SID(0x0f) 27 #define TEGRA264_SID_FSI1 TEGRA264_SID(0x10) 28 #define TEGRA264_SID_PVA TEGRA264_SID(0x11) 29 #define TEGRA264_SID_SDMMC0 TEGRA264_SID(0x12) 30 #define TEGRA264_SID_MGBE0 TEGRA264_SID(0x13) 31 #define TEGRA264_SID_MGBE1 TEGRA264_SID(0x14) 32 #define TEGRA264_SID_MGBE2 TEGRA264_SID(0x15) 33 #define TEGRA264_SID_MGBE3 TEGRA264_SID(0x16) 34 #define TEGRA264_SID_MSSSEQ TEGRA264_SID(0x17) 35 #define TEGRA264_SID_SE TEGRA264_SID(0x18) 36 #define TEGRA264_SID_SEU1 TEGRA264_SID(0x19) 37 #define TEGRA264_SID_SEU2 TEGRA264_SID(0x1a) 38 #define TEGRA264_SID_SEU3 TEGRA264_SID(0x1b) 39 #define TEGRA264_SID_PSC TEGRA264_SID(0x1c) 40 #define TEGRA264_SID_OESP TEGRA264_SID(0x23) 41 #define TEGRA264_SID_SB TEGRA264_SID(0x24) 42 #define TEGRA264_SID_XSPI0 TEGRA264_SID(0x25) 43 #define TEGRA264_SID_TSEC TEGRA264_SID(0x29) 44 #define TEGRA264_SID_UFS TEGRA264_SID(0x2a) 45 #define TEGRA264_SID_RCE TEGRA264_SID(0x2b) 46 #define TEGRA264_SID_RCE1 TEGRA264_SID(0x2c) 47 #define TEGRA264_SID_VI TEGRA264_SID(0x2e) 48 #define TEGRA264_SID_VI1 TEGRA264_SID(0x2f) 49 #define TEGRA264_SID_VIC TEGRA264_SID(0x30) 50 #define TEGRA264_SID_XUSB_DEV TEGRA264_SID(0x32) 51 #define TEGRA264_SID_XUSB_DEV1 TEGRA264_SID(0x33) 52 #define TEGRA264_SID_XUSB_DEV2 TEGRA264_SID(0x34) 53 #define TEGRA264_SID_XUSB_DEV3 TEGRA264_SID(0x35) 54 #define TEGRA264_SID_XUSB_DEV4 TEGRA264_SID(0x36) 55 #define TEGRA264_SID_XUSB_DEV5 TEGRA264_SID(0x37) 56 57 /* 58 * memory client IDs 59 */ 60 61 /* HOST1X read client */ 62 #define TEGRA264_MEMORY_CLIENT_HOST1XR 0x16 63 /* VIC read client */ 64 #define TEGRA264_MEMORY_CLIENT_VICR 0x6c 65 /* VIC Write client */ 66 #define TEGRA264_MEMORY_CLIENT_VICW 0x6d 67 /* VI R5 Write client */ 68 #define TEGRA264_MEMORY_CLIENT_VIW 0x72 69 #define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC 0x78 70 #define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC 0x79 71 /* Audio processor(APE) Read client */ 72 #define TEGRA264_MEMORY_CLIENT_APER 0x7a 73 /* Audio processor(APE) Write client */ 74 #define TEGRA264_MEMORY_CLIENT_APEW 0x7b 75 /* Audio DMA Read client */ 76 #define TEGRA264_MEMORY_CLIENT_APEDMAR 0x9f 77 /* Audio DMA Write client */ 78 #define TEGRA264_MEMORY_CLIENT_APEDMAW 0xa0 79 #define TEGRA264_MEMORY_CLIENT_GPUR02MC 0xb6 80 #define TEGRA264_MEMORY_CLIENT_GPUW02MC 0xb7 81 /* VI Falcon Read client */ 82 #define TEGRA264_MEMORY_CLIENT_VIFALCONR 0xbc 83 /* VI Falcon Write client */ 84 #define TEGRA264_MEMORY_CLIENT_VIFALCONW 0xbd 85 /* Read Client of RCE */ 86 #define TEGRA264_MEMORY_CLIENT_RCER 0xd2 87 /* Write client of RCE */ 88 #define TEGRA264_MEMORY_CLIENT_RCEW 0xd3 89 /* PCIE0/MSI Write clients */ 90 #define TEGRA264_MEMORY_CLIENT_PCIE0W 0xd9 91 /* PCIE1/RPX4 Read clients */ 92 #define TEGRA264_MEMORY_CLIENT_PCIE1R 0xda 93 /* PCIE1/RPX4 Write clients */ 94 #define TEGRA264_MEMORY_CLIENT_PCIE1W 0xdb 95 /* PCIE2/DMX4 Read clients */ 96 #define TEGRA264_MEMORY_CLIENT_PCIE2AR 0xdc 97 /* PCIE2/DMX4 Write clients */ 98 #define TEGRA264_MEMORY_CLIENT_PCIE2AW 0xdd 99 /* PCIE3/RPX4 Read clients */ 100 #define TEGRA264_MEMORY_CLIENT_PCIE3R 0xde 101 /* PCIE3/RPX4 Write clients */ 102 #define TEGRA264_MEMORY_CLIENT_PCIE3W 0xdf 103 /* PCIE4/DMX8 Read clients */ 104 #define TEGRA264_MEMORY_CLIENT_PCIE4R 0xe0 105 /* PCIE4/DMX8 Write clients */ 106 #define TEGRA264_MEMORY_CLIENT_PCIE4W 0xe1 107 /* PCIE5/DMX4 Read clients */ 108 #define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2 109 /* PCIE5/DMX4 Write clients */ 110 #define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3 111 /* UFS Read client */ 112 #define TEGRA264_MEMORY_CLIENT_UFSR 0x15c 113 /* UFS write client */ 114 #define TEGRA264_MEMORY_CLIENT_UFSW 0x15d 115 /* HDA Read client */ 116 #define TEGRA264_MEMORY_CLIENT_HDAR 0x17c 117 /* HDA Write client */ 118 #define TEGRA264_MEMORY_CLIENT_HDAW 0x17d 119 /* Disp ISO Read Client */ 120 #define TEGRA264_MEMORY_CLIENT_DISPR 0x182 121 /* MGBE0 Read mccif */ 122 #define TEGRA264_MEMORY_CLIENT_MGBE0R 0x1a2 123 /* MGBE0 Write mccif */ 124 #define TEGRA264_MEMORY_CLIENT_MGBE0W 0x1a3 125 /* MGBE1 Read mccif */ 126 #define TEGRA264_MEMORY_CLIENT_MGBE1R 0x1a4 127 /* MGBE1 Write mccif */ 128 #define TEGRA264_MEMORY_CLIENT_MGBE1W 0x1a5 129 /* VI1 R5 Write client */ 130 #define TEGRA264_MEMORY_CLIENT_VI1W 0x1a6 131 /* SDMMC0 Read mccif */ 132 #define TEGRA264_MEMORY_CLIENT_SDMMC0R 0x1c2 133 /* SDMMC0 Write mccif */ 134 #define TEGRA264_MEMORY_CLIENT_SDMMC0W 0x1c3 135 136 #endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */ 137