1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // SpacemiT K1 SPI controller driver
4 //
5 // Copyright (C) 2026, RISCstar Solutions Corporation
6 // Copyright (C) 2023, SpacemiT Corporation
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
18 #include <linux/scatterlist.h>
19 #include <linux/sizes.h>
20 #include <linux/spi/spi.h>
21 #include <linux/units.h>
22
23 #include "internals.h"
24
25 /* This is the range of transfer rates supported by the K1 SoC */
26 #define K1_SPI_MIN_SPEED_HZ 6250
27 #define K1_SPI_MAX_SPEED_HZ 51200000
28
29 /* DMA constraints */
30 #define K1_SPI_DMA_ALIGNMENT 64
31 #define K1_SPI_MAX_DMA_LEN SZ_512K
32
33 /* SSP Top Control Register */
34 #define SSP_TOP_CTRL 0x00
35 #define TOP_SSE BIT(0) /* Enable port */
36 #define TOP_FRF_MASK GENMASK(2, 1) /* Frame format */
37 #define TOP_FRF_MOTOROLA 0 /* Motorola SPI */
38 #define TOP_DSS_MASK GENMASK(9, 5) /* Data size (1-32) */
39 #define TOP_SPO BIT(10) /* Polarity: 0=low */
40 #define TOP_SPH BIT(11) /* Half-cycle phase */
41 #define TOP_LBM BIT(12) /* Loopback mode */
42 #define TOP_TRAIL BIT(13) /* Trailing bytes */
43 #define TOP_HOLD_FRAME_LOW BIT(14) /* Chip select */
44
45 /* SSP FIFO Control Register */
46 #define SSP_FIFO_CTRL 0x04
47 #define FIFO_TFT_MASK GENMASK(4, 0) /* TX FIFO threshold */
48 #define FIFO_RFT_MASK GENMASK(9, 5) /* RX FIFO threshold */
49 #define FIFO_TSRE BIT(10) /* TX service request */
50 #define FIFO_RSRE BIT(11) /* RX service request */
51
52 /* SSP Interrupt Enable Register */
53 #define SSP_INT_EN 0x08
54 #define SSP_INT_EN_TINTE BIT(1) /* RX timeout */
55 #define SSP_INT_EN_RIE BIT(2) /* RX FIFO */
56 #define SSP_INT_EN_TIE BIT(3) /* TX FIFO */
57 #define SSP_INT_EN_RIM BIT(4) /* RX FIFO overrun */
58 #define SSP_INT_EN_TIM BIT(5) /* TX FIFO underrun */
59 #define SSP_INT_EN_EBCEI BIT(6) /* Bit count error */
60
61 /* TX interrupts, RX interrupts, and error interrupts */
62 #define SSP_INT_EN_TX SSP_INT_EN_TIE
63 #define SSP_INT_EN_RX \
64 (SSP_INT_EN_TINTE | SSP_INT_EN_RIE)
65 #define SSP_INT_EN_ERROR \
66 (SSP_INT_EN_RIM | SSP_INT_EN_TIM | SSP_INT_EN_EBCEI)
67
68 /* SSP Time Out Register */
69 #define SSP_TIMEOUT 0x0c
70 #define SSP_TIMEOUT_MASK GENMASK(23, 0)
71
72 /* SSP Data Register */
73 #define SSP_DATAR 0x10
74
75 /* SSP Status Register */
76 #define SSP_STATUS 0x14
77 #define SSP_STATUS_BSY BIT(0) /* SPI/I2S busy */
78 #define SSP_STATUS_TNF BIT(6) /* TX FIFO not full */
79 #define SSP_STATUS_TFL GENMASK(11, 7) /* TX FIFO level */
80 #define SSP_STATUS_TUR BIT(12) /* TX FIFO underrun */
81 #define SSP_STATUS_RNE BIT(14) /* RX FIFO not empty */
82 #define SSP_STATUS_RFL GENMASK(19, 15) /* RX FIFO level */
83 #define SSP_STATUS_ROR BIT(20) /* RX FIFO overrun */
84 #define SSP_STATUS_BCE BIT(21) /* Bit count error */
85
86 /* Error status mask */
87 #define SSP_STATUS_ERROR \
88 (SSP_STATUS_TUR | SSP_STATUS_ROR | SSP_STATUS_BCE)
89
90 /* The FIFO sizes and thresholds are the same for RX and TX */
91 #define K1_SPI_FIFO_SIZE 32
92 #define K1_SPI_THRESH (K1_SPI_FIFO_SIZE / 2)
93
94 struct k1_spi_driver_data {
95 struct spi_controller *host;
96 void __iomem *base;
97 phys_addr_t base_addr;
98 unsigned long bus_rate;
99 struct clk *clk;
100 unsigned long rate;
101 int irq;
102
103 /* Current transfer information; not valid if message is null */
104 u32 bytes; /* Bytes used for bits_per_word */
105 unsigned int rx_resid; /* RX bytes left in transfer */
106 unsigned int tx_resid; /* TX bytes left in transfer */
107 struct spi_transfer *transfer; /* Current transfer */
108
109 bool dma_enabled;
110 };
111
112 /* Set our registers to a known initial state */
113 static void
k1_spi_register_reset(struct k1_spi_driver_data * drv_data,bool initial)114 k1_spi_register_reset(struct k1_spi_driver_data *drv_data, bool initial)
115 {
116 u32 val = 0;
117
118 writel(0, drv_data->base + SSP_TOP_CTRL);
119
120 if (initial) {
121 /*
122 * The TX and RX FIFO thresholds are the same no matter
123 * what the speed or bits per word, so we can just set
124 * them once. The thresholds are one more than the values
125 * in the register.
126 */
127 val = FIELD_PREP(FIFO_RFT_MASK, K1_SPI_THRESH - 1);
128 val |= FIELD_PREP(FIFO_TFT_MASK, K1_SPI_THRESH - 1);
129 }
130 writel(val, drv_data->base + SSP_FIFO_CTRL);
131
132 writel(0, drv_data->base + SSP_INT_EN);
133 writel(0, drv_data->base + SSP_TIMEOUT);
134
135 /* Clear any pending interrupt conditions */
136 writel(~0, drv_data->base + SSP_STATUS);
137 }
138
139 /*
140 * The client can call the setup function multiple times, and each call
141 * can specify a different SPI mode (and transfer speed). Each transfer
142 * can specify its own speed though, and the core code ensures each
143 * transfer's speed is set to something nonzero and supported by both
144 * the controller and the device. We just set the speed for each transfer.
145 */
k1_spi_setup(struct spi_device * spi)146 static int k1_spi_setup(struct spi_device *spi)
147 {
148 struct k1_spi_driver_data *drv_data;
149 u32 val;
150
151 drv_data = spi_controller_get_devdata(spi->controller);
152
153 /*
154 * Configure the message format for this device. We only
155 * support Motorola SPI format in master mode.
156 */
157 val = FIELD_PREP(TOP_FRF_MASK, TOP_FRF_MOTOROLA);
158
159 /* Translate the mode into the value used to program the hardware. */
160 if (spi->mode & SPI_CPHA)
161 val |= TOP_SPH; /* 1/2 cycle */
162 if (spi->mode & SPI_CPOL)
163 val |= TOP_SPO; /* active low */
164 if (spi->mode & SPI_LOOP)
165 val |= TOP_LBM; /* enable loopback */
166 writel(val, drv_data->base + SSP_TOP_CTRL);
167
168 return 0;
169 }
170
k1_spi_cleanup(struct spi_device * spi)171 static void k1_spi_cleanup(struct spi_device *spi)
172 {
173 struct k1_spi_driver_data *drv_data;
174
175 drv_data = spi_controller_get_devdata(spi->controller);
176 k1_spi_register_reset(drv_data, false);
177 }
178
k1_spi_can_dma(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * transfer)179 static bool k1_spi_can_dma(struct spi_controller *host, struct spi_device *spi,
180 struct spi_transfer *transfer)
181 {
182 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host);
183 u32 burst_size;
184
185 if (!drv_data->dma_enabled)
186 return false;
187
188 if (transfer->len > SZ_2K)
189 return false;
190
191 /* Don't bother with DMA if we can't do even a single burst */
192 burst_size = K1_SPI_THRESH * spi_bpw_to_bytes(transfer->bits_per_word);
193
194 return transfer->len >= burst_size;
195 }
196
k1_spi_dma_callback(void * param)197 static void k1_spi_dma_callback(void *param)
198 {
199 struct k1_spi_driver_data *drv_data = param;
200 u32 val;
201
202 val = readl(drv_data->base + SSP_FIFO_CTRL);
203 val &= ~(FIFO_TSRE | FIFO_RSRE);
204 writel(val, drv_data->base + SSP_FIFO_CTRL);
205
206 val = readl(drv_data->base + SSP_TOP_CTRL);
207 val &= ~TOP_TRAIL;
208 writel(val, drv_data->base + SSP_TOP_CTRL);
209
210 /* Check for any error conditions */
211 val = readl(drv_data->base + SSP_STATUS);
212 if (val & SSP_STATUS_ERROR)
213 drv_data->transfer->error |= SPI_TRANS_FAIL_IO;
214
215 /* Disable the port */
216 val = readl(drv_data->base + SSP_TOP_CTRL);
217 val &= ~TOP_SSE;
218 writel(val, drv_data->base + SSP_TOP_CTRL);
219
220 drv_data->transfer = NULL;
221
222 spi_finalize_current_transfer(drv_data->host);
223 }
224
225 /* Prepare a descriptor for TX or RX DMA */
226 static struct dma_async_tx_descriptor *
k1_spi_dma_prep(struct k1_spi_driver_data * drv_data,struct spi_transfer * transfer,bool tx)227 k1_spi_dma_prep(struct k1_spi_driver_data *drv_data,
228 struct spi_transfer *transfer, bool tx)
229 {
230 phys_addr_t addr = drv_data->base_addr + SSP_DATAR;
231 u32 burst_size = K1_SPI_THRESH * drv_data->bytes;
232 struct dma_slave_config cfg = { };
233 enum dma_transfer_direction dir;
234 enum dma_slave_buswidth width;
235 struct dma_chan *chan;
236 struct sg_table *sgt;
237
238 switch (drv_data->bytes) {
239 case 1:
240 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
241 break;
242 case 2:
243 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
244 break;
245 default: /* bytes == 4 */
246 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
247 break;
248 }
249
250 if (tx) {
251 chan = drv_data->host->dma_tx;
252 sgt = &transfer->tx_sg;
253 dir = DMA_MEM_TO_DEV;
254
255 cfg.dst_addr = addr;
256 cfg.dst_addr_width = width;
257 cfg.dst_maxburst = burst_size;
258 } else {
259 chan = drv_data->host->dma_rx;
260 sgt = &transfer->rx_sg;
261 dir = DMA_DEV_TO_MEM;
262
263 cfg.src_addr = addr;
264 cfg.src_addr_width = width;
265 cfg.src_maxburst = burst_size;
266 }
267 cfg.direction = dir;
268
269 if (dmaengine_slave_config(chan, &cfg))
270 return NULL;
271
272 return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir,
273 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
274
275 }
276
k1_spi_dma_one(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * transfer)277 static int k1_spi_dma_one(struct spi_controller *host, struct spi_device *spi,
278 struct spi_transfer *transfer)
279 {
280 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host);
281 struct dma_async_tx_descriptor *txdesc, *rxdesc;
282 u32 val;
283
284 /* Prepare the TX descriptor */
285 txdesc = k1_spi_dma_prep(drv_data, transfer, true);
286 if (!txdesc)
287 goto fallback;
288
289 /* Prepare the RX descriptor and submit it */
290 rxdesc = k1_spi_dma_prep(drv_data, transfer, false);
291 if (!rxdesc) {
292 dmaengine_terminate_sync(host->dma_tx);
293 goto fallback;
294 }
295
296 /* When RX is complete we also know TX has completed */
297 rxdesc->callback = k1_spi_dma_callback;
298 rxdesc->callback_param = drv_data;
299
300 dmaengine_submit(txdesc);
301 dmaengine_submit(rxdesc);
302
303 val = readl(drv_data->base + SSP_TOP_CTRL);
304 val |= TOP_TRAIL; /* Trailing bytes handled by DMA */
305 writel(val, drv_data->base + SSP_TOP_CTRL);
306
307 val = readl(drv_data->base + SSP_FIFO_CTRL);
308 val |= FIFO_TSRE | FIFO_RSRE;
309 writel(val, drv_data->base + SSP_FIFO_CTRL);
310
311 /* Start RX first so we're ready the instant we start transmitting */
312 dma_async_issue_pending(host->dma_rx);
313 dma_async_issue_pending(host->dma_tx);
314
315 return 1;
316 fallback:
317 transfer->error |= SPI_TRANS_FAIL_NO_START;
318
319 return -EAGAIN;
320 }
321
322 /* Flush the RX FIFO of any leftover data before processing a message */
k1_spi_prepare_message(struct spi_controller * host,struct spi_message * message)323 static int k1_spi_prepare_message(struct spi_controller *host,
324 struct spi_message *message)
325 {
326 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host);
327 u32 val = readl(drv_data->base + SSP_STATUS);
328 u32 count;
329
330 /* If there's nothing in the FIFO, we're done */
331 if (!(val & SSP_STATUS_RNE))
332 return 0;
333
334 /* Read and discard what's there (one more than what the field says) */
335 count = FIELD_GET(SSP_STATUS_RFL, val) + 1;
336 do
337 (void)readl(drv_data->base + SSP_DATAR);
338 while (--count);
339
340 return 0;
341 }
342
343 /* Set logic level of chip select line (high=true means CS deasserted) */
k1_spi_set_cs(struct spi_device * spi,bool high)344 static void k1_spi_set_cs(struct spi_device *spi, bool high)
345 {
346 struct k1_spi_driver_data *drv_data;
347 u32 val;
348
349 drv_data = spi_controller_get_devdata(spi->controller);
350
351 val = readl(drv_data->base + SSP_TOP_CTRL);
352 if (high)
353 val &= ~TOP_HOLD_FRAME_LOW;
354 else
355 val |= TOP_HOLD_FRAME_LOW;
356 writel(val, drv_data->base + SSP_TOP_CTRL);
357 }
358
359 /* Set the transfer speed; the SPI core code ensures it is supported */
k1_spi_set_speed(struct k1_spi_driver_data * drv_data,struct spi_transfer * transfer)360 static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data,
361 struct spi_transfer *transfer)
362 {
363 struct clk *clk = drv_data->clk;
364 u64 nsec_per_word;
365 u64 bus_ticks;
366 u32 timeout;
367 u32 val;
368 int ret;
369
370 ret = clk_set_rate(clk, transfer->speed_hz);
371 if (ret)
372 return ret;
373
374 drv_data->rate = clk_get_rate(clk);
375
376 /* No need for RX FIFO timeout if we're not receiving anything */
377 if (!transfer->rx_buf)
378 return 0;
379
380 /*
381 * Compute the RX FIFO inactivity timeout value that should be used.
382 * The inactivity timer restarts with each word that lands in the
383 * FIFO. If several "word transfer times" pass without any new data
384 * in the RX FIFO, we might as well read what's there.
385 *
386 * The rate at which words land in the FIFO is determined by the
387 * word size and the transfer rate. One bit is transferred per
388 * clock tick, and 8 (or 16 or 32) bits are transferred per word.
389 *
390 * So we can get word transfer time (in nanoseconds) from:
391 * nsec_per_tick = NSEC_PER_SEC / drv_data->rate;
392 * ticks_per_word = BITS_PER_BYTE * drv_data->bytes;
393 * We do the divide last for better accuracy.
394 */
395 nsec_per_word = (u64)NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes;
396 nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate);
397
398 /*
399 * The timeout (which we'll set to three word transfer times) is
400 * expressed as a number of APB clock ticks.
401 * bus_ticks = 3 * nsec * (drv_data->bus_rate / NSEC_PER_SEC)
402 */
403 bus_ticks = 3 * nsec_per_word * drv_data->bus_rate;
404 timeout = DIV_ROUND_UP_ULL(bus_ticks, NSEC_PER_SEC);
405
406 /* Set the RX timeout period (required for both DMA and PIO) */
407 val = FIELD_PREP(SSP_TIMEOUT_MASK, timeout);
408 writel(val, drv_data->base + SSP_TIMEOUT);
409
410 return 0;
411 }
412
k1_spi_transfer_one(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * transfer)413 static int k1_spi_transfer_one(struct spi_controller *host,
414 struct spi_device *spi,
415 struct spi_transfer *transfer)
416 {
417 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host);
418 u32 ctrl;
419 u32 val;
420 int ret;
421
422 /* Bits per word can change on a per-transfer basis */
423 drv_data->bytes = spi_bpw_to_bytes(transfer->bits_per_word);
424
425 /* Each transfer can also specify a different rate */
426 ret = k1_spi_set_speed(drv_data, transfer);
427 if (ret) {
428 dev_err(&host->dev,
429 "failed to set transfer speed: %d\n", ret);
430 return ret;
431 }
432
433 drv_data->rx_resid = transfer->len;
434 drv_data->tx_resid = transfer->len;
435
436 drv_data->transfer = transfer;
437
438 /* Clear any existing interrupt conditions */
439 writel(~0, drv_data->base + SSP_STATUS);
440
441 /* Set the data (word) size, and enable the port */
442 ctrl = readl(drv_data->base + SSP_TOP_CTRL);
443 ctrl &= ~TOP_DSS_MASK;
444 ctrl |= FIELD_PREP(TOP_DSS_MASK, transfer->bits_per_word - 1);
445 ctrl |= TOP_SSE;
446 writel(ctrl, drv_data->base + SSP_TOP_CTRL);
447
448 if (spi_xfer_is_dma_mapped(host, spi, transfer))
449 return k1_spi_dma_one(host, spi, transfer);
450
451 /* An interrupt will initiate the transfer */
452 val = SSP_INT_EN_TX | SSP_INT_EN_RX | SSP_INT_EN_ERROR;
453 writel(val, drv_data->base + SSP_INT_EN);
454
455 return 1; /* We will call spi_finalize_current_transfer() */
456 }
457
458 static void
k1_spi_handle_err(struct spi_controller * host,struct spi_message * message)459 k1_spi_handle_err(struct spi_controller *host, struct spi_message *message)
460 {
461 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host);
462
463 if (drv_data->dma_enabled) {
464 dmaengine_terminate_sync(host->dma_rx);
465 dmaengine_terminate_sync(host->dma_tx);
466 }
467 }
468
k1_spi_write_word(struct k1_spi_driver_data * drv_data)469 static void k1_spi_write_word(struct k1_spi_driver_data *drv_data)
470 {
471 struct spi_transfer *transfer = drv_data->transfer;
472 u32 bytes = drv_data->bytes;
473 u32 val;
474
475 if (transfer->tx_buf) {
476 const void *buf;
477
478 buf = transfer->tx_buf + (transfer->len - drv_data->tx_resid);
479 if (bytes == 1)
480 val = *(u8 *)buf;
481 else if (bytes == 2)
482 val = *(u16 *)buf;
483 else /* bytes == 4 */
484 val = *(u32 *)buf;
485 } else {
486 val = 0; /* Null writer; write 1, 2, or 4 zero bytes */
487 }
488 /* Fill the next TX FIFO entry */
489 writel(val, drv_data->base + SSP_DATAR);
490
491 drv_data->tx_resid -= bytes;
492 }
493
494 /* The last-read status value is provided; we know SSP_STATUS_TNF is set */
k1_spi_write(struct k1_spi_driver_data * drv_data,u32 val)495 static bool k1_spi_write(struct k1_spi_driver_data *drv_data, u32 val)
496 {
497 unsigned int count;
498
499 /* Get the number of free slots in the FIFO */
500 count = K1_SPI_FIFO_SIZE - FIELD_GET(SSP_STATUS_TFL, val);
501
502 /*
503 * Limit how much we try to send at a time, to reduce the
504 * chance the other side can overrun our RX FIFO.
505 */
506 count = min3(count, K1_SPI_THRESH, drv_data->tx_resid / drv_data->bytes);
507 do
508 k1_spi_write_word(drv_data);
509 while (--count);
510
511 return !drv_data->tx_resid;
512 }
513
k1_spi_read_word(struct k1_spi_driver_data * drv_data)514 static void k1_spi_read_word(struct k1_spi_driver_data *drv_data)
515 {
516 struct spi_transfer *transfer = drv_data->transfer;
517 u32 bytes = drv_data->bytes;
518 u32 val;
519
520 /* Consume the next RX FIFO entry */
521 val = readl(drv_data->base + SSP_DATAR);
522 if (transfer->rx_buf) {
523 void *buf;
524
525 buf = transfer->rx_buf + (transfer->len - drv_data->rx_resid);
526
527 if (bytes == 1)
528 *(u8 *)buf = val;
529 else if (bytes == 2)
530 *(u16 *)buf = val;
531 else /* bytes == 4 */
532 *(u32 *)buf = val;
533 } /* Otherwise null reader: discard the data */
534
535 drv_data->rx_resid -= bytes;
536 }
537
538 /* The last-read status value is provided; we know SSP_STATUS_RNE is set */
k1_spi_read(struct k1_spi_driver_data * drv_data,u32 val)539 static bool k1_spi_read(struct k1_spi_driver_data *drv_data, u32 val)
540 {
541 do {
542 unsigned int count = FIELD_GET(SSP_STATUS_RFL, val) + 1;
543
544 /* Only read what we need */
545 count = min(count, drv_data->rx_resid / drv_data->bytes);
546 do
547 k1_spi_read_word(drv_data);
548 while (--count);
549
550 /* If there's no more to read, we're done */
551 if (!drv_data->rx_resid)
552 return true;
553
554 /* Check again in case more became available to read */
555 val = readl(drv_data->base + SSP_STATUS);
556 if (val & SSP_STATUS_RNE)
557 writel(SSP_STATUS_RNE, drv_data->base + SSP_STATUS);
558 else
559 return false;
560 } while (true);
561 }
562
k1_spi_ssp_isr(int irq,void * dev_id)563 static irqreturn_t k1_spi_ssp_isr(int irq, void *dev_id)
564 {
565 struct k1_spi_driver_data *drv_data = dev_id;
566 u32 status;
567 u32 top_ctrl;
568
569 /* Get status and clear pending interrupts */
570 status = readl(drv_data->base + SSP_STATUS);
571 writel(status, drv_data->base + SSP_STATUS);
572
573 /* If no actionable status bits are set, this is not our interrupt */
574 if (!(status & (SSP_STATUS_ERROR | SSP_STATUS_TNF | SSP_STATUS_RNE)))
575 return IRQ_NONE;
576
577 /* Check for any error conditions first */
578 if (status & SSP_STATUS_ERROR) {
579 if (drv_data->transfer)
580 drv_data->transfer->error |= SPI_TRANS_FAIL_IO;
581 goto done;
582 }
583
584 /*
585 * For SPI, bytes are transferred in both directions equally, and
586 * RX always follows TX. Start by writing if there is anything to
587 * write, then read. Once there's no more to read, we're done.
588 */
589 if (drv_data->tx_resid && (status & SSP_STATUS_TNF)) {
590 /* If we finish writing, disable TX interrupts */
591 if (k1_spi_write(drv_data, status))
592 writel(SSP_INT_EN_RX | SSP_INT_EN_ERROR,
593 drv_data->base + SSP_INT_EN);
594 }
595
596 /* We're not done unless we've read all that was requested */
597 if (drv_data->rx_resid) {
598 /* Read more if the FIFO is not empty */
599 if (status & SSP_STATUS_RNE)
600 if (k1_spi_read(drv_data, status))
601 goto done;
602
603 return IRQ_HANDLED;
604 }
605 done:
606 /* Disable the port */
607 top_ctrl = readl(drv_data->base + SSP_TOP_CTRL);
608 top_ctrl &= ~TOP_SSE;
609 writel(top_ctrl, drv_data->base + SSP_TOP_CTRL);
610
611 /* Disable all interrupts */
612 writel(0, drv_data->base + SSP_INT_EN);
613
614 if (drv_data->transfer) {
615 drv_data->transfer = NULL;
616 spi_finalize_current_transfer(drv_data->host);
617 }
618
619 return IRQ_HANDLED;
620 }
621
622 static int
k1_spi_dma_setup(struct k1_spi_driver_data * drv_data,struct device * dev)623 k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev)
624 {
625 struct spi_controller *host = drv_data->host;
626 struct dma_chan *chan;
627
628 chan = dma_request_chan(dev, "tx");
629 if (IS_ERR(chan))
630 return PTR_ERR(chan);
631 host->dma_tx = chan;
632
633 chan = dma_request_chan(dev, "rx");
634 if (IS_ERR(chan)) {
635 dma_release_channel(host->dma_tx);
636 host->dma_tx = NULL;
637 return PTR_ERR(chan);
638 }
639 host->dma_rx = chan;
640
641 drv_data->dma_enabled = true;
642
643 return 0;
644 }
645
k1_spi_dma_cleanup(struct device * dev,void * res)646 static void k1_spi_dma_cleanup(struct device *dev, void *res)
647 {
648 struct k1_spi_driver_data **ptr = res;
649 struct k1_spi_driver_data *drv_data = *ptr;
650 struct spi_controller *host = drv_data->host;
651
652 if (!drv_data->dma_enabled)
653 return;
654
655 drv_data->dma_enabled = false;
656
657 dma_release_channel(host->dma_rx);
658 host->dma_rx = NULL;
659 dma_release_channel(host->dma_tx);
660 host->dma_tx = NULL;
661 }
662
663 static int
devm_k1_spi_dma_setup(struct k1_spi_driver_data * drv_data,struct device * dev)664 devm_k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev)
665 {
666 struct k1_spi_driver_data **ptr;
667 int ret;
668
669 if (!IS_ENABLED(CONFIG_MMP_PDMA)) {
670 dev_info(dev, "DMA not available; using PIO\n");
671 return 0;
672 }
673
674 ptr = devres_alloc(k1_spi_dma_cleanup, sizeof(*ptr), GFP_KERNEL);
675 if (!ptr)
676 return -ENOMEM;
677
678 ret = k1_spi_dma_setup(drv_data, dev);
679 if (ret) {
680 devres_free(ptr);
681 return ret;
682 }
683
684 *ptr = drv_data;
685 devres_add(dev, ptr);
686
687 return 0;
688 }
689
k1_spi_probe(struct platform_device * pdev)690 static int k1_spi_probe(struct platform_device *pdev)
691 {
692 struct k1_spi_driver_data *drv_data;
693 struct device *dev = &pdev->dev;
694 struct reset_control *reset;
695 struct spi_controller *host;
696 struct resource *iores;
697 struct clk *clk_bus;
698 int ret;
699
700 host = devm_spi_alloc_host(dev, sizeof(*drv_data));
701 if (!host)
702 return -ENOMEM;
703 drv_data = spi_controller_get_devdata(host);
704 drv_data->host = host;
705 platform_set_drvdata(pdev, drv_data);
706
707 ret = devm_k1_spi_dma_setup(drv_data, dev);
708 if (ret == -EPROBE_DEFER)
709 return ret;
710 if (ret)
711 dev_warn(dev, "DMA setup failed (%d), falling back to PIO\n", ret);
712
713 drv_data->base = devm_platform_get_and_ioremap_resource(pdev, 0,
714 &iores);
715 if (IS_ERR(drv_data->base))
716 return dev_err_probe(dev, PTR_ERR(drv_data->base),
717 "error mapping memory\n");
718 drv_data->base_addr = iores->start;
719
720 clk_bus = devm_clk_get_enabled(dev, "bus");
721 if (IS_ERR(clk_bus))
722 return dev_err_probe(dev, PTR_ERR(clk_bus),
723 "error getting/enabling bus clock\n");
724 drv_data->bus_rate = clk_get_rate(clk_bus);
725
726 drv_data->clk = devm_clk_get_enabled(dev, "core");
727 if (IS_ERR(drv_data->clk))
728 return dev_err_probe(dev, PTR_ERR(drv_data->clk),
729 "error getting/enabling core clock\n");
730
731 reset = devm_reset_control_get_exclusive_deasserted(dev, NULL);
732 if (IS_ERR(reset))
733 return dev_err_probe(dev, PTR_ERR(reset),
734 "error getting/deasserting reset\n");
735
736 k1_spi_register_reset(drv_data, true);
737
738 drv_data->irq = platform_get_irq(pdev, 0);
739 if (drv_data->irq < 0)
740 return drv_data->irq;
741
742 ret = devm_request_irq(dev, drv_data->irq, k1_spi_ssp_isr,
743 IRQF_SHARED, dev_name(dev), drv_data);
744 if (ret < 0)
745 return ret;
746
747 /* Initialize the host structure, then register it */
748 host->dev.of_node = dev_of_node(dev);
749 host->dev.parent = dev;
750 host->num_chipselect = 1;
751 if (drv_data->dma_enabled)
752 host->dma_alignment = K1_SPI_DMA_ALIGNMENT;
753 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
754 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
755 host->min_speed_hz = K1_SPI_MIN_SPEED_HZ;
756 host->max_speed_hz = K1_SPI_MAX_SPEED_HZ;
757 host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
758 host->max_dma_len = K1_SPI_MAX_DMA_LEN;
759
760 host->setup = k1_spi_setup;
761 host->cleanup = k1_spi_cleanup;
762 host->can_dma = k1_spi_can_dma;
763 host->prepare_message = k1_spi_prepare_message;
764 host->set_cs = k1_spi_set_cs;
765 host->transfer_one = k1_spi_transfer_one;
766 host->handle_err = k1_spi_handle_err;
767
768 ret = devm_spi_register_controller(dev, host);
769 if (ret)
770 dev_err(dev, "error registering controller\n");
771
772 return ret;
773 }
774
775 static const struct of_device_id k1_spi_dt_ids[] = {
776 { .compatible = "spacemit,k1-spi", },
777 {}
778 };
779 MODULE_DEVICE_TABLE(of, k1_spi_dt_ids);
780
781 static struct platform_driver k1_spi_driver = {
782 .probe = k1_spi_probe,
783 .driver = {
784 .name = "k1-spi",
785 .of_match_table = k1_spi_dt_ids,
786 },
787 };
788 module_platform_driver(k1_spi_driver);
789
790 MODULE_DESCRIPTION("SpacemiT K1 SPI controller driver");
791 MODULE_LICENSE("GPL");
792