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Searched defs:Rt (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dhvx_hexagon_protos.h63 #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) argument
129 #define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP… argument
151 #define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILT… argument
162 #define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(_… argument
173 #define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__B… argument
184 #define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN… argument
536 #define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) argument
569 #define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WR… argument
580 #define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUIL… argument
591 #define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_W… argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp618 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
646 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
691 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch() local
719 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP37GroupBranchMMR6() local
760 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP65GroupBranchMMR6() local
799 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP75GroupBranchMMR6() local
843 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch() local
888 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzlGroupBranch() local
930 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranch() local
979 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranch() local
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/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp41 uint32_t Rt, in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
H A Dxray_mips64.cpp42 uint32_t Rt, in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp377 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
388 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
400 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
597 MCOperand &Rt = Inst.getOperand(1); in HexagonProcessInstruction() local
H A DHexagonBitTracker.cpp295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
H A DHexagonSplitDouble.cpp374 Register Rt = MI->getOperand(2).getReg(); in profit() local
H A DHexagonISelDAGToDAGHVX.cpp816 MaskT vshuffvdd(ArrayRef<int> Vu, ArrayRef<int> Vv, unsigned Rt) { in vshuffvdd() argument
836 MaskT vdealvdd(ArrayRef<int> Vu, ArrayRef<int> Vv, unsigned Rt) { in vdealvdd() argument
2704 SDValue Rt = N->getOperand(2); selectVAlign() local
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H A DHexagonBitSimplify.cpp1920 BitTracker::RegisterRef &Rt) { in matchPackhl()
2054 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
H A DHexagonInstrInfo.cpp1348 Register Rt = Op3.getReg(); in expandPostRAPseudo() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp707 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
774 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
981 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeExclusiveLdStInstruction() local
1075 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodePairLdStInstruction() local
1221 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeAuthLoadInstruction() local
1553 uint64_t Rt = fieldFromInstruction(insn, 0, 5); in DecodeTestAndBranch() local
1609 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSyspXzrInstruction() local
1751 uint64_t Rt = fieldFromInstruction(insn, 0, 5); in DecodePRFMRegInstruction() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2048 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
2210 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
4073 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadShift() local
4158 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm8() local
4243 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm12() local
4323 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadT() local
4362 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadLabel() local
4603 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LdStPre() local
5098 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeDoubleRegLoad() local
5121 unsigned Rt = fieldFromInstruction(Insn, 0, 4); in DecodeDoubleRegStore() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp187 Register Rt = TailAdd.getOperand(2).getReg(); in foldLargeOffset() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3508 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3515 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3545 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3557 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3580 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3595 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3621 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3631 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3668 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
H A DThumb2SizeReduction.cpp465 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1445 MCOperand &Rt = Inst.getOperand(1); in processInstruction() local
1866 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local
1886 MCOperand &Rt = Inst.getOperand(3); in processInstruction() local
1909 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp927 uint32_t Rt; // the source register in EmulatePUSH() local
1043 uint32_t Rt; // the destination register in EmulatePOP() local
1774 uint32_t Rt; // the destination register in EmulateLDRRtPCRelative() local
2477 uint32_t Rt; // the source register in EmulateSTRRtSP() local
4428 uint32_t Rt; // the destination register in EmulateLDRRtRnImm() local
5742 uint32_t Rt = ReadCoreReg(t, &success); in EmulateSTRHRegister() local
10402 uint32_t Rt = in EmulateSTREX() local
10494 uint32_t Rt = ReadCoreReg(t, &success); in EmulateSTRBImmARM() local
10595 uint32_t Rt = ReadCoreReg(t, &success); in EmulateSTRImmARM() local
11137 uint32_t Rt = ReadCoreReg(t, &success); in EmulateSTRDReg() local
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp703 uint32_t Rt = Bits32(opcode, 4, 0); in EmulateLDPSTP() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp5354 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
5379 unsigned Rt = Inst.getOperand(0).getReg(); in validateInstruction() local
5392 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
5408 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
5441 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
5460 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
5476 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3509 Register Rt = MI.getOperand(1).getReg(); in emitST_F16_PSEUDO() local
3574 Register Rt = RegInfo.createVirtualRegister(RC); in emitLD_F16_PSEUDO() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7413 unsigned Rt = MRI->getEncodingValue(Reg1); in ParseInstruction() local
7553 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); in validateLDRDSTRD() local
7820 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction() local
7833 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() local
7981 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() local
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGOpenMPRuntimeGPU.cpp1013 auto &Rt = in emitTeamsOutlinedFunction() local
H A DCGBuiltin.cpp8701 Value *Rt = Builder.CreateTruncOrBitCast(RtAndRt2, Int32Ty); in EmitARMBuiltinExpr() local
8730 Value *Rt = Builder.CreateExtractValue(RtAndRt2, 1); in EmitARMBuiltinExpr() local