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Searched defs:OpIdx (Results 1 – 25 of 114) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp228 getLdStUImm12OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStUImm12OpValue() argument
249 getAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAdrLabelOpValue() argument
275 getAddSubImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddSubImmOpValue() argument
312 getCondBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCondBranchTargetOpValue() argument
333 getLoadLiteralOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLoadLiteralOpValue() argument
353 getMemExtendOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemExtendOpValue() argument
362 getMoveWideImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMoveWideImmOpValue() argument
382 getTestBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTestBranchTargetOpValue() argument
403 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
431 getVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShifterOpValue() argument
456 getFixedPointScaleOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getFixedPointScaleOpValue() argument
464 getVecShiftR64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR64OpValue() argument
473 getVecShiftR32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR32OpValue() argument
482 getVecShiftR16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR16OpValue() argument
491 getVecShiftR8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR8OpValue() argument
500 getVecShiftL64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL64OpValue() argument
509 getVecShiftL32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL32OpValue() argument
518 getVecShiftL16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL16OpValue() argument
527 getVecShiftL8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL8OpValue() argument
537 EncodeRegAsMultipleOf(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeRegAsMultipleOf() argument
547 EncodePPR_p8to15(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodePPR_p8to15() argument
555 EncodeZPR2StridedRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeZPR2StridedRegisterClass() argument
565 EncodeZPR4StridedRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeZPR4StridedRegisterClass() argument
575 EncodeMatrixTileListRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeMatrixTileListRegisterClass() argument
584 encodeMatrixIndexGPR32(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeMatrixIndexGPR32() argument
592 getImm8OptLsl(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm8OptLsl() argument
610 getSVEIncDecImm(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSVEIncDecImm() argument
622 getMoveVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMoveVecShifterOpValue() argument
[all...]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutorImpl.h156 uint64_t OpIdx = readULEB(); in executeMatchTable() local
267 uint64_t OpIdx = readULEB(); in executeMatchTable() local
328 unsigned OpIdx = in executeMatchTable() local
641 uint64_t OpIdx = readULEB(); in executeMatchTable() local
691 uint64_t OpIdx = readULEB(); in executeMatchTable() local
707 uint64_t OpIdx = readULEB(); in executeMatchTable() local
738 uint64_t OpIdx = readULEB(); in executeMatchTable() local
752 uint64_t OpIdx = readULEB(); in executeMatchTable() local
774 uint64_t OpIdx = readULEB(); in executeMatchTable() local
794 uint64_t OpIdx = readULEB(); in executeMatchTable() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp232 getLdStmModeOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStmModeOpValue() argument
592 EncodeAddrModeOpValues(const MCInst & MI,unsigned OpIdx,unsigned & Reg,unsigned & Imm,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeAddrModeOpValues() argument
621 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,unsigned FixupKind,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getBranchTargetOpValue() argument
659 getThumbBLTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBLTargetOpValue() argument
672 getThumbBLXTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBLXTargetOpValue() argument
684 getThumbBRTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBRTargetOpValue() argument
696 getThumbBCCTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBCCTargetOpValue() argument
708 getThumbCBTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbCBTargetOpValue() argument
737 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
751 getARMBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBranchTargetOpValue() argument
767 getARMBLTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBLTargetOpValue() argument
782 getARMBLXTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBLXTargetOpValue() argument
795 getThumbBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBranchTargetOpValue() argument
824 getAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAdrLabelOpValue() argument
865 getT2AdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AdrLabelOpValue() argument
885 getITMaskOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getITMaskOpValue() argument
912 getThumbAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbAdrLabelOpValue() argument
925 getThumbAddrModeRegRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> &,const MCSubtargetInfo & STI) const getThumbAddrModeRegRegOpValue() argument
941 getMVEShiftImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMVEShiftImmOpValue() argument
975 getAddrModeImm12OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeImm12OpValue() argument
1030 getT2ScaledImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2ScaledImmOpValue() argument
1061 getMveAddrModeRQOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMveAddrModeRQOpValue() argument
1081 getMveAddrModeQOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMveAddrModeQOpValue() argument
1112 getT2AddrModeImm8s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm8s4OpValue() argument
1154 getT2AddrModeImm7s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm7s4OpValue() argument
1181 getT2AddrModeImm0_1020s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm0_1020s4OpValue() argument
1193 getHiLoImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getHiLoImmOpValue() argument
1281 getLdStSORegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStSORegOpValue() argument
1315 getAddrMode2OffsetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode2OffsetOpValue() argument
1338 getPostIdxRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getPostIdxRegOpValue() argument
1350 getAddrMode3OffsetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode3OffsetOpValue() argument
1370 getAddrMode3OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode3OpValue() argument
1407 getAddrModeThumbSPOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeThumbSPOpValue() argument
1423 getAddrModeISOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeISOpValue() argument
1438 getAddrModePCOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModePCOpValue() argument
1449 getAddrMode5OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode5OpValue() argument
1489 getAddrMode5FP16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode5FP16OpValue() argument
1528 getSORegRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSORegRegOpValue() argument
1576 getSORegImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSORegImmOpValue() argument
1685 getT2SORegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2SORegOpValue() argument
1926 getBFTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBFTargetOpValue() argument
1936 getBFAfterTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBFAfterTargetOpValue() argument
1958 getVPTMaskOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVPTMaskOpValue() argument
1990 getRestrictedCondCodeOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRestrictedCondCodeOpValue() argument
2018 getPowerTwoOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getPowerTwoOpValue() argument
2028 getMVEPairVectorIndexOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMVEPairVectorIndexOpValue() argument
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMIRFormatter.cpp21 std::optional<unsigned int> OpIdx, int64_t Imm) const { in printImm()
37 const unsigned OpIdx, in parseImmMnemonic()
95 const unsigned int OpIdx, int64_t &Imm, llvm::StringRef &Src, in parseSDelayAluImmMnemonic()
H A DR600ExpandSpecialInstrs.cpp65 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI() local
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMIRFormatter.h44 std::optional<unsigned> OpIdx, int64_t Imm) const { in printImm()
50 virtual bool parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx, in parseImmMnemonic()
H A DMachineOperand.h190 unsigned OpIdx; member
722 void setInstrRefOpIndex(unsigned OpIdx) { in setInstrRefOpIndex() argument
955 CreateDbgInstrRef(unsigned InstrIdx,unsigned OpIdx) CreateDbgInstrRef() argument
[all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DBreakFalseDeps.cpp110 bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, in pickBestRegisterForUndef()
175 bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence()
248 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local
H A DRegisterBankInfo.cpp115 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints()
185 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; in getInstrMappingImpl() local
444 for (unsigned OpIdx = 0, in applyDefaultMapping() local
656 for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) { in print() local
676 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) { in getVRegsMem()
712 void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) { in createVRegs()
732 void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx, in setVRegs()
747 RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx, in getVRegs()
H A DMachineInstr.cpp737 for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx) in isEquivalentDbgInstr() local
874 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx()
945 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint()
1000 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, in getRegClassConstraintEffectForVRegImpl()
1012 unsigned OpIdx, const TargetRegisterClass *CurRC, in getRegClassConstraintEffect()
1598 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, in getTypeToPrint()
1692 auto getTiedOperandIdx = [&](unsigned OpIdx) { in print()
1772 const unsigned OpIdx = InlineAsm::MIOp_AsmString; in print() local
2041 unsigned OpIdx = DeadOps.back(); in addRegisterKilled() local
2105 unsigned OpIdx = DeadOps.back(); in addRegisterDead() local
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/
H A DGlobalISelMatchTable.h830 unsigned OpIdx; variable
882 unsigned OpIdx) in OperandPredicateMatcher()
907 SameOperandMatcher(unsigned InsnVarID, unsigned OpIdx, StringRef MatchingName, in SameOperandMatcher()
942 LLTOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const LLTCodeGen &Ty) in LLTOperandMatcher()
980 PointerToAnyOperandMatcher(unsigned InsnVarID, unsigned OpIdx, in PointerToAnyOperandMatcher()
1007 RecordNamedOperandMatcher(unsigned InsnVarID, unsigned OpIdx, in RecordNamedOperandMatcher()
1033 RecordRegisterType(unsigned InsnVarID, unsigned OpIdx, TempTypeIdx Idx) in RecordRegisterType()
1061 ComplexPatternOperandMatcher(unsigned InsnVarID, unsigned OpIdx, in ComplexPatternOperandMatcher()
1082 RegisterBankOperandMatcher(unsigned InsnVarID, unsigned OpIdx, in RegisterBankOperandMatcher()
1099 MBBOperandMatcher(unsigned InsnVarID, unsigned OpIdx) in MBBOperandMatcher()
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/
H A DGIMatchTree.h
H A DGIMatchTree.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp116 Register OpReg, unsigned OpIdx, in doInsertBitcast()
152 MachineInstr &I, unsigned OpIdx, in validatePtrTypes()
188 constexpr unsigned OpIdx = 2; in validateGroupWaitEventsPtr() local
209 unsigned OpIdx) { in validateGroupAsyncCopyPtr()
254 unsigned OpIdx = 3; in validateFunCallMachineDef() local
H A DSPIRVEmitIntrinsics.cpp374 Function *CalledF, unsigned OpIdx) { in getPointeeTypeByCallInst()
934 for (unsigned OpIdx = 0; OpIdx < Call.arg_size(); OpIdx++) in visitCallInst() local
1159 for (unsigned OpIdx = 0; OpIdx < CalledF->arg_size(); ++OpIdx) { in insertPtrCastOrAssignTypeInstr() local
1192 for (unsigned OpIdx = 0; OpIdx < CI->arg_size(); OpIdx++) { in insertPtrCastOrAssignTypeInstr() local
1547 unsigned OpIdx) { in deduceFunParamElementType()
1553 Function *F, unsigned OpIdx, std::unordered_set<Function *> &FVisited) { in deduceFunParamElementType()
1611 for (unsigned OpIdx = 0; OpIdx < F->arg_size(); ++OpIdx) { in processParamTypesByFunHeader() local
1624 for (unsigned OpIdx = 0; OpIdx < F->arg_size(); ++OpIdx) { in processParamTypes() local
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCInstPrinter.cpp64 const MCRegisterInfo &MRI, unsigned &OpIdx, in matchAliasCondition() argument
148 unsigned OpIdx = 0; in matchAliasPatterns() local
/freebsd/contrib/llvm-project/llvm/include/llvm/SandboxIR/
H A DSandboxIR.h378 Value *getOperand(unsigned OpIdx) const { return getOperandUse(OpIdx).get(); } in getOperand()
381 Use getOperandUse(unsigned OpIdx) const { in getOperandUse()
411 Use getOperandUseInternal(unsigned OpIdx, bool Verify) const final { in getOperandUseInternal()
580 Use getOperandUseInternal(unsigned OpIdx, bool Verify) const final { in getOperandUseInternal()
625 Use getOperandUseInternal(unsigned OpIdx, bool Verify) const final { in getOperandUseInternal()
664 Use getOperandUseInternal(unsigned OpIdx, bool Verify) const final { in getOperandUseInternal()
703 Use getOperandUseInternal(unsigned OpIdx, bool Verify) const final { in getOperandUseInternal()
741 Use getOperandUseInternal(unsigned OpIdx, bool Verify) const final { in getOperandUseInternal()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kMCCodeEmitter.cpp113 encodeRelocImm(const MCInst & MI,unsigned OpIdx,unsigned InsertPos,APInt & Value,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeRelocImm() argument
140 encodePCRelImm(const MCInst & MI,unsigned OpIdx,unsigned InsertPos,APInt & Value,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodePCRelImm() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp404 int OpIdx = mapRegToGPRIndex(AddMI->getOperand(0).getReg()); handleADRP() local
572 int OpIdx = mapRegToGPRIndex(Op.getReg()); runOnMachineFunction() local
H A DAArch64SLSHardening.cpp460 for (unsigned OpIdx = BL->getNumExplicitOperands(); in convertBLRToBL() local
481 for (unsigned OpIdx = 0; OpIdx < NumRegOperands; ++OpIdx) { in convertBLRToBL() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp470 for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands(); in computeMapping() local
601 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local
762 MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, in RepairingPlacement()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenInstruction.cpp200 unsigned OpIdx; in getOperandNamed() local
252 unsigned OpIdx; in ParseOperandName() local
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXPrologEpilogPass.cpp85 unsigned OpIdx = MI.getDebugOperandIndex(&Op); in runOnMachineFunction() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp226 int OpIdx = findFirstVPTPredOperandIdx(*Iter); in CreateVPTBlock() local
H A DARMExpandPseudoInsts.cpp564 unsigned OpIdx = 0; in ExpandVLD() local
682 unsigned OpIdx = 0; in ExpandVST() local
759 unsigned OpIdx = 0; in ExpandLaneOp() local
843 unsigned OpIdx = 0; in ExpandVTBL() local
2779 unsigned OpIdx = 0; in ExpandMI() local
2810 unsigned OpIdx = 0; in ExpandMI() local

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