Lines Matching defs:OpIdx
69 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
75 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
81 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
87 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
106 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
112 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
118 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
129 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
135 uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
141 uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,
145 uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
148 uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
151 uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
154 uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
157 uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
160 uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
163 uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
166 uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
170 uint32_t getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
173 uint32_t getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
195 uint32_t EncodeRegAsMultipleOf(const MCInst &MI, unsigned OpIdx,
198 uint32_t EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
202 uint32_t EncodeZPR2StridedRegisterClass(const MCInst &MI, unsigned OpIdx,
205 uint32_t EncodeZPR4StridedRegisterClass(const MCInst &MI, unsigned OpIdx,
209 uint32_t EncodeMatrixTileListRegisterClass(const MCInst &MI, unsigned OpIdx,
213 uint32_t encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,
234 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
237 const MCOperand &MO = MI.getOperand(OpIdx);
255 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
258 const MCOperand &MO = MI.getOperand(OpIdx);
281 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
285 const MCOperand &MO = MI.getOperand(OpIdx);
286 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
318 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
320 const MCOperand &MO = MI.getOperand(OpIdx);
339 AArch64MCCodeEmitter::getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
342 const MCOperand &MO = MI.getOperand(OpIdx);
362 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
365 const MCOperand &MO = MI.getOperand(OpIdx);
382 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
385 unsigned SignExtend = MI.getOperand(OpIdx).getImm();
386 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm();
391 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
394 const MCOperand &MO = MI.getOperand(OpIdx);
411 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
413 const MCOperand &MO = MI.getOperand(OpIdx);
432 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
435 const MCOperand &MO = MI.getOperand(OpIdx);
460 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
463 const MCOperand &MO = MI.getOperand(OpIdx);
485 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
487 const MCOperand &MO = MI.getOperand(OpIdx);
493 AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
496 const MCOperand &MO = MI.getOperand(OpIdx);
502 AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
505 const MCOperand &MO = MI.getOperand(OpIdx);
511 AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
514 const MCOperand &MO = MI.getOperand(OpIdx);
520 AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
523 const MCOperand &MO = MI.getOperand(OpIdx);
529 AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
532 const MCOperand &MO = MI.getOperand(OpIdx);
538 AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
541 const MCOperand &MO = MI.getOperand(OpIdx);
547 AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
550 const MCOperand &MO = MI.getOperand(OpIdx);
556 AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
559 const MCOperand &MO = MI.getOperand(OpIdx);
566 AArch64MCCodeEmitter::EncodeRegAsMultipleOf(const MCInst &MI, unsigned OpIdx,
570 auto RegOpnd = MI.getOperand(OpIdx).getReg();
576 AArch64MCCodeEmitter::EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
579 auto RegOpnd = MI.getOperand(OpIdx).getReg();
584 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
586 auto RegOpnd = MI.getOperand(OpIdx).getReg();
594 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
596 auto RegOpnd = MI.getOperand(OpIdx).getReg();
604 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
606 unsigned RegMask = MI.getOperand(OpIdx).getImm();
613 AArch64MCCodeEmitter::encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,
616 auto RegOpnd = MI.getOperand(OpIdx).getReg();
621 AArch64MCCodeEmitter::getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
625 auto ShiftOpnd = MI.getOperand(OpIdx + 1).getImm();
634 auto Immediate = MI.getOperand(OpIdx).getImm();
639 AArch64MCCodeEmitter::getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
642 const MCOperand &MO = MI.getOperand(OpIdx);
651 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
653 const MCOperand &MO = MI.getOperand(OpIdx);