Lines Matching defs:OpIdx
95 uint32_t getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
99 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
106 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
112 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
117 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
122 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
127 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
133 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
139 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
145 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
148 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
151 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
157 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
160 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
163 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
167 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
173 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
179 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
184 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
190 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
196 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
202 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
209 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
215 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
222 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
228 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
233 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
236 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
262 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
267 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
272 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
277 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
283 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
288 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
293 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
298 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
303 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
436 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
445 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
449 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
453 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
456 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
460 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
581 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
584 const MCOperand &MO = MI.getOperand(OpIdx);
585 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
610 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
614 const MCOperand &MO = MI.getOperand(OpIdx);
648 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
651 const MCOperand MO = MI.getOperand(OpIdx);
653 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
661 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
664 const MCOperand MO = MI.getOperand(OpIdx);
666 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
673 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
676 const MCOperand MO = MI.getOperand(OpIdx);
678 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
685 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
688 const MCOperand MO = MI.getOperand(OpIdx);
690 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
697 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
700 const MCOperand MO = MI.getOperand(OpIdx);
702 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
726 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
733 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
734 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
740 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
743 const MCOperand MO = MI.getOperand(OpIdx);
746 return ::getBranchTargetOpValue(MI, OpIdx,
748 return ::getBranchTargetOpValue(MI, OpIdx,
756 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
759 const MCOperand MO = MI.getOperand(OpIdx);
762 return ::getBranchTargetOpValue(MI, OpIdx,
764 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
771 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
774 const MCOperand MO = MI.getOperand(OpIdx);
776 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
784 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
787 const MCOperand MO = MI.getOperand(OpIdx);
790 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
813 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
816 const MCOperand MO = MI.getOperand(OpIdx);
818 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
854 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
857 const MCOperand MO = MI.getOperand(OpIdx);
859 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
874 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
877 const MCOperand MaskMO = MI.getOperand(OpIdx);
886 assert(OpIdx > 0 && "IT mask appears first!");
887 const MCOperand CondMO = MI.getOperand(OpIdx-1);
901 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
904 const MCOperand MO = MI.getOperand(OpIdx);
906 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
914 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
920 const MCOperand &MO1 = MI.getOperand(OpIdx);
921 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
930 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
958 ShiftImm = MI.getOperand(OpIdx).getImm();
964 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
973 const MCOperand &MO = MI.getOperand(OpIdx);
975 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
977 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
1019 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1031 int32_t Imm = MI.getOperand(OpIdx).getImm();
1050 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1055 const MCOperand &M0 = MI.getOperand(OpIdx);
1056 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1070 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1075 const MCOperand &M0 = MI.getOperand(OpIdx);
1076 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1101 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1110 const MCOperand &MO = MI.getOperand(OpIdx);
1123 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1143 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1151 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1170 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1175 const MCOperand &MO = MI.getOperand(OpIdx);
1176 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1182 uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
1187 const MCOperand &MO = MI.getOperand(OpIdx);
1270 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1273 const MCOperand &MO = MI.getOperand(OpIdx);
1274 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1275 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1304 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1310 const MCOperand &MO = MI.getOperand(OpIdx);
1311 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1327 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1332 const MCOperand &MO = MI.getOperand(OpIdx);
1333 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1339 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1346 const MCOperand &MO = MI.getOperand(OpIdx);
1347 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1359 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1367 const MCOperand &MO = MI.getOperand(OpIdx);
1368 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1369 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1396 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1401 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1402 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1412 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1418 const MCOperand &MO = MI.getOperand(OpIdx);
1419 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1427 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1430 const MCOperand MO = MI.getOperand(OpIdx);
1432 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1438 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1447 const MCOperand &MO = MI.getOperand(OpIdx);
1464 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1478 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1487 const MCOperand &MO = MI.getOperand(OpIdx);
1504 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1517 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1530 const MCOperand &MO = MI.getOperand(OpIdx);
1531 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1532 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1565 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1576 const MCOperand &MO = MI.getOperand(OpIdx);
1577 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1674 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1685 const MCOperand &MO = MI.getOperand(OpIdx);
1686 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1920 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1923 const MCOperand MO = MI.getOperand(OpIdx);
1925 return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1930 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1933 const MCOperand MO = MI.getOperand(OpIdx);
1952 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1955 const MCOperand MO = MI.getOperand(OpIdx);
1984 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1987 const MCOperand MO = MI.getOperand(OpIdx);
2012 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
2015 const MCOperand &MO = MI.getOperand(OpIdx);
2022 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
2025 const MCOperand MO = MI.getOperand(OpIdx);