1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include <linux/delay.h> 5 #include <linux/iopoll.h> 6 #include "ice_common.h" 7 #include "ice_ptp_hw.h" 8 #include "ice_ptp_consts.h" 9 10 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = { 11 DPLL_PIN_FREQUENCY_1PPS, 12 DPLL_PIN_FREQUENCY_10MHZ, 13 }; 14 15 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = { 16 DPLL_PIN_FREQUENCY_1PPS, 17 }; 18 19 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = { 20 DPLL_PIN_FREQUENCY_10MHZ, 21 }; 22 23 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = { 24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 25 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 27 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, 29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, 30 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 31 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 32 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 33 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 35 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 36 }; 37 38 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = { 39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 40 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 42 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, 44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, 45 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, }, 46 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, }, 47 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 48 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 49 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 50 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 51 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 52 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 53 }; 54 55 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = { 56 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 57 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 58 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 59 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 60 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 61 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 62 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT, 63 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 64 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT, 65 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 66 }; 67 68 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = { 69 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 70 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 71 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 72 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 73 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 74 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 75 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 76 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT, 77 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 78 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT, 79 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 80 }; 81 82 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = { 83 { "NONE", SI_REF0P, 0, 0 }, 84 { "NONE", SI_REF0N, 0, 0 }, 85 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 86 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 87 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT, 88 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 89 { "NONE", SI_REF2N, 0, 0 }, 90 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT, 91 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 92 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT, 93 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 94 }; 95 96 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = { 97 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT, 98 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 99 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 100 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT, 101 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 102 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT, 103 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 104 }; 105 106 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = { 107 { "NONE", ZL_REF0P, 0, 0 }, 108 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT, 109 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 110 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 111 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 112 { "NONE", ZL_REF2P, 0, 0 }, 113 { "NONE", ZL_REF2N, 0, 0 }, 114 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT, 115 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 116 { "NONE", ZL_REF3N, 0, 0 }, 117 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT, 118 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 119 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 }, 120 }; 121 122 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = { 123 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 124 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 125 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 126 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 127 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 128 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 129 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT, 130 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 131 { "NONE", ZL_OUT5, 0, 0 }, 132 }; 133 134 /* Low level functions for interacting with and managing the device clock used 135 * for the Precision Time Protocol. 136 * 137 * The ice hardware represents the current time using three registers: 138 * 139 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 140 * +---------------+ +---------------+ +---------------+ 141 * | 32 bits | | 32 bits | | 32 bits | 142 * +---------------+ +---------------+ +---------------+ 143 * 144 * The registers are incremented every clock tick using a 40bit increment 145 * value defined over two registers: 146 * 147 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 148 * +---------------+ +---------------+ 149 * | 8 bit s | | 32 bits | 150 * +---------------+ +---------------+ 151 * 152 * The increment value is added to the GLTSYN_TIME_R and GLTSYN_TIME_L 153 * registers every clock source tick. Depending on the specific device 154 * configuration, the clock source frequency could be one of a number of 155 * values. 156 * 157 * For E810 devices, the increment frequency is 812.5 MHz 158 * 159 * For E822 devices the clock can be derived from different sources, and the 160 * increment has an effective frequency of one of the following: 161 * - 823.4375 MHz 162 * - 783.36 MHz 163 * - 796.875 MHz 164 * - 816 MHz 165 * - 830.078125 MHz 166 * - 783.36 MHz 167 * 168 * The hardware captures timestamps in the PHY for incoming packets, and for 169 * outgoing packets on request. To support this, the PHY maintains a timer 170 * that matches the lower 64 bits of the global source timer. 171 * 172 * In order to ensure that the PHY timers and the source timer are equivalent, 173 * shadow registers are used to prepare the desired initial values. A special 174 * sync command is issued to trigger copying from the shadow registers into 175 * the appropriate source and PHY registers simultaneously. 176 * 177 * The driver supports devices which have different PHYs with subtly different 178 * mechanisms to program and control the timers. We divide the devices into 179 * families named after the first major device, E810 and similar devices, and 180 * E822 and similar devices. 181 * 182 * - E822 based devices have additional support for fine grained Vernier 183 * calibration which requires significant setup 184 * - The layout of timestamp data in the PHY register blocks is different 185 * - The way timer synchronization commands are issued is different. 186 * 187 * To support this, very low level functions have an e810 or e822 suffix 188 * indicating what type of device they work on. Higher level abstractions for 189 * tasks that can be done on both devices do not have the suffix and will 190 * correctly look up the appropriate low level function when running. 191 * 192 * Functions which only make sense on a single device family may not have 193 * a suitable generic implementation 194 */ 195 196 /** 197 * ice_get_ptp_src_clock_index - determine source clock index 198 * @hw: pointer to HW struct 199 * 200 * Determine the source clock index currently in use, based on device 201 * capabilities reported during initialization. 202 */ 203 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 204 { 205 return hw->func_caps.ts_func_info.tmr_index_assoc; 206 } 207 208 /** 209 * ice_ptp_read_src_incval - Read source timer increment value 210 * @hw: pointer to HW struct 211 * 212 * Read the increment value of the source timer and return it. 213 */ 214 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 215 { 216 u32 lo, hi; 217 u8 tmr_idx; 218 219 tmr_idx = ice_get_ptp_src_clock_index(hw); 220 221 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 222 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 223 224 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 225 } 226 227 /** 228 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value 229 * @hw: pointer to HW struct 230 * @cmd: Timer command 231 * 232 * Return: the source timer command register value for the given PTP timer 233 * command. 234 */ 235 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw, 236 enum ice_ptp_tmr_cmd cmd) 237 { 238 u32 cmd_val, tmr_idx; 239 240 switch (cmd) { 241 case ICE_PTP_INIT_TIME: 242 cmd_val = GLTSYN_CMD_INIT_TIME; 243 break; 244 case ICE_PTP_INIT_INCVAL: 245 cmd_val = GLTSYN_CMD_INIT_INCVAL; 246 break; 247 case ICE_PTP_ADJ_TIME: 248 cmd_val = GLTSYN_CMD_ADJ_TIME; 249 break; 250 case ICE_PTP_ADJ_TIME_AT_TIME: 251 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 252 break; 253 case ICE_PTP_NOP: 254 case ICE_PTP_READ_TIME: 255 cmd_val = GLTSYN_CMD_READ_TIME; 256 break; 257 default: 258 dev_warn(ice_hw_to_dev(hw), 259 "Ignoring unrecognized timer command %u\n", cmd); 260 cmd_val = 0; 261 } 262 263 tmr_idx = ice_get_ptp_src_clock_index(hw); 264 265 return tmr_idx << SEL_CPK_SRC | cmd_val; 266 } 267 268 /** 269 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value 270 * @hw: pointer to HW struct 271 * @cmd: Timer command 272 * 273 * Note that some hardware families use a different command register value for 274 * the PHY ports, while other hardware families use the same register values 275 * as the source timer. 276 * 277 * Return: the PHY port timer command register value for the given PTP timer 278 * command. 279 */ 280 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, 281 enum ice_ptp_tmr_cmd cmd) 282 { 283 u32 cmd_val, tmr_idx; 284 285 /* Certain hardware families share the same register values for the 286 * port register and source timer register. 287 */ 288 switch (hw->mac_type) { 289 case ICE_MAC_E810: 290 case ICE_MAC_E830: 291 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810; 292 default: 293 break; 294 } 295 296 switch (cmd) { 297 case ICE_PTP_INIT_TIME: 298 cmd_val = PHY_CMD_INIT_TIME; 299 break; 300 case ICE_PTP_INIT_INCVAL: 301 cmd_val = PHY_CMD_INIT_INCVAL; 302 break; 303 case ICE_PTP_ADJ_TIME: 304 cmd_val = PHY_CMD_ADJ_TIME; 305 break; 306 case ICE_PTP_ADJ_TIME_AT_TIME: 307 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME; 308 break; 309 case ICE_PTP_READ_TIME: 310 cmd_val = PHY_CMD_READ_TIME; 311 break; 312 case ICE_PTP_NOP: 313 cmd_val = 0; 314 break; 315 default: 316 dev_warn(ice_hw_to_dev(hw), 317 "Ignoring unrecognized timer command %u\n", cmd); 318 cmd_val = 0; 319 } 320 321 tmr_idx = ice_get_ptp_src_clock_index(hw); 322 323 return tmr_idx << SEL_PHY_SRC | cmd_val; 324 } 325 326 /** 327 * ice_ptp_src_cmd - Prepare source timer for a timer command 328 * @hw: pointer to HW structure 329 * @cmd: Timer command 330 * 331 * Prepare the source timer for an upcoming timer sync command. 332 */ 333 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 334 { 335 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 336 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd); 337 338 if (!ice_is_primary(hw)) 339 hw = ice_get_primary_hw(pf); 340 341 wr32(hw, GLTSYN_CMD, cmd_val); 342 } 343 344 /** 345 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 346 * @hw: pointer to HW struct 347 * 348 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 349 * write immediately. This triggers the hardware to begin executing all of the 350 * source and PHY timer commands synchronously. 351 */ 352 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 353 { 354 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 355 356 if (!ice_is_primary(hw)) 357 hw = ice_get_primary_hw(pf); 358 359 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); 360 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 361 ice_flush(hw); 362 } 363 364 /** 365 * ice_ptp_cfg_sync_delay - Configure PHC to PHY synchronization delay 366 * @hw: pointer to HW struct 367 * @delay: delay between PHC and PHY SYNC command execution in nanoseconds 368 */ 369 static void ice_ptp_cfg_sync_delay(const struct ice_hw *hw, u32 delay) 370 { 371 wr32(hw, GLTSYN_SYNC_DLAY, delay); 372 ice_flush(hw); 373 } 374 375 /* 56G PHY device functions 376 * 377 * The following functions operate on devices with the ETH 56G PHY. 378 */ 379 380 /** 381 * ice_ptp_init_phc_e825c - Perform E825C specific PHC initialization 382 * @hw: pointer to HW struct 383 * 384 * Perform E825C-specific PTP hardware clock initialization steps. 385 * 386 * Return: 0 on success, or a negative error value on failure. 387 */ 388 static int ice_ptp_init_phc_e825c(struct ice_hw *hw) 389 { 390 int err; 391 392 /* Soft reset all ports, to ensure everything is at a clean state */ 393 for (int port = 0; port < hw->ptp.num_lports; port++) { 394 err = ice_ptp_phy_soft_reset_eth56g(hw, port); 395 if (err) { 396 ice_debug(hw, ICE_DBG_PTP, "Failed to soft reset port %d, err %d\n", 397 port, err); 398 return err; 399 } 400 } 401 402 return 0; 403 } 404 405 /** 406 * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number 407 * @hw: pointer to the HW struct 408 * @port: destination port 409 * 410 * Return: destination sideband queue PHY device. 411 */ 412 static enum ice_sbq_dev_id ice_ptp_get_dest_dev_e825(struct ice_hw *hw, 413 u8 port) 414 { 415 u8 curr_phy, tgt_phy; 416 417 tgt_phy = port >= hw->ptp.ports_per_phy; 418 curr_phy = hw->lane_num >= hw->ptp.ports_per_phy; 419 /* In the driver, lanes 4..7 are in fact 0..3 on a second PHY. 420 * On a single complex E825C, PHY 0 is always destination device phy_0 421 * and PHY 1 is phy_0_peer. 422 * On dual complex E825C, device phy_0 points to PHY on a current 423 * complex and phy_0_peer to PHY on a different complex. 424 */ 425 if ((!ice_is_dual(hw) && tgt_phy == 1) || 426 (ice_is_dual(hw) && tgt_phy != curr_phy)) 427 return ice_sbq_dev_phy_0_peer; 428 else 429 return ice_sbq_dev_phy_0; 430 } 431 432 /** 433 * ice_write_phy_eth56g - Write a PHY port register 434 * @hw: pointer to the HW struct 435 * @port: destination port 436 * @addr: PHY register address 437 * @val: Value to write 438 * 439 * Return: 0 on success, other error codes when failed to write to PHY 440 */ 441 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val) 442 { 443 struct ice_sbq_msg_input msg = { 444 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 445 .opcode = ice_sbq_msg_wr, 446 .msg_addr_low = lower_16_bits(addr), 447 .msg_addr_high = upper_16_bits(addr), 448 .data = val 449 }; 450 int err; 451 452 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 453 if (err) 454 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 455 err); 456 457 return err; 458 } 459 460 /** 461 * ice_read_phy_eth56g - Read a PHY port register 462 * @hw: pointer to the HW struct 463 * @port: destination port 464 * @addr: PHY register address 465 * @val: Value to write 466 * 467 * Return: 0 on success, other error codes when failed to read from PHY 468 */ 469 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 *val) 470 { 471 struct ice_sbq_msg_input msg = { 472 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 473 .opcode = ice_sbq_msg_rd, 474 .msg_addr_low = lower_16_bits(addr), 475 .msg_addr_high = upper_16_bits(addr) 476 }; 477 int err; 478 479 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 480 if (err) 481 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 482 err); 483 else 484 *val = msg.data; 485 486 return err; 487 } 488 489 /** 490 * ice_get_serdes_ref_sel_e825c - Read current Tx ref clock source 491 * @hw: pointer to the HW struct 492 * @port: port number for which Tx reference clock is read 493 * @clk: Tx reference clock value (output) 494 * 495 * Return: 0 on success, other error codes when failed to read from PHY 496 */ 497 int ice_get_serdes_ref_sel_e825c(struct ice_hw *hw, u8 port, 498 enum ice_e825c_ref_clk *clk) 499 { 500 u8 lane = port % hw->ptp.ports_per_phy; 501 u32 serdes_rx_nt, serdes_tx_nt; 502 u32 val; 503 int ret; 504 505 ret = ice_read_phy_eth56g(hw, port, 506 SERDES_IP_IF_LN_FLXM_GENERAL(lane, 0), 507 &val); 508 if (ret) 509 return ret; 510 511 serdes_rx_nt = FIELD_GET(CFG_ICTL_PCS_REF_SEL_RX_NT, val); 512 serdes_tx_nt = FIELD_GET(CFG_ICTL_PCS_REF_SEL_TX_NT, val); 513 514 if (serdes_tx_nt == REF_SEL_NT_SYNCE && 515 serdes_rx_nt == REF_SEL_NT_SYNCE) 516 *clk = ICE_REF_CLK_SYNCE; 517 else if (serdes_tx_nt == REF_SEL_NT_EREF0 && 518 serdes_rx_nt == REF_SEL_NT_EREF0) 519 *clk = ICE_REF_CLK_EREF0; 520 else 521 *clk = ICE_REF_CLK_ENET; 522 523 return 0; 524 } 525 526 /** 527 * ice_phy_res_address_eth56g - Calculate a PHY port register address 528 * @hw: pointer to the HW struct 529 * @lane: Lane number to be written 530 * @res_type: resource type (register/memory) 531 * @offset: Offset from PHY port register base 532 * @addr: The result address 533 * 534 * Return: 535 * * %0 - success 536 * * %EINVAL - invalid port number or resource type 537 */ 538 static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane, 539 enum eth56g_res_type res_type, 540 u32 offset, 541 u32 *addr) 542 { 543 if (res_type >= NUM_ETH56G_PHY_RES) 544 return -EINVAL; 545 546 /* Lanes 4..7 are in fact 0..3 on a second PHY */ 547 lane %= hw->ptp.ports_per_phy; 548 *addr = eth56g_phy_res[res_type].base_addr + 549 lane * eth56g_phy_res[res_type].step + offset; 550 551 return 0; 552 } 553 554 /** 555 * ice_write_port_eth56g - Write a PHY port register 556 * @hw: pointer to the HW struct 557 * @offset: PHY register offset 558 * @port: Port number 559 * @val: Value to write 560 * @res_type: resource type (register/memory) 561 * 562 * Return: 563 * * %0 - success 564 * * %EINVAL - invalid port number or resource type 565 * * %other - failed to write to PHY 566 */ 567 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 568 u32 val, enum eth56g_res_type res_type) 569 { 570 u32 addr; 571 int err; 572 573 if (port >= hw->ptp.num_lports) 574 return -EINVAL; 575 576 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 577 if (err) 578 return err; 579 580 return ice_write_phy_eth56g(hw, port, addr, val); 581 } 582 583 /** 584 * ice_read_port_eth56g - Read a PHY port register 585 * @hw: pointer to the HW struct 586 * @offset: PHY register offset 587 * @port: Port number 588 * @val: Value to write 589 * @res_type: resource type (register/memory) 590 * 591 * Return: 592 * * %0 - success 593 * * %EINVAL - invalid port number or resource type 594 * * %other - failed to read from PHY 595 */ 596 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 597 u32 *val, enum eth56g_res_type res_type) 598 { 599 u32 addr; 600 int err; 601 602 if (port >= hw->ptp.num_lports) 603 return -EINVAL; 604 605 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 606 if (err) 607 return err; 608 609 return ice_read_phy_eth56g(hw, port, addr, val); 610 } 611 612 /** 613 * ice_write_ptp_reg_eth56g - Write a PHY port register 614 * @hw: pointer to the HW struct 615 * @port: Port number to be written 616 * @offset: Offset from PHY port register base 617 * @val: Value to write 618 * 619 * Return: 620 * * %0 - success 621 * * %EINVAL - invalid port number or resource type 622 * * %other - failed to write to PHY 623 */ 624 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 625 u32 val) 626 { 627 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 628 } 629 630 /** 631 * ice_write_mac_reg_eth56g - Write a MAC PHY port register 632 * parameter 633 * @hw: pointer to the HW struct 634 * @port: Port number to be written 635 * @offset: Offset from PHY port register base 636 * @val: Value to write 637 * 638 * Return: 639 * * %0 - success 640 * * %EINVAL - invalid port number or resource type 641 * * %other - failed to write to PHY 642 */ 643 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 644 u32 val) 645 { 646 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 647 } 648 649 /** 650 * ice_write_xpcs_reg_eth56g - Write a PHY port register 651 * @hw: pointer to the HW struct 652 * @port: Port number to be written 653 * @offset: Offset from PHY port register base 654 * @val: Value to write 655 * 656 * Return: 657 * * %0 - success 658 * * %EINVAL - invalid port number or resource type 659 * * %other - failed to write to PHY 660 */ 661 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 662 u32 val) 663 { 664 return ice_write_port_eth56g(hw, port, offset, val, 665 ETH56G_PHY_REG_XPCS); 666 } 667 668 /** 669 * ice_read_ptp_reg_eth56g - Read a PHY port register 670 * @hw: pointer to the HW struct 671 * @port: Port number to be read 672 * @offset: Offset from PHY port register base 673 * @val: Pointer to the value to read (out param) 674 * 675 * Return: 676 * * %0 - success 677 * * %EINVAL - invalid port number or resource type 678 * * %other - failed to read from PHY 679 */ 680 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 681 u32 *val) 682 { 683 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 684 } 685 686 /** 687 * ice_read_mac_reg_eth56g - Read a PHY port register 688 * @hw: pointer to the HW struct 689 * @port: Port number to be read 690 * @offset: Offset from PHY port register base 691 * @val: Pointer to the value to read (out param) 692 * 693 * Return: 694 * * %0 - success 695 * * %EINVAL - invalid port number or resource type 696 * * %other - failed to read from PHY 697 */ 698 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 699 u32 *val) 700 { 701 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 702 } 703 704 /** 705 * ice_read_gpcs_reg_eth56g - Read a PHY port register 706 * @hw: pointer to the HW struct 707 * @port: Port number to be read 708 * @offset: Offset from PHY port register base 709 * @val: Pointer to the value to read (out param) 710 * 711 * Return: 712 * * %0 - success 713 * * %EINVAL - invalid port number or resource type 714 * * %other - failed to read from PHY 715 */ 716 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 717 u32 *val) 718 { 719 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS); 720 } 721 722 /** 723 * ice_read_port_mem_eth56g - Read a PHY port memory location 724 * @hw: pointer to the HW struct 725 * @port: Port number to be read 726 * @offset: Offset from PHY port register base 727 * @val: Pointer to the value to read (out param) 728 * 729 * Return: 730 * * %0 - success 731 * * %EINVAL - invalid port number or resource type 732 * * %other - failed to read from PHY 733 */ 734 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 735 u32 *val) 736 { 737 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 738 } 739 740 /** 741 * ice_write_port_mem_eth56g - Write a PHY port memory location 742 * @hw: pointer to the HW struct 743 * @port: Port number to be read 744 * @offset: Offset from PHY port register base 745 * @val: Pointer to the value to read (out param) 746 * 747 * Return: 748 * * %0 - success 749 * * %EINVAL - invalid port number or resource type 750 * * %other - failed to write to PHY 751 */ 752 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 753 u32 val) 754 { 755 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 756 } 757 758 /** 759 * ice_write_quad_ptp_reg_eth56g - Write a PHY quad register 760 * @hw: pointer to the HW struct 761 * @offset: PHY register offset 762 * @port: Port number 763 * @val: Value to write 764 * 765 * Return: 766 * * %0 - success 767 * * %EIO - invalid port number or resource type 768 * * %other - failed to write to PHY 769 */ 770 static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 771 u32 offset, u32 val) 772 { 773 u32 addr; 774 775 if (port >= hw->ptp.num_lports) 776 return -EIO; 777 778 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; 779 780 return ice_write_phy_eth56g(hw, port, addr, val); 781 } 782 783 /** 784 * ice_read_quad_ptp_reg_eth56g - Read a PHY quad register 785 * @hw: pointer to the HW struct 786 * @offset: PHY register offset 787 * @port: Port number 788 * @val: Value to read 789 * 790 * Return: 791 * * %0 - success 792 * * %EIO - invalid port number or resource type 793 * * %other - failed to read from PHY 794 */ 795 static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 796 u32 offset, u32 *val) 797 { 798 u32 addr; 799 800 if (port >= hw->ptp.num_lports) 801 return -EIO; 802 803 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; 804 805 return ice_read_phy_eth56g(hw, port, addr, val); 806 } 807 808 /** 809 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register 810 * @low_addr: the low address to check 811 * @high_addr: on return, contains the high address of the 64bit register 812 * 813 * Write the appropriate high register offset to use. 814 * 815 * Return: true if the provided low address is one of the known 64bit PHY values 816 * represented as two 32bit registers, false otherwise. 817 */ 818 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 819 { 820 switch (low_addr) { 821 case PHY_REG_TX_TIMER_INC_PRE_L: 822 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U; 823 return true; 824 case PHY_REG_RX_TIMER_INC_PRE_L: 825 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U; 826 return true; 827 case PHY_REG_TX_CAPTURE_L: 828 *high_addr = PHY_REG_TX_CAPTURE_U; 829 return true; 830 case PHY_REG_RX_CAPTURE_L: 831 *high_addr = PHY_REG_RX_CAPTURE_U; 832 return true; 833 case PHY_REG_TOTAL_TX_OFFSET_L: 834 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U; 835 return true; 836 case PHY_REG_TOTAL_RX_OFFSET_L: 837 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U; 838 return true; 839 case PHY_REG_TX_MEMORY_STATUS_L: 840 *high_addr = PHY_REG_TX_MEMORY_STATUS_U; 841 return true; 842 default: 843 return false; 844 } 845 } 846 847 /** 848 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register 849 * @low_addr: the low address to check 850 * @high_addr: on return, contains the high address of the 40bit value 851 * 852 * Write the appropriate high register offset to use. 853 * 854 * Return: true if the provided low address is one of the known 40bit PHY 855 * values split into two registers with the lower 8 bits in the low register and 856 * the upper 32 bits in the high register, false otherwise. 857 */ 858 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 859 { 860 switch (low_addr) { 861 case PHY_REG_TIMETUS_L: 862 *high_addr = PHY_REG_TIMETUS_U; 863 return true; 864 case PHY_PCS_REF_TUS_L: 865 *high_addr = PHY_PCS_REF_TUS_U; 866 return true; 867 case PHY_PCS_REF_INC_L: 868 *high_addr = PHY_PCS_REF_INC_U; 869 return true; 870 default: 871 return false; 872 } 873 } 874 875 /** 876 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers 877 * @hw: pointer to the HW struct 878 * @port: PHY port to read from 879 * @low_addr: offset of the lower register to read from 880 * @val: on return, the contents of the 64bit value from the PHY registers 881 * @res_type: resource type 882 * 883 * Check if the caller has specified a known 40 bit register offset and read 884 * the two registers associated with a 40bit value and return it in the val 885 * pointer. 886 * 887 * Return: 888 * * %0 - success 889 * * %EINVAL - not a 64 bit register 890 * * %other - failed to read from PHY 891 */ 892 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 893 u64 *val, enum eth56g_res_type res_type) 894 { 895 u16 high_addr; 896 u32 lo, hi; 897 int err; 898 899 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 900 return -EINVAL; 901 902 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type); 903 if (err) { 904 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d", 905 low_addr, err); 906 return err; 907 } 908 909 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type); 910 if (err) { 911 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d", 912 high_addr, err); 913 return err; 914 } 915 916 *val = ((u64)hi << 32) | lo; 917 918 return 0; 919 } 920 921 /** 922 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers 923 * @hw: pointer to the HW struct 924 * @port: PHY port to read from 925 * @low_addr: offset of the lower register to read from 926 * @val: on return, the contents of the 64bit value from the PHY registers 927 * 928 * Check if the caller has specified a known 40 bit register offset and read 929 * the two registers associated with a 40bit value and return it in the val 930 * pointer. 931 * 932 * Return: 933 * * %0 - success 934 * * %EINVAL - not a 64 bit register 935 * * %other - failed to read from PHY 936 */ 937 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 938 u64 *val) 939 { 940 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val, 941 ETH56G_PHY_REG_PTP); 942 } 943 944 /** 945 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY 946 * @hw: pointer to the HW struct 947 * @port: port to write to 948 * @low_addr: offset of the low register 949 * @val: 40b value to write 950 * @res_type: resource type 951 * 952 * Check if the caller has specified a known 40 bit register offset and write 953 * provided 40b value to the two associated registers by splitting it up into 954 * two chunks, the lower 8 bits and the upper 32 bits. 955 * 956 * Return: 957 * * %0 - success 958 * * %EINVAL - not a 40 bit register 959 * * %other - failed to write to PHY 960 */ 961 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 962 u16 low_addr, u64 val, 963 enum eth56g_res_type res_type) 964 { 965 u16 high_addr; 966 u32 lo, hi; 967 int err; 968 969 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) 970 return -EINVAL; 971 972 lo = FIELD_GET(P_REG_40B_LOW_M, val); 973 hi = (u32)(val >> P_REG_40B_HIGH_S); 974 975 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 976 if (err) { 977 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 978 low_addr, err); 979 return err; 980 } 981 982 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 983 if (err) { 984 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 985 high_addr, err); 986 return err; 987 } 988 989 return 0; 990 } 991 992 /** 993 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY 994 * @hw: pointer to the HW struct 995 * @port: port to write to 996 * @low_addr: offset of the low register 997 * @val: 40b value to write 998 * 999 * Check if the caller has specified a known 40 bit register offset and write 1000 * provided 40b value to the two associated registers by splitting it up into 1001 * two chunks, the lower 8 bits and the upper 32 bits. 1002 * 1003 * Return: 1004 * * %0 - success 1005 * * %EINVAL - not a 40 bit register 1006 * * %other - failed to write to PHY 1007 */ 1008 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1009 u16 low_addr, u64 val) 1010 { 1011 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val, 1012 ETH56G_PHY_REG_PTP); 1013 } 1014 1015 /** 1016 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers 1017 * @hw: pointer to the HW struct 1018 * @port: PHY port to read from 1019 * @low_addr: offset of the lower register to read from 1020 * @val: the contents of the 64bit value to write to PHY 1021 * @res_type: resource type 1022 * 1023 * Check if the caller has specified a known 64 bit register offset and write 1024 * the 64bit value to the two associated 32bit PHY registers. 1025 * 1026 * Return: 1027 * * %0 - success 1028 * * %EINVAL - not a 64 bit register 1029 * * %other - failed to write to PHY 1030 */ 1031 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1032 u16 low_addr, u64 val, 1033 enum eth56g_res_type res_type) 1034 { 1035 u16 high_addr; 1036 u32 lo, hi; 1037 int err; 1038 1039 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1040 return -EINVAL; 1041 1042 lo = lower_32_bits(val); 1043 hi = upper_32_bits(val); 1044 1045 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1046 if (err) { 1047 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1048 low_addr, err); 1049 return err; 1050 } 1051 1052 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1053 if (err) { 1054 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1055 high_addr, err); 1056 return err; 1057 } 1058 1059 return 0; 1060 } 1061 1062 /** 1063 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers 1064 * @hw: pointer to the HW struct 1065 * @port: PHY port to read from 1066 * @low_addr: offset of the lower register to read from 1067 * @val: the contents of the 64bit value to write to PHY 1068 * 1069 * Check if the caller has specified a known 64 bit register offset and write 1070 * the 64bit value to the two associated 32bit PHY registers. 1071 * 1072 * Return: 1073 * * %0 - success 1074 * * %EINVAL - not a 64 bit register 1075 * * %other - failed to write to PHY 1076 */ 1077 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1078 u16 low_addr, u64 val) 1079 { 1080 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val, 1081 ETH56G_PHY_REG_PTP); 1082 } 1083 1084 /** 1085 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory 1086 * @hw: pointer to the HW struct 1087 * @port: the port to read from 1088 * @idx: the timestamp index to read 1089 * @tstamp: on return, the 40bit timestamp value 1090 * 1091 * Read a 40bit timestamp value out of the two associated entries in the 1092 * port memory block of the internal PHYs of the 56G devices. 1093 * 1094 * Return: 1095 * * %0 - success 1096 * * %other - failed to read from PHY 1097 */ 1098 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, 1099 u64 *tstamp) 1100 { 1101 u16 lo_addr, hi_addr; 1102 u32 lo, hi; 1103 int err; 1104 1105 lo_addr = (u16)PHY_TSTAMP_L(idx); 1106 hi_addr = (u16)PHY_TSTAMP_U(idx); 1107 1108 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo); 1109 if (err) { 1110 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 1111 err); 1112 return err; 1113 } 1114 1115 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi); 1116 if (err) { 1117 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 1118 err); 1119 return err; 1120 } 1121 1122 /* For 56G based internal PHYs, the timestamp is reported with the 1123 * lower 8 bits in the low register, and the upper 32 bits in the high 1124 * register. 1125 */ 1126 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 1127 FIELD_PREP(PHY_40B_LOW_M, lo); 1128 return 0; 1129 } 1130 1131 /** 1132 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block 1133 * @hw: pointer to the HW struct 1134 * @port: the quad to read from 1135 * @idx: the timestamp index to reset 1136 * 1137 * Read and then forcibly clear the timestamp index to ensure the valid bit is 1138 * cleared and the timestamp status bit is reset in the PHY port memory of 1139 * internal PHYs of the 56G devices. 1140 * 1141 * To directly clear the contents of the timestamp block entirely, discarding 1142 * all timestamp data at once, software should instead use 1143 * ice_ptp_reset_ts_memory_quad_eth56g(). 1144 * 1145 * This function should only be called on an idx whose bit is set according to 1146 * ice_get_phy_tx_tstamp_ready(). 1147 * 1148 * Return: 1149 * * %0 - success 1150 * * %other - failed to write to PHY 1151 */ 1152 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) 1153 { 1154 u64 unused_tstamp; 1155 u16 lo_addr; 1156 int err; 1157 1158 /* Read the timestamp register to ensure the timestamp status bit is 1159 * cleared. 1160 */ 1161 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp); 1162 if (err) { 1163 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", 1164 port, idx, err); 1165 } 1166 1167 lo_addr = (u16)PHY_TSTAMP_L(idx); 1168 1169 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0); 1170 if (err) { 1171 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n", 1172 port, idx, err); 1173 return err; 1174 } 1175 1176 return 0; 1177 } 1178 1179 /** 1180 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block 1181 * @hw: pointer to the HW struct 1182 */ 1183 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) 1184 { 1185 unsigned int port; 1186 1187 for (port = 0; port < hw->ptp.num_lports; port++) { 1188 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 1189 0); 1190 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, 1191 0); 1192 } 1193 } 1194 1195 /** 1196 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time 1197 * @hw: pointer to the HW struct 1198 * @port: port number 1199 * @time: time to initialize the PHY port clocks to 1200 * 1201 * Write a new initial time value into registers of a specific PHY port. 1202 * 1203 * Return: 1204 * * %0 - success 1205 * * %other - failed to write to PHY 1206 */ 1207 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port, 1208 u64 time) 1209 { 1210 int err; 1211 1212 /* Tx case */ 1213 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1214 time); 1215 if (err) 1216 return err; 1217 1218 /* Rx case */ 1219 return ice_write_64b_ptp_reg_eth56g(hw, port, 1220 PHY_REG_RX_TIMER_INC_PRE_L, time); 1221 } 1222 1223 /** 1224 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time 1225 * @hw: pointer to the HW struct 1226 * @time: Time to initialize the PHY port clocks to 1227 * 1228 * Program the PHY port registers with a new initial time value. The port 1229 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 1230 * command. The time value is the upper 32 bits of the PHY timer, usually in 1231 * units of nominal nanoseconds. 1232 * 1233 * Return: 1234 * * %0 - success 1235 * * %other - failed to write to PHY 1236 */ 1237 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) 1238 { 1239 u64 phy_time; 1240 u8 port; 1241 1242 /* The time represents the upper 32 bits of the PHY timer, so we need 1243 * to shift to account for this when programming. 1244 */ 1245 phy_time = (u64)time << 32; 1246 1247 for (port = 0; port < hw->ptp.num_lports; port++) { 1248 int err; 1249 1250 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time); 1251 if (err) { 1252 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1253 port, err); 1254 return err; 1255 } 1256 } 1257 1258 return 0; 1259 } 1260 1261 /** 1262 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust 1263 * @hw: pointer to HW struct 1264 * @port: Port number to be programmed 1265 * @time: time in cycles to adjust the port clocks 1266 * 1267 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1268 * registers. The atomic adjustment won't be completed until the driver issues 1269 * an ICE_PTP_ADJ_TIME command. 1270 * 1271 * Note that time is not in units of nanoseconds. It is in clock time 1272 * including the lower sub-nanosecond portion of the port timer. 1273 * 1274 * Negative adjustments are supported using 2s complement arithmetic. 1275 * 1276 * Return: 1277 * * %0 - success 1278 * * %other - failed to write to PHY 1279 */ 1280 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time) 1281 { 1282 u32 l_time, u_time; 1283 int err; 1284 1285 l_time = lower_32_bits(time); 1286 u_time = upper_32_bits(time); 1287 1288 /* Tx case */ 1289 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1290 l_time); 1291 if (err) 1292 goto exit_err; 1293 1294 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U, 1295 u_time); 1296 if (err) 1297 goto exit_err; 1298 1299 /* Rx case */ 1300 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L, 1301 l_time); 1302 if (err) 1303 goto exit_err; 1304 1305 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U, 1306 u_time); 1307 if (err) 1308 goto exit_err; 1309 1310 return 0; 1311 1312 exit_err: 1313 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1314 port, err); 1315 return err; 1316 } 1317 1318 /** 1319 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment 1320 * @hw: pointer to HW struct 1321 * @adj: adjustment in nanoseconds 1322 * 1323 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1324 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1325 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 1326 * 1327 * Return: 1328 * * %0 - success 1329 * * %other - failed to write to PHY 1330 */ 1331 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj) 1332 { 1333 s64 cycles; 1334 u8 port; 1335 1336 /* The port clock supports adjustment of the sub-nanosecond portion of 1337 * the clock (lowest 32 bits). We shift the provided adjustment in 1338 * nanoseconds by 32 to calculate the appropriate adjustment to program 1339 * into the PHY ports. 1340 */ 1341 cycles = (s64)adj << 32; 1342 1343 for (port = 0; port < hw->ptp.num_lports; port++) { 1344 int err; 1345 1346 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles); 1347 if (err) 1348 return err; 1349 } 1350 1351 return 0; 1352 } 1353 1354 /** 1355 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment 1356 * @hw: pointer to HW struct 1357 * @incval: new increment value to prepare 1358 * 1359 * Prepare each of the PHY ports for a new increment value by programming the 1360 * port's TIMETUS registers. The new increment value will be updated after 1361 * issuing an ICE_PTP_INIT_INCVAL command. 1362 * 1363 * Return: 1364 * * %0 - success 1365 * * %other - failed to write to PHY 1366 */ 1367 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) 1368 { 1369 u8 port; 1370 1371 for (port = 0; port < hw->ptp.num_lports; port++) { 1372 int err; 1373 1374 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, 1375 incval); 1376 if (err) { 1377 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1378 port, err); 1379 return err; 1380 } 1381 } 1382 1383 return 0; 1384 } 1385 1386 /** 1387 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture 1388 * @hw: pointer to HW struct 1389 * @port: Port number to read 1390 * @tx_ts: on return, the Tx port time capture 1391 * @rx_ts: on return, the Rx port time capture 1392 * 1393 * Read the port's Tx and Rx local time capture values. 1394 * 1395 * Return: 1396 * * %0 - success 1397 * * %other - failed to read from PHY 1398 */ 1399 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, 1400 u64 *tx_ts, u64 *rx_ts) 1401 { 1402 int err; 1403 1404 /* Tx case */ 1405 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L, 1406 tx_ts); 1407 if (err) { 1408 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1409 err); 1410 return err; 1411 } 1412 1413 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts); 1414 1415 /* Rx case */ 1416 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L, 1417 rx_ts); 1418 if (err) { 1419 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1420 err); 1421 return err; 1422 } 1423 1424 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts); 1425 1426 return 0; 1427 } 1428 1429 /** 1430 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command 1431 * @hw: pointer to HW struct 1432 * @port: Port to which cmd has to be sent 1433 * @cmd: Command to be sent to the port 1434 * 1435 * Prepare the requested port for an upcoming timer sync command. 1436 * 1437 * Return: 1438 * * %0 - success 1439 * * %other - failed to write to PHY 1440 */ 1441 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port, 1442 enum ice_ptp_tmr_cmd cmd) 1443 { 1444 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 1445 int err; 1446 1447 /* Tx case */ 1448 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val); 1449 if (err) { 1450 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1451 err); 1452 return err; 1453 } 1454 1455 /* Rx case */ 1456 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val); 1457 if (err) { 1458 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1459 err); 1460 return err; 1461 } 1462 1463 return 0; 1464 } 1465 1466 /** 1467 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type 1468 * @li: pointer to link information struct 1469 * 1470 * Return: simplified ETH56G PHY speed 1471 */ 1472 static enum ice_eth56g_link_spd 1473 ice_phy_get_speed_eth56g(struct ice_link_status *li) 1474 { 1475 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, 1476 li->phy_type_high); 1477 1478 switch (speed) { 1479 case ICE_AQ_LINK_SPEED_1000MB: 1480 return ICE_ETH56G_LNK_SPD_1G; 1481 case ICE_AQ_LINK_SPEED_2500MB: 1482 return ICE_ETH56G_LNK_SPD_2_5G; 1483 case ICE_AQ_LINK_SPEED_10GB: 1484 return ICE_ETH56G_LNK_SPD_10G; 1485 case ICE_AQ_LINK_SPEED_25GB: 1486 return ICE_ETH56G_LNK_SPD_25G; 1487 case ICE_AQ_LINK_SPEED_40GB: 1488 return ICE_ETH56G_LNK_SPD_40G; 1489 case ICE_AQ_LINK_SPEED_50GB: 1490 switch (li->phy_type_low) { 1491 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1492 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1493 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1494 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1495 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1496 case ICE_PHY_TYPE_LOW_50G_AUI1: 1497 return ICE_ETH56G_LNK_SPD_50G; 1498 default: 1499 return ICE_ETH56G_LNK_SPD_50G2; 1500 } 1501 case ICE_AQ_LINK_SPEED_100GB: 1502 if (li->phy_type_high || 1503 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) 1504 return ICE_ETH56G_LNK_SPD_100G2; 1505 else 1506 return ICE_ETH56G_LNK_SPD_100G; 1507 default: 1508 return ICE_ETH56G_LNK_SPD_1G; 1509 } 1510 } 1511 1512 /** 1513 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle 1514 * @hw: pointer to the HW struct 1515 * @port: port to configure 1516 * 1517 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1518 * timestamp calibration process. 1519 * 1520 * Return: 1521 * * %0 - success 1522 * * %other - PHY read/write failed 1523 */ 1524 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port) 1525 { 1526 u32 val; 1527 int err; 1528 1529 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH, 1530 ICE_ETH56G_NOMINAL_THRESH4); 1531 if (err) { 1532 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d", 1533 err); 1534 return err; 1535 } 1536 1537 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 1538 case ICE_ETH56G_LNK_SPD_1G: 1539 case ICE_ETH56G_LNK_SPD_2_5G: 1540 err = ice_read_quad_ptp_reg_eth56g(hw, port, 1541 PHY_GPCS_CONFIG_REG0, &val); 1542 if (err) { 1543 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d", 1544 err); 1545 return err; 1546 } 1547 1548 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M; 1549 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M, 1550 ICE_ETH56G_NOMINAL_TX_THRESH); 1551 1552 err = ice_write_quad_ptp_reg_eth56g(hw, port, 1553 PHY_GPCS_CONFIG_REG0, val); 1554 if (err) { 1555 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d", 1556 err); 1557 return err; 1558 } 1559 break; 1560 default: 1561 break; 1562 } 1563 1564 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L, 1565 ICE_ETH56G_NOMINAL_PCS_REF_TUS); 1566 if (err) { 1567 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d", 1568 err); 1569 return err; 1570 } 1571 1572 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L, 1573 ICE_ETH56G_NOMINAL_PCS_REF_INC); 1574 if (err) { 1575 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d", 1576 err); 1577 return err; 1578 } 1579 1580 return 0; 1581 } 1582 1583 /** 1584 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings 1585 * @hw: Pointer to the HW struct 1586 * @port: Port to configure 1587 * 1588 * Return: 1589 * * %0 - success 1590 * * %other - PHY read/write failed 1591 */ 1592 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port) 1593 { 1594 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 1595 u32 addr, val, peer_delay; 1596 bool enable, sfd_ena; 1597 int err; 1598 1599 enable = hw->ptp.phy.eth56g.onestep_ena; 1600 peer_delay = hw->ptp.phy.eth56g.peer_delay; 1601 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; 1602 1603 addr = PHY_PTP_1STEP_CONFIG; 1604 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &val); 1605 if (err) 1606 return err; 1607 1608 if (enable) 1609 val |= BIT(quad_lane); 1610 else 1611 val &= ~BIT(quad_lane); 1612 1613 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M); 1614 1615 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 1616 if (err) 1617 return err; 1618 1619 addr = PHY_PTP_1STEP_PEER_DELAY(quad_lane); 1620 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay); 1621 if (peer_delay) 1622 val |= PHY_PTP_1STEP_PD_ADD_PD_M; 1623 val |= PHY_PTP_1STEP_PD_DLY_V_M; 1624 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 1625 if (err) 1626 return err; 1627 1628 val &= ~PHY_PTP_1STEP_PD_DLY_V_M; 1629 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 1630 if (err) 1631 return err; 1632 1633 addr = PHY_MAC_XIF_MODE; 1634 err = ice_read_mac_reg_eth56g(hw, port, addr, &val); 1635 if (err) 1636 return err; 1637 1638 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M | 1639 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M); 1640 1641 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 1642 case ICE_ETH56G_LNK_SPD_1G: 1643 case ICE_ETH56G_LNK_SPD_2_5G: 1644 val |= PHY_MAC_XIF_GMII_TS_SEL_M; 1645 break; 1646 default: 1647 break; 1648 } 1649 1650 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) | 1651 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) | 1652 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena); 1653 1654 return ice_write_mac_reg_eth56g(hw, port, addr, val); 1655 } 1656 1657 /** 1658 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values 1659 * @a: multiplier value 1660 * @b: multiplicand value 1661 * 1662 * Return: result of multiplication 1663 */ 1664 static u32 mul_u32_u32_fx_q9(u32 a, u32 b) 1665 { 1666 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W); 1667 } 1668 1669 /** 1670 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow 1671 * @a: first value 1672 * @b: second value 1673 * 1674 * Return: result of addition 1675 */ 1676 static u32 add_u32_u32_fx(u32 a, u32 b) 1677 { 1678 return lower_32_bits(((u64)a + b)); 1679 } 1680 1681 /** 1682 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value 1683 * @hw: pointer to the HW struct 1684 * @port: port to configure 1685 * @bs: bitslip multiplier 1686 * @fc: FC-FEC enabled 1687 * @rs: RS-FEC enabled 1688 * @spd: link speed 1689 * 1690 * Return: calculated bitslip value 1691 */ 1692 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, 1693 bool fc, bool rs, 1694 enum ice_eth56g_link_spd spd) 1695 { 1696 u32 bitslip; 1697 int err; 1698 1699 if (!bs || rs) 1700 return 0; 1701 1702 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) { 1703 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP, 1704 &bitslip); 1705 } else { 1706 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 1707 u32 addr; 1708 1709 addr = PHY_REG_SD_BIT_SLIP(quad_lane); 1710 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &bitslip); 1711 } 1712 if (err) 1713 return 0; 1714 1715 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) { 1716 /* Bitslip register value of 0 corresponds to 10 so substitute 1717 * it for calculations 1718 */ 1719 bitslip = 10; 1720 } else if (spd == ICE_ETH56G_LNK_SPD_10G || 1721 spd == ICE_ETH56G_LNK_SPD_25G) { 1722 if (fc) 1723 bitslip = bitslip * 2 + 32; 1724 else 1725 bitslip = (u32)((s32)bitslip * -1 + 20); 1726 } 1727 1728 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W; 1729 return mul_u32_u32_fx_q9(bitslip, bs); 1730 } 1731 1732 /** 1733 * ice_ptp_calc_deskew_eth56g - Calculate deskew value 1734 * @hw: pointer to the HW struct 1735 * @port: port to configure 1736 * @ds: deskew multiplier 1737 * @rs: RS-FEC enabled 1738 * @spd: link speed 1739 * 1740 * Return: calculated deskew value 1741 */ 1742 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, 1743 bool rs, enum ice_eth56g_link_spd spd) 1744 { 1745 u32 deskew_i, deskew_f; 1746 int err; 1747 1748 if (!ds) 1749 return 0; 1750 1751 read_poll_timeout(ice_read_ptp_reg_eth56g, err, 1752 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500, 1753 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0, 1754 &deskew_i); 1755 if (err) 1756 return err; 1757 1758 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i); 1759 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i); 1760 1761 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2) 1762 ds = 0x633; /* 3.1 */ 1763 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G) 1764 ds = 0x31b; /* 1.552 */ 1765 1766 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i); 1767 /* Shift 3 fractional bits to the end of the integer part */ 1768 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; 1769 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); 1770 } 1771 1772 /** 1773 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values 1774 * @hw: pointer to the HW struct 1775 * @port: port to configure 1776 * @spd: link speed 1777 * @cfg: structure to store output values 1778 * @fc: FC-FEC enabled 1779 * @rs: RS-FEC enabled 1780 * 1781 * Return: 1782 * * %0 - success 1783 * * %other - failed to write to PHY 1784 */ 1785 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, 1786 enum ice_eth56g_link_spd spd, 1787 const struct ice_eth56g_mac_reg_cfg *cfg, 1788 bool fc, bool rs) 1789 { 1790 u32 rx_offset, tx_offset, bs_ds; 1791 bool onestep, sfd; 1792 1793 onestep = hw->ptp.phy.eth56g.onestep_ena; 1794 sfd = hw->ptp.phy.eth56g.sfd_ena; 1795 bs_ds = cfg->rx_offset.bs_ds; 1796 1797 if (fc) 1798 rx_offset = cfg->rx_offset.fc; 1799 else if (rs) 1800 rx_offset = cfg->rx_offset.rs; 1801 else 1802 rx_offset = cfg->rx_offset.no_fec; 1803 1804 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); 1805 if (sfd) 1806 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); 1807 1808 if (spd < ICE_ETH56G_LNK_SPD_40G) 1809 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs, 1810 spd); 1811 else 1812 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd); 1813 rx_offset = add_u32_u32_fx(rx_offset, bs_ds); 1814 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT | 1815 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC; 1816 1817 if (fc) 1818 tx_offset = cfg->tx_offset.fc; 1819 else if (rs) 1820 tx_offset = cfg->tx_offset.rs; 1821 else 1822 tx_offset = cfg->tx_offset.no_fec; 1823 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + 1824 cfg->tx_offset.onestep * onestep; 1825 1826 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset); 1827 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset); 1828 } 1829 1830 /** 1831 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP 1832 * @hw: Pointer to the HW struct 1833 * @port: Port to configure 1834 * 1835 * Return: 1836 * * %0 - success 1837 * * %other - failed to write to PHY 1838 */ 1839 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port) 1840 { 1841 const struct ice_eth56g_mac_reg_cfg *cfg; 1842 enum ice_eth56g_link_spd spd; 1843 struct ice_link_status *li; 1844 bool fc = false; 1845 bool rs = false; 1846 bool onestep; 1847 u32 val; 1848 int err; 1849 1850 onestep = hw->ptp.phy.eth56g.onestep_ena; 1851 li = &hw->port_info->phy.link_info; 1852 spd = ice_phy_get_speed_eth56g(li); 1853 if (!!(li->an_info & ICE_AQ_FEC_EN)) { 1854 if (spd == ICE_ETH56G_LNK_SPD_10G) { 1855 fc = true; 1856 } else { 1857 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); 1858 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); 1859 } 1860 } 1861 cfg = ð56g_mac_cfg[spd]; 1862 1863 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0); 1864 if (err) 1865 return err; 1866 1867 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0); 1868 if (err) 1869 return err; 1870 1871 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M, 1872 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | 1873 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | 1874 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M, 1875 cfg->tx_cw_dly.def + 1876 onestep * cfg->tx_cw_dly.onestep) | 1877 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M, 1878 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | 1879 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M, 1880 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | 1881 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M, 1882 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | 1883 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); 1884 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val); 1885 if (err) 1886 return err; 1887 1888 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME, 1889 cfg->blktime); 1890 if (err) 1891 return err; 1892 1893 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs); 1894 if (err) 1895 return err; 1896 1897 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs) 1898 val = 0; 1899 else 1900 val = cfg->mktime; 1901 1902 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val); 1903 } 1904 1905 /** 1906 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt 1907 * @hw: pointer to the HW struct 1908 * @port: the timestamp port 1909 * @ena: enable or disable interrupt 1910 * @threshold: interrupt threshold 1911 * 1912 * The threshold cannot be 0 while the interrupt is enabled. 1913 * 1914 * Configure TX timestamp interrupt for the specified port 1915 * 1916 * Return: 1917 * * %0 - success 1918 * * %other - PHY read/write failed 1919 */ 1920 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) 1921 { 1922 int err; 1923 u32 val; 1924 1925 if (ena && !threshold) 1926 return -EINVAL; 1927 1928 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val); 1929 if (err) 1930 return err; 1931 1932 val &= ~PHY_TS_INT_CONFIG_ENA_M; 1933 if (ena) { 1934 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M; 1935 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold); 1936 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, 1937 val); 1938 if (err) { 1939 ice_debug(hw, ICE_DBG_PTP, 1940 "Failed to update 'threshold' PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\n", 1941 port, !!ena, threshold); 1942 return err; 1943 } 1944 val |= PHY_TS_INT_CONFIG_ENA_M; 1945 } 1946 1947 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val); 1948 if (err) { 1949 ice_debug(hw, ICE_DBG_PTP, 1950 "Failed to update 'ena' PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\n", 1951 port, !!ena, threshold); 1952 return err; 1953 } 1954 1955 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val); 1956 if (err) { 1957 ice_debug(hw, ICE_DBG_PTP, 1958 "Failed to read PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\n", 1959 port, !!ena, threshold); 1960 return err; 1961 } 1962 1963 return 0; 1964 } 1965 1966 /** 1967 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time 1968 * @hw: pointer to the HW struct 1969 * @port: the PHY port to read 1970 * @phy_time: on return, the 64bit PHY timer value 1971 * @phc_time: on return, the lower 64bits of PHC time 1972 * 1973 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 1974 * and PHC timer values. 1975 * 1976 * Return: 1977 * * %0 - success 1978 * * %other - PHY read/write failed 1979 */ 1980 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, 1981 u64 *phy_time, u64 *phc_time) 1982 { 1983 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1984 u64 tx_time, rx_time; 1985 u32 zo, lo; 1986 u8 tmr_idx; 1987 int err; 1988 1989 tmr_idx = ice_get_ptp_src_clock_index(hw); 1990 1991 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 1992 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 1993 1994 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 1995 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 1996 if (err) 1997 return err; 1998 1999 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 2000 ice_ptp_exec_tmr_cmd(hw); 2001 2002 /* Read the captured PHC time from the shadow time registers */ 2003 if (ice_is_primary(hw)) { 2004 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 2005 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 2006 } else { 2007 zo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_0(tmr_idx)); 2008 lo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_L(tmr_idx)); 2009 } 2010 *phc_time = (u64)lo << 32 | zo; 2011 2012 /* Read the captured PHY time from the PHY shadow registers */ 2013 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time); 2014 if (err) 2015 return err; 2016 2017 /* If the PHY Tx and Rx timers don't match, log a warning message. 2018 * Note that this should not happen in normal circumstances since the 2019 * driver always programs them together. 2020 */ 2021 if (tx_time != rx_time) 2022 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 2023 port, tx_time, rx_time); 2024 2025 *phy_time = tx_time; 2026 2027 return 0; 2028 } 2029 2030 /** 2031 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer 2032 * @hw: pointer to the HW struct 2033 * @port: the PHY port to synchronize 2034 * 2035 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 2036 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 2037 * simultaneous read of the PHY timer and PHC timer. Then we use the 2038 * difference to calculate an appropriate 2s complement addition to add 2039 * to the PHY timer in order to ensure it reads the same value as the 2040 * primary PHC timer. 2041 * 2042 * Return: 2043 * * %0 - success 2044 * * %-EBUSY- failed to acquire PTP semaphore 2045 * * %other - PHY read/write failed 2046 */ 2047 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2048 { 2049 u64 phc_time, phy_time, difference; 2050 int err; 2051 2052 if (!ice_ptp_lock(hw)) { 2053 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 2054 return -EBUSY; 2055 } 2056 2057 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2058 if (err) 2059 goto err_unlock; 2060 2061 /* Calculate the amount required to add to the port time in order for 2062 * it to match the PHC time. 2063 * 2064 * Note that the port adjustment is done using 2s complement 2065 * arithmetic. This is convenient since it means that we can simply 2066 * calculate the difference between the PHC time and the port time, 2067 * and it will be interpreted correctly. 2068 */ 2069 2070 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2071 difference = phc_time - phy_time; 2072 2073 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference); 2074 if (err) 2075 goto err_unlock; 2076 2077 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 2078 if (err) 2079 goto err_unlock; 2080 2081 /* Issue the sync to activate the time adjustment */ 2082 ice_ptp_exec_tmr_cmd(hw); 2083 2084 /* Re-capture the timer values to flush the command registers and 2085 * verify that the time was properly adjusted. 2086 */ 2087 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2088 if (err) 2089 goto err_unlock; 2090 2091 dev_info(ice_hw_to_dev(hw), 2092 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 2093 port, phy_time, phc_time); 2094 2095 err_unlock: 2096 ice_ptp_unlock(hw); 2097 return err; 2098 } 2099 2100 /** 2101 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer 2102 * @hw: pointer to the HW struct 2103 * @port: the PHY port to stop 2104 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS 2105 * 2106 * Stop the clock of a PHY port. This must be done as part of the flow to 2107 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2108 * initialized or when link speed changes. 2109 * 2110 * Return: 2111 * * %0 - success 2112 * * %other - failed to write to PHY 2113 */ 2114 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) 2115 { 2116 int err; 2117 2118 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0); 2119 if (err) 2120 return err; 2121 2122 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0); 2123 if (err) 2124 return err; 2125 2126 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 2127 2128 return 0; 2129 } 2130 2131 /** 2132 * ice_start_phy_timer_eth56g - Start the PHY clock timer 2133 * @hw: pointer to the HW struct 2134 * @port: the PHY port to start 2135 * 2136 * Start the clock of a PHY port. This must be done as part of the flow to 2137 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2138 * initialized or when link speed changes. 2139 * 2140 * Return: 2141 * * %0 - success 2142 * * %other - PHY read/write failed 2143 */ 2144 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2145 { 2146 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 2147 u32 lo, hi; 2148 u64 incval; 2149 u8 tmr_idx; 2150 int err; 2151 2152 tmr_idx = ice_get_ptp_src_clock_index(hw); 2153 2154 err = ice_stop_phy_timer_eth56g(hw, port, false); 2155 if (err) 2156 return err; 2157 2158 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2159 2160 err = ice_phy_cfg_parpcs_eth56g(hw, port); 2161 if (err) 2162 return err; 2163 2164 err = ice_phy_cfg_ptp_1step_eth56g(hw, port); 2165 if (err) 2166 return err; 2167 2168 err = ice_phy_cfg_mac_eth56g(hw, port); 2169 if (err) 2170 return err; 2171 2172 if (ice_is_primary(hw)) { 2173 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2174 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2175 } else { 2176 lo = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_L(tmr_idx)); 2177 hi = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_H(tmr_idx)); 2178 } 2179 incval = (u64)hi << 32 | lo; 2180 2181 if (!ice_ptp_lock(hw)) { 2182 dev_err(ice_hw_to_dev(hw), "Failed to acquire PTP semaphore\n"); 2183 return -EBUSY; 2184 } 2185 2186 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval); 2187 if (err) 2188 goto err_ptp_unlock; 2189 2190 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 2191 if (err) 2192 goto err_ptp_unlock; 2193 2194 ice_ptp_exec_tmr_cmd(hw); 2195 2196 ice_ptp_unlock(hw); 2197 2198 err = ice_sync_phy_timer_eth56g(hw, port); 2199 if (err) 2200 return err; 2201 2202 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); 2203 if (err) 2204 return err; 2205 2206 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); 2207 if (err) 2208 return err; 2209 2210 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2211 2212 return 0; 2213 2214 err_ptp_unlock: 2215 ice_ptp_unlock(hw); 2216 return err; 2217 } 2218 2219 /** 2220 * ice_check_phy_tx_tstamp_ready_eth56g - Check Tx memory status for all ports 2221 * @hw: pointer to the HW struct 2222 * 2223 * Check the PHY_REG_TX_MEMORY_STATUS for all ports. A set bit indicates 2224 * a waiting timestamp. 2225 * 2226 * Return: 1 if any port has at least one timestamp ready bit set, 2227 * 0 otherwise, and a negative error code if unable to read the bitmap. 2228 */ 2229 static int ice_check_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw) 2230 { 2231 int port; 2232 2233 for (port = 0; port < hw->ptp.num_lports; port++) { 2234 u64 tstamp_ready; 2235 int err; 2236 2237 err = ice_get_phy_tx_tstamp_ready(hw, port, &tstamp_ready); 2238 if (err) 2239 return err; 2240 2241 if (tstamp_ready) 2242 return 1; 2243 } 2244 2245 return 0; 2246 } 2247 2248 /** 2249 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status 2250 * @hw: pointer to the HW struct 2251 * @ts_status: the timestamp mask pointer 2252 * 2253 * Read the PHY Tx timestamp status mask indicating which ports have Tx 2254 * timestamps available. 2255 * 2256 * Return: 2257 * * %0 - success 2258 * * %other - failed to read from PHY 2259 */ 2260 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) 2261 { 2262 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; 2263 u8 phy, mask; 2264 u32 status; 2265 2266 mask = (1 << hw->ptp.ports_per_phy) - 1; 2267 *ts_status = 0; 2268 2269 for (phy = 0; phy < params->num_phys; phy++) { 2270 u8 port; 2271 int err; 2272 2273 /* ice_read_phy_eth56g expects a port index, so use the first 2274 * port of the PHY 2275 */ 2276 port = phy * hw->ptp.ports_per_phy; 2277 2278 err = ice_read_phy_eth56g(hw, port, PHY_PTP_INT_STATUS, &status); 2279 if (err) 2280 return err; 2281 2282 *ts_status |= (status & mask) << port; 2283 } 2284 2285 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status); 2286 2287 return 0; 2288 } 2289 2290 /** 2291 * ice_ptp_phy_soft_reset_eth56g - Perform a PHY soft reset on ETH56G 2292 * @hw: pointer to the HW structure 2293 * @port: PHY port number 2294 * 2295 * Trigger a soft reset of the ETH56G PHY by toggling the soft reset 2296 * bit in the PHY global register. The reset sequence consists of: 2297 * 1. Clearing the soft reset bit 2298 * 2. Asserting the soft reset bit 2299 * 3. Clearing the soft reset bit again 2300 * 2301 * Short delays are inserted between each step to allow the hardware 2302 * to settle. This provides a controlled way to reinitialize the PHY 2303 * without requiring a full device reset. 2304 * 2305 * Return: 0 on success, or a negative error code on failure when 2306 * reading or writing the PHY register. 2307 */ 2308 int ice_ptp_phy_soft_reset_eth56g(struct ice_hw *hw, u8 port) 2309 { 2310 u32 global_val; 2311 int err; 2312 2313 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, &global_val); 2314 if (err) { 2315 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_REG_GLOBAL for port %d, err %d\n", 2316 port, err); 2317 return err; 2318 } 2319 2320 global_val &= ~PHY_REG_GLOBAL_SOFT_RESET_M; 2321 ice_debug(hw, ICE_DBG_PTP, "Clearing soft reset bit for port %d, val: 0x%x\n", 2322 port, global_val); 2323 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val); 2324 if (err) { 2325 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_REG_GLOBAL for port %d, err %d\n", 2326 port, err); 2327 return err; 2328 } 2329 2330 usleep_range(5000, 6000); 2331 2332 global_val |= PHY_REG_GLOBAL_SOFT_RESET_M; 2333 ice_debug(hw, ICE_DBG_PTP, "Set soft reset bit for port %d, val: 0x%x\n", 2334 port, global_val); 2335 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val); 2336 if (err) { 2337 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_REG_GLOBAL for port %d, err %d\n", 2338 port, err); 2339 return err; 2340 } 2341 usleep_range(5000, 6000); 2342 2343 global_val &= ~PHY_REG_GLOBAL_SOFT_RESET_M; 2344 ice_debug(hw, ICE_DBG_PTP, "Clear soft reset bit for port %d, val: 0x%x\n", 2345 port, global_val); 2346 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val); 2347 if (err) 2348 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_REG_GLOBAL for port %d, err %d\n", 2349 port, err); 2350 return err; 2351 } 2352 2353 /** 2354 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register 2355 * @hw: pointer to the HW struct 2356 * @port: the PHY port to read from 2357 * @tstamp_ready: contents of the Tx memory status register 2358 * 2359 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in 2360 * the PHY are ready. A set bit means the corresponding timestamp is valid and 2361 * ready to be captured from the PHY timestamp block. 2362 * 2363 * Return: 2364 * * %0 - success 2365 * * %other - failed to read from PHY 2366 */ 2367 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, 2368 u64 *tstamp_ready) 2369 { 2370 int err; 2371 2372 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 2373 tstamp_ready); 2374 if (err) { 2375 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n", 2376 port, err); 2377 return err; 2378 } 2379 2380 return 0; 2381 } 2382 2383 /** 2384 * ice_ptp_init_phy_e825 - initialize PHY parameters 2385 * @hw: pointer to the HW struct 2386 */ 2387 static void ice_ptp_init_phy_e825(struct ice_hw *hw) 2388 { 2389 struct ice_ptp_hw *ptp = &hw->ptp; 2390 struct ice_eth56g_params *params; 2391 2392 params = &ptp->phy.eth56g; 2393 params->onestep_ena = false; 2394 params->peer_delay = 0; 2395 params->sfd_ena = false; 2396 params->num_phys = 2; 2397 ptp->ports_per_phy = 4; 2398 ptp->num_lports = params->num_phys * ptp->ports_per_phy; 2399 } 2400 2401 /* E822 family functions 2402 * 2403 * The following functions operate on the E822 family of devices. 2404 */ 2405 2406 /** 2407 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access 2408 * @hw: pointer to the HW struct 2409 * @msg: the PHY message buffer to fill in 2410 * @port: the port to access 2411 * @offset: the register offset 2412 */ 2413 static void ice_fill_phy_msg_e82x(struct ice_hw *hw, 2414 struct ice_sbq_msg_input *msg, u8 port, 2415 u16 offset) 2416 { 2417 int phy_port, quadtype; 2418 2419 phy_port = port % hw->ptp.ports_per_phy; 2420 quadtype = ICE_GET_QUAD_NUM(port) % 2421 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); 2422 2423 if (quadtype == 0) { 2424 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 2425 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 2426 } else { 2427 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 2428 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 2429 } 2430 2431 msg->dest_dev = ice_sbq_dev_phy_0; 2432 } 2433 2434 /** 2435 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register 2436 * @low_addr: the low address to check 2437 * @high_addr: on return, contains the high address of the 64bit register 2438 * 2439 * Checks if the provided low address is one of the known 64bit PHY values 2440 * represented as two 32bit registers. If it is, return the appropriate high 2441 * register offset to use. 2442 */ 2443 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2444 { 2445 switch (low_addr) { 2446 case P_REG_PAR_PCS_TX_OFFSET_L: 2447 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 2448 return true; 2449 case P_REG_PAR_PCS_RX_OFFSET_L: 2450 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 2451 return true; 2452 case P_REG_PAR_TX_TIME_L: 2453 *high_addr = P_REG_PAR_TX_TIME_U; 2454 return true; 2455 case P_REG_PAR_RX_TIME_L: 2456 *high_addr = P_REG_PAR_RX_TIME_U; 2457 return true; 2458 case P_REG_TOTAL_TX_OFFSET_L: 2459 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 2460 return true; 2461 case P_REG_TOTAL_RX_OFFSET_L: 2462 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 2463 return true; 2464 case P_REG_UIX66_10G_40G_L: 2465 *high_addr = P_REG_UIX66_10G_40G_U; 2466 return true; 2467 case P_REG_UIX66_25G_100G_L: 2468 *high_addr = P_REG_UIX66_25G_100G_U; 2469 return true; 2470 case P_REG_TX_CAPTURE_L: 2471 *high_addr = P_REG_TX_CAPTURE_U; 2472 return true; 2473 case P_REG_RX_CAPTURE_L: 2474 *high_addr = P_REG_RX_CAPTURE_U; 2475 return true; 2476 case P_REG_TX_TIMER_INC_PRE_L: 2477 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 2478 return true; 2479 case P_REG_RX_TIMER_INC_PRE_L: 2480 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 2481 return true; 2482 default: 2483 return false; 2484 } 2485 } 2486 2487 /** 2488 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register 2489 * @low_addr: the low address to check 2490 * @high_addr: on return, contains the high address of the 40bit value 2491 * 2492 * Checks if the provided low address is one of the known 40bit PHY values 2493 * split into two registers with the lower 8 bits in the low register and the 2494 * upper 32 bits in the high register. If it is, return the appropriate high 2495 * register offset to use. 2496 */ 2497 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2498 { 2499 switch (low_addr) { 2500 case P_REG_TIMETUS_L: 2501 *high_addr = P_REG_TIMETUS_U; 2502 return true; 2503 case P_REG_PAR_RX_TUS_L: 2504 *high_addr = P_REG_PAR_RX_TUS_U; 2505 return true; 2506 case P_REG_PAR_TX_TUS_L: 2507 *high_addr = P_REG_PAR_TX_TUS_U; 2508 return true; 2509 case P_REG_PCS_RX_TUS_L: 2510 *high_addr = P_REG_PCS_RX_TUS_U; 2511 return true; 2512 case P_REG_PCS_TX_TUS_L: 2513 *high_addr = P_REG_PCS_TX_TUS_U; 2514 return true; 2515 case P_REG_DESK_PAR_RX_TUS_L: 2516 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 2517 return true; 2518 case P_REG_DESK_PAR_TX_TUS_L: 2519 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 2520 return true; 2521 case P_REG_DESK_PCS_RX_TUS_L: 2522 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 2523 return true; 2524 case P_REG_DESK_PCS_TX_TUS_L: 2525 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 2526 return true; 2527 default: 2528 return false; 2529 } 2530 } 2531 2532 /** 2533 * ice_read_phy_reg_e82x - Read a PHY register 2534 * @hw: pointer to the HW struct 2535 * @port: PHY port to read from 2536 * @offset: PHY register offset to read 2537 * @val: on return, the contents read from the PHY 2538 * 2539 * Read a PHY register for the given port over the device sideband queue. 2540 */ 2541 static int 2542 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 2543 { 2544 struct ice_sbq_msg_input msg = {0}; 2545 int err; 2546 2547 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2548 msg.opcode = ice_sbq_msg_rd; 2549 2550 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2551 if (err) { 2552 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2553 err); 2554 return err; 2555 } 2556 2557 *val = msg.data; 2558 2559 return 0; 2560 } 2561 2562 /** 2563 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers 2564 * @hw: pointer to the HW struct 2565 * @port: PHY port to read from 2566 * @low_addr: offset of the lower register to read from 2567 * @val: on return, the contents of the 64bit value from the PHY registers 2568 * 2569 * Reads the two registers associated with a 64bit value and returns it in the 2570 * val pointer. The offset always specifies the lower register offset to use. 2571 * The high offset is looked up. This function only operates on registers 2572 * known to be two parts of a 64bit value. 2573 */ 2574 static int 2575 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 2576 { 2577 u32 low, high; 2578 u16 high_addr; 2579 int err; 2580 2581 /* Only operate on registers known to be split into two 32bit 2582 * registers. 2583 */ 2584 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2585 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2586 low_addr); 2587 return -EINVAL; 2588 } 2589 2590 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low); 2591 if (err) { 2592 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 2593 low_addr, err); 2594 return err; 2595 } 2596 2597 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high); 2598 if (err) { 2599 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 2600 high_addr, err); 2601 return err; 2602 } 2603 2604 *val = (u64)high << 32 | low; 2605 2606 return 0; 2607 } 2608 2609 /** 2610 * ice_write_phy_reg_e82x - Write a PHY register 2611 * @hw: pointer to the HW struct 2612 * @port: PHY port to write to 2613 * @offset: PHY register offset to write 2614 * @val: The value to write to the register 2615 * 2616 * Write a PHY register for the given port over the device sideband queue. 2617 */ 2618 static int 2619 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val) 2620 { 2621 struct ice_sbq_msg_input msg = {0}; 2622 int err; 2623 2624 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2625 msg.opcode = ice_sbq_msg_wr; 2626 msg.data = val; 2627 2628 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2629 if (err) { 2630 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2631 err); 2632 return err; 2633 } 2634 2635 return 0; 2636 } 2637 2638 /** 2639 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY 2640 * @hw: pointer to the HW struct 2641 * @port: port to write to 2642 * @low_addr: offset of the low register 2643 * @val: 40b value to write 2644 * 2645 * Write the provided 40b value to the two associated registers by splitting 2646 * it up into two chunks, the lower 8 bits and the upper 32 bits. 2647 */ 2648 static int 2649 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 2650 { 2651 u32 low, high; 2652 u16 high_addr; 2653 int err; 2654 2655 /* Only operate on registers known to be split into a lower 8 bit 2656 * register and an upper 32 bit register. 2657 */ 2658 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) { 2659 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 2660 low_addr); 2661 return -EINVAL; 2662 } 2663 low = FIELD_GET(P_REG_40B_LOW_M, val); 2664 high = (u32)(val >> P_REG_40B_HIGH_S); 2665 2666 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 2667 if (err) { 2668 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 2669 low_addr, err); 2670 return err; 2671 } 2672 2673 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 2674 if (err) { 2675 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 2676 high_addr, err); 2677 return err; 2678 } 2679 2680 return 0; 2681 } 2682 2683 /** 2684 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers 2685 * @hw: pointer to the HW struct 2686 * @port: PHY port to read from 2687 * @low_addr: offset of the lower register to read from 2688 * @val: the contents of the 64bit value to write to PHY 2689 * 2690 * Write the 64bit value to the two associated 32bit PHY registers. The offset 2691 * is always specified as the lower register, and the high address is looked 2692 * up. This function only operates on registers known to be two parts of 2693 * a 64bit value. 2694 */ 2695 static int 2696 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 2697 { 2698 u32 low, high; 2699 u16 high_addr; 2700 int err; 2701 2702 /* Only operate on registers known to be split into two 32bit 2703 * registers. 2704 */ 2705 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2706 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2707 low_addr); 2708 return -EINVAL; 2709 } 2710 2711 low = lower_32_bits(val); 2712 high = upper_32_bits(val); 2713 2714 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 2715 if (err) { 2716 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 2717 low_addr, err); 2718 return err; 2719 } 2720 2721 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 2722 if (err) { 2723 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 2724 high_addr, err); 2725 return err; 2726 } 2727 2728 return 0; 2729 } 2730 2731 /** 2732 * ice_fill_quad_msg_e82x - Fill message data for quad register access 2733 * @hw: pointer to the HW struct 2734 * @msg: the PHY message buffer to fill in 2735 * @quad: the quad to access 2736 * @offset: the register offset 2737 * 2738 * Fill a message buffer for accessing a register in a quad shared between 2739 * multiple PHYs. 2740 * 2741 * Return: 2742 * * %0 - OK 2743 * * %-EINVAL - invalid quad number 2744 */ 2745 static int ice_fill_quad_msg_e82x(struct ice_hw *hw, 2746 struct ice_sbq_msg_input *msg, u8 quad, 2747 u16 offset) 2748 { 2749 u32 addr; 2750 2751 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) 2752 return -EINVAL; 2753 2754 msg->dest_dev = ice_sbq_dev_phy_0; 2755 2756 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) 2757 addr = Q_0_BASE + offset; 2758 else 2759 addr = Q_1_BASE + offset; 2760 2761 msg->msg_addr_low = lower_16_bits(addr); 2762 msg->msg_addr_high = upper_16_bits(addr); 2763 2764 return 0; 2765 } 2766 2767 /** 2768 * ice_read_quad_reg_e82x - Read a PHY quad register 2769 * @hw: pointer to the HW struct 2770 * @quad: quad to read from 2771 * @offset: quad register offset to read 2772 * @val: on return, the contents read from the quad 2773 * 2774 * Read a quad register over the device sideband queue. Quad registers are 2775 * shared between multiple PHYs. 2776 */ 2777 int 2778 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 2779 { 2780 struct ice_sbq_msg_input msg = {0}; 2781 int err; 2782 2783 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 2784 if (err) 2785 return err; 2786 2787 msg.opcode = ice_sbq_msg_rd; 2788 2789 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2790 if (err) { 2791 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2792 err); 2793 return err; 2794 } 2795 2796 *val = msg.data; 2797 2798 return 0; 2799 } 2800 2801 /** 2802 * ice_write_quad_reg_e82x - Write a PHY quad register 2803 * @hw: pointer to the HW struct 2804 * @quad: quad to write to 2805 * @offset: quad register offset to write 2806 * @val: The value to write to the register 2807 * 2808 * Write a quad register over the device sideband queue. Quad registers are 2809 * shared between multiple PHYs. 2810 */ 2811 int 2812 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 2813 { 2814 struct ice_sbq_msg_input msg = {0}; 2815 int err; 2816 2817 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 2818 if (err) 2819 return err; 2820 2821 msg.opcode = ice_sbq_msg_wr; 2822 msg.data = val; 2823 2824 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2825 if (err) { 2826 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2827 err); 2828 return err; 2829 } 2830 2831 return 0; 2832 } 2833 2834 /** 2835 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block 2836 * @hw: pointer to the HW struct 2837 * @quad: the quad to read from 2838 * @idx: the timestamp index to read 2839 * @tstamp: on return, the 40bit timestamp value 2840 * 2841 * Read a 40bit timestamp value out of the two associated registers in the 2842 * quad memory block that is shared between the internal PHYs of the E822 2843 * family of devices. 2844 */ 2845 static int 2846 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 2847 { 2848 u16 lo_addr, hi_addr; 2849 u32 lo, hi; 2850 int err; 2851 2852 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 2853 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 2854 2855 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo); 2856 if (err) { 2857 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 2858 err); 2859 return err; 2860 } 2861 2862 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); 2863 if (err) { 2864 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 2865 err); 2866 return err; 2867 } 2868 2869 /* For E822 based internal PHYs, the timestamp is reported with the 2870 * lower 8 bits in the low register, and the upper 32 bits in the high 2871 * register. 2872 */ 2873 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 2874 FIELD_PREP(PHY_40B_LOW_M, lo); 2875 2876 return 0; 2877 } 2878 2879 /** 2880 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block 2881 * @hw: pointer to the HW struct 2882 * @quad: the quad to read from 2883 * @idx: the timestamp index to reset 2884 * 2885 * Read the timestamp out of the quad to clear its timestamp status bit from 2886 * the PHY quad block that is shared between the internal PHYs of the E822 2887 * devices. 2888 * 2889 * Note that unlike E810, software cannot directly write to the quad memory 2890 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function 2891 * to determine which timestamps are valid. Reading a timestamp auto-clears 2892 * the valid bit. 2893 * 2894 * To directly clear the contents of the timestamp block entirely, discarding 2895 * all timestamp data at once, software should instead use 2896 * ice_ptp_reset_ts_memory_quad_e82x(). 2897 * 2898 * This function should only be called on an idx whose bit is set according to 2899 * ice_get_phy_tx_tstamp_ready(). 2900 */ 2901 static int 2902 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) 2903 { 2904 u64 unused_tstamp; 2905 int err; 2906 2907 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp); 2908 if (err) { 2909 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", 2910 quad, idx, err); 2911 return err; 2912 } 2913 2914 return 0; 2915 } 2916 2917 /** 2918 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block 2919 * @hw: pointer to the HW struct 2920 * @quad: the quad to read from 2921 * 2922 * Clear all timestamps from the PHY quad block that is shared between the 2923 * internal PHYs on the E822 devices. 2924 */ 2925 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) 2926 { 2927 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); 2928 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); 2929 } 2930 2931 /** 2932 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks 2933 * @hw: pointer to the HW struct 2934 */ 2935 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw) 2936 { 2937 unsigned int quad; 2938 2939 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) 2940 ice_ptp_reset_ts_memory_quad_e82x(hw, quad); 2941 } 2942 2943 /** 2944 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 2945 * @hw: pointer to the HW struct 2946 * 2947 * Set the window length used for the vernier port calibration process. 2948 */ 2949 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 2950 { 2951 u8 port; 2952 2953 for (port = 0; port < hw->ptp.num_lports; port++) { 2954 int err; 2955 2956 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL, 2957 PTP_VERNIER_WL); 2958 if (err) { 2959 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 2960 port, err); 2961 return err; 2962 } 2963 } 2964 2965 return 0; 2966 } 2967 2968 /** 2969 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization 2970 * @hw: pointer to HW struct 2971 * 2972 * Perform PHC initialization steps specific to E822 devices. 2973 */ 2974 static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 2975 { 2976 u32 val; 2977 2978 /* Enable reading switch and PHY registers over the sideband queue */ 2979 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 2980 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 2981 val = rd32(hw, PF_SB_REM_DEV_CTL); 2982 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0); 2983 wr32(hw, PF_SB_REM_DEV_CTL, val); 2984 2985 /* Set window length for all the ports */ 2986 return ice_ptp_set_vernier_wl(hw); 2987 } 2988 2989 /** 2990 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time 2991 * @hw: pointer to the HW struct 2992 * @time: Time to initialize the PHY port clocks to 2993 * 2994 * Program the PHY port registers with a new initial time value. The port 2995 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 2996 * command. The time value is the upper 32 bits of the PHY timer, usually in 2997 * units of nominal nanoseconds. 2998 */ 2999 static int 3000 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time) 3001 { 3002 u64 phy_time; 3003 u8 port; 3004 int err; 3005 3006 /* The time represents the upper 32 bits of the PHY timer, so we need 3007 * to shift to account for this when programming. 3008 */ 3009 phy_time = (u64)time << 32; 3010 3011 for (port = 0; port < hw->ptp.num_lports; port++) { 3012 /* Tx case */ 3013 err = ice_write_64b_phy_reg_e82x(hw, port, 3014 P_REG_TX_TIMER_INC_PRE_L, 3015 phy_time); 3016 if (err) 3017 goto exit_err; 3018 3019 /* Rx case */ 3020 err = ice_write_64b_phy_reg_e82x(hw, port, 3021 P_REG_RX_TIMER_INC_PRE_L, 3022 phy_time); 3023 if (err) 3024 goto exit_err; 3025 } 3026 3027 return 0; 3028 3029 exit_err: 3030 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 3031 port, err); 3032 3033 return err; 3034 } 3035 3036 /** 3037 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust 3038 * @hw: pointer to HW struct 3039 * @port: Port number to be programmed 3040 * @time: time in cycles to adjust the port Tx and Rx clocks 3041 * 3042 * Program the port for an atomic adjustment by writing the Tx and Rx timer 3043 * registers. The atomic adjustment won't be completed until the driver issues 3044 * an ICE_PTP_ADJ_TIME command. 3045 * 3046 * Note that time is not in units of nanoseconds. It is in clock time 3047 * including the lower sub-nanosecond portion of the port timer. 3048 * 3049 * Negative adjustments are supported using 2s complement arithmetic. 3050 */ 3051 static int 3052 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time) 3053 { 3054 u32 l_time, u_time; 3055 int err; 3056 3057 l_time = lower_32_bits(time); 3058 u_time = upper_32_bits(time); 3059 3060 /* Tx case */ 3061 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L, 3062 l_time); 3063 if (err) 3064 goto exit_err; 3065 3066 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U, 3067 u_time); 3068 if (err) 3069 goto exit_err; 3070 3071 /* Rx case */ 3072 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L, 3073 l_time); 3074 if (err) 3075 goto exit_err; 3076 3077 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U, 3078 u_time); 3079 if (err) 3080 goto exit_err; 3081 3082 return 0; 3083 3084 exit_err: 3085 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 3086 port, err); 3087 return err; 3088 } 3089 3090 /** 3091 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment 3092 * @hw: pointer to HW struct 3093 * @adj: adjustment in nanoseconds 3094 * 3095 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 3096 * Tx and Rx port registers. The actual adjustment is completed by issuing an 3097 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 3098 */ 3099 static int 3100 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj) 3101 { 3102 s64 cycles; 3103 u8 port; 3104 3105 /* The port clock supports adjustment of the sub-nanosecond portion of 3106 * the clock. We shift the provided adjustment in nanoseconds to 3107 * calculate the appropriate adjustment to program into the PHY ports. 3108 */ 3109 if (adj > 0) 3110 cycles = (s64)adj << 32; 3111 else 3112 cycles = -(((s64)-adj) << 32); 3113 3114 for (port = 0; port < hw->ptp.num_lports; port++) { 3115 int err; 3116 3117 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles); 3118 if (err) 3119 return err; 3120 } 3121 3122 return 0; 3123 } 3124 3125 /** 3126 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment 3127 * @hw: pointer to HW struct 3128 * @incval: new increment value to prepare 3129 * 3130 * Prepare each of the PHY ports for a new increment value by programming the 3131 * port's TIMETUS registers. The new increment value will be updated after 3132 * issuing an ICE_PTP_INIT_INCVAL command. 3133 */ 3134 static int 3135 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval) 3136 { 3137 int err; 3138 u8 port; 3139 3140 for (port = 0; port < hw->ptp.num_lports; port++) { 3141 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, 3142 incval); 3143 if (err) 3144 goto exit_err; 3145 } 3146 3147 return 0; 3148 3149 exit_err: 3150 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 3151 port, err); 3152 3153 return err; 3154 } 3155 3156 /** 3157 * ice_ptp_read_port_capture - Read a port's local time capture 3158 * @hw: pointer to HW struct 3159 * @port: Port number to read 3160 * @tx_ts: on return, the Tx port time capture 3161 * @rx_ts: on return, the Rx port time capture 3162 * 3163 * Read the port's Tx and Rx local time capture values. 3164 * 3165 * Note this has no equivalent for the E810 devices. 3166 */ 3167 static int 3168 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 3169 { 3170 int err; 3171 3172 /* Tx case */ 3173 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 3174 if (err) { 3175 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 3176 err); 3177 return err; 3178 } 3179 3180 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 3181 (unsigned long long)*tx_ts); 3182 3183 /* Rx case */ 3184 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 3185 if (err) { 3186 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 3187 err); 3188 return err; 3189 } 3190 3191 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 3192 (unsigned long long)*rx_ts); 3193 3194 return 0; 3195 } 3196 3197 /** 3198 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command 3199 * @hw: pointer to HW struct 3200 * @port: Port to which cmd has to be sent 3201 * @cmd: Command to be sent to the port 3202 * 3203 * Prepare the requested port for an upcoming timer sync command. 3204 * 3205 * Note there is no equivalent of this operation on E810, as that device 3206 * always handles all external PHYs internally. 3207 * 3208 * Return: 3209 * * %0 - success 3210 * * %other - failed to write to PHY 3211 */ 3212 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port, 3213 enum ice_ptp_tmr_cmd cmd) 3214 { 3215 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 3216 int err; 3217 3218 /* Tx case */ 3219 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val); 3220 if (err) { 3221 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 3222 err); 3223 return err; 3224 } 3225 3226 /* Rx case */ 3227 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, 3228 val | TS_CMD_RX_TYPE); 3229 if (err) { 3230 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 3231 err); 3232 return err; 3233 } 3234 3235 return 0; 3236 } 3237 3238 /* E822 Vernier calibration functions 3239 * 3240 * The following functions are used as part of the vernier calibration of 3241 * a port. This calibration increases the precision of the timestamps on the 3242 * port. 3243 */ 3244 3245 /** 3246 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode 3247 * @hw: pointer to HW struct 3248 * @port: the port to read from 3249 * @link_out: if non-NULL, holds link speed on success 3250 * @fec_out: if non-NULL, holds FEC algorithm on success 3251 * 3252 * Read the serdes data for the PHY port and extract the link speed and FEC 3253 * algorithm. 3254 */ 3255 static int 3256 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port, 3257 enum ice_ptp_link_spd *link_out, 3258 enum ice_ptp_fec_mode *fec_out) 3259 { 3260 enum ice_ptp_link_spd link; 3261 enum ice_ptp_fec_mode fec; 3262 u32 serdes; 3263 int err; 3264 3265 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes); 3266 if (err) { 3267 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 3268 return err; 3269 } 3270 3271 /* Determine the FEC algorithm */ 3272 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 3273 3274 serdes &= P_REG_LINK_SPEED_SERDES_M; 3275 3276 /* Determine the link speed */ 3277 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 3278 switch (serdes) { 3279 case ICE_PTP_SERDES_25G: 3280 link = ICE_PTP_LNK_SPD_25G_RS; 3281 break; 3282 case ICE_PTP_SERDES_50G: 3283 link = ICE_PTP_LNK_SPD_50G_RS; 3284 break; 3285 case ICE_PTP_SERDES_100G: 3286 link = ICE_PTP_LNK_SPD_100G_RS; 3287 break; 3288 default: 3289 return -EIO; 3290 } 3291 } else { 3292 switch (serdes) { 3293 case ICE_PTP_SERDES_1G: 3294 link = ICE_PTP_LNK_SPD_1G; 3295 break; 3296 case ICE_PTP_SERDES_10G: 3297 link = ICE_PTP_LNK_SPD_10G; 3298 break; 3299 case ICE_PTP_SERDES_25G: 3300 link = ICE_PTP_LNK_SPD_25G; 3301 break; 3302 case ICE_PTP_SERDES_40G: 3303 link = ICE_PTP_LNK_SPD_40G; 3304 break; 3305 case ICE_PTP_SERDES_50G: 3306 link = ICE_PTP_LNK_SPD_50G; 3307 break; 3308 default: 3309 return -EIO; 3310 } 3311 } 3312 3313 if (link_out) 3314 *link_out = link; 3315 if (fec_out) 3316 *fec_out = fec; 3317 3318 return 0; 3319 } 3320 3321 /** 3322 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp 3323 * @hw: pointer to HW struct 3324 * @port: to configure the quad for 3325 */ 3326 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port) 3327 { 3328 enum ice_ptp_link_spd link_spd; 3329 int err; 3330 u32 val; 3331 u8 quad; 3332 3333 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL); 3334 if (err) { 3335 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 3336 err); 3337 return; 3338 } 3339 3340 quad = ICE_GET_QUAD_NUM(port); 3341 3342 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 3343 if (err) { 3344 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 3345 err); 3346 return; 3347 } 3348 3349 if (link_spd >= ICE_PTP_LNK_SPD_40G) 3350 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3351 else 3352 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3353 3354 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 3355 if (err) { 3356 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 3357 err); 3358 return; 3359 } 3360 } 3361 3362 /** 3363 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822 3364 * @hw: pointer to the HW structure 3365 * @port: the port to configure 3366 * 3367 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 3368 * hardware clock time units (TUs). That is, determine the number of TUs per 3369 * serdes unit interval, and program the UIX registers with this conversion. 3370 * 3371 * This conversion is used as part of the calibration process when determining 3372 * the additional error of a timestamp vs the real time of transmission or 3373 * receipt of the packet. 3374 * 3375 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 3376 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 3377 * 3378 * To calculate the conversion ratio, we use the following facts: 3379 * 3380 * a) the clock frequency in Hz (cycles per second) 3381 * b) the number of TUs per cycle (the increment value of the clock) 3382 * c) 1 second per 1 billion nanoseconds 3383 * d) the duration of 66 UIs in nanoseconds 3384 * 3385 * Given these facts, we can use the following table to work out what ratios 3386 * to multiply in order to get the number of TUs per 66 UIs: 3387 * 3388 * cycles | 1 second | incval (TUs) | nanoseconds 3389 * -------+--------------+--------------+------------- 3390 * second | 1 billion ns | cycle | 66 UIs 3391 * 3392 * To perform the multiplication using integers without too much loss of 3393 * precision, we can take use the following equation: 3394 * 3395 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 3396 * 3397 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 3398 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 3399 * 3400 * The increment value has a maximum expected range of about 34 bits, while 3401 * the frequency value is about 29 bits. Multiplying these values shouldn't 3402 * overflow the 64 bits. However, we must then further multiply them again by 3403 * the Serdes unit interval duration. To avoid overflow here, we split the 3404 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 3405 * a divide by 390,625,000. This does lose some precision, but avoids 3406 * miscalculation due to arithmetic overflow. 3407 */ 3408 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port) 3409 { 3410 u64 cur_freq, clk_incval, tu_per_sec, uix; 3411 int err; 3412 3413 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3414 clk_incval = ice_ptp_read_src_incval(hw); 3415 3416 /* Calculate TUs per second divided by 256 */ 3417 tu_per_sec = (cur_freq * clk_incval) >> 8; 3418 3419 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 3420 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 3421 3422 /* Program the 10Gb/40Gb conversion ratio */ 3423 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 3424 3425 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L, 3426 uix); 3427 if (err) { 3428 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 3429 err); 3430 return err; 3431 } 3432 3433 /* Program the 25Gb/100Gb conversion ratio */ 3434 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 3435 3436 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L, 3437 uix); 3438 if (err) { 3439 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 3440 err); 3441 return err; 3442 } 3443 3444 return 0; 3445 } 3446 3447 /** 3448 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle 3449 * @hw: pointer to the HW struct 3450 * @port: port to configure 3451 * 3452 * Configure the number of TUs for the PAR and PCS clocks used as part of the 3453 * timestamp calibration process. This depends on the link speed, as the PHY 3454 * uses different markers depending on the speed. 3455 * 3456 * 1Gb/10Gb/25Gb: 3457 * - Tx/Rx PAR/PCS markers 3458 * 3459 * 25Gb RS: 3460 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3461 * 3462 * 40Gb/50Gb: 3463 * - Tx/Rx PAR/PCS markers 3464 * - Rx Deskew PAR/PCS markers 3465 * 3466 * 50G RS and 100GB RS: 3467 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3468 * - Rx Deskew PAR/PCS markers 3469 * - Tx PAR/PCS markers 3470 * 3471 * To calculate the conversion, we use the PHC clock frequency (cycles per 3472 * second), the increment value (TUs per cycle), and the related PHY clock 3473 * frequency to calculate the TUs per unit of the PHY link clock. The 3474 * following table shows how the units convert: 3475 * 3476 * cycles | TUs | second 3477 * -------+-------+-------- 3478 * second | cycle | cycles 3479 * 3480 * For each conversion register, look up the appropriate frequency from the 3481 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 3482 * this to the appropriate register, preparing hardware to perform timestamp 3483 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 3484 * in order to calibrate for the internal PHY delays. 3485 * 3486 * Note that the increment value ranges up to ~34 bits, and the clock 3487 * frequency is ~29 bits, so multiplying them together should fit within the 3488 * 64 bit arithmetic. 3489 */ 3490 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port) 3491 { 3492 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 3493 enum ice_ptp_link_spd link_spd; 3494 enum ice_ptp_fec_mode fec_mode; 3495 int err; 3496 3497 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3498 if (err) 3499 return err; 3500 3501 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3502 clk_incval = ice_ptp_read_src_incval(hw); 3503 3504 /* Calculate TUs per cycle of the PHC clock */ 3505 tu_per_sec = cur_freq * clk_incval; 3506 3507 /* For each PHY conversion register, look up the appropriate link 3508 * speed frequency and determine the TUs per that clock's cycle time. 3509 * Split this into a high and low value and then program the 3510 * appropriate register. If that link speed does not use the 3511 * associated register, write zeros to clear it instead. 3512 */ 3513 3514 /* P_REG_PAR_TX_TUS */ 3515 if (e822_vernier[link_spd].tx_par_clk) 3516 phy_tus = div_u64(tu_per_sec, 3517 e822_vernier[link_spd].tx_par_clk); 3518 else 3519 phy_tus = 0; 3520 3521 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L, 3522 phy_tus); 3523 if (err) 3524 return err; 3525 3526 /* P_REG_PAR_RX_TUS */ 3527 if (e822_vernier[link_spd].rx_par_clk) 3528 phy_tus = div_u64(tu_per_sec, 3529 e822_vernier[link_spd].rx_par_clk); 3530 else 3531 phy_tus = 0; 3532 3533 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L, 3534 phy_tus); 3535 if (err) 3536 return err; 3537 3538 /* P_REG_PCS_TX_TUS */ 3539 if (e822_vernier[link_spd].tx_pcs_clk) 3540 phy_tus = div_u64(tu_per_sec, 3541 e822_vernier[link_spd].tx_pcs_clk); 3542 else 3543 phy_tus = 0; 3544 3545 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L, 3546 phy_tus); 3547 if (err) 3548 return err; 3549 3550 /* P_REG_PCS_RX_TUS */ 3551 if (e822_vernier[link_spd].rx_pcs_clk) 3552 phy_tus = div_u64(tu_per_sec, 3553 e822_vernier[link_spd].rx_pcs_clk); 3554 else 3555 phy_tus = 0; 3556 3557 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L, 3558 phy_tus); 3559 if (err) 3560 return err; 3561 3562 /* P_REG_DESK_PAR_TX_TUS */ 3563 if (e822_vernier[link_spd].tx_desk_rsgb_par) 3564 phy_tus = div_u64(tu_per_sec, 3565 e822_vernier[link_spd].tx_desk_rsgb_par); 3566 else 3567 phy_tus = 0; 3568 3569 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L, 3570 phy_tus); 3571 if (err) 3572 return err; 3573 3574 /* P_REG_DESK_PAR_RX_TUS */ 3575 if (e822_vernier[link_spd].rx_desk_rsgb_par) 3576 phy_tus = div_u64(tu_per_sec, 3577 e822_vernier[link_spd].rx_desk_rsgb_par); 3578 else 3579 phy_tus = 0; 3580 3581 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L, 3582 phy_tus); 3583 if (err) 3584 return err; 3585 3586 /* P_REG_DESK_PCS_TX_TUS */ 3587 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 3588 phy_tus = div_u64(tu_per_sec, 3589 e822_vernier[link_spd].tx_desk_rsgb_pcs); 3590 else 3591 phy_tus = 0; 3592 3593 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L, 3594 phy_tus); 3595 if (err) 3596 return err; 3597 3598 /* P_REG_DESK_PCS_RX_TUS */ 3599 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 3600 phy_tus = div_u64(tu_per_sec, 3601 e822_vernier[link_spd].rx_desk_rsgb_pcs); 3602 else 3603 phy_tus = 0; 3604 3605 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L, 3606 phy_tus); 3607 } 3608 3609 /** 3610 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port 3611 * @hw: pointer to the HW struct 3612 * @link_spd: the Link speed to calculate for 3613 * 3614 * Calculate the fixed offset due to known static latency data. 3615 */ 3616 static u64 3617 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3618 { 3619 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3620 3621 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3622 clk_incval = ice_ptp_read_src_incval(hw); 3623 3624 /* Calculate TUs per second */ 3625 tu_per_sec = cur_freq * clk_incval; 3626 3627 /* Calculate number of TUs to add for the fixed Tx latency. Since the 3628 * latency measurement is in 1/100th of a nanosecond, we need to 3629 * multiply by tu_per_sec and then divide by 1e11. This calculation 3630 * overflows 64 bit integer arithmetic, so break it up into two 3631 * divisions by 1e4 first then by 1e7. 3632 */ 3633 fixed_offset = div_u64(tu_per_sec, 10000); 3634 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 3635 fixed_offset = div_u64(fixed_offset, 10000000); 3636 3637 return fixed_offset; 3638 } 3639 3640 /** 3641 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset 3642 * @hw: pointer to the HW struct 3643 * @port: the PHY port to configure 3644 * 3645 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to 3646 * adjust Tx timestamps by. This is calculated by combining some known static 3647 * latency along with the Vernier offset computations done by hardware. 3648 * 3649 * This function will not return successfully until the Tx offset calculations 3650 * have been completed, which requires waiting until at least one packet has 3651 * been transmitted by the device. It is safe to call this function 3652 * periodically until calibration succeeds, as it will only program the offset 3653 * once. 3654 * 3655 * To avoid overflow, when calculating the offset based on the known static 3656 * latency values, we use measurements in 1/100th of a nanosecond, and divide 3657 * the TUs per second up front. This avoids overflow while allowing 3658 * calculation of the adjustment using integer arithmetic. 3659 * 3660 * Returns zero on success, -EBUSY if the hardware vernier offset 3661 * calibration has not completed, or another error code on failure. 3662 */ 3663 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port) 3664 { 3665 enum ice_ptp_link_spd link_spd; 3666 enum ice_ptp_fec_mode fec_mode; 3667 u64 total_offset, val; 3668 int err; 3669 u32 reg; 3670 3671 /* Nothing to do if we've already programmed the offset */ 3672 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®); 3673 if (err) { 3674 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", 3675 port, err); 3676 return err; 3677 } 3678 3679 if (reg) 3680 return 0; 3681 3682 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®); 3683 if (err) { 3684 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", 3685 port, err); 3686 return err; 3687 } 3688 3689 if (!(reg & P_REG_TX_OV_STATUS_OV_M)) 3690 return -EBUSY; 3691 3692 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3693 if (err) 3694 return err; 3695 3696 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd); 3697 3698 /* Read the first Vernier offset from the PHY register and add it to 3699 * the total offset. 3700 */ 3701 if (link_spd == ICE_PTP_LNK_SPD_1G || 3702 link_spd == ICE_PTP_LNK_SPD_10G || 3703 link_spd == ICE_PTP_LNK_SPD_25G || 3704 link_spd == ICE_PTP_LNK_SPD_25G_RS || 3705 link_spd == ICE_PTP_LNK_SPD_40G || 3706 link_spd == ICE_PTP_LNK_SPD_50G) { 3707 err = ice_read_64b_phy_reg_e82x(hw, port, 3708 P_REG_PAR_PCS_TX_OFFSET_L, 3709 &val); 3710 if (err) 3711 return err; 3712 3713 total_offset += val; 3714 } 3715 3716 /* For Tx, we only need to use the second Vernier offset for 3717 * multi-lane link speeds with RS-FEC. The lanes will always be 3718 * aligned. 3719 */ 3720 if (link_spd == ICE_PTP_LNK_SPD_50G_RS || 3721 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 3722 err = ice_read_64b_phy_reg_e82x(hw, port, 3723 P_REG_PAR_TX_TIME_L, 3724 &val); 3725 if (err) 3726 return err; 3727 3728 total_offset += val; 3729 } 3730 3731 /* Now that the total offset has been calculated, program it to the 3732 * PHY and indicate that the Tx offset is ready. After this, 3733 * timestamps will be enabled. 3734 */ 3735 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L, 3736 total_offset); 3737 if (err) 3738 return err; 3739 3740 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1); 3741 if (err) 3742 return err; 3743 3744 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n", 3745 port); 3746 3747 return 0; 3748 } 3749 3750 /** 3751 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx 3752 * @hw: pointer to the HW struct 3753 * @port: the PHY port to adjust for 3754 * @link_spd: the current link speed of the PHY 3755 * @fec_mode: the current FEC mode of the PHY 3756 * @pmd_adj: on return, the amount to adjust the Rx total offset by 3757 * 3758 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. 3759 * This varies by link speed and FEC mode. The value calculated accounts for 3760 * various delays caused when receiving a packet. 3761 */ 3762 static int 3763 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port, 3764 enum ice_ptp_link_spd link_spd, 3765 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) 3766 { 3767 u64 cur_freq, clk_incval, tu_per_sec, mult, adj; 3768 u8 pmd_align; 3769 u32 val; 3770 int err; 3771 3772 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val); 3773 if (err) { 3774 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n", 3775 err); 3776 return err; 3777 } 3778 3779 pmd_align = (u8)val; 3780 3781 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3782 clk_incval = ice_ptp_read_src_incval(hw); 3783 3784 /* Calculate TUs per second */ 3785 tu_per_sec = cur_freq * clk_incval; 3786 3787 /* The PMD alignment adjustment measurement depends on the link speed, 3788 * and whether FEC is enabled. For each link speed, the alignment 3789 * adjustment is calculated by dividing a value by the length of 3790 * a Time Unit in nanoseconds. 3791 * 3792 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8 3793 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33) 3794 * 10G w/FEC: align * 0.1 * 32/33 3795 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33) 3796 * 25G w/FEC: align * 0.4 * 32/33 3797 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33) 3798 * 40G w/FEC: align * 0.1 * 32/33 3799 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33) 3800 * 50G w/FEC: align * 0.8 * 32/33 3801 * 3802 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. 3803 * 3804 * To allow for calculating this value using integer arithmetic, we 3805 * instead start with the number of TUs per second, (inverse of the 3806 * length of a Time Unit in nanoseconds), multiply by a value based 3807 * on the PMD alignment register, and then divide by the right value 3808 * calculated based on the table above. To avoid integer overflow this 3809 * division is broken up into a step of dividing by 125 first. 3810 */ 3811 if (link_spd == ICE_PTP_LNK_SPD_1G) { 3812 if (pmd_align == 4) 3813 mult = 10; 3814 else 3815 mult = (pmd_align + 6) % 10; 3816 } else if (link_spd == ICE_PTP_LNK_SPD_10G || 3817 link_spd == ICE_PTP_LNK_SPD_25G || 3818 link_spd == ICE_PTP_LNK_SPD_40G || 3819 link_spd == ICE_PTP_LNK_SPD_50G) { 3820 /* If Clause 74 FEC, always calculate PMD adjust */ 3821 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74) 3822 mult = pmd_align; 3823 else 3824 mult = 0; 3825 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS || 3826 link_spd == ICE_PTP_LNK_SPD_50G_RS || 3827 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 3828 if (pmd_align < 17) 3829 mult = pmd_align + 40; 3830 else 3831 mult = pmd_align; 3832 } else { 3833 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", 3834 link_spd); 3835 mult = 0; 3836 } 3837 3838 /* In some cases, there's no need to adjust for the PMD alignment */ 3839 if (!mult) { 3840 *pmd_adj = 0; 3841 return 0; 3842 } 3843 3844 /* Calculate the adjustment by multiplying TUs per second by the 3845 * appropriate multiplier and divisor. To avoid overflow, we first 3846 * divide by 125, and then handle remaining divisor based on the link 3847 * speed pmd_adj_divisor value. 3848 */ 3849 adj = div_u64(tu_per_sec, 125); 3850 adj *= mult; 3851 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor); 3852 3853 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx 3854 * cycle count is necessary. 3855 */ 3856 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) { 3857 u64 cycle_adj; 3858 u8 rx_cycle; 3859 3860 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT, 3861 &val); 3862 if (err) { 3863 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", 3864 err); 3865 return err; 3866 } 3867 3868 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M; 3869 if (rx_cycle) { 3870 mult = (4 - rx_cycle) * 40; 3871 3872 cycle_adj = div_u64(tu_per_sec, 125); 3873 cycle_adj *= mult; 3874 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 3875 3876 adj += cycle_adj; 3877 } 3878 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) { 3879 u64 cycle_adj; 3880 u8 rx_cycle; 3881 3882 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT, 3883 &val); 3884 if (err) { 3885 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", 3886 err); 3887 return err; 3888 } 3889 3890 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M; 3891 if (rx_cycle) { 3892 mult = rx_cycle * 40; 3893 3894 cycle_adj = div_u64(tu_per_sec, 125); 3895 cycle_adj *= mult; 3896 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 3897 3898 adj += cycle_adj; 3899 } 3900 } 3901 3902 /* Return the calculated adjustment */ 3903 *pmd_adj = adj; 3904 3905 return 0; 3906 } 3907 3908 /** 3909 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port 3910 * @hw: pointer to HW struct 3911 * @link_spd: The Link speed to calculate for 3912 * 3913 * Determine the fixed Rx latency for a given link speed. 3914 */ 3915 static u64 3916 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3917 { 3918 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3919 3920 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3921 clk_incval = ice_ptp_read_src_incval(hw); 3922 3923 /* Calculate TUs per second */ 3924 tu_per_sec = cur_freq * clk_incval; 3925 3926 /* Calculate number of TUs to add for the fixed Rx latency. Since the 3927 * latency measurement is in 1/100th of a nanosecond, we need to 3928 * multiply by tu_per_sec and then divide by 1e11. This calculation 3929 * overflows 64 bit integer arithmetic, so break it up into two 3930 * divisions by 1e4 first then by 1e7. 3931 */ 3932 fixed_offset = div_u64(tu_per_sec, 10000); 3933 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 3934 fixed_offset = div_u64(fixed_offset, 10000000); 3935 3936 return fixed_offset; 3937 } 3938 3939 /** 3940 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset 3941 * @hw: pointer to the HW struct 3942 * @port: the PHY port to configure 3943 * 3944 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to 3945 * adjust Rx timestamps by. This combines calculations from the Vernier offset 3946 * measurements taken in hardware with some data about known fixed delay as 3947 * well as adjusting for multi-lane alignment delay. 3948 * 3949 * This function will not return successfully until the Rx offset calculations 3950 * have been completed, which requires waiting until at least one packet has 3951 * been received by the device. It is safe to call this function periodically 3952 * until calibration succeeds, as it will only program the offset once. 3953 * 3954 * This function must be called only after the offset registers are valid, 3955 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY 3956 * has measured the offset. 3957 * 3958 * To avoid overflow, when calculating the offset based on the known static 3959 * latency values, we use measurements in 1/100th of a nanosecond, and divide 3960 * the TUs per second up front. This avoids overflow while allowing 3961 * calculation of the adjustment using integer arithmetic. 3962 * 3963 * Returns zero on success, -EBUSY if the hardware vernier offset 3964 * calibration has not completed, or another error code on failure. 3965 */ 3966 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) 3967 { 3968 enum ice_ptp_link_spd link_spd; 3969 enum ice_ptp_fec_mode fec_mode; 3970 u64 total_offset, pmd, val; 3971 int err; 3972 u32 reg; 3973 3974 /* Nothing to do if we've already programmed the offset */ 3975 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®); 3976 if (err) { 3977 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", 3978 port, err); 3979 return err; 3980 } 3981 3982 if (reg) 3983 return 0; 3984 3985 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®); 3986 if (err) { 3987 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", 3988 port, err); 3989 return err; 3990 } 3991 3992 if (!(reg & P_REG_RX_OV_STATUS_OV_M)) 3993 return -EBUSY; 3994 3995 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3996 if (err) 3997 return err; 3998 3999 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd); 4000 4001 /* Read the first Vernier offset from the PHY register and add it to 4002 * the total offset. 4003 */ 4004 err = ice_read_64b_phy_reg_e82x(hw, port, 4005 P_REG_PAR_PCS_RX_OFFSET_L, 4006 &val); 4007 if (err) 4008 return err; 4009 4010 total_offset += val; 4011 4012 /* For Rx, all multi-lane link speeds include a second Vernier 4013 * calibration, because the lanes might not be aligned. 4014 */ 4015 if (link_spd == ICE_PTP_LNK_SPD_40G || 4016 link_spd == ICE_PTP_LNK_SPD_50G || 4017 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4018 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4019 err = ice_read_64b_phy_reg_e82x(hw, port, 4020 P_REG_PAR_RX_TIME_L, 4021 &val); 4022 if (err) 4023 return err; 4024 4025 total_offset += val; 4026 } 4027 4028 /* In addition, Rx must account for the PMD alignment */ 4029 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd); 4030 if (err) 4031 return err; 4032 4033 /* For RS-FEC, this adjustment adds delay, but for other modes, it 4034 * subtracts delay. 4035 */ 4036 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC) 4037 total_offset += pmd; 4038 else 4039 total_offset -= pmd; 4040 4041 /* Now that the total offset has been calculated, program it to the 4042 * PHY and indicate that the Rx offset is ready. After this, 4043 * timestamps will be enabled. 4044 */ 4045 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L, 4046 total_offset); 4047 if (err) 4048 return err; 4049 4050 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1); 4051 if (err) 4052 return err; 4053 4054 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n", 4055 port); 4056 4057 return 0; 4058 } 4059 4060 /** 4061 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers 4062 * @hw: pointer to the HW struct 4063 * 4064 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted 4065 * and received timestamps as invalid. 4066 * 4067 * Return: 0 on success, other error codes when failed to write to PHY 4068 */ 4069 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw) 4070 { 4071 u8 port; 4072 4073 for (port = 0; port < hw->ptp.num_lports; port++) { 4074 int err; 4075 4076 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4077 if (err) { 4078 dev_warn(ice_hw_to_dev(hw), 4079 "Failed to clear PHY TX_OFFSET_READY register\n"); 4080 return err; 4081 } 4082 4083 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4084 if (err) { 4085 dev_warn(ice_hw_to_dev(hw), 4086 "Failed to clear PHY RX_OFFSET_READY register\n"); 4087 return err; 4088 } 4089 } 4090 4091 return 0; 4092 } 4093 4094 /** 4095 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time 4096 * @hw: pointer to the HW struct 4097 * @port: the PHY port to read 4098 * @phy_time: on return, the 64bit PHY timer value 4099 * @phc_time: on return, the lower 64bits of PHC time 4100 * 4101 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 4102 * and PHC timer values. 4103 */ 4104 static int 4105 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time, 4106 u64 *phc_time) 4107 { 4108 u64 tx_time, rx_time; 4109 u32 zo, lo; 4110 u8 tmr_idx; 4111 int err; 4112 4113 tmr_idx = ice_get_ptp_src_clock_index(hw); 4114 4115 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 4116 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 4117 4118 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 4119 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 4120 if (err) 4121 return err; 4122 4123 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 4124 ice_ptp_exec_tmr_cmd(hw); 4125 4126 /* Read the captured PHC time from the shadow time registers */ 4127 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 4128 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 4129 *phc_time = (u64)lo << 32 | zo; 4130 4131 /* Read the captured PHY time from the PHY shadow registers */ 4132 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 4133 if (err) 4134 return err; 4135 4136 /* If the PHY Tx and Rx timers don't match, log a warning message. 4137 * Note that this should not happen in normal circumstances since the 4138 * driver always programs them together. 4139 */ 4140 if (tx_time != rx_time) 4141 dev_warn(ice_hw_to_dev(hw), 4142 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 4143 port, (unsigned long long)tx_time, 4144 (unsigned long long)rx_time); 4145 4146 *phy_time = tx_time; 4147 4148 return 0; 4149 } 4150 4151 /** 4152 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer 4153 * @hw: pointer to the HW struct 4154 * @port: the PHY port to synchronize 4155 * 4156 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 4157 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 4158 * simultaneous read of the PHY timer and PHC timer. Then we use the 4159 * difference to calculate an appropriate 2s complement addition to add 4160 * to the PHY timer in order to ensure it reads the same value as the 4161 * primary PHC timer. 4162 */ 4163 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port) 4164 { 4165 u64 phc_time, phy_time, difference; 4166 int err; 4167 4168 if (!ice_ptp_lock(hw)) { 4169 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 4170 return -EBUSY; 4171 } 4172 4173 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4174 if (err) 4175 goto err_unlock; 4176 4177 /* Calculate the amount required to add to the port time in order for 4178 * it to match the PHC time. 4179 * 4180 * Note that the port adjustment is done using 2s complement 4181 * arithmetic. This is convenient since it means that we can simply 4182 * calculate the difference between the PHC time and the port time, 4183 * and it will be interpreted correctly. 4184 */ 4185 difference = phc_time - phy_time; 4186 4187 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference); 4188 if (err) 4189 goto err_unlock; 4190 4191 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 4192 if (err) 4193 goto err_unlock; 4194 4195 /* Do not perform any action on the main timer */ 4196 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4197 4198 /* Issue the sync to activate the time adjustment */ 4199 ice_ptp_exec_tmr_cmd(hw); 4200 4201 /* Re-capture the timer values to flush the command registers and 4202 * verify that the time was properly adjusted. 4203 */ 4204 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4205 if (err) 4206 goto err_unlock; 4207 4208 dev_info(ice_hw_to_dev(hw), 4209 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 4210 port, (unsigned long long)phy_time, 4211 (unsigned long long)phc_time); 4212 4213 ice_ptp_unlock(hw); 4214 4215 return 0; 4216 4217 err_unlock: 4218 ice_ptp_unlock(hw); 4219 return err; 4220 } 4221 4222 /** 4223 * ice_stop_phy_timer_e82x - Stop the PHY clock timer 4224 * @hw: pointer to the HW struct 4225 * @port: the PHY port to stop 4226 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 4227 * 4228 * Stop the clock of a PHY port. This must be done as part of the flow to 4229 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4230 * initialized or when link speed changes. 4231 */ 4232 int 4233 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset) 4234 { 4235 int err; 4236 u32 val; 4237 4238 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4239 if (err) 4240 return err; 4241 4242 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4243 if (err) 4244 return err; 4245 4246 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4247 if (err) 4248 return err; 4249 4250 val &= ~P_REG_PS_START_M; 4251 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4252 if (err) 4253 return err; 4254 4255 val &= ~P_REG_PS_ENA_CLK_M; 4256 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4257 if (err) 4258 return err; 4259 4260 if (soft_reset) { 4261 val |= P_REG_PS_SFT_RESET_M; 4262 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4263 if (err) 4264 return err; 4265 } 4266 4267 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 4268 4269 return 0; 4270 } 4271 4272 /** 4273 * ice_start_phy_timer_e82x - Start the PHY clock timer 4274 * @hw: pointer to the HW struct 4275 * @port: the PHY port to start 4276 * 4277 * Start the clock of a PHY port. This must be done as part of the flow to 4278 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4279 * initialized or when link speed changes. 4280 * 4281 * Hardware will take Vernier measurements on Tx or Rx of packets. 4282 */ 4283 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port) 4284 { 4285 u32 lo, hi, val; 4286 u64 incval; 4287 u8 tmr_idx; 4288 int err; 4289 4290 tmr_idx = ice_get_ptp_src_clock_index(hw); 4291 4292 err = ice_stop_phy_timer_e82x(hw, port, false); 4293 if (err) 4294 return err; 4295 4296 ice_phy_cfg_lane_e82x(hw, port); 4297 4298 err = ice_phy_cfg_uix_e82x(hw, port); 4299 if (err) 4300 return err; 4301 4302 err = ice_phy_cfg_parpcs_e82x(hw, port); 4303 if (err) 4304 return err; 4305 4306 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 4307 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 4308 incval = (u64)hi << 32 | lo; 4309 4310 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval); 4311 if (err) 4312 return err; 4313 4314 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4315 if (err) 4316 return err; 4317 4318 /* Do not perform any action on the main timer */ 4319 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4320 4321 ice_ptp_exec_tmr_cmd(hw); 4322 4323 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4324 if (err) 4325 return err; 4326 4327 val |= P_REG_PS_SFT_RESET_M; 4328 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4329 if (err) 4330 return err; 4331 4332 val |= P_REG_PS_START_M; 4333 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4334 if (err) 4335 return err; 4336 4337 val &= ~P_REG_PS_SFT_RESET_M; 4338 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4339 if (err) 4340 return err; 4341 4342 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4343 if (err) 4344 return err; 4345 4346 ice_ptp_exec_tmr_cmd(hw); 4347 4348 val |= P_REG_PS_ENA_CLK_M; 4349 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4350 if (err) 4351 return err; 4352 4353 val |= P_REG_PS_LOAD_OFFSET_M; 4354 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4355 if (err) 4356 return err; 4357 4358 ice_ptp_exec_tmr_cmd(hw); 4359 4360 err = ice_sync_phy_timer_e82x(hw, port); 4361 if (err) 4362 return err; 4363 4364 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 4365 4366 return 0; 4367 } 4368 4369 /** 4370 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register 4371 * @hw: pointer to the HW struct 4372 * @quad: the timestamp quad to read from 4373 * @tstamp_ready: contents of the Tx memory status register 4374 * 4375 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in 4376 * the PHY are ready. A set bit means the corresponding timestamp is valid and 4377 * ready to be captured from the PHY timestamp block. 4378 */ 4379 static int 4380 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 4381 { 4382 u32 hi, lo; 4383 int err; 4384 4385 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); 4386 if (err) { 4387 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", 4388 quad, err); 4389 return err; 4390 } 4391 4392 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); 4393 if (err) { 4394 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", 4395 quad, err); 4396 return err; 4397 } 4398 4399 *tstamp_ready = (u64)hi << 32 | (u64)lo; 4400 4401 return 0; 4402 } 4403 4404 /** 4405 * ice_check_phy_tx_tstamp_ready_e82x - Check Tx memory status for all quads 4406 * @hw: pointer to the HW struct 4407 * 4408 * Check the Q_REG_TX_MEMORY_STATUS for all quads. A set bit indicates 4409 * a waiting timestamp. 4410 * 4411 * Return: 1 if any quad has at least one timestamp ready bit set, 4412 * 0 otherwise, and a negative error value if unable to read the bitmap. 4413 */ 4414 static int ice_check_phy_tx_tstamp_ready_e82x(struct ice_hw *hw) 4415 { 4416 int quad; 4417 4418 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) { 4419 u64 tstamp_ready; 4420 int err; 4421 4422 err = ice_get_phy_tx_tstamp_ready(hw, quad, &tstamp_ready); 4423 if (err) 4424 return err; 4425 4426 if (tstamp_ready) 4427 return 1; 4428 } 4429 4430 return 0; 4431 } 4432 4433 /** 4434 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt 4435 * @hw: pointer to the HW struct 4436 * @quad: the timestamp quad 4437 * @ena: enable or disable interrupt 4438 * @threshold: interrupt threshold 4439 * 4440 * Configure TX timestamp interrupt for the specified quad 4441 * 4442 * Return: 0 on success, other error codes when failed to read/write quad 4443 */ 4444 4445 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) 4446 { 4447 int err; 4448 u32 val; 4449 4450 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 4451 if (err) 4452 return err; 4453 4454 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4455 if (ena) { 4456 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4457 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 4458 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold); 4459 } 4460 4461 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 4462 } 4463 4464 /** 4465 * ice_ptp_init_phy_e82x - initialize PHY parameters 4466 * @ptp: pointer to the PTP HW struct 4467 */ 4468 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) 4469 { 4470 ptp->num_lports = 8; 4471 ptp->ports_per_phy = 8; 4472 } 4473 4474 /* E810 functions 4475 * 4476 * The following functions operate on the E810 series devices which use 4477 * a separate external PHY. 4478 */ 4479 4480 /** 4481 * ice_read_phy_reg_e810 - Read register from external PHY on E810 4482 * @hw: pointer to the HW struct 4483 * @addr: the address to read from 4484 * @val: On return, the value read from the PHY 4485 * 4486 * Read a register from the external PHY on the E810 device. 4487 */ 4488 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 4489 { 4490 struct ice_sbq_msg_input msg = {0}; 4491 int err; 4492 4493 msg.msg_addr_low = lower_16_bits(addr); 4494 msg.msg_addr_high = upper_16_bits(addr); 4495 msg.opcode = ice_sbq_msg_rd; 4496 msg.dest_dev = ice_sbq_dev_phy_0; 4497 4498 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 4499 if (err) { 4500 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4501 err); 4502 return err; 4503 } 4504 4505 *val = msg.data; 4506 4507 return 0; 4508 } 4509 4510 /** 4511 * ice_write_phy_reg_e810 - Write register on external PHY on E810 4512 * @hw: pointer to the HW struct 4513 * @addr: the address to writem to 4514 * @val: the value to write to the PHY 4515 * 4516 * Write a value to a register of the external PHY on the E810 device. 4517 */ 4518 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 4519 { 4520 struct ice_sbq_msg_input msg = {0}; 4521 int err; 4522 4523 msg.msg_addr_low = lower_16_bits(addr); 4524 msg.msg_addr_high = upper_16_bits(addr); 4525 msg.opcode = ice_sbq_msg_wr; 4526 msg.dest_dev = ice_sbq_dev_phy_0; 4527 msg.data = val; 4528 4529 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 4530 if (err) { 4531 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4532 err); 4533 return err; 4534 } 4535 4536 return 0; 4537 } 4538 4539 /** 4540 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW 4541 * @hw: pointer to the HW struct 4542 * @idx: the timestamp index to read 4543 * @hi: 8 bit timestamp high value 4544 * @lo: 32 bit timestamp low value 4545 * 4546 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4547 * timestamp block of the external PHY on the E810 device using the low latency 4548 * timestamp read. 4549 */ 4550 static int 4551 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 4552 { 4553 struct ice_e810_params *params = &hw->ptp.phy.e810; 4554 u32 val; 4555 int err; 4556 4557 spin_lock_irq(¶ms->atqbal_wq.lock); 4558 4559 /* Wait for any pending in-progress low latency interrupt */ 4560 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4561 !(params->atqbal_flags & 4562 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4563 if (err) { 4564 spin_unlock_irq(¶ms->atqbal_wq.lock); 4565 return err; 4566 } 4567 4568 /* Write TS index to read to the PF register so the FW can read it */ 4569 val = FIELD_PREP(REG_LL_PROXY_H_TS_IDX, idx) | REG_LL_PROXY_H_EXEC; 4570 wr32(hw, REG_LL_PROXY_H, val); 4571 4572 /* Read the register repeatedly until the FW provides us the TS */ 4573 err = read_poll_timeout_atomic(rd32, val, 4574 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 10, 4575 REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4576 REG_LL_PROXY_H); 4577 if (err) { 4578 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); 4579 spin_unlock_irq(¶ms->atqbal_wq.lock); 4580 return err; 4581 } 4582 4583 /* High 8 bit value of the TS is on the bits 16:23 */ 4584 *hi = FIELD_GET(REG_LL_PROXY_H_TS_HIGH, val); 4585 4586 /* Read the low 32 bit value and set the TS valid bit */ 4587 *lo = rd32(hw, REG_LL_PROXY_L) | TS_VALID; 4588 4589 spin_unlock_irq(¶ms->atqbal_wq.lock); 4590 4591 return 0; 4592 } 4593 4594 /** 4595 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq 4596 * @hw: pointer to the HW struct 4597 * @lport: the lport to read from 4598 * @idx: the timestamp index to read 4599 * @hi: 8 bit timestamp high value 4600 * @lo: 32 bit timestamp low value 4601 * 4602 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4603 * timestamp block of the external PHY on the E810 device using sideband queue. 4604 */ 4605 static int 4606 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, 4607 u32 *lo) 4608 { 4609 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4610 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4611 u32 lo_val, hi_val; 4612 int err; 4613 4614 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val); 4615 if (err) { 4616 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 4617 err); 4618 return err; 4619 } 4620 4621 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val); 4622 if (err) { 4623 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 4624 err); 4625 return err; 4626 } 4627 4628 *lo = lo_val; 4629 *hi = (u8)hi_val; 4630 4631 return 0; 4632 } 4633 4634 /** 4635 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 4636 * @hw: pointer to the HW struct 4637 * @lport: the lport to read from 4638 * @idx: the timestamp index to read 4639 * @tstamp: on return, the 40bit timestamp value 4640 * 4641 * Read a 40bit timestamp value out of the timestamp block of the external PHY 4642 * on the E810 device. 4643 */ 4644 static int 4645 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 4646 { 4647 u32 lo = 0; 4648 u8 hi = 0; 4649 int err; 4650 4651 if (hw->dev_caps.ts_dev_info.ts_ll_read) 4652 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); 4653 else 4654 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); 4655 4656 if (err) 4657 return err; 4658 4659 /* For E810 devices, the timestamp is reported with the lower 32 bits 4660 * in the low register, and the upper 8 bits in the high register. 4661 */ 4662 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 4663 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 4664 4665 return 0; 4666 } 4667 4668 /** 4669 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 4670 * @hw: pointer to the HW struct 4671 * @lport: the lport to read from 4672 * @idx: the timestamp index to reset 4673 * 4674 * Read the timestamp and then forcibly overwrite its value to clear the valid 4675 * bit from the timestamp block of the external PHY on the E810 device. 4676 * 4677 * This function should only be called on an idx whose bit is set according to 4678 * ice_get_phy_tx_tstamp_ready(). 4679 */ 4680 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 4681 { 4682 u32 lo_addr, hi_addr; 4683 u64 unused_tstamp; 4684 int err; 4685 4686 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); 4687 if (err) { 4688 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", 4689 lport, idx, err); 4690 return err; 4691 } 4692 4693 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4694 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4695 4696 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 4697 if (err) { 4698 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", 4699 lport, idx, err); 4700 return err; 4701 } 4702 4703 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 4704 if (err) { 4705 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", 4706 lport, idx, err); 4707 return err; 4708 } 4709 4710 return 0; 4711 } 4712 4713 /** 4714 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 4715 * @hw: pointer to HW struct 4716 * 4717 * Perform E810-specific PTP hardware clock initialization steps. 4718 * 4719 * Return: 0 on success, other error codes when failed to initialize TimeSync 4720 */ 4721 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 4722 { 4723 u8 tmr_idx; 4724 int err; 4725 4726 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 4727 4728 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4729 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 4730 GLTSYN_ENA_TSYN_ENA_M); 4731 if (err) 4732 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 4733 err); 4734 4735 return err; 4736 } 4737 4738 /** 4739 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 4740 * @hw: Board private structure 4741 * @time: Time to initialize the PHY port clock to 4742 * 4743 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 4744 * initial clock time. The time will not actually be programmed until the 4745 * driver issues an ICE_PTP_INIT_TIME command. 4746 * 4747 * The time value is the upper 32 bits of the PHY timer, usually in units of 4748 * nominal nanoseconds. 4749 */ 4750 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 4751 { 4752 u8 tmr_idx; 4753 int err; 4754 4755 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4756 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 4757 if (err) { 4758 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 4759 err); 4760 return err; 4761 } 4762 4763 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 4764 if (err) { 4765 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 4766 err); 4767 return err; 4768 } 4769 4770 return 0; 4771 } 4772 4773 /** 4774 * ice_ptp_prep_phy_adj_ll_e810 - Prep PHY ports for a time adjustment 4775 * @hw: pointer to HW struct 4776 * @adj: adjustment value to program 4777 * 4778 * Use the low latency firmware interface to program PHY time adjustment to 4779 * all PHY ports. 4780 * 4781 * Return: 0 on success, -EBUSY on timeout 4782 */ 4783 static int ice_ptp_prep_phy_adj_ll_e810(struct ice_hw *hw, s32 adj) 4784 { 4785 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4786 struct ice_e810_params *params = &hw->ptp.phy.e810; 4787 u32 val; 4788 int err; 4789 4790 spin_lock_irq(¶ms->atqbal_wq.lock); 4791 4792 /* Wait for any pending in-progress low latency interrupt */ 4793 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4794 !(params->atqbal_flags & 4795 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4796 if (err) { 4797 spin_unlock_irq(¶ms->atqbal_wq.lock); 4798 return err; 4799 } 4800 4801 wr32(hw, REG_LL_PROXY_L, adj); 4802 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_ADJ) | 4803 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 4804 wr32(hw, REG_LL_PROXY_H, val); 4805 4806 /* Read the register repeatedly until the FW indicates completion */ 4807 err = read_poll_timeout_atomic(rd32, val, 4808 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 4809 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4810 REG_LL_PROXY_H); 4811 if (err) { 4812 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n"); 4813 spin_unlock_irq(¶ms->atqbal_wq.lock); 4814 return err; 4815 } 4816 4817 spin_unlock_irq(¶ms->atqbal_wq.lock); 4818 4819 return 0; 4820 } 4821 4822 /** 4823 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 4824 * @hw: pointer to HW struct 4825 * @adj: adjustment value to program 4826 * 4827 * Prepare the PHY port for an atomic adjustment by programming the PHY 4828 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 4829 * is completed by issuing an ICE_PTP_ADJ_TIME sync command. 4830 * 4831 * The adjustment value only contains the portion used for the upper 32bits of 4832 * the PHY timer, usually in units of nominal nanoseconds. Negative 4833 * adjustments are supported using 2s complement arithmetic. 4834 */ 4835 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 4836 { 4837 u8 tmr_idx; 4838 int err; 4839 4840 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 4841 return ice_ptp_prep_phy_adj_ll_e810(hw, adj); 4842 4843 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4844 4845 /* Adjustments are represented as signed 2's complement values in 4846 * nanoseconds. Sub-nanosecond adjustment is not supported. 4847 */ 4848 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 4849 if (err) { 4850 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 4851 err); 4852 return err; 4853 } 4854 4855 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 4856 if (err) { 4857 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 4858 err); 4859 return err; 4860 } 4861 4862 return 0; 4863 } 4864 4865 /** 4866 * ice_ptp_prep_phy_incval_ll_e810 - Prep PHY ports increment value change 4867 * @hw: pointer to HW struct 4868 * @incval: The new 40bit increment value to prepare 4869 * 4870 * Use the low latency firmware interface to program PHY time increment value 4871 * for all PHY ports. 4872 * 4873 * Return: 0 on success, -EBUSY on timeout 4874 */ 4875 static int ice_ptp_prep_phy_incval_ll_e810(struct ice_hw *hw, u64 incval) 4876 { 4877 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4878 struct ice_e810_params *params = &hw->ptp.phy.e810; 4879 u32 val; 4880 int err; 4881 4882 spin_lock_irq(¶ms->atqbal_wq.lock); 4883 4884 /* Wait for any pending in-progress low latency interrupt */ 4885 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4886 !(params->atqbal_flags & 4887 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4888 if (err) { 4889 spin_unlock_irq(¶ms->atqbal_wq.lock); 4890 return err; 4891 } 4892 4893 wr32(hw, REG_LL_PROXY_L, lower_32_bits(incval)); 4894 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_FREQ) | 4895 FIELD_PREP(REG_LL_PROXY_H_TS_HIGH, (u8)upper_32_bits(incval)) | 4896 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 4897 wr32(hw, REG_LL_PROXY_H, val); 4898 4899 /* Read the register repeatedly until the FW indicates completion */ 4900 err = read_poll_timeout_atomic(rd32, val, 4901 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 4902 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4903 REG_LL_PROXY_H); 4904 if (err) { 4905 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n"); 4906 spin_unlock_irq(¶ms->atqbal_wq.lock); 4907 return err; 4908 } 4909 4910 spin_unlock_irq(¶ms->atqbal_wq.lock); 4911 4912 return 0; 4913 } 4914 4915 /** 4916 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 4917 * @hw: pointer to HW struct 4918 * @incval: The new 40bit increment value to prepare 4919 * 4920 * Prepare the PHY port for a new increment value by programming the PHY 4921 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 4922 * completed by issuing an ICE_PTP_INIT_INCVAL command. 4923 */ 4924 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 4925 { 4926 u32 high, low; 4927 u8 tmr_idx; 4928 int err; 4929 4930 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 4931 return ice_ptp_prep_phy_incval_ll_e810(hw, incval); 4932 4933 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4934 low = lower_32_bits(incval); 4935 high = upper_32_bits(incval); 4936 4937 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 4938 if (err) { 4939 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 4940 err); 4941 return err; 4942 } 4943 4944 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 4945 if (err) { 4946 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 4947 err); 4948 return err; 4949 } 4950 4951 return 0; 4952 } 4953 4954 /** 4955 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 4956 * @hw: pointer to HW struct 4957 * @cmd: Command to be sent to the port 4958 * 4959 * Prepare the external PHYs connected to this device for a timer sync 4960 * command. 4961 */ 4962 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 4963 { 4964 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 4965 4966 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val); 4967 } 4968 4969 /** 4970 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register 4971 * @hw: pointer to the HW struct 4972 * @port: the PHY port to read 4973 * @tstamp_ready: contents of the Tx memory status register 4974 * 4975 * E810 devices do not use a Tx memory status register. Instead simply 4976 * indicate that all timestamps are currently ready. 4977 */ 4978 static int 4979 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) 4980 { 4981 *tstamp_ready = 0xFFFFFFFFFFFFFFFF; 4982 return 0; 4983 } 4984 4985 /** 4986 * ice_check_phy_tx_tstamp_ready_e810 - Check Tx memory status register 4987 * @hw: pointer to the HW struct 4988 * 4989 * The E810 devices do not have a Tx memory status register. Note this is 4990 * intentionally different behavior from ice_get_phy_tx_tstamp_ready_e810 4991 * which always says that all bits are ready. This function is called in cases 4992 * where code will trigger interrupts if timestamps are waiting, and should 4993 * not be called for E810 hardware. 4994 * 4995 * Return: 0. 4996 */ 4997 static int ice_check_phy_tx_tstamp_ready_e810(struct ice_hw *hw) 4998 { 4999 return 0; 5000 } 5001 5002 /* E810 SMA functions 5003 * 5004 * The following functions operate specifically on E810 hardware and are used 5005 * to access the extended GPIOs available. 5006 */ 5007 5008 /** 5009 * ice_read_sma_ctrl 5010 * @hw: pointer to the hw struct 5011 * @data: pointer to data to be read from the GPIO controller 5012 * 5013 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 5014 * PCA9575 expander, so only bits 3-7 in data are valid. 5015 */ 5016 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data) 5017 { 5018 int status; 5019 u16 handle; 5020 u8 i; 5021 5022 status = ice_get_pca9575_handle(hw, &handle); 5023 if (status) 5024 return status; 5025 5026 *data = 0; 5027 5028 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5029 bool pin; 5030 5031 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5032 &pin, NULL); 5033 if (status) 5034 break; 5035 *data |= (u8)(!pin) << i; 5036 } 5037 5038 return status; 5039 } 5040 5041 /** 5042 * ice_write_sma_ctrl 5043 * @hw: pointer to the hw struct 5044 * @data: data to be written to the GPIO controller 5045 * 5046 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 5047 * of the PCA9575 expander, so only bits 3-7 in data are valid. 5048 */ 5049 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data) 5050 { 5051 int status; 5052 u16 handle; 5053 u8 i; 5054 5055 status = ice_get_pca9575_handle(hw, &handle); 5056 if (status) 5057 return status; 5058 5059 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5060 bool pin; 5061 5062 pin = !(data & (1 << i)); 5063 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5064 pin, NULL); 5065 if (status) 5066 break; 5067 } 5068 5069 return status; 5070 } 5071 5072 /** 5073 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM 5074 * @hw: pointer to the HW struct 5075 * @entries: returns the SDP available connections section from NVM 5076 * @num_entries: returns the number of valid entries 5077 * 5078 * Return: 0 on success, negative error code if NVM read failed or section does 5079 * not exist or is corrupted 5080 */ 5081 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries) 5082 { 5083 __le16 data; 5084 u32 offset; 5085 int err; 5086 5087 err = ice_acquire_nvm(hw, ICE_RES_READ); 5088 if (err) 5089 goto exit; 5090 5091 /* Read the offset of SDP_AC */ 5092 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET; 5093 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5094 NULL); 5095 if (err) 5096 goto exit; 5097 5098 /* Check if section exist */ 5099 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data)); 5100 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) { 5101 err = -EINVAL; 5102 goto exit; 5103 } 5104 5105 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) { 5106 offset &= ICE_AQC_NVM_SDP_AC_PTR_M; 5107 offset *= ICE_AQC_NVM_SECTOR_UNIT; 5108 } else { 5109 offset *= sizeof(data); 5110 } 5111 5112 /* Skip reading section length and read the number of valid entries */ 5113 offset += sizeof(data); 5114 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5115 NULL); 5116 if (err) 5117 goto exit; 5118 *num_entries = le16_to_cpu(data); 5119 5120 /* Read SDP configuration section */ 5121 offset += sizeof(data); 5122 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data), 5123 entries, false, true, NULL); 5124 5125 exit: 5126 if (err) 5127 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n"); 5128 ice_release_nvm(hw); 5129 return err; 5130 } 5131 5132 /** 5133 * ice_ptp_init_phy_e810 - initialize PHY parameters 5134 * @ptp: pointer to the PTP HW struct 5135 */ 5136 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) 5137 { 5138 ptp->num_lports = 8; 5139 ptp->ports_per_phy = 4; 5140 5141 init_waitqueue_head(&ptp->phy.e810.atqbal_wq); 5142 } 5143 5144 /* E830 functions 5145 * 5146 * The following functions operate on the E830 series devices. 5147 * 5148 */ 5149 5150 /** 5151 * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization 5152 * @hw: pointer to HW struct 5153 * 5154 * Perform E830-specific PTP hardware clock initialization steps. 5155 */ 5156 static void ice_ptp_init_phc_e830(const struct ice_hw *hw) 5157 { 5158 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 5159 } 5160 5161 /** 5162 * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change 5163 * @hw: pointer to HW struct 5164 * @incval: The new 40bit increment value to prepare 5165 * 5166 * Prepare the PHY port for a new increment value by programming the PHC 5167 * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is 5168 * completed by FW automatically. 5169 */ 5170 static void ice_ptp_write_direct_incval_e830(const struct ice_hw *hw, 5171 u64 incval) 5172 { 5173 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5174 5175 wr32(hw, GLTSYN_INCVAL_L(tmr_idx), lower_32_bits(incval)); 5176 wr32(hw, GLTSYN_INCVAL_H(tmr_idx), upper_32_bits(incval)); 5177 } 5178 5179 /** 5180 * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time 5181 * @hw: Board private structure 5182 * @time: Time to initialize the PHY port clock to 5183 * 5184 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 5185 * initial clock time. The time will not actually be programmed until the 5186 * driver issues an ICE_PTP_INIT_TIME command. 5187 * 5188 * The time value is the upper 32 bits of the PHY timer, usually in units of 5189 * nominal nanoseconds. 5190 */ 5191 static void ice_ptp_write_direct_phc_time_e830(const struct ice_hw *hw, 5192 u64 time) 5193 { 5194 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5195 5196 wr32(hw, GLTSYN_TIME_0(tmr_idx), 0); 5197 wr32(hw, GLTSYN_TIME_L(tmr_idx), lower_32_bits(time)); 5198 wr32(hw, GLTSYN_TIME_H(tmr_idx), upper_32_bits(time)); 5199 } 5200 5201 /** 5202 * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command 5203 * @hw: pointer to HW struct 5204 * @cmd: Command to be sent to the port 5205 * 5206 * Prepare the external PHYs connected to this device for a timer sync 5207 * command. 5208 * 5209 * Return: 0 on success, negative error code when PHY write failed 5210 */ 5211 static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5212 { 5213 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 5214 5215 return ice_write_phy_reg_e810(hw, E830_ETH_GLTSYN_CMD, val); 5216 } 5217 5218 /** 5219 * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY 5220 * @hw: pointer to the HW struct 5221 * @idx: the timestamp index to read 5222 * @tstamp: on return, the 40bit timestamp value 5223 * 5224 * Read a 40bit timestamp value out of the timestamp block of the external PHY 5225 * on the E830 device. 5226 */ 5227 static void ice_read_phy_tstamp_e830(const struct ice_hw *hw, u8 idx, 5228 u64 *tstamp) 5229 { 5230 u32 hi, lo; 5231 5232 hi = rd32(hw, E830_PRTTSYN_TXTIME_H(idx)); 5233 lo = rd32(hw, E830_PRTTSYN_TXTIME_L(idx)); 5234 5235 /* For E830 devices, the timestamp is reported with the lower 32 bits 5236 * in the low register, and the upper 8 bits in the high register. 5237 */ 5238 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 5239 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 5240 } 5241 5242 /** 5243 * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register 5244 * @hw: pointer to the HW struct 5245 * @port: the PHY port to read 5246 * @tstamp_ready: contents of the Tx memory status register 5247 */ 5248 static void ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw *hw, u8 port, 5249 u64 *tstamp_ready) 5250 { 5251 *tstamp_ready = rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_H); 5252 *tstamp_ready <<= 32; 5253 *tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L); 5254 } 5255 5256 /** 5257 * ice_check_phy_tx_tstamp_ready_e830 - Check Tx memory status register 5258 * @hw: pointer to the HW struct 5259 * 5260 * Return: 1 if the device has waiting timestamps, 0 otherwise. 5261 */ 5262 static int ice_check_phy_tx_tstamp_ready_e830(struct ice_hw *hw) 5263 { 5264 u64 tstamp_ready; 5265 5266 ice_get_phy_tx_tstamp_ready_e830(hw, 0, &tstamp_ready); 5267 5268 return !!tstamp_ready; 5269 } 5270 5271 /** 5272 * ice_ptp_init_phy_e830 - initialize PHY parameters 5273 * @ptp: pointer to the PTP HW struct 5274 */ 5275 static void ice_ptp_init_phy_e830(struct ice_ptp_hw *ptp) 5276 { 5277 ptp->num_lports = 8; 5278 ptp->ports_per_phy = 4; 5279 } 5280 5281 /* Device agnostic functions 5282 * 5283 * The following functions implement shared behavior common to all devices, 5284 * possibly calling a device specific implementation where necessary. 5285 */ 5286 5287 /** 5288 * ice_ptp_lock - Acquire PTP global semaphore register lock 5289 * @hw: pointer to the HW struct 5290 * 5291 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 5292 * was acquired, false otherwise. 5293 * 5294 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 5295 * value. If software sees the busy bit cleared, this means that this function 5296 * acquired the lock (and the busy bit is now set). If software sees the busy 5297 * bit set, it means that another function acquired the lock. 5298 * 5299 * Software must clear the busy bit with a write to release the lock for other 5300 * functions when done. 5301 */ 5302 bool ice_ptp_lock(struct ice_hw *hw) 5303 { 5304 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 5305 u32 hw_lock; 5306 int i; 5307 5308 if (!ice_is_primary(hw)) 5309 hw = ice_get_primary_hw(pf); 5310 5311 #define MAX_TRIES 15 5312 5313 for (i = 0; i < MAX_TRIES; i++) { 5314 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 5315 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 5316 if (hw_lock) { 5317 /* Somebody is holding the lock */ 5318 usleep_range(5000, 6000); 5319 continue; 5320 } 5321 5322 break; 5323 } 5324 5325 return !hw_lock; 5326 } 5327 5328 /** 5329 * ice_ptp_unlock - Release PTP global semaphore register lock 5330 * @hw: pointer to the HW struct 5331 * 5332 * Release the global PTP hardware semaphore lock. This is done by writing to 5333 * the PFTSYN_SEM register. 5334 */ 5335 void ice_ptp_unlock(struct ice_hw *hw) 5336 { 5337 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 5338 5339 if (!ice_is_primary(hw)) 5340 hw = ice_get_primary_hw(pf); 5341 5342 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 5343 } 5344 5345 /** 5346 * ice_ptp_init_hw - Initialize hw based on device type 5347 * @hw: pointer to the HW structure 5348 * 5349 * Determine the PHY model for the device, and initialize hw 5350 * for use by other functions. 5351 */ 5352 void ice_ptp_init_hw(struct ice_hw *hw) 5353 { 5354 struct ice_ptp_hw *ptp = &hw->ptp; 5355 5356 switch (hw->mac_type) { 5357 case ICE_MAC_E810: 5358 ice_ptp_init_phy_e810(ptp); 5359 break; 5360 case ICE_MAC_E830: 5361 ice_ptp_init_phy_e830(ptp); 5362 break; 5363 case ICE_MAC_GENERIC: 5364 ice_ptp_init_phy_e82x(ptp); 5365 break; 5366 case ICE_MAC_GENERIC_3K_E825: 5367 ice_ptp_init_phy_e825(hw); 5368 break; 5369 default: 5370 return; 5371 } 5372 } 5373 5374 /** 5375 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command 5376 * @hw: pointer to HW struct 5377 * @port: Port to which cmd has to be sent 5378 * @cmd: Command to be sent to the port 5379 * 5380 * Prepare one port for the upcoming timer sync command. Do not use this for 5381 * programming only a single port, instead use ice_ptp_one_port_cmd() to 5382 * ensure non-modified ports get properly initialized to ICE_PTP_NOP. 5383 * 5384 * Return: 5385 * * %0 - success 5386 * %-EBUSY - PHY type not supported 5387 * * %other - failed to write port command 5388 */ 5389 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, 5390 enum ice_ptp_tmr_cmd cmd) 5391 { 5392 switch (hw->mac_type) { 5393 case ICE_MAC_GENERIC: 5394 return ice_ptp_write_port_cmd_e82x(hw, port, cmd); 5395 case ICE_MAC_GENERIC_3K_E825: 5396 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd); 5397 default: 5398 return -EOPNOTSUPP; 5399 } 5400 } 5401 5402 /** 5403 * ice_ptp_one_port_cmd - Program one PHY port for a timer command 5404 * @hw: pointer to HW struct 5405 * @configured_port: the port that should execute the command 5406 * @configured_cmd: the command to be executed on the configured port 5407 * 5408 * Prepare one port for executing a timer command, while preparing all other 5409 * ports to ICE_PTP_NOP. This allows executing a command on a single port 5410 * while ensuring all other ports do not execute stale commands. 5411 * 5412 * Return: 5413 * * %0 - success 5414 * * %other - failed to write port command 5415 */ 5416 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, 5417 enum ice_ptp_tmr_cmd configured_cmd) 5418 { 5419 u32 port; 5420 5421 for (port = 0; port < hw->ptp.num_lports; port++) { 5422 int err; 5423 5424 /* Program the configured port with the configured command, 5425 * program all other ports with ICE_PTP_NOP. 5426 */ 5427 if (port == configured_port) 5428 err = ice_ptp_write_port_cmd(hw, port, configured_cmd); 5429 else 5430 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP); 5431 5432 if (err) 5433 return err; 5434 } 5435 5436 return 0; 5437 } 5438 5439 /** 5440 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command 5441 * @hw: pointer to HW struct 5442 * @cmd: the timer command to setup 5443 * 5444 * Prepare all PHY ports on this device for the requested timer command. For 5445 * some families this can be done in one shot, but for other families each 5446 * port must be configured individually. 5447 * 5448 * Return: 5449 * * %0 - success 5450 * * %other - failed to write port command 5451 */ 5452 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5453 { 5454 u32 port; 5455 5456 /* PHY models which can program all ports simultaneously */ 5457 switch (hw->mac_type) { 5458 case ICE_MAC_E810: 5459 return ice_ptp_port_cmd_e810(hw, cmd); 5460 case ICE_MAC_E830: 5461 return ice_ptp_port_cmd_e830(hw, cmd); 5462 default: 5463 break; 5464 } 5465 5466 /* PHY models which require programming each port separately */ 5467 for (port = 0; port < hw->ptp.num_lports; port++) { 5468 int err; 5469 5470 err = ice_ptp_write_port_cmd(hw, port, cmd); 5471 if (err) 5472 return err; 5473 } 5474 5475 return 0; 5476 } 5477 5478 /** 5479 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 5480 * @hw: pointer to HW struct 5481 * @cmd: the command to issue 5482 * 5483 * Prepare the source timer and PHY timers and then trigger the requested 5484 * command. This causes the shadow registers previously written in preparation 5485 * for the command to be synchronously applied to both the source and PHY 5486 * timers. 5487 */ 5488 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5489 { 5490 int err; 5491 5492 /* First, prepare the source timer */ 5493 ice_ptp_src_cmd(hw, cmd); 5494 5495 /* Next, prepare the ports */ 5496 err = ice_ptp_port_cmd(hw, cmd); 5497 if (err) { 5498 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 5499 cmd, err); 5500 return err; 5501 } 5502 5503 /* Write the sync command register to drive both source and PHY timer 5504 * commands synchronously 5505 */ 5506 ice_ptp_exec_tmr_cmd(hw); 5507 5508 return 0; 5509 } 5510 5511 /** 5512 * ice_ptp_init_time - Initialize device time to provided value 5513 * @hw: pointer to HW struct 5514 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 5515 * 5516 * Initialize the device to the specified time provided. This requires a three 5517 * step process: 5518 * 5519 * 1) write the new init time to the source timer shadow registers 5520 * 2) write the new init time to the PHY timer shadow registers 5521 * 3) issue an init_time timer command to synchronously switch both the source 5522 * and port timers to the new init time value at the next clock cycle. 5523 */ 5524 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 5525 { 5526 u8 tmr_idx; 5527 int err; 5528 5529 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5530 5531 /* Source timers */ 5532 /* For E830 we don't need to use shadow registers, its automatic */ 5533 if (hw->mac_type == ICE_MAC_E830) { 5534 ice_ptp_write_direct_phc_time_e830(hw, time); 5535 return 0; 5536 } 5537 5538 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 5539 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 5540 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 5541 5542 /* PHY timers */ 5543 /* Fill Rx and Tx ports and send msg to PHY */ 5544 switch (hw->mac_type) { 5545 case ICE_MAC_E810: 5546 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 5547 break; 5548 case ICE_MAC_GENERIC: 5549 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF); 5550 break; 5551 case ICE_MAC_GENERIC_3K_E825: 5552 err = ice_ptp_prep_phy_time_eth56g(hw, 5553 (u32)(time & 0xFFFFFFFF)); 5554 break; 5555 default: 5556 err = -EOPNOTSUPP; 5557 } 5558 5559 if (err) 5560 return err; 5561 5562 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME); 5563 } 5564 5565 /** 5566 * ice_ptp_write_incval - Program PHC with new increment value 5567 * @hw: pointer to HW struct 5568 * @incval: Source timer increment value per clock cycle 5569 * 5570 * Program the PHC with a new increment value. This requires a three-step 5571 * process: 5572 * 5573 * 1) Write the increment value to the source timer shadow registers 5574 * 2) Write the increment value to the PHY timer shadow registers 5575 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both 5576 * the source and port timers to the new increment value at the next clock 5577 * cycle. 5578 */ 5579 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 5580 { 5581 u8 tmr_idx; 5582 int err; 5583 5584 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5585 5586 /* For E830 we don't need to use shadow registers, its automatic */ 5587 if (hw->mac_type == ICE_MAC_E830) { 5588 ice_ptp_write_direct_incval_e830(hw, incval); 5589 return 0; 5590 } 5591 5592 /* Shadow Adjust */ 5593 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 5594 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 5595 5596 switch (hw->mac_type) { 5597 case ICE_MAC_E810: 5598 err = ice_ptp_prep_phy_incval_e810(hw, incval); 5599 break; 5600 case ICE_MAC_GENERIC: 5601 err = ice_ptp_prep_phy_incval_e82x(hw, incval); 5602 break; 5603 case ICE_MAC_GENERIC_3K_E825: 5604 err = ice_ptp_prep_phy_incval_eth56g(hw, incval); 5605 break; 5606 default: 5607 err = -EOPNOTSUPP; 5608 } 5609 5610 if (err) 5611 return err; 5612 5613 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL); 5614 } 5615 5616 /** 5617 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 5618 * @hw: pointer to HW struct 5619 * @incval: Source timer increment value per clock cycle 5620 * 5621 * Program a new PHC incval while holding the PTP semaphore. 5622 */ 5623 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 5624 { 5625 int err; 5626 5627 if (!ice_ptp_lock(hw)) 5628 return -EBUSY; 5629 5630 err = ice_ptp_write_incval(hw, incval); 5631 5632 ice_ptp_unlock(hw); 5633 5634 return err; 5635 } 5636 5637 /** 5638 * ice_ptp_adj_clock - Adjust PHC clock time atomically 5639 * @hw: pointer to HW struct 5640 * @adj: Adjustment in nanoseconds 5641 * 5642 * Perform an atomic adjustment of the PHC time by the specified number of 5643 * nanoseconds. This requires a three-step process: 5644 * 5645 * 1) Write the adjustment to the source timer shadow registers 5646 * 2) Write the adjustment to the PHY timer shadow registers 5647 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the 5648 * adjustment to both the source and port timers at the next clock cycle. 5649 */ 5650 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 5651 { 5652 int err = 0; 5653 u8 tmr_idx; 5654 5655 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5656 5657 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 5658 * For an ICE_PTP_ADJ_TIME command, this set of registers represents 5659 * the value to add to the clock time. It supports subtraction by 5660 * interpreting the value as a 2's complement integer. 5661 */ 5662 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 5663 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 5664 5665 switch (hw->mac_type) { 5666 case ICE_MAC_E810: 5667 err = ice_ptp_prep_phy_adj_e810(hw, adj); 5668 break; 5669 case ICE_MAC_E830: 5670 /* E830 sync PHYs automatically after setting cmd register */ 5671 break; 5672 case ICE_MAC_GENERIC: 5673 err = ice_ptp_prep_phy_adj_e82x(hw, adj); 5674 break; 5675 case ICE_MAC_GENERIC_3K_E825: 5676 err = ice_ptp_prep_phy_adj_eth56g(hw, adj); 5677 break; 5678 default: 5679 err = -EOPNOTSUPP; 5680 } 5681 5682 if (err) 5683 return err; 5684 5685 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME); 5686 } 5687 5688 /** 5689 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 5690 * @hw: pointer to the HW struct 5691 * @block: the block to read from 5692 * @idx: the timestamp index to read 5693 * @tstamp: on return, the 40bit timestamp value 5694 * 5695 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 5696 * the block is the quad to read from. For E810 devices, the block is the 5697 * logical port to read from. 5698 */ 5699 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 5700 { 5701 switch (hw->mac_type) { 5702 case ICE_MAC_E810: 5703 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 5704 case ICE_MAC_E830: 5705 ice_read_phy_tstamp_e830(hw, idx, tstamp); 5706 return 0; 5707 case ICE_MAC_GENERIC: 5708 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp); 5709 case ICE_MAC_GENERIC_3K_E825: 5710 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); 5711 default: 5712 return -EOPNOTSUPP; 5713 } 5714 } 5715 5716 /** 5717 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 5718 * @hw: pointer to the HW struct 5719 * @block: the block to read from 5720 * @idx: the timestamp index to reset 5721 * 5722 * Clear a timestamp from the timestamp block, discarding its value without 5723 * returning it. This resets the memory status bit for the timestamp index 5724 * allowing it to be reused for another timestamp in the future. 5725 * 5726 * For E822 devices, the block number is the PHY quad to clear from. For E810 5727 * devices, the block number is the logical port to clear from. 5728 * 5729 * This function must only be called on a timestamp index whose valid bit is 5730 * set according to ice_get_phy_tx_tstamp_ready(). 5731 */ 5732 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 5733 { 5734 switch (hw->mac_type) { 5735 case ICE_MAC_E810: 5736 return ice_clear_phy_tstamp_e810(hw, block, idx); 5737 case ICE_MAC_GENERIC: 5738 return ice_clear_phy_tstamp_e82x(hw, block, idx); 5739 case ICE_MAC_GENERIC_3K_E825: 5740 return ice_clear_ptp_tstamp_eth56g(hw, block, idx); 5741 default: 5742 return -EOPNOTSUPP; 5743 } 5744 } 5745 5746 /** 5747 * ice_get_pf_c827_idx - find and return the C827 index for the current pf 5748 * @hw: pointer to the hw struct 5749 * @idx: index of the found C827 PHY 5750 * Return: 5751 * * 0 - success 5752 * * negative - failure 5753 */ 5754 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) 5755 { 5756 struct ice_aqc_get_link_topo cmd; 5757 u8 node_part_number; 5758 u16 node_handle; 5759 int status; 5760 u8 ctx; 5761 5762 if (hw->mac_type != ICE_MAC_E810) 5763 return -ENODEV; 5764 5765 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { 5766 *idx = C827_0; 5767 return 0; 5768 } 5769 5770 memset(&cmd, 0, sizeof(cmd)); 5771 5772 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S; 5773 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S; 5774 cmd.addr.topo_params.node_type_ctx = ctx; 5775 5776 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 5777 &node_handle); 5778 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 5779 return -ENOENT; 5780 5781 if (node_handle == E810C_QSFP_C827_0_HANDLE) 5782 *idx = C827_0; 5783 else if (node_handle == E810C_QSFP_C827_1_HANDLE) 5784 *idx = C827_1; 5785 else 5786 return -EIO; 5787 5788 return 0; 5789 } 5790 5791 /** 5792 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks 5793 * @hw: pointer to the HW struct 5794 */ 5795 void ice_ptp_reset_ts_memory(struct ice_hw *hw) 5796 { 5797 switch (hw->mac_type) { 5798 case ICE_MAC_GENERIC: 5799 ice_ptp_reset_ts_memory_e82x(hw); 5800 break; 5801 case ICE_MAC_GENERIC_3K_E825: 5802 ice_ptp_reset_ts_memory_eth56g(hw); 5803 break; 5804 case ICE_MAC_E810: 5805 default: 5806 return; 5807 } 5808 } 5809 5810 /** 5811 * ice_ptp_init_phc - Initialize PTP hardware clock 5812 * @hw: pointer to the HW struct 5813 * 5814 * Perform the steps required to initialize the PTP hardware clock. 5815 */ 5816 int ice_ptp_init_phc(struct ice_hw *hw) 5817 { 5818 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5819 5820 /* Enable source clocks */ 5821 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 5822 5823 /* Clear event err indications for auxiliary pins */ 5824 (void)rd32(hw, GLTSYN_STAT(src_idx)); 5825 5826 switch (hw->mac_type) { 5827 case ICE_MAC_E810: 5828 return ice_ptp_init_phc_e810(hw); 5829 case ICE_MAC_E830: 5830 ice_ptp_init_phc_e830(hw); 5831 return 0; 5832 case ICE_MAC_GENERIC: 5833 return ice_ptp_init_phc_e82x(hw); 5834 case ICE_MAC_GENERIC_3K_E825: 5835 return ice_ptp_init_phc_e825c(hw); 5836 default: 5837 return -EOPNOTSUPP; 5838 } 5839 } 5840 5841 /** 5842 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication 5843 * @hw: pointer to the HW struct 5844 * @block: the timestamp block to check 5845 * @tstamp_ready: storage for the PHY Tx memory status information 5846 * 5847 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value 5848 * which indicates which timestamps in the block may be captured. A set bit 5849 * means the timestamp can be read. An unset bit means the timestamp is not 5850 * ready and software should avoid reading the register. 5851 */ 5852 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) 5853 { 5854 switch (hw->mac_type) { 5855 case ICE_MAC_E810: 5856 return ice_get_phy_tx_tstamp_ready_e810(hw, block, 5857 tstamp_ready); 5858 case ICE_MAC_E830: 5859 ice_get_phy_tx_tstamp_ready_e830(hw, block, tstamp_ready); 5860 return 0; 5861 case ICE_MAC_GENERIC: 5862 return ice_get_phy_tx_tstamp_ready_e82x(hw, block, 5863 tstamp_ready); 5864 case ICE_MAC_GENERIC_3K_E825: 5865 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, 5866 tstamp_ready); 5867 default: 5868 return -EOPNOTSUPP; 5869 } 5870 } 5871 5872 /** 5873 * ice_check_phy_tx_tstamp_ready - Check PHY Tx timestamp memory status 5874 * @hw: pointer to the HW struct 5875 * 5876 * Check the PHY for Tx timestamp memory status on all ports. If you need to 5877 * see individual timestamp status for each index, use 5878 * ice_get_phy_tx_tstamp_ready() instead. 5879 * 5880 * Return: 1 if any port has timestamps available, 0 if there are no timestamps 5881 * available, and a negative error code on failure. 5882 */ 5883 int ice_check_phy_tx_tstamp_ready(struct ice_hw *hw) 5884 { 5885 switch (hw->mac_type) { 5886 case ICE_MAC_E810: 5887 return ice_check_phy_tx_tstamp_ready_e810(hw); 5888 case ICE_MAC_E830: 5889 return ice_check_phy_tx_tstamp_ready_e830(hw); 5890 case ICE_MAC_GENERIC: 5891 return ice_check_phy_tx_tstamp_ready_e82x(hw); 5892 case ICE_MAC_GENERIC_3K_E825: 5893 return ice_check_phy_tx_tstamp_ready_eth56g(hw); 5894 default: 5895 return -EOPNOTSUPP; 5896 } 5897 } 5898 5899 /** 5900 * ice_cgu_get_pin_desc_e823 - get pin description array 5901 * @hw: pointer to the hw struct 5902 * @input: if request is done against input or output pin 5903 * @size: number of inputs/outputs 5904 * 5905 * Return: pointer to pin description array associated to given hw. 5906 */ 5907 static const struct ice_cgu_pin_desc * 5908 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size) 5909 { 5910 static const struct ice_cgu_pin_desc *t; 5911 5912 if (hw->cgu_part_number == 5913 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) { 5914 if (input) { 5915 t = ice_e823_zl_cgu_inputs; 5916 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs); 5917 } else { 5918 t = ice_e823_zl_cgu_outputs; 5919 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs); 5920 } 5921 } else if (hw->cgu_part_number == 5922 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) { 5923 if (input) { 5924 t = ice_e823_si_cgu_inputs; 5925 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs); 5926 } else { 5927 t = ice_e823_si_cgu_outputs; 5928 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs); 5929 } 5930 } else { 5931 t = NULL; 5932 *size = 0; 5933 } 5934 5935 return t; 5936 } 5937 5938 /** 5939 * ice_cgu_get_pin_desc - get pin description array 5940 * @hw: pointer to the hw struct 5941 * @input: if request is done against input or output pins 5942 * @size: size of array returned by function 5943 * 5944 * Return: pointer to pin description array associated to given hw. 5945 */ 5946 static const struct ice_cgu_pin_desc * 5947 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size) 5948 { 5949 const struct ice_cgu_pin_desc *t = NULL; 5950 5951 switch (hw->device_id) { 5952 case ICE_DEV_ID_E810C_SFP: 5953 if (input) { 5954 t = ice_e810t_sfp_cgu_inputs; 5955 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs); 5956 } else { 5957 t = ice_e810t_sfp_cgu_outputs; 5958 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs); 5959 } 5960 break; 5961 case ICE_DEV_ID_E810C_QSFP: 5962 if (input) { 5963 t = ice_e810t_qsfp_cgu_inputs; 5964 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs); 5965 } else { 5966 t = ice_e810t_qsfp_cgu_outputs; 5967 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs); 5968 } 5969 break; 5970 case ICE_DEV_ID_E823L_10G_BASE_T: 5971 case ICE_DEV_ID_E823L_1GBE: 5972 case ICE_DEV_ID_E823L_BACKPLANE: 5973 case ICE_DEV_ID_E823L_QSFP: 5974 case ICE_DEV_ID_E823L_SFP: 5975 case ICE_DEV_ID_E823C_10G_BASE_T: 5976 case ICE_DEV_ID_E823C_BACKPLANE: 5977 case ICE_DEV_ID_E823C_QSFP: 5978 case ICE_DEV_ID_E823C_SFP: 5979 case ICE_DEV_ID_E823C_SGMII: 5980 t = ice_cgu_get_pin_desc_e823(hw, input, size); 5981 break; 5982 default: 5983 break; 5984 } 5985 5986 return t; 5987 } 5988 5989 /** 5990 * ice_cgu_get_num_pins - get pin description array size 5991 * @hw: pointer to the hw struct 5992 * @input: if request is done against input or output pins 5993 * 5994 * Return: size of pin description array for given hw. 5995 */ 5996 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input) 5997 { 5998 const struct ice_cgu_pin_desc *t; 5999 int size; 6000 6001 t = ice_cgu_get_pin_desc(hw, input, &size); 6002 if (t) 6003 return size; 6004 6005 return 0; 6006 } 6007 6008 /** 6009 * ice_cgu_get_pin_type - get pin's type 6010 * @hw: pointer to the hw struct 6011 * @pin: pin index 6012 * @input: if request is done against input or output pin 6013 * 6014 * Return: type of a pin. 6015 */ 6016 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input) 6017 { 6018 const struct ice_cgu_pin_desc *t; 6019 int t_size; 6020 6021 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6022 6023 if (!t) 6024 return 0; 6025 6026 if (pin >= t_size) 6027 return 0; 6028 6029 return t[pin].type; 6030 } 6031 6032 /** 6033 * ice_cgu_get_pin_freq_supp - get pin's supported frequency 6034 * @hw: pointer to the hw struct 6035 * @pin: pin index 6036 * @input: if request is done against input or output pin 6037 * @num: output number of supported frequencies 6038 * 6039 * Get frequency supported number and array of supported frequencies. 6040 * 6041 * Return: array of supported frequencies for given pin. 6042 */ 6043 struct dpll_pin_frequency * 6044 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num) 6045 { 6046 const struct ice_cgu_pin_desc *t; 6047 int t_size; 6048 6049 *num = 0; 6050 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6051 if (!t) 6052 return NULL; 6053 if (pin >= t_size) 6054 return NULL; 6055 *num = t[pin].freq_supp_num; 6056 6057 return t[pin].freq_supp; 6058 } 6059 6060 /** 6061 * ice_cgu_get_pin_name - get pin's name 6062 * @hw: pointer to the hw struct 6063 * @pin: pin index 6064 * @input: if request is done against input or output pin 6065 * 6066 * Return: 6067 * * null terminated char array with name 6068 * * NULL in case of failure 6069 */ 6070 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input) 6071 { 6072 const struct ice_cgu_pin_desc *t; 6073 int t_size; 6074 6075 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6076 6077 if (!t) 6078 return NULL; 6079 6080 if (pin >= t_size) 6081 return NULL; 6082 6083 return t[pin].name; 6084 } 6085 6086 /** 6087 * ice_get_cgu_state - get the state of the DPLL 6088 * @hw: pointer to the hw struct 6089 * @dpll_idx: Index of internal DPLL unit 6090 * @last_dpll_state: last known state of DPLL 6091 * @pin: pointer to a buffer for returning currently active pin 6092 * @ref_state: reference clock state 6093 * @eec_mode: eec mode of the DPLL 6094 * @phase_offset: pointer to a buffer for returning phase offset 6095 * @dpll_state: state of the DPLL (output) 6096 * 6097 * This function will read the state of the DPLL(dpll_idx). Non-null 6098 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to 6099 * retrieve currently active pin, state, mode and phase_offset respectively. 6100 * 6101 * Return: state of the DPLL 6102 */ 6103 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, 6104 enum dpll_lock_status last_dpll_state, u8 *pin, 6105 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, 6106 enum dpll_lock_status *dpll_state) 6107 { 6108 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config; 6109 s64 hw_phase_offset; 6110 int status; 6111 6112 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state, 6113 &hw_dpll_state, &hw_config, 6114 &hw_phase_offset, &hw_eec_mode); 6115 if (status) 6116 return status; 6117 6118 if (pin) 6119 /* current ref pin in dpll_state_refsel_status_X register */ 6120 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL; 6121 if (phase_offset) 6122 *phase_offset = hw_phase_offset; 6123 if (ref_state) 6124 *ref_state = hw_ref_state; 6125 if (eec_mode) 6126 *eec_mode = hw_eec_mode; 6127 if (!dpll_state) 6128 return 0; 6129 6130 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ 6131 * it would never return to FREERUN. This aligns to ITU-T G.781 6132 * Recommendation. We cannot report HOLDOVER as HO memory is cleared 6133 * while switching to another reference. 6134 * Only for situations where previous state was either: "LOCKED without 6135 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN. 6136 */ 6137 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) { 6138 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY) 6139 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 6140 else 6141 *dpll_state = DPLL_LOCK_STATUS_LOCKED; 6142 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ || 6143 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) { 6144 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER; 6145 } else { 6146 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED; 6147 } 6148 6149 return 0; 6150 } 6151 6152 /** 6153 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins 6154 * @hw: pointer to the hw struct 6155 * @base_idx: returns index of first recovered clock pin on device 6156 * @pin_num: returns number of recovered clock pins available on device 6157 * 6158 * Based on hw provide caller info about recovery clock pins available on the 6159 * board. 6160 * 6161 * Return: 6162 * * 0 - success, information is valid 6163 * * negative - failure, information is not valid 6164 */ 6165 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num) 6166 { 6167 u8 phy_idx; 6168 int ret; 6169 6170 switch (hw->device_id) { 6171 case ICE_DEV_ID_E810C_SFP: 6172 case ICE_DEV_ID_E810C_QSFP: 6173 6174 ret = ice_get_pf_c827_idx(hw, &phy_idx); 6175 if (ret) 6176 return ret; 6177 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN); 6178 *pin_num = ICE_E810_RCLK_PINS_NUM; 6179 ret = 0; 6180 break; 6181 case ICE_DEV_ID_E823L_10G_BASE_T: 6182 case ICE_DEV_ID_E823L_1GBE: 6183 case ICE_DEV_ID_E823L_BACKPLANE: 6184 case ICE_DEV_ID_E823L_QSFP: 6185 case ICE_DEV_ID_E823L_SFP: 6186 case ICE_DEV_ID_E823C_10G_BASE_T: 6187 case ICE_DEV_ID_E823C_BACKPLANE: 6188 case ICE_DEV_ID_E823C_QSFP: 6189 case ICE_DEV_ID_E823C_SFP: 6190 case ICE_DEV_ID_E823C_SGMII: 6191 *pin_num = ICE_E82X_RCLK_PINS_NUM; 6192 ret = 0; 6193 if (hw->cgu_part_number == 6194 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) 6195 *base_idx = ZL_REF1P; 6196 else if (hw->cgu_part_number == 6197 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) 6198 *base_idx = SI_REF1P; 6199 else 6200 ret = -ENODEV; 6201 break; 6202 case ICE_DEV_ID_E825C_BACKPLANE: 6203 case ICE_DEV_ID_E825C_QSFP: 6204 case ICE_DEV_ID_E825C_SFP: 6205 case ICE_DEV_ID_E825C_SGMII: 6206 *pin_num = ICE_SYNCE_CLK_NUM; 6207 *base_idx = 0; 6208 ret = 0; 6209 break; 6210 default: 6211 ret = -ENODEV; 6212 break; 6213 } 6214 6215 return ret; 6216 } 6217 6218 /** 6219 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities 6220 * @hw: pointer to the hw struct 6221 * @pin_id: id of a pin 6222 * @caps: capabilities to modify 6223 * 6224 * Return: 6225 * * 0 - success, state capabilities were modified 6226 * * negative - failure, capabilities were not modified 6227 */ 6228 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, 6229 unsigned long *caps) 6230 { 6231 bool can_change = true; 6232 6233 switch (hw->device_id) { 6234 case ICE_DEV_ID_E810C_SFP: 6235 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3) 6236 can_change = false; 6237 break; 6238 case ICE_DEV_ID_E810C_QSFP: 6239 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4) 6240 can_change = false; 6241 break; 6242 case ICE_DEV_ID_E823L_10G_BASE_T: 6243 case ICE_DEV_ID_E823L_1GBE: 6244 case ICE_DEV_ID_E823L_BACKPLANE: 6245 case ICE_DEV_ID_E823L_QSFP: 6246 case ICE_DEV_ID_E823L_SFP: 6247 case ICE_DEV_ID_E823C_10G_BASE_T: 6248 case ICE_DEV_ID_E823C_BACKPLANE: 6249 case ICE_DEV_ID_E823C_QSFP: 6250 case ICE_DEV_ID_E823C_SFP: 6251 case ICE_DEV_ID_E823C_SGMII: 6252 if (hw->cgu_part_number == 6253 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 && 6254 pin_id == ZL_OUT2) 6255 can_change = false; 6256 else if (hw->cgu_part_number == 6257 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 && 6258 pin_id == SI_OUT1) 6259 can_change = false; 6260 break; 6261 default: 6262 return -EINVAL; 6263 } 6264 if (can_change) 6265 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6266 else 6267 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6268 6269 return 0; 6270 } 6271