1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 /* 3 * Copyright (C) 2026 Amlogic, Inc. All rights reserved 4 */ 5 6 #include <dt-bindings/clock/amlogic,a9-peripherals-clkc.h> 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include "clk-regmap.h" 11 #include "clk-dualdiv.h" 12 #include "meson-clkc-utils.h" 13 #include "vid-pll-div.h" 14 15 #define SYS_CLK_EN0_REG0 0x30 16 #define SYS_CLK_EN0_REG1 0x34 17 #define SYS_CLK_EN0_REG2 0x38 18 #define SYS_CLK_EN0_REG3 0x3c 19 #define SD_EMMC_CLK_CTRL0 0x90 20 #define SD_EMMC_CLK_CTRL1 0x94 21 #define PWM_CLK_H_CTRL 0xbc 22 #define PWM_CLK_I_CTRL 0xc0 23 #define PWM_CLK_J_CTRL 0xc4 24 #define PWM_CLK_K_CTRL 0xc8 25 #define PWM_CLK_L_CTRL 0xcc 26 #define PWM_CLK_M_CTRL 0xd0 27 #define PWM_CLK_N_CTRL 0xd4 28 #define SPISG_CLK_CTRL 0x100 29 #define SPISG_CLK_CTRL1 0x104 30 #define SAR_CLK_CTRL 0x150 31 #define AMFC_CLK_CTRL 0x154 32 #define NNA_CLK_CTRL 0x15c 33 #define USB_CLK_CTRL 0x160 34 #define PCIE_TL_CLK_CTRL 0x164 35 #define CMPR_CLK_CTRL 0x168 36 #define DEWARP_CLK_CTRL 0x16c 37 #define SC_CLK_CTRL 0x170 38 #define DPTX_CLK_CTRL 0x178 39 #define ISP_CLK_CTRL 0x17c 40 #define CVE_CLK_CTRL 0x180 41 #define PP_CLK_CTRL 0x184 42 #define GLB_CLK_CTRL 0x188 43 #define USB_CLK_CTRL0 0x18c 44 #define USB_CLK_CTRL1 0x190 45 #define CAN_CLK_CTRL 0x194 46 #define CAN_CLK_CTRL1 0x198 47 #define I3C_CLK_CTRL 0x19c 48 #define TS_CLK_CTRL 0x1a0 49 #define ETH_CLK_CTRL 0x1a4 50 #define GEN_CLK_CTRL 0x1a8 51 #define CLK12_24_CTRL 0x1ac 52 #define MALI_CLK_CTRL 0x200 53 #define MALI_STACK_CLK_CTRL 0x204 54 #define DSPA_CLK_CTRL 0x220 55 #define HEVCF_CLK_CTRL 0x240 56 #define HCODEC_CLK_CTRL 0x244 57 #define VPU_CLK_CTRL 0x260 58 #define VAPB_CLK_CTRL 0x268 59 #define VPU_CLKB_CTRL 0x280 60 #define HDMI_CLK_CTRL 0x284 61 #define HTX_CLK_CTRL 0x28c 62 #define HTX_CLK_CTRL1 0x290 63 #define HRX_CLK_CTRL 0x294 64 #define HRX_CLK_CTRL1 0x298 65 #define HRX_CLK_CTRL2 0x29c 66 #define HRX_CLK_CTRL3 0x2a0 67 #define VID_LOCK_CLK_CTRL 0x2a4 68 #define VDIN_MEAS_CLK_CTRL 0x2a8 69 #define VID_PLL_CLK_DIV 0x2b0 70 #define VID_CLK_CTRL 0x2c0 71 #define VID_CLK_CTRL2 0x2c4 72 #define VID_CLK_DIV 0x2c8 73 #define VIID_CLK_DIV 0x2cc 74 #define VIID_CLK_CTRL 0x2d0 75 #define MIPI_CSI_PHY_CLK_CTRL 0x2e0 76 #define DSI_MEAS_CLK_CTRL 0x2f4 77 78 #define A9_COMP_SEL(_name, _reg, _shift, _mask, _pdata, _table) \ 79 MESON_COMP_SEL(a9_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0) 80 81 #define A9_COMP_DIV(_name, _reg, _shift, _width) \ 82 MESON_COMP_DIV(a9_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) 83 84 #define A9_COMP_GATE(_name, _reg, _bit, _iflags) \ 85 MESON_COMP_GATE(a9_, _name, _reg, _bit, CLK_SET_RATE_PARENT | (_iflags)) 86 87 static const struct clk_parent_data a9_sys_pclk_parents = { .fw_name = "sys" }; 88 89 #define A9_SYS_PCLK(_name, _reg, _bit) \ 90 MESON_PCLK(a9_##_name, _reg, _bit, &a9_sys_pclk_parents, 0) 91 92 static A9_SYS_PCLK(sys_am_axi, SYS_CLK_EN0_REG0, 0); 93 static A9_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG0, 1); 94 static A9_SYS_PCLK(sys_mipi_dsi0, SYS_CLK_EN0_REG0, 3); 95 static A9_SYS_PCLK(sys_eth_phy, SYS_CLK_EN0_REG0, 4); 96 static A9_SYS_PCLK(sys_amfc, SYS_CLK_EN0_REG0, 5); 97 static A9_SYS_PCLK(sys_mali, SYS_CLK_EN0_REG0, 6); 98 static A9_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 7); 99 static A9_SYS_PCLK(sys_eth_axi, SYS_CLK_EN0_REG0, 8); 100 static A9_SYS_PCLK(sys_dp_apb, SYS_CLK_EN0_REG0, 9); 101 static A9_SYS_PCLK(sys_edptx_apb, SYS_CLK_EN0_REG0, 10); 102 static A9_SYS_PCLK(sys_u3hsg, SYS_CLK_EN0_REG0, 11); 103 static A9_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14); 104 static A9_SYS_PCLK(sys_glb, SYS_CLK_EN0_REG0, 15); 105 static A9_SYS_PCLK(sys_combo_dphy_apb, SYS_CLK_EN0_REG0, 17); 106 static A9_SYS_PCLK(sys_hdmirx_apb, SYS_CLK_EN0_REG0, 18); 107 static A9_SYS_PCLK(sys_hdmirx_pclk, SYS_CLK_EN0_REG0, 19); 108 static A9_SYS_PCLK(sys_mipi_dsi0_phy, SYS_CLK_EN0_REG0, 20); 109 static A9_SYS_PCLK(sys_can0, SYS_CLK_EN0_REG0, 21); 110 static A9_SYS_PCLK(sys_can1, SYS_CLK_EN0_REG0, 22); 111 static A9_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG0, 24); 112 static A9_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG0, 25); 113 static A9_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG0, 26); 114 static A9_SYS_PCLK(sys_sc, SYS_CLK_EN0_REG0, 27); 115 static A9_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG0, 28); 116 static A9_SYS_PCLK(sys_mipi_isp, SYS_CLK_EN0_REG0, 29); 117 static A9_SYS_PCLK(sys_msr, SYS_CLK_EN0_REG0, 30); 118 static A9_SYS_PCLK(sys_audio, SYS_CLK_EN0_REG1, 0); 119 static A9_SYS_PCLK(sys_mipi_dsi1, SYS_CLK_EN0_REG1, 1); 120 static A9_SYS_PCLK(sys_mipi_dsi1_phy, SYS_CLK_EN0_REG1, 2); 121 static A9_SYS_PCLK(sys_eth, SYS_CLK_EN0_REG1, 3); 122 static A9_SYS_PCLK(sys_eth_1g_mac, SYS_CLK_EN0_REG1, 4); 123 static A9_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 5); 124 static A9_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG1, 10); 125 static A9_SYS_PCLK(sys_ts_a55, SYS_CLK_EN0_REG1, 11); 126 static A9_SYS_PCLK(sys_eth_1g_axi, SYS_CLK_EN0_REG1, 12); 127 static A9_SYS_PCLK(sys_ts_dos, SYS_CLK_EN0_REG1, 13); 128 static A9_SYS_PCLK(sys_u3drd_b, SYS_CLK_EN0_REG1, 14); 129 static A9_SYS_PCLK(sys_ts_core, SYS_CLK_EN0_REG1, 15); 130 static A9_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG1, 16); 131 static A9_SYS_PCLK(sys_csi_dig_clkin, SYS_CLK_EN0_REG1, 18); 132 static A9_SYS_PCLK(sys_cve, SYS_CLK_EN0_REG1, 19); 133 static A9_SYS_PCLK(sys_ge2d, SYS_CLK_EN0_REG1, 20); 134 static A9_SYS_PCLK(sys_spisg, SYS_CLK_EN0_REG1, 21); 135 static A9_SYS_PCLK(sys_u2h, SYS_CLK_EN0_REG1, 23); 136 static A9_SYS_PCLK(sys_pcie_mac_a, SYS_CLK_EN0_REG1, 24); 137 static A9_SYS_PCLK(sys_u3drd_a, SYS_CLK_EN0_REG1, 25); 138 static A9_SYS_PCLK(sys_u2drd, SYS_CLK_EN0_REG1, 26); 139 static A9_SYS_PCLK(sys_pcie_phy, SYS_CLK_EN0_REG1, 27); 140 static A9_SYS_PCLK(sys_pcie_mac_b, SYS_CLK_EN0_REG1, 28); 141 static A9_SYS_PCLK(sys_periph, SYS_CLK_EN0_REG1, 29); 142 static A9_SYS_PCLK(sys_pio, SYS_CLK_EN0_REG2, 0); 143 static A9_SYS_PCLK(sys_i3c, SYS_CLK_EN0_REG2, 1); 144 static A9_SYS_PCLK(sys_i2c_m_e, SYS_CLK_EN0_REG2, 2); 145 static A9_SYS_PCLK(sys_i2c_m_f, SYS_CLK_EN0_REG2, 3); 146 static A9_SYS_PCLK(sys_hdmitx_apb, SYS_CLK_EN0_REG2, 4); 147 static A9_SYS_PCLK(sys_i2c_m_i, SYS_CLK_EN0_REG2, 5); 148 static A9_SYS_PCLK(sys_i2c_m_g, SYS_CLK_EN0_REG2, 6); 149 static A9_SYS_PCLK(sys_i2c_m_h, SYS_CLK_EN0_REG2, 7); 150 static A9_SYS_PCLK(sys_hdmi20_aes, SYS_CLK_EN0_REG2, 9); 151 static A9_SYS_PCLK(sys_csi2_host, SYS_CLK_EN0_REG2, 16); 152 static A9_SYS_PCLK(sys_csi2_adapt, SYS_CLK_EN0_REG2, 17); 153 static A9_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG2, 21); 154 static A9_SYS_PCLK(sys_pp_dma, SYS_CLK_EN0_REG2, 22); 155 static A9_SYS_PCLK(sys_pp_wrapper, SYS_CLK_EN0_REG2, 23); 156 static A9_SYS_PCLK(sys_vpu_intr, SYS_CLK_EN0_REG2, 25); 157 static A9_SYS_PCLK(sys_csi2_phy, SYS_CLK_EN0_REG2, 27); 158 static A9_SYS_PCLK(sys_saradc, SYS_CLK_EN0_REG2, 28); 159 static A9_SYS_PCLK(sys_pwm_j, SYS_CLK_EN0_REG2, 30); 160 static A9_SYS_PCLK(sys_pwm_i, SYS_CLK_EN0_REG2, 31); 161 static A9_SYS_PCLK(sys_pwm_h, SYS_CLK_EN0_REG3, 0); 162 static A9_SYS_PCLK(sys_pwm_n, SYS_CLK_EN0_REG3, 8); 163 static A9_SYS_PCLK(sys_pwm_m, SYS_CLK_EN0_REG3, 9); 164 static A9_SYS_PCLK(sys_pwm_l, SYS_CLK_EN0_REG3, 10); 165 static A9_SYS_PCLK(sys_pwm_k, SYS_CLK_EN0_REG3, 11); 166 167 /* Channel 5 is unconnected. */ 168 static u32 a9_sd_emmc_parents_val_table[] = { 0, 1, 2, 3, 4, 6, 7 }; 169 static const struct clk_parent_data a9_sd_emmc_parents[] = { 170 { .fw_name = "xtal", }, 171 { .fw_name = "fdiv2", }, 172 { .fw_name = "fdiv3", }, 173 { .fw_name = "hifi0", }, 174 { .fw_name = "fdiv2p5", }, 175 { .fw_name = "gp1", }, 176 { .fw_name = "gp0", } 177 }; 178 179 static A9_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL0, 9, 0x7, a9_sd_emmc_parents, 180 a9_sd_emmc_parents_val_table); 181 static A9_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL0, 0, 7); 182 static A9_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL0, 8, 0); 183 184 static A9_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL0, 25, 0x7, a9_sd_emmc_parents, 185 a9_sd_emmc_parents_val_table); 186 static A9_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL0, 16, 7); 187 static A9_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL0, 24, 0); 188 189 static A9_COMP_SEL(sd_emmc_c, SD_EMMC_CLK_CTRL1, 9, 0x7, a9_sd_emmc_parents, 190 a9_sd_emmc_parents_val_table); 191 static A9_COMP_DIV(sd_emmc_c, SD_EMMC_CLK_CTRL1, 0, 7); 192 static A9_COMP_GATE(sd_emmc_c, SD_EMMC_CLK_CTRL1, 8, 0); 193 194 static const struct clk_parent_data a9_pwm_parents[] = { 195 { .fw_name = "xtal", }, 196 { .fw_name = "fdiv5", }, 197 { .fw_name = "fdiv4", }, 198 { .fw_name = "fdiv3", } 199 }; 200 201 static A9_COMP_SEL(pwm_h, PWM_CLK_H_CTRL, 9, 0x7, a9_pwm_parents, NULL); 202 static A9_COMP_DIV(pwm_h, PWM_CLK_H_CTRL, 0, 8); 203 static A9_COMP_GATE(pwm_h, PWM_CLK_H_CTRL, 8, 0); 204 205 static A9_COMP_SEL(pwm_i, PWM_CLK_I_CTRL, 9, 0x7, a9_pwm_parents, NULL); 206 static A9_COMP_DIV(pwm_i, PWM_CLK_I_CTRL, 0, 8); 207 static A9_COMP_GATE(pwm_i, PWM_CLK_I_CTRL, 8, 0); 208 209 static A9_COMP_SEL(pwm_j, PWM_CLK_J_CTRL, 9, 0x7, a9_pwm_parents, NULL); 210 static A9_COMP_DIV(pwm_j, PWM_CLK_J_CTRL, 0, 8); 211 static A9_COMP_GATE(pwm_j, PWM_CLK_J_CTRL, 8, 0); 212 213 static A9_COMP_SEL(pwm_k, PWM_CLK_K_CTRL, 9, 0x7, a9_pwm_parents, NULL); 214 static A9_COMP_DIV(pwm_k, PWM_CLK_K_CTRL, 0, 8); 215 static A9_COMP_GATE(pwm_k, PWM_CLK_K_CTRL, 8, 0); 216 217 static A9_COMP_SEL(pwm_l, PWM_CLK_L_CTRL, 9, 0x7, a9_pwm_parents, NULL); 218 static A9_COMP_DIV(pwm_l, PWM_CLK_L_CTRL, 0, 8); 219 static A9_COMP_GATE(pwm_l, PWM_CLK_L_CTRL, 8, 0); 220 221 static A9_COMP_SEL(pwm_m, PWM_CLK_M_CTRL, 9, 0x7, a9_pwm_parents, NULL); 222 static A9_COMP_DIV(pwm_m, PWM_CLK_M_CTRL, 0, 8); 223 static A9_COMP_GATE(pwm_m, PWM_CLK_M_CTRL, 8, 0); 224 225 static A9_COMP_SEL(pwm_n, PWM_CLK_N_CTRL, 9, 0x7, a9_pwm_parents, NULL); 226 static A9_COMP_DIV(pwm_n, PWM_CLK_N_CTRL, 0, 8); 227 static A9_COMP_GATE(pwm_n, PWM_CLK_N_CTRL, 8, 0); 228 229 static const struct clk_parent_data a9_spisg_parents[] = { 230 { .fw_name = "xtal", }, 231 { .fw_name = "sys", }, 232 { .fw_name = "fdiv4", }, 233 { .fw_name = "fdiv3", }, 234 { .fw_name = "fdiv2", }, 235 { .fw_name = "fdiv5", }, 236 { .fw_name = "fdiv7", }, 237 { .fw_name = "gp0", } 238 }; 239 240 static A9_COMP_SEL(spisg0, SPISG_CLK_CTRL, 9, 0x7, a9_spisg_parents, NULL); 241 static A9_COMP_DIV(spisg0, SPISG_CLK_CTRL, 0, 6); 242 static A9_COMP_GATE(spisg0, SPISG_CLK_CTRL, 8, 0); 243 244 static A9_COMP_SEL(spisg1, SPISG_CLK_CTRL, 25, 0x7, a9_spisg_parents, NULL); 245 static A9_COMP_DIV(spisg1, SPISG_CLK_CTRL, 16, 6); 246 static A9_COMP_GATE(spisg1, SPISG_CLK_CTRL, 24, 0); 247 248 static A9_COMP_SEL(spisg2, SPISG_CLK_CTRL1, 9, 0x7, a9_spisg_parents, NULL); 249 static A9_COMP_DIV(spisg2, SPISG_CLK_CTRL1, 0, 6); 250 static A9_COMP_GATE(spisg2, SPISG_CLK_CTRL1, 8, 0); 251 252 static const struct clk_parent_data a9_saradc_parents[] = { 253 { .fw_name = "xtal", }, 254 { .fw_name = "sys", } 255 }; 256 257 static A9_COMP_SEL(saradc, SAR_CLK_CTRL, 9, 0x7, a9_saradc_parents, NULL); 258 static A9_COMP_DIV(saradc, SAR_CLK_CTRL, 0, 8); 259 static A9_COMP_GATE(saradc, SAR_CLK_CTRL, 8, 0); 260 261 static const struct clk_parent_data a9_amfc_parents[] = { 262 { .fw_name = "xtal", }, 263 { .fw_name = "sys", }, 264 { .fw_name = "fdiv2", }, 265 { .fw_name = "fdiv2p5", }, 266 { .fw_name = "fdiv3", }, 267 { .fw_name = "fdiv4", }, 268 { .fw_name = "fdiv5", }, 269 { .fw_name = "fdiv7", } 270 }; 271 272 static A9_COMP_SEL(amfc, AMFC_CLK_CTRL, 9, 0x7, a9_amfc_parents, NULL); 273 static A9_COMP_DIV(amfc, AMFC_CLK_CTRL, 0, 6); 274 static A9_COMP_GATE(amfc, AMFC_CLK_CTRL, 8, 0); 275 276 static const struct clk_parent_data a9_nna_parents[] = { 277 { .fw_name = "xtal", }, 278 { .fw_name = "fdiv2p5", }, 279 { .fw_name = "fdiv4", }, 280 { .fw_name = "fdiv3", }, 281 { .fw_name = "fdiv5", }, 282 { .fw_name = "fdiv2", }, 283 { .fw_name = "gp2", }, 284 { .fw_name = "hifi0", } 285 }; 286 287 static A9_COMP_SEL(nna, NNA_CLK_CTRL, 9, 0x7, a9_nna_parents, NULL); 288 static A9_COMP_DIV(nna, NNA_CLK_CTRL, 0, 7); 289 static A9_COMP_GATE(nna, NNA_CLK_CTRL, 8, 0); 290 291 /* Channel 5 and 6 are unconnected. */ 292 static u32 a9_usb_250m_parents_val_table[] = { 0, 1, 2, 3, 4, 7 }; 293 static const struct clk_parent_data a9_usb_250m_parents[] = { 294 { .fw_name = "fdiv4", }, 295 { .fw_name = "fdiv3", }, 296 { .fw_name = "fdiv5", }, 297 { .fw_name = "fdiv2", }, 298 { .fw_name = "fdiv7", }, 299 { .fw_name = "fdiv2p5", } 300 }; 301 302 static A9_COMP_SEL(usb_250m, USB_CLK_CTRL, 9, 0x7, a9_usb_250m_parents, 303 a9_usb_250m_parents_val_table); 304 static A9_COMP_DIV(usb_250m, USB_CLK_CTRL, 0, 7); 305 static A9_COMP_GATE(usb_250m, USB_CLK_CTRL, 8, 0); 306 307 static const struct clk_parent_data a9_usb_48m_pre_parents[] = { 308 { .fw_name = "gp0", }, 309 { .fw_name = "gp1", }, 310 { .fw_name = "gp2", }, 311 { .fw_name = "fdiv2", } 312 }; 313 314 static A9_COMP_SEL(usb_48m_pre, USB_CLK_CTRL, 25, 0x3, a9_usb_48m_pre_parents, NULL); 315 static A9_COMP_DIV(usb_48m_pre, USB_CLK_CTRL, 16, 7); 316 static A9_COMP_GATE(usb_48m_pre, USB_CLK_CTRL, 24, 0); 317 318 static const struct clk_parent_data a9_pcie_tl_parents[] = { 319 { .fw_name = "fdiv4", }, 320 { .fw_name = "fdiv3", }, 321 { .fw_name = "fdiv5", }, 322 { .fw_name = "fdiv2", }, 323 { .fw_name = "fdiv2p5", }, 324 { .fw_name = "gp0", }, 325 { .fw_name = "sys", }, 326 { .fw_name = "xtal", } 327 }; 328 329 static A9_COMP_SEL(pcie0_tl, PCIE_TL_CLK_CTRL, 9, 0x7, a9_pcie_tl_parents, NULL); 330 static A9_COMP_DIV(pcie0_tl, PCIE_TL_CLK_CTRL, 0, 7); 331 static A9_COMP_GATE(pcie0_tl, PCIE_TL_CLK_CTRL, 8, 0); 332 333 static A9_COMP_SEL(pcie1_tl, PCIE_TL_CLK_CTRL, 25, 0x7, a9_pcie_tl_parents, NULL); 334 static A9_COMP_DIV(pcie1_tl, PCIE_TL_CLK_CTRL, 16, 7); 335 static A9_COMP_GATE(pcie1_tl, PCIE_TL_CLK_CTRL, 24, 0); 336 337 static const struct clk_parent_data a9_cmpr_parents[] = { 338 { .fw_name = "xtal", }, 339 { .fw_name = "fdiv2p5", }, 340 { .fw_name = "fdiv3", }, 341 { .fw_name = "fdiv4", }, 342 { .fw_name = "fdiv5", }, 343 { .fw_name = "fdiv7", }, 344 { .fw_name = "hifi0", }, 345 { .fw_name = "gp1", } 346 }; 347 348 static A9_COMP_SEL(cmpr, CMPR_CLK_CTRL, 25, 0x7, a9_cmpr_parents, NULL); 349 static A9_COMP_DIV(cmpr, CMPR_CLK_CTRL, 16, 7); 350 static A9_COMP_GATE(cmpr, CMPR_CLK_CTRL, 24, 0); 351 352 static const struct clk_parent_data a9_dewarpa_parents[] = { 353 { .fw_name = "fdiv2p5", }, 354 { .fw_name = "fdiv3", }, 355 { .fw_name = "fdiv4", }, 356 { .fw_name = "fdiv5", }, 357 { .fw_name = "fdiv7", }, 358 { .fw_name = "gp0", }, 359 { .fw_name = "hifi0", }, 360 { .fw_name = "gp1", } 361 }; 362 363 static A9_COMP_SEL(dewarpa, DEWARP_CLK_CTRL, 9, 0x7, a9_dewarpa_parents, NULL); 364 static A9_COMP_DIV(dewarpa, DEWARP_CLK_CTRL, 0, 7); 365 static A9_COMP_GATE(dewarpa, DEWARP_CLK_CTRL, 8, 0); 366 367 static const struct clk_parent_data a9_sc_parents[] = { 368 { .fw_name = "fdiv2", }, 369 { .fw_name = "fdiv3", }, 370 { .fw_name = "fdiv5", }, 371 { .fw_name = "xtal", } 372 }; 373 374 static A9_COMP_SEL(sc_pre, SC_CLK_CTRL, 9, 0x7, a9_sc_parents, NULL); 375 static A9_COMP_DIV(sc_pre, SC_CLK_CTRL, 0, 8); 376 static A9_COMP_GATE(sc_pre, SC_CLK_CTRL, 8, 0); 377 378 static struct clk_regmap a9_sc = { 379 .data = &(struct clk_regmap_div_data) { 380 .offset = SC_CLK_CTRL, 381 .shift = 16, 382 .width = 4, 383 }, 384 .hw.init = &(struct clk_init_data) { 385 .name = "sc", 386 .ops = &clk_regmap_divider_ops, 387 .parent_hws = (const struct clk_hw *[]) { 388 &a9_sc_pre.hw 389 }, 390 .num_parents = 1, 391 .flags = CLK_SET_RATE_PARENT, 392 }, 393 }; 394 395 static const struct clk_parent_data a9_dptx_apb2_parents[] = { 396 { .fw_name = "xtal", }, 397 { .fw_name = "sys", }, 398 { .fw_name = "fdiv4", }, 399 { .fw_name = "fdiv5", } 400 }; 401 402 static A9_COMP_SEL(dptx_apb2, DPTX_CLK_CTRL, 9, 0x7, a9_dptx_apb2_parents, NULL); 403 static A9_COMP_DIV(dptx_apb2, DPTX_CLK_CTRL, 0, 7); 404 static A9_COMP_GATE(dptx_apb2, DPTX_CLK_CTRL, 8, 0); 405 406 static const struct clk_parent_data a9_dptx_aud_parents[] = { 407 { .fw_name = "xtal", }, 408 { .fw_name = "sys", }, 409 { .fw_name = "fdiv3", }, 410 { .fw_name = "fdiv4", } 411 }; 412 413 static A9_COMP_SEL(dptx_aud, DPTX_CLK_CTRL, 25, 0x7, a9_dptx_aud_parents, NULL); 414 static A9_COMP_DIV(dptx_aud, DPTX_CLK_CTRL, 16, 7); 415 static A9_COMP_GATE(dptx_aud, DPTX_CLK_CTRL, 24, 0); 416 417 static const struct clk_parent_data a9_isp_parents[] = { 418 { .fw_name = "fdiv2p5", }, 419 { .fw_name = "fdiv3", }, 420 { .fw_name = "fdiv4", }, 421 { .fw_name = "fdiv5", }, 422 { .fw_name = "gp0", }, 423 { .fw_name = "hifi0", }, 424 { .fw_name = "fdiv2", }, 425 { .fw_name = "xtal", } 426 }; 427 428 static A9_COMP_SEL(isp, ISP_CLK_CTRL, 9, 0x7, a9_isp_parents, NULL); 429 static A9_COMP_DIV(isp, ISP_CLK_CTRL, 0, 7); 430 static A9_COMP_GATE(isp, ISP_CLK_CTRL, 8, 0); 431 432 static const struct clk_parent_data a9_cve_vge_parents[] = { 433 { .fw_name = "xtal", }, 434 { .fw_name = "fdiv2p5", }, 435 { .fw_name = "fdiv3", }, 436 { .fw_name = "fdiv4", }, 437 { .fw_name = "hifi0", }, 438 { .fw_name = "fdiv5", }, 439 { .fw_name = "gp0", }, 440 { .fw_name = "rtc", } 441 }; 442 443 static A9_COMP_SEL(cve, CVE_CLK_CTRL, 9, 0x7, a9_cve_vge_parents, NULL); 444 static A9_COMP_DIV(cve, CVE_CLK_CTRL, 0, 7); 445 static A9_COMP_GATE(cve, CVE_CLK_CTRL, 8, 0); 446 447 static A9_COMP_SEL(vge, CVE_CLK_CTRL, 25, 0x7, a9_cve_vge_parents, NULL); 448 static A9_COMP_DIV(vge, CVE_CLK_CTRL, 16, 7); 449 static A9_COMP_GATE(vge, CVE_CLK_CTRL, 24, 0); 450 451 static const struct clk_parent_data a9_pp_parents[] = { 452 { .fw_name = "fdiv4", }, 453 { .fw_name = "fdiv3", }, 454 { .fw_name = "fdiv5", }, 455 { .fw_name = "fdiv2", }, 456 { .fw_name = "fdiv2p5", }, 457 { .fw_name = "gp0", }, 458 { .fw_name = "sys", }, 459 { .fw_name = "xtal", } 460 }; 461 462 static A9_COMP_SEL(pp, PP_CLK_CTRL, 9, 0x7, a9_pp_parents, NULL); 463 static A9_COMP_DIV(pp, PP_CLK_CTRL, 0, 6); 464 static A9_COMP_GATE(pp, PP_CLK_CTRL, 8, 0); 465 466 static const struct clk_parent_data a9_dspa_parents[] = { 467 { .fw_name = "xtal", }, 468 { .fw_name = "fdiv2p5", }, 469 { .fw_name = "fdiv3", }, 470 { .fw_name = "fdiv5", }, 471 { .fw_name = "gp2", }, 472 { .fw_name = "fdiv4", }, 473 { .fw_name = "hifi0", }, 474 { .fw_name = "rtc", } 475 }; 476 477 static A9_COMP_SEL(dspa_0, DSPA_CLK_CTRL, 9, 0x7, a9_dspa_parents, NULL); 478 static A9_COMP_DIV(dspa_0, DSPA_CLK_CTRL, 0, 7); 479 static A9_COMP_GATE(dspa_0, DSPA_CLK_CTRL, 8, CLK_SET_RATE_GATE); 480 481 static A9_COMP_SEL(dspa_1, DSPA_CLK_CTRL, 25, 0x7, a9_dspa_parents, NULL); 482 static A9_COMP_DIV(dspa_1, DSPA_CLK_CTRL, 16, 7); 483 static A9_COMP_GATE(dspa_1, DSPA_CLK_CTRL, 24, CLK_SET_RATE_GATE); 484 485 static struct clk_regmap a9_dspa = { 486 .data = &(struct clk_regmap_mux_data){ 487 .offset = DSPA_CLK_CTRL, 488 .mask = 0x1, 489 .shift = 31, 490 }, 491 .hw.init = &(struct clk_init_data){ 492 .name = "dspa", 493 .ops = &clk_regmap_mux_ops, 494 .parent_hws = (const struct clk_hw *[]) { 495 &a9_dspa_0.hw, 496 &a9_dspa_1.hw 497 }, 498 .num_parents = 2, 499 .flags = CLK_SET_RATE_PARENT, 500 }, 501 }; 502 503 /* Channel 6 is unconnected. */ 504 static u32 a9_glb_parents_val_table[] = { 0, 1, 2, 3, 4, 5, 7 }; 505 static const struct clk_parent_data a9_glb_parents[] = { 506 { .fw_name = "xtal", }, 507 { .hw = &a9_dspa.hw }, 508 { .fw_name = "fdiv3", }, 509 { .fw_name = "fdiv4", }, 510 { .fw_name = "fdiv5", }, 511 { .hw = &a9_isp.hw }, 512 { .fw_name = "rtc", } 513 }; 514 515 static A9_COMP_SEL(glb, GLB_CLK_CTRL, 9, 0x7, a9_glb_parents, a9_glb_parents_val_table); 516 static A9_COMP_DIV(glb, GLB_CLK_CTRL, 0, 7); 517 static A9_COMP_GATE(glb, GLB_CLK_CTRL, 8, 0); 518 519 static struct clk_regmap a9_usb_48m_dualdiv_in = { 520 .data = &(struct clk_regmap_gate_data) { 521 .offset = USB_CLK_CTRL, 522 .bit_idx = 31, 523 }, 524 .hw.init = &(struct clk_init_data) { 525 .name = "usb_48m_dualdiv_in", 526 .ops = &clk_regmap_gate_ops, 527 .parent_hws = (const struct clk_hw *[]) { 528 &a9_usb_48m_pre.hw 529 }, 530 .num_parents = 1, 531 }, 532 }; 533 534 static const struct meson_clk_dualdiv_param a9_usb_48m_dualdiv_div_table[] = { 535 { 733, 732, 8, 11, 1 }, 536 { /* sentinel */ } 537 }; 538 539 static struct clk_regmap a9_usb_48m_dualdiv_div = { 540 .data = &(struct meson_clk_dualdiv_data) { 541 .n1 = { 542 .reg_off = USB_CLK_CTRL0, 543 .shift = 0, 544 .width = 12, 545 }, 546 .n2 = { 547 .reg_off = USB_CLK_CTRL0, 548 .shift = 12, 549 .width = 12, 550 }, 551 .m1 = { 552 .reg_off = USB_CLK_CTRL1, 553 .shift = 0, 554 .width = 12, 555 }, 556 .m2 = { 557 .reg_off = USB_CLK_CTRL1, 558 .shift = 12, 559 .width = 12, 560 }, 561 .dual = { 562 .reg_off = USB_CLK_CTRL0, 563 .shift = 28, 564 .width = 1, 565 }, 566 .table = a9_usb_48m_dualdiv_div_table, 567 }, 568 .hw.init = &(struct clk_init_data) { 569 .name = "usb_48m_dualdiv_div", 570 .ops = &meson_clk_dualdiv_ops, 571 .parent_hws = (const struct clk_hw *[]) { 572 &a9_usb_48m_dualdiv_in.hw 573 }, 574 .num_parents = 1, 575 }, 576 }; 577 578 static struct clk_regmap a9_usb_48m_dualdiv_sel = { 579 .data = &(struct clk_regmap_mux_data) { 580 .offset = USB_CLK_CTRL1, 581 .mask = 0x1, 582 .shift = 24, 583 }, 584 .hw.init = &(struct clk_init_data) { 585 .name = "usb_48m_dualdiv_sel", 586 .ops = &clk_regmap_mux_ops, 587 .parent_hws = (const struct clk_hw *[]) { 588 &a9_usb_48m_dualdiv_in.hw, 589 &a9_usb_48m_dualdiv_div.hw, 590 }, 591 .num_parents = 2, 592 .flags = CLK_SET_RATE_PARENT, 593 }, 594 }; 595 596 static struct clk_regmap a9_usb_48m_dualdiv = { 597 .data = &(struct clk_regmap_gate_data) { 598 .offset = USB_CLK_CTRL0, 599 .bit_idx = 30, 600 }, 601 .hw.init = &(struct clk_init_data) { 602 .name = "usb_48m_dualdiv", 603 .ops = &clk_regmap_gate_ops, 604 .parent_hws = (const struct clk_hw *[]) { 605 &a9_usb_48m_dualdiv_sel.hw 606 }, 607 .num_parents = 1, 608 .flags = CLK_SET_RATE_PARENT, 609 }, 610 }; 611 612 static struct clk_regmap a9_usb_48m = { 613 .data = &(struct clk_regmap_mux_data) { 614 .offset = USB_CLK_CTRL1, 615 .mask = 0x3, 616 .shift = 30, 617 }, 618 .hw.init = &(struct clk_init_data) { 619 .name = "usb_48m", 620 .ops = &clk_regmap_mux_ops, 621 .parent_hws = (const struct clk_hw *[]) { 622 &a9_usb_48m_pre.hw, 623 &a9_usb_48m_dualdiv.hw, 624 }, 625 .num_parents = 2, 626 .flags = CLK_SET_RATE_PARENT, 627 }, 628 }; 629 630 /* Channel 2 is unconnected. */ 631 static u32 a9_can_pe_parents_val_table[] = { 0, 1, 3 }; 632 static const struct clk_parent_data a9_can_pe_parents[] = { 633 { .fw_name = "sys", }, 634 { .fw_name = "xtal", }, 635 { .fw_name = "fdiv5", } 636 }; 637 638 static A9_COMP_SEL(can0_pe, CAN_CLK_CTRL, 9, 0x7, a9_can_pe_parents, a9_can_pe_parents_val_table); 639 static A9_COMP_DIV(can0_pe, CAN_CLK_CTRL, 0, 7); 640 static A9_COMP_GATE(can0_pe, CAN_CLK_CTRL, 8, 0); 641 642 static A9_COMP_SEL(can1_pe, CAN_CLK_CTRL, 25, 0x7, a9_can_pe_parents, a9_can_pe_parents_val_table); 643 static A9_COMP_DIV(can1_pe, CAN_CLK_CTRL, 16, 7); 644 static A9_COMP_GATE(can1_pe, CAN_CLK_CTRL, 24, 0); 645 646 static const struct clk_parent_data a9_can_filter_parents[] = { 647 { .fw_name = "sys", }, 648 { .fw_name = "xtal", }, 649 { .fw_name = "fdiv4", }, 650 { .fw_name = "fdiv5", } 651 }; 652 653 static A9_COMP_SEL(can0_filter, CAN_CLK_CTRL1, 9, 0x7, a9_can_filter_parents, NULL); 654 static A9_COMP_DIV(can0_filter, CAN_CLK_CTRL1, 0, 7); 655 static A9_COMP_GATE(can0_filter, CAN_CLK_CTRL1, 8, 0); 656 657 static A9_COMP_SEL(can1_filter, CAN_CLK_CTRL1, 25, 0x7, a9_can_filter_parents, NULL); 658 static A9_COMP_DIV(can1_filter, CAN_CLK_CTRL1, 16, 7); 659 static A9_COMP_GATE(can1_filter, CAN_CLK_CTRL1, 24, 0); 660 661 static const struct clk_parent_data a9_i3c_parents[] = { 662 { .fw_name = "sys", }, 663 { .fw_name = "xtal", }, 664 { .fw_name = "fdiv5", } 665 }; 666 667 static A9_COMP_SEL(i3c, I3C_CLK_CTRL, 9, 0x7, a9_i3c_parents, NULL); 668 static A9_COMP_DIV(i3c, I3C_CLK_CTRL, 0, 8); 669 static A9_COMP_GATE(i3c, I3C_CLK_CTRL, 8, 0); 670 671 static struct clk_regmap a9_ts_div = { 672 .data = &(struct clk_regmap_div_data) { 673 .offset = TS_CLK_CTRL, 674 .shift = 0, 675 .width = 8, 676 }, 677 .hw.init = &(struct clk_init_data) { 678 .name = "ts_div", 679 .ops = &clk_regmap_divider_ops, 680 .parent_data = &(const struct clk_parent_data) { 681 .fw_name = "xtal", 682 }, 683 .num_parents = 1, 684 }, 685 }; 686 687 static struct clk_regmap a9_ts = { 688 .data = &(struct clk_regmap_gate_data) { 689 .offset = TS_CLK_CTRL, 690 .bit_idx = 8, 691 }, 692 .hw.init = &(struct clk_init_data) { 693 .name = "ts", 694 .ops = &clk_regmap_gate_ops, 695 .parent_hws = (const struct clk_hw *[]) { 696 &a9_ts_div.hw 697 }, 698 .num_parents = 1, 699 .flags = CLK_SET_RATE_PARENT, 700 }, 701 }; 702 703 static struct clk_fixed_factor a9_eth_125m_div = { 704 .mult = 1, 705 .div = 8, 706 .hw.init = &(struct clk_init_data) { 707 .name = "eth_125m_div", 708 .ops = &clk_fixed_factor_ops, 709 .parent_data = &(const struct clk_parent_data) { 710 .fw_name = "fdiv2", 711 }, 712 .num_parents = 1, 713 }, 714 }; 715 716 static struct clk_regmap a9_eth_125m = { 717 .data = &(struct clk_regmap_gate_data) { 718 .offset = ETH_CLK_CTRL, 719 .bit_idx = 7, 720 }, 721 .hw.init = &(struct clk_init_data) { 722 .name = "eth_125m", 723 .ops = &clk_regmap_gate_ops, 724 .parent_hws = (const struct clk_hw *[]) { 725 &a9_eth_125m_div.hw 726 }, 727 .num_parents = 1, 728 .flags = CLK_SET_RATE_PARENT, 729 }, 730 }; 731 732 /* 733 * Channel 1, 2, 3, 4, 5 and 6 are unconnected, 734 * Channel 7(ext_rmii) connects external PAD. Do not automatically reparent. 735 */ 736 static u32 a9_eth_rmii_parents_val_table[] = { 0, 7 }; 737 static const struct clk_parent_data a9_eth_rmii_parents[] = { 738 { .fw_name = "fdiv2", }, 739 { .fw_name = "ext_rmii", } 740 }; 741 742 static struct clk_regmap a9_eth_rmii_sel = { 743 .data = &(struct clk_regmap_mux_data) { 744 .offset = ETH_CLK_CTRL, 745 .mask = 0x7, 746 .shift = 9, 747 .table = a9_eth_rmii_parents_val_table, 748 }, 749 .hw.init = &(struct clk_init_data){ 750 .name = "eth_rmii_sel", 751 .ops = &clk_regmap_mux_ops, 752 .parent_data = a9_eth_rmii_parents, 753 .num_parents = ARRAY_SIZE(a9_eth_rmii_parents), 754 .flags = CLK_SET_RATE_NO_REPARENT, 755 }, 756 }; 757 758 static struct clk_regmap a9_eth_rmii_div = { 759 .data = &(struct clk_regmap_div_data) { 760 .offset = ETH_CLK_CTRL, 761 .shift = 0, 762 .width = 7, 763 }, 764 .hw.init = &(struct clk_init_data){ 765 .name = "eth_rmii_div", 766 .ops = &clk_regmap_divider_ops, 767 .parent_hws = (const struct clk_hw *[]) { 768 &a9_eth_rmii_sel.hw 769 }, 770 .num_parents = 1, 771 .flags = CLK_SET_RATE_PARENT, 772 }, 773 }; 774 775 static struct clk_regmap a9_eth_rmii = { 776 .data = &(struct clk_regmap_gate_data) { 777 .offset = ETH_CLK_CTRL, 778 .bit_idx = 8, 779 }, 780 .hw.init = &(struct clk_init_data){ 781 .name = "eth_rmii", 782 .ops = &clk_regmap_gate_ops, 783 .parent_hws = (const struct clk_hw *[]) { 784 &a9_eth_rmii_div.hw 785 }, 786 .num_parents = 1, 787 .flags = CLK_SET_RATE_PARENT, 788 }, 789 }; 790 791 static struct clk_regmap a9_vid_pll_div = { 792 .data = &(struct meson_vid_pll_div_data){ 793 .val = { 794 .reg_off = VID_PLL_CLK_DIV, 795 .shift = 0, 796 .width = 15, 797 }, 798 .sel = { 799 .reg_off = VID_PLL_CLK_DIV, 800 .shift = 16, 801 .width = 2, 802 }, 803 }, 804 .hw.init = &(struct clk_init_data) { 805 .name = "vid_pll_div", 806 .ops = &meson_vid_pll_div_ro_ops, 807 .parent_data = (const struct clk_parent_data []) { 808 { .fw_name = "hdmiout2", } 809 }, 810 .num_parents = 1, 811 }, 812 }; 813 814 static struct clk_regmap a9_vid_pll_sel = { 815 .data = &(struct clk_regmap_mux_data){ 816 .offset = VID_PLL_CLK_DIV, 817 .mask = 0x1, 818 .shift = 18, 819 }, 820 .hw.init = &(struct clk_init_data){ 821 .name = "vid_pll_sel", 822 .ops = &clk_regmap_mux_ops, 823 .parent_data = (const struct clk_parent_data []) { 824 { .hw = &a9_vid_pll_div.hw }, 825 { .fw_name = "hdmiout2", } 826 }, 827 .num_parents = 2, 828 .flags = CLK_SET_RATE_PARENT, 829 }, 830 }; 831 832 static struct clk_regmap a9_vid_pll = { 833 .data = &(struct clk_regmap_gate_data){ 834 .offset = VID_PLL_CLK_DIV, 835 .bit_idx = 19, 836 }, 837 .hw.init = &(struct clk_init_data) { 838 .name = "vid_pll", 839 .ops = &clk_regmap_gate_ops, 840 .parent_hws = (const struct clk_hw *[]) { 841 &a9_vid_pll_sel.hw 842 }, 843 .num_parents = 1, 844 .flags = CLK_SET_RATE_PARENT, 845 }, 846 }; 847 848 /* 849 * Channel 12 (msr_clk) is managed by the clock measurement module and is not part of the clock 850 * tree. It depends on the measurement source selected through the measurement control registers. 851 * 852 * Channel 10, 11, 13, 14 and 16 are unconnected. 853 */ 854 static u32 a9_gen_parents_val_table[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 17, 18, 855 19, 20, 21, 22, 23, 24, 25, 26}; 856 static const struct clk_parent_data a9_gen_parents[] = { 857 { .fw_name = "xtal" }, 858 { .fw_name = "rtc" }, 859 { .fw_name = "sysplldiv16" }, 860 { .fw_name = "ddr_test" }, 861 { .hw = &a9_vid_pll.hw }, 862 { .fw_name = "gp0" }, 863 { .fw_name = "hifi1" }, 864 { .fw_name = "hifi0" }, 865 { .fw_name = "gp1" }, 866 { .fw_name = "gp2" }, 867 { .fw_name = "dsudiv16" }, 868 { .fw_name = "cpudiv16" }, 869 { .fw_name = "a78div16" }, 870 { .fw_name = "fdiv2" }, 871 { .fw_name = "fdiv2p5" }, 872 { .fw_name = "fdiv3" }, 873 { .fw_name = "fdiv4" }, 874 { .fw_name = "fdiv5" }, 875 { .fw_name = "fdiv7" }, 876 { .fw_name = "mclk0" }, 877 { .fw_name = "mclk1" } 878 }; 879 880 static A9_COMP_SEL(gen, GEN_CLK_CTRL, 12, 0x1f, a9_gen_parents, a9_gen_parents_val_table); 881 static A9_COMP_DIV(gen, GEN_CLK_CTRL, 0, 11); 882 static A9_COMP_GATE(gen, GEN_CLK_CTRL, 11, 0); 883 884 static struct clk_regmap a9_24m_in = { 885 .data = &(struct clk_regmap_gate_data) { 886 .offset = CLK12_24_CTRL, 887 .bit_idx = 11, 888 }, 889 .hw.init = &(struct clk_init_data) { 890 .name = "24m_in", 891 .ops = &clk_regmap_gate_ops, 892 .parent_data = &(const struct clk_parent_data) { 893 .fw_name = "xtal", 894 }, 895 .num_parents = 1, 896 }, 897 }; 898 899 static struct clk_regmap a9_12_24m = { 900 .data = &(struct clk_regmap_div_data) { 901 .offset = CLK12_24_CTRL, 902 .shift = 10, 903 .width = 1, 904 }, 905 .hw.init = &(struct clk_init_data) { 906 .name = "12_24m", 907 .ops = &clk_regmap_divider_ops, 908 .parent_hws = (const struct clk_hw *[]) { 909 &a9_24m_in.hw 910 }, 911 .num_parents = 1, 912 }, 913 }; 914 915 static const struct clk_parent_data a9_mali_parents[] = { 916 { .fw_name = "xtal", }, 917 { .fw_name = "gp1", }, 918 { .fw_name = "fdiv2", }, 919 { .fw_name = "fdiv2p5", }, 920 { .fw_name = "fdiv3", }, 921 { .fw_name = "fdiv4", }, 922 { .fw_name = "fdiv5", }, 923 { .fw_name = "fdiv7", } 924 }; 925 926 static A9_COMP_SEL(mali_0, MALI_CLK_CTRL, 9, 0x7, a9_mali_parents, NULL); 927 static A9_COMP_DIV(mali_0, MALI_CLK_CTRL, 0, 7); 928 static A9_COMP_GATE(mali_0, MALI_CLK_CTRL, 8, CLK_SET_RATE_GATE); 929 930 static A9_COMP_SEL(mali_1, MALI_CLK_CTRL, 25, 0x7, a9_mali_parents, NULL); 931 static A9_COMP_DIV(mali_1, MALI_CLK_CTRL, 16, 7); 932 static A9_COMP_GATE(mali_1, MALI_CLK_CTRL, 24, CLK_SET_RATE_GATE); 933 934 static struct clk_regmap a9_mali = { 935 .data = &(struct clk_regmap_mux_data){ 936 .offset = MALI_CLK_CTRL, 937 .mask = 0x1, 938 .shift = 31, 939 }, 940 .hw.init = &(struct clk_init_data){ 941 .name = "mali", 942 .ops = &clk_regmap_mux_ops, 943 .parent_hws = (const struct clk_hw *[]) { 944 &a9_mali_0.hw, 945 &a9_mali_1.hw 946 }, 947 .num_parents = 2, 948 .flags = CLK_SET_RATE_PARENT, 949 }, 950 }; 951 952 static A9_COMP_SEL(mali_stack_0, MALI_STACK_CLK_CTRL, 9, 0x7, a9_mali_parents, NULL); 953 static A9_COMP_DIV(mali_stack_0, MALI_STACK_CLK_CTRL, 0, 7); 954 static A9_COMP_GATE(mali_stack_0, MALI_STACK_CLK_CTRL, 8, CLK_SET_RATE_GATE); 955 956 static A9_COMP_SEL(mali_stack_1, MALI_STACK_CLK_CTRL, 25, 0x7, a9_mali_parents, NULL); 957 static A9_COMP_DIV(mali_stack_1, MALI_STACK_CLK_CTRL, 16, 7); 958 static A9_COMP_GATE(mali_stack_1, MALI_STACK_CLK_CTRL, 24, CLK_SET_RATE_GATE); 959 960 static struct clk_regmap a9_mali_stack = { 961 .data = &(struct clk_regmap_mux_data){ 962 .offset = MALI_STACK_CLK_CTRL, 963 .mask = 0x1, 964 .shift = 31, 965 }, 966 .hw.init = &(struct clk_init_data){ 967 .name = "mali_stack", 968 .ops = &clk_regmap_mux_ops, 969 .parent_hws = (const struct clk_hw *[]) { 970 &a9_mali_stack_0.hw, 971 &a9_mali_stack_1.hw 972 }, 973 .num_parents = 2, 974 .flags = CLK_SET_RATE_PARENT, 975 }, 976 }; 977 978 static const struct clk_parent_data a9_hevcf_parents[] = { 979 { .fw_name = "fdiv2p5", }, 980 { .fw_name = "fdiv3", }, 981 { .fw_name = "fdiv4", }, 982 { .fw_name = "fdiv5", }, 983 { .fw_name = "fdiv7", }, 984 { .fw_name = "hifi0", }, 985 { .fw_name = "gp1", }, 986 { .fw_name = "xtal", } 987 }; 988 989 static A9_COMP_SEL(hevcf_0, HEVCF_CLK_CTRL, 9, 0x7, a9_hevcf_parents, NULL); 990 static A9_COMP_DIV(hevcf_0, HEVCF_CLK_CTRL, 0, 7); 991 static A9_COMP_GATE(hevcf_0, HEVCF_CLK_CTRL, 8, CLK_SET_RATE_GATE); 992 993 static A9_COMP_SEL(hevcf_1, HEVCF_CLK_CTRL, 25, 0x7, a9_hevcf_parents, NULL); 994 static A9_COMP_DIV(hevcf_1, HEVCF_CLK_CTRL, 16, 7); 995 static A9_COMP_GATE(hevcf_1, HEVCF_CLK_CTRL, 24, CLK_SET_RATE_GATE); 996 997 static struct clk_regmap a9_hevcf = { 998 .data = &(struct clk_regmap_mux_data){ 999 .offset = HEVCF_CLK_CTRL, 1000 .mask = 0x1, 1001 .shift = 31, 1002 }, 1003 .hw.init = &(struct clk_init_data){ 1004 .name = "hevcf", 1005 .ops = &clk_regmap_mux_ops, 1006 .parent_hws = (const struct clk_hw *[]) { 1007 &a9_hevcf_0.hw, 1008 &a9_hevcf_1.hw 1009 }, 1010 .num_parents = 2, 1011 .flags = CLK_SET_RATE_PARENT, 1012 }, 1013 }; 1014 1015 static const struct clk_parent_data a9_hcodec_parents[] = { 1016 { .fw_name = "fdiv2p5", }, 1017 { .fw_name = "fdiv3", }, 1018 { .fw_name = "fdiv4", }, 1019 { .fw_name = "fdiv5", }, 1020 { .fw_name = "fdiv7", }, 1021 { .fw_name = "hifi0", }, 1022 { .fw_name = "gp0", }, 1023 { .fw_name = "xtal", } 1024 }; 1025 1026 static A9_COMP_SEL(hcodec_0, HCODEC_CLK_CTRL, 9, 0x7, a9_hcodec_parents, NULL); 1027 static A9_COMP_DIV(hcodec_0, HCODEC_CLK_CTRL, 0, 7); 1028 static A9_COMP_GATE(hcodec_0, HCODEC_CLK_CTRL, 8, CLK_SET_RATE_GATE); 1029 1030 static A9_COMP_SEL(hcodec_1, HCODEC_CLK_CTRL, 25, 0x7, a9_hcodec_parents, NULL); 1031 static A9_COMP_DIV(hcodec_1, HCODEC_CLK_CTRL, 16, 7); 1032 static A9_COMP_GATE(hcodec_1, HCODEC_CLK_CTRL, 24, CLK_SET_RATE_GATE); 1033 1034 static struct clk_regmap a9_hcodec = { 1035 .data = &(struct clk_regmap_mux_data){ 1036 .offset = HCODEC_CLK_CTRL, 1037 .mask = 0x1, 1038 .shift = 31, 1039 }, 1040 .hw.init = &(struct clk_init_data){ 1041 .name = "hcodec", 1042 .ops = &clk_regmap_mux_ops, 1043 .parent_hws = (const struct clk_hw *[]) { 1044 &a9_hcodec_0.hw, 1045 &a9_hcodec_1.hw 1046 }, 1047 .num_parents = 2, 1048 .flags = CLK_SET_RATE_PARENT, 1049 }, 1050 }; 1051 1052 static const struct clk_parent_data a9_vpu_parents[] = { 1053 { .fw_name = "fdiv3", }, 1054 { .fw_name = "fdiv4", }, 1055 { .fw_name = "fdiv5", }, 1056 { .fw_name = "vid1", }, 1057 { .fw_name = "fdiv2", }, 1058 { .hw = &a9_vid_pll.hw }, 1059 { .fw_name = "vid2", }, 1060 { .fw_name = "gp1", } 1061 }; 1062 1063 static A9_COMP_SEL(vpu_0, VPU_CLK_CTRL, 9, 0x7, a9_vpu_parents, NULL); 1064 static A9_COMP_DIV(vpu_0, VPU_CLK_CTRL, 0, 7); 1065 static A9_COMP_GATE(vpu_0, VPU_CLK_CTRL, 8, CLK_SET_RATE_GATE); 1066 1067 static A9_COMP_SEL(vpu_1, VPU_CLK_CTRL, 25, 0x7, a9_vpu_parents, NULL); 1068 static A9_COMP_DIV(vpu_1, VPU_CLK_CTRL, 16, 7); 1069 static A9_COMP_GATE(vpu_1, VPU_CLK_CTRL, 24, CLK_SET_RATE_GATE); 1070 1071 static struct clk_regmap a9_vpu = { 1072 .data = &(struct clk_regmap_mux_data){ 1073 .offset = VPU_CLK_CTRL, 1074 .mask = 0x1, 1075 .shift = 31, 1076 }, 1077 .hw.init = &(struct clk_init_data){ 1078 .name = "vpu", 1079 .ops = &clk_regmap_mux_ops, 1080 .parent_hws = (const struct clk_hw *[]) { 1081 &a9_vpu_0.hw, 1082 &a9_vpu_1.hw 1083 }, 1084 .num_parents = 2, 1085 .flags = CLK_SET_RATE_PARENT, 1086 }, 1087 }; 1088 1089 static const struct clk_parent_data a9_vapb_parents[] = { 1090 { .fw_name = "fdiv4", }, 1091 { .fw_name = "fdiv3", }, 1092 { .fw_name = "fdiv5", }, 1093 { .fw_name = "fdiv7", }, 1094 { .fw_name = "fdiv2", }, 1095 { .hw = &a9_vid_pll.hw }, 1096 { .fw_name = "hifi0", }, 1097 { .fw_name = "fdiv2p5", } 1098 }; 1099 1100 static A9_COMP_SEL(vapb_0, VAPB_CLK_CTRL, 9, 0x7, a9_vapb_parents, NULL); 1101 static A9_COMP_DIV(vapb_0, VAPB_CLK_CTRL, 0, 7); 1102 static A9_COMP_GATE(vapb_0, VAPB_CLK_CTRL, 8, CLK_SET_RATE_GATE); 1103 1104 static A9_COMP_SEL(vapb_1, VAPB_CLK_CTRL, 25, 0x7, a9_vapb_parents, NULL); 1105 static A9_COMP_DIV(vapb_1, VAPB_CLK_CTRL, 16, 7); 1106 static A9_COMP_GATE(vapb_1, VAPB_CLK_CTRL, 24, CLK_SET_RATE_GATE); 1107 1108 static struct clk_regmap a9_vapb = { 1109 .data = &(struct clk_regmap_mux_data){ 1110 .offset = VAPB_CLK_CTRL, 1111 .mask = 0x1, 1112 .shift = 31, 1113 }, 1114 .hw.init = &(struct clk_init_data){ 1115 .name = "vapb", 1116 .ops = &clk_regmap_mux_ops, 1117 .parent_hws = (const struct clk_hw *[]) { 1118 &a9_vapb_0.hw, 1119 &a9_vapb_1.hw 1120 }, 1121 .num_parents = 2, 1122 .flags = CLK_SET_RATE_PARENT, 1123 }, 1124 }; 1125 1126 static struct clk_regmap a9_ge2d = { 1127 .data = &(struct clk_regmap_gate_data) { 1128 .offset = VAPB_CLK_CTRL, 1129 .bit_idx = 30, 1130 }, 1131 .hw.init = &(struct clk_init_data) { 1132 .name = "ge2d", 1133 .ops = &clk_regmap_gate_ops, 1134 .parent_hws = (const struct clk_hw *[]) { 1135 &a9_vapb.hw, 1136 }, 1137 .num_parents = 1, 1138 }, 1139 }; 1140 1141 static const struct clk_parent_data a9_vpu_clkb_tmp_parents[] = { 1142 { .hw = &a9_vpu.hw }, 1143 { .fw_name = "fdiv4", }, 1144 { .fw_name = "fdiv5", }, 1145 { .fw_name = "fdiv7", } 1146 }; 1147 1148 static A9_COMP_SEL(vpu_clkb_tmp, VPU_CLKB_CTRL, 25, 0x7, a9_vpu_clkb_tmp_parents, NULL); 1149 static A9_COMP_DIV(vpu_clkb_tmp, VPU_CLKB_CTRL, 16, 4); 1150 static A9_COMP_GATE(vpu_clkb_tmp, VPU_CLKB_CTRL, 24, 0); 1151 1152 static struct clk_regmap a9_vpu_clkb_div = { 1153 .data = &(struct clk_regmap_div_data) { 1154 .offset = VPU_CLKB_CTRL, 1155 .shift = 0, 1156 .width = 8, 1157 }, 1158 .hw.init = &(struct clk_init_data) { 1159 .name = "vpu_clkb_div", 1160 .ops = &clk_regmap_divider_ops, 1161 .parent_hws = (const struct clk_hw *[]) { 1162 &a9_vpu_clkb_tmp.hw, 1163 }, 1164 .num_parents = 1, 1165 }, 1166 }; 1167 1168 static struct clk_regmap a9_vpu_clkb = { 1169 .data = &(struct clk_regmap_gate_data) { 1170 .offset = VPU_CLKB_CTRL, 1171 .bit_idx = 8, 1172 }, 1173 .hw.init = &(struct clk_init_data) { 1174 .name = "vpu_clkb", 1175 .ops = &clk_regmap_gate_ops, 1176 .parent_hws = (const struct clk_hw *[]) { 1177 &a9_vpu_clkb_div.hw 1178 }, 1179 .num_parents = 1, 1180 .flags = CLK_SET_RATE_PARENT, 1181 }, 1182 }; 1183 1184 static const struct clk_parent_data a9_hdmi_parents[] = { 1185 { .fw_name = "xtal", }, 1186 { .fw_name = "fdiv4", }, 1187 { .fw_name = "fdiv3", }, 1188 { .fw_name = "fdiv5", } 1189 }; 1190 1191 static A9_COMP_SEL(hdmitx_sys, HDMI_CLK_CTRL, 9, 0x7, a9_hdmi_parents, NULL); 1192 static A9_COMP_DIV(hdmitx_sys, HDMI_CLK_CTRL, 0, 7); 1193 static A9_COMP_GATE(hdmitx_sys, HDMI_CLK_CTRL, 8, 0); 1194 1195 static A9_COMP_SEL(hdmitx_prif, HTX_CLK_CTRL, 9, 0x7, a9_hdmi_parents, NULL); 1196 static A9_COMP_DIV(hdmitx_prif, HTX_CLK_CTRL, 0, 7); 1197 static A9_COMP_GATE(hdmitx_prif, HTX_CLK_CTRL, 8, 0); 1198 1199 static A9_COMP_SEL(hdmitx_200m, HTX_CLK_CTRL, 25, 0x7, a9_hdmi_parents, NULL); 1200 static A9_COMP_DIV(hdmitx_200m, HTX_CLK_CTRL, 16, 7); 1201 static A9_COMP_GATE(hdmitx_200m, HTX_CLK_CTRL, 24, 0); 1202 1203 static A9_COMP_SEL(hdmitx_aud, HTX_CLK_CTRL1, 9, 0x7, a9_hdmi_parents, NULL); 1204 static A9_COMP_DIV(hdmitx_aud, HTX_CLK_CTRL1, 0, 7); 1205 static A9_COMP_GATE(hdmitx_aud, HTX_CLK_CTRL1, 8, 0); 1206 1207 static A9_COMP_SEL(hdmirx_5m, HRX_CLK_CTRL, 9, 0x7, a9_hdmi_parents, NULL); 1208 static A9_COMP_DIV(hdmirx_5m, HRX_CLK_CTRL, 0, 7); 1209 static A9_COMP_GATE(hdmirx_5m, HRX_CLK_CTRL, 8, 0); 1210 1211 static A9_COMP_SEL(hdmirx_2m, HRX_CLK_CTRL, 25, 0x7, a9_hdmi_parents, NULL); 1212 static A9_COMP_DIV(hdmirx_2m, HRX_CLK_CTRL, 16, 7); 1213 static A9_COMP_GATE(hdmirx_2m, HRX_CLK_CTRL, 24, 0); 1214 1215 static A9_COMP_SEL(hdmirx_cfg, HRX_CLK_CTRL1, 9, 0x7, a9_hdmi_parents, NULL); 1216 static A9_COMP_DIV(hdmirx_cfg, HRX_CLK_CTRL1, 0, 7); 1217 static A9_COMP_GATE(hdmirx_cfg, HRX_CLK_CTRL1, 8, 0); 1218 1219 static A9_COMP_SEL(hdmirx_hdcp2x, HRX_CLK_CTRL1, 25, 0x7, a9_hdmi_parents, NULL); 1220 static A9_COMP_DIV(hdmirx_hdcp2x, HRX_CLK_CTRL1, 16, 7); 1221 static A9_COMP_GATE(hdmirx_hdcp2x, HRX_CLK_CTRL1, 24, 0); 1222 1223 static A9_COMP_SEL(hdmirx_acr_ref, HRX_CLK_CTRL2, 25, 0x7, a9_hdmi_parents, NULL); 1224 static A9_COMP_DIV(hdmirx_acr_ref, HRX_CLK_CTRL2, 16, 7); 1225 static A9_COMP_GATE(hdmirx_acr_ref, HRX_CLK_CTRL2, 24, 0); 1226 1227 static A9_COMP_SEL(hdmirx_meter, HRX_CLK_CTRL3, 9, 0x7, a9_hdmi_parents, NULL); 1228 static A9_COMP_DIV(hdmirx_meter, HRX_CLK_CTRL3, 0, 7); 1229 static A9_COMP_GATE(hdmirx_meter, HRX_CLK_CTRL3, 8, 0); 1230 1231 static struct clk_regmap a9_vid_pll_vclk = { 1232 .data = &(struct clk_regmap_mux_data){ 1233 .offset = HDMI_CLK_CTRL, 1234 .mask = 0x1, 1235 .shift = 15, 1236 }, 1237 .hw.init = &(struct clk_init_data){ 1238 .name = "vid_pll_vclk", 1239 .ops = &clk_regmap_mux_ops, 1240 .parent_data = (const struct clk_parent_data []) { 1241 { .hw = &a9_vid_pll.hw }, 1242 { .fw_name = "hdmipix", } 1243 }, 1244 .num_parents = 2, 1245 }, 1246 }; 1247 1248 static const struct clk_parent_data a9_vclk_parents[] = { 1249 { .hw = &a9_vid_pll_vclk.hw }, 1250 { .fw_name = "pix0", }, 1251 { .fw_name = "vid1", }, 1252 { .fw_name = "pix1", }, 1253 { .fw_name = "fdiv3", }, 1254 { .fw_name = "fdiv4", }, 1255 { .fw_name = "fdiv5", }, 1256 { .fw_name = "vid2", } 1257 }; 1258 1259 static struct clk_regmap a9_vclk0_sel = { 1260 .data = &(struct clk_regmap_mux_data){ 1261 .offset = VID_CLK_CTRL, 1262 .mask = 0x7, 1263 .shift = 16, 1264 }, 1265 .hw.init = &(struct clk_init_data){ 1266 .name = "vclk0_sel", 1267 .ops = &clk_regmap_mux_ops, 1268 .parent_data = a9_vclk_parents, 1269 .num_parents = ARRAY_SIZE(a9_vclk_parents), 1270 }, 1271 }; 1272 1273 static struct clk_regmap a9_vclk0_in = { 1274 .data = &(struct clk_regmap_gate_data){ 1275 .offset = VID_CLK_DIV, 1276 .bit_idx = 16, 1277 }, 1278 .hw.init = &(struct clk_init_data) { 1279 .name = "vclk0_in", 1280 .ops = &clk_regmap_gate_ops, 1281 .parent_hws = (const struct clk_hw *[]) { &a9_vclk0_sel.hw }, 1282 .num_parents = 1, 1283 .flags = CLK_SET_RATE_PARENT, 1284 }, 1285 }; 1286 1287 static struct clk_regmap a9_vclk0_div = { 1288 .data = &(struct clk_regmap_div_data){ 1289 .offset = VID_CLK_DIV, 1290 .shift = 0, 1291 .width = 8, 1292 }, 1293 .hw.init = &(struct clk_init_data){ 1294 .name = "vclk0_div", 1295 .ops = &clk_regmap_divider_ops, 1296 .parent_hws = (const struct clk_hw *[]) { 1297 &a9_vclk0_in.hw 1298 }, 1299 .num_parents = 1, 1300 .flags = CLK_SET_RATE_PARENT, 1301 }, 1302 }; 1303 1304 static struct clk_regmap a9_vclk0 = { 1305 .data = &(struct clk_regmap_gate_data){ 1306 .offset = VID_CLK_CTRL, 1307 .bit_idx = 19, 1308 }, 1309 .hw.init = &(struct clk_init_data) { 1310 .name = "vclk0", 1311 .ops = &clk_regmap_gate_ops, 1312 .parent_hws = (const struct clk_hw *[]) { &a9_vclk0_div.hw }, 1313 .num_parents = 1, 1314 .flags = CLK_SET_RATE_PARENT, 1315 }, 1316 }; 1317 1318 #define A9_VCLK_GATE(_name, _reg, _bit, _parent) \ 1319 struct clk_regmap a9_##_name##_en = { \ 1320 .data = &(struct clk_regmap_gate_data) { \ 1321 .offset = (_reg), \ 1322 .bit_idx = (_bit), \ 1323 }, \ 1324 .hw.init = &(struct clk_init_data) { \ 1325 .name = #_name "_en", \ 1326 .ops = &clk_regmap_gate_ops, \ 1327 .parent_hws = (const struct clk_hw *[]) { \ 1328 &(_parent).hw \ 1329 }, \ 1330 .num_parents = 1, \ 1331 .flags = CLK_SET_RATE_PARENT, \ 1332 }, \ 1333 } 1334 1335 #define A9_VCLK_DIV(_name, _div) \ 1336 struct clk_fixed_factor a9_##_name = { \ 1337 .mult = 1, \ 1338 .div = (_div), \ 1339 .hw.init = &(struct clk_init_data) { \ 1340 .name = #_name, \ 1341 .ops = &clk_fixed_factor_ops, \ 1342 .parent_hws = (const struct clk_hw *[]) { \ 1343 &a9_##_name##_en.hw \ 1344 }, \ 1345 .num_parents = 1, \ 1346 .flags = CLK_SET_RATE_PARENT, \ 1347 }, \ 1348 } 1349 1350 static A9_VCLK_GATE(vclk0_div1, VID_CLK_CTRL, 0, a9_vclk0); 1351 static A9_VCLK_GATE(vclk0_div2, VID_CLK_CTRL, 1, a9_vclk0); 1352 static A9_VCLK_DIV(vclk0_div2, 2); 1353 static A9_VCLK_GATE(vclk0_div4, VID_CLK_CTRL, 2, a9_vclk0); 1354 static A9_VCLK_DIV(vclk0_div4, 4); 1355 static A9_VCLK_GATE(vclk0_div6, VID_CLK_CTRL, 3, a9_vclk0); 1356 static A9_VCLK_DIV(vclk0_div6, 6); 1357 static A9_VCLK_GATE(vclk0_div12, VID_CLK_CTRL, 4, a9_vclk0); 1358 static A9_VCLK_DIV(vclk0_div12, 12); 1359 1360 static struct clk_regmap a9_vclk1_sel = { 1361 .data = &(struct clk_regmap_mux_data){ 1362 .offset = VIID_CLK_CTRL, 1363 .mask = 0x7, 1364 .shift = 16, 1365 }, 1366 .hw.init = &(struct clk_init_data){ 1367 .name = "vclk1_sel", 1368 .ops = &clk_regmap_mux_ops, 1369 .parent_data = a9_vclk_parents, 1370 .num_parents = ARRAY_SIZE(a9_vclk_parents), 1371 }, 1372 }; 1373 1374 static struct clk_regmap a9_vclk1_in = { 1375 .data = &(struct clk_regmap_gate_data){ 1376 .offset = VIID_CLK_DIV, 1377 .bit_idx = 16, 1378 }, 1379 .hw.init = &(struct clk_init_data) { 1380 .name = "vclk1_in", 1381 .ops = &clk_regmap_gate_ops, 1382 .parent_hws = (const struct clk_hw *[]) { &a9_vclk1_sel.hw }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 }, 1386 }; 1387 1388 static struct clk_regmap a9_vclk1_div = { 1389 .data = &(struct clk_regmap_div_data){ 1390 .offset = VIID_CLK_DIV, 1391 .shift = 0, 1392 .width = 8, 1393 }, 1394 .hw.init = &(struct clk_init_data){ 1395 .name = "vclk1_div", 1396 .ops = &clk_regmap_divider_ops, 1397 .parent_hws = (const struct clk_hw *[]) { 1398 &a9_vclk1_in.hw 1399 }, 1400 .num_parents = 1, 1401 .flags = CLK_SET_RATE_PARENT, 1402 }, 1403 }; 1404 1405 static struct clk_regmap a9_vclk1 = { 1406 .data = &(struct clk_regmap_gate_data){ 1407 .offset = VIID_CLK_CTRL, 1408 .bit_idx = 19, 1409 }, 1410 .hw.init = &(struct clk_init_data) { 1411 .name = "vclk1", 1412 .ops = &clk_regmap_gate_ops, 1413 .parent_hws = (const struct clk_hw *[]) { &a9_vclk1_div.hw }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT, 1416 }, 1417 }; 1418 1419 static A9_VCLK_GATE(vclk1_div1, VIID_CLK_CTRL, 0, a9_vclk1); 1420 static A9_VCLK_GATE(vclk1_div2, VIID_CLK_CTRL, 1, a9_vclk1); 1421 static A9_VCLK_DIV(vclk1_div2, 2); 1422 static A9_VCLK_GATE(vclk1_div4, VIID_CLK_CTRL, 2, a9_vclk1); 1423 static A9_VCLK_DIV(vclk1_div4, 4); 1424 static A9_VCLK_GATE(vclk1_div6, VIID_CLK_CTRL, 3, a9_vclk1); 1425 static A9_VCLK_DIV(vclk1_div6, 6); 1426 static A9_VCLK_GATE(vclk1_div12, VIID_CLK_CTRL, 4, a9_vclk1); 1427 static A9_VCLK_DIV(vclk1_div12, 12); 1428 1429 /* Channel 5, 6 and 7 are unconnected */ 1430 static u32 a9_vid_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1431 static const struct clk_hw *a9_vid_parents[] = { 1432 &a9_vclk0_div1_en.hw, 1433 &a9_vclk0_div2.hw, 1434 &a9_vclk0_div4.hw, 1435 &a9_vclk0_div6.hw, 1436 &a9_vclk0_div12.hw, 1437 &a9_vclk1_div1_en.hw, 1438 &a9_vclk1_div2.hw, 1439 &a9_vclk1_div4.hw, 1440 &a9_vclk1_div6.hw, 1441 &a9_vclk1_div12.hw 1442 }; 1443 1444 static struct clk_regmap a9_encoder0_sel = { 1445 .data = &(struct clk_regmap_mux_data){ 1446 .offset = VIID_CLK_DIV, 1447 .mask = 0xf, 1448 .shift = 12, 1449 .table = a9_vid_parents_val_table, 1450 }, 1451 .hw.init = &(struct clk_init_data){ 1452 .name = "encoder0_sel", 1453 .ops = &clk_regmap_mux_ops, 1454 .parent_hws = a9_vid_parents, 1455 .num_parents = ARRAY_SIZE(a9_vid_parents), 1456 }, 1457 }; 1458 1459 static struct clk_regmap a9_encoder0 = { 1460 .data = &(struct clk_regmap_gate_data){ 1461 .offset = VID_CLK_CTRL2, 1462 .bit_idx = 10, 1463 }, 1464 .hw.init = &(struct clk_init_data) { 1465 .name = "encoder0", 1466 .ops = &clk_regmap_gate_ops, 1467 .parent_hws = (const struct clk_hw *[]) { 1468 &a9_encoder0_sel.hw 1469 }, 1470 .num_parents = 1, 1471 .flags = CLK_SET_RATE_PARENT, 1472 }, 1473 }; 1474 1475 static struct clk_regmap a9_encoder1_sel = { 1476 .data = &(struct clk_regmap_mux_data){ 1477 .offset = VIID_CLK_DIV, 1478 .mask = 0xf, 1479 .shift = 8, 1480 .table = a9_vid_parents_val_table, 1481 }, 1482 .hw.init = &(struct clk_init_data){ 1483 .name = "encoder1_sel", 1484 .ops = &clk_regmap_mux_ops, 1485 .parent_hws = a9_vid_parents, 1486 .num_parents = ARRAY_SIZE(a9_vid_parents), 1487 }, 1488 }; 1489 1490 static struct clk_regmap a9_encoder1 = { 1491 .data = &(struct clk_regmap_gate_data){ 1492 .offset = VID_CLK_CTRL2, 1493 .bit_idx = 11, 1494 }, 1495 .hw.init = &(struct clk_init_data) { 1496 .name = "encoder1", 1497 .ops = &clk_regmap_gate_ops, 1498 .parent_hws = (const struct clk_hw *[]) { 1499 &a9_encoder1_sel.hw 1500 }, 1501 .num_parents = 1, 1502 .flags = CLK_SET_RATE_PARENT, 1503 }, 1504 }; 1505 1506 static const struct clk_parent_data a9_vid_lock_parents[] = { 1507 { .fw_name = "xtal", }, 1508 { .hw = &a9_encoder0.hw }, 1509 { .hw = &a9_encoder1.hw } 1510 }; 1511 1512 static A9_COMP_SEL(vid_lock, VID_LOCK_CLK_CTRL, 9, 0x7, a9_vid_lock_parents, NULL); 1513 static A9_COMP_DIV(vid_lock, VID_LOCK_CLK_CTRL, 0, 7); 1514 static A9_COMP_GATE(vid_lock, VID_LOCK_CLK_CTRL, 8, 0); 1515 1516 static const struct clk_parent_data a9_vdin_meas_parents[] = { 1517 { .fw_name = "xtal", }, 1518 { .fw_name = "fdiv4", }, 1519 { .fw_name = "fdiv3", }, 1520 { .fw_name = "fdiv5", } 1521 }; 1522 1523 static A9_COMP_SEL(vdin_meas, VDIN_MEAS_CLK_CTRL, 9, 0x7, a9_vdin_meas_parents, NULL); 1524 static A9_COMP_DIV(vdin_meas, VDIN_MEAS_CLK_CTRL, 0, 7); 1525 static A9_COMP_GATE(vdin_meas, VDIN_MEAS_CLK_CTRL, 8, 0); 1526 1527 static struct clk_regmap a9_vdac_sel = { 1528 .data = &(struct clk_regmap_mux_data){ 1529 .offset = VIID_CLK_DIV, 1530 .mask = 0xf, 1531 .shift = 28, 1532 .table = a9_vid_parents_val_table, 1533 }, 1534 .hw.init = &(struct clk_init_data){ 1535 .name = "vdac_sel", 1536 .ops = &clk_regmap_mux_ops, 1537 .parent_hws = a9_vid_parents, 1538 .num_parents = ARRAY_SIZE(a9_vid_parents), 1539 }, 1540 }; 1541 1542 static struct clk_regmap a9_vdac = { 1543 .data = &(struct clk_regmap_gate_data){ 1544 .offset = VID_CLK_CTRL2, 1545 .bit_idx = 4, 1546 }, 1547 .hw.init = &(struct clk_init_data) { 1548 .name = "vdac", 1549 .ops = &clk_regmap_gate_ops, 1550 .parent_hws = (const struct clk_hw *[]) { 1551 &a9_vdac_sel.hw 1552 }, 1553 .num_parents = 1, 1554 .flags = CLK_SET_RATE_PARENT, 1555 }, 1556 }; 1557 1558 static struct clk_regmap a9_hdmitx0_pixel_sel = { 1559 .data = &(struct clk_regmap_mux_data){ 1560 .offset = HDMI_CLK_CTRL, 1561 .mask = 0xf, 1562 .shift = 16, 1563 .table = a9_vid_parents_val_table, 1564 }, 1565 .hw.init = &(struct clk_init_data){ 1566 .name = "hdmitx0_pixel_sel", 1567 .ops = &clk_regmap_mux_ops, 1568 .parent_hws = a9_vid_parents, 1569 .num_parents = ARRAY_SIZE(a9_vid_parents), 1570 }, 1571 }; 1572 1573 static struct clk_regmap a9_hdmitx0_pixel = { 1574 .data = &(struct clk_regmap_gate_data){ 1575 .offset = VID_CLK_CTRL2, 1576 .bit_idx = 5, 1577 }, 1578 .hw.init = &(struct clk_init_data) { 1579 .name = "hdmitx0_pixel", 1580 .ops = &clk_regmap_gate_ops, 1581 .parent_hws = (const struct clk_hw *[]) { 1582 &a9_hdmitx0_pixel_sel.hw 1583 }, 1584 .num_parents = 1, 1585 .flags = CLK_SET_RATE_PARENT, 1586 }, 1587 }; 1588 1589 static struct clk_regmap a9_hdmitx0_fe_sel = { 1590 .data = &(struct clk_regmap_mux_data){ 1591 .offset = HDMI_CLK_CTRL, 1592 .mask = 0xf, 1593 .shift = 20, 1594 .table = a9_vid_parents_val_table, 1595 }, 1596 .hw.init = &(struct clk_init_data){ 1597 .name = "hdmitx0_fe_sel", 1598 .ops = &clk_regmap_mux_ops, 1599 .parent_hws = a9_vid_parents, 1600 .num_parents = ARRAY_SIZE(a9_vid_parents), 1601 }, 1602 }; 1603 1604 static struct clk_regmap a9_hdmitx0_fe = { 1605 .data = &(struct clk_regmap_gate_data){ 1606 .offset = VID_CLK_CTRL2, 1607 .bit_idx = 9, 1608 }, 1609 .hw.init = &(struct clk_init_data) { 1610 .name = "hdmitx0_fe", 1611 .ops = &clk_regmap_gate_ops, 1612 .parent_hws = (const struct clk_hw *[]) { 1613 &a9_hdmitx0_fe_sel.hw 1614 }, 1615 .num_parents = 1, 1616 .flags = CLK_SET_RATE_PARENT, 1617 }, 1618 }; 1619 1620 static struct clk_regmap a9_hdmitx1_pixel_sel = { 1621 .data = &(struct clk_regmap_mux_data){ 1622 .offset = HDMI_CLK_CTRL, 1623 .mask = 0xf, 1624 .shift = 24, 1625 .table = a9_vid_parents_val_table, 1626 }, 1627 .hw.init = &(struct clk_init_data){ 1628 .name = "hdmitx1_pixel_sel", 1629 .ops = &clk_regmap_mux_ops, 1630 .parent_hws = a9_vid_parents, 1631 .num_parents = ARRAY_SIZE(a9_vid_parents), 1632 }, 1633 }; 1634 1635 static struct clk_regmap a9_hdmitx1_pixel = { 1636 .data = &(struct clk_regmap_gate_data){ 1637 .offset = VID_CLK_CTRL2, 1638 .bit_idx = 12, 1639 }, 1640 .hw.init = &(struct clk_init_data) { 1641 .name = "hdmitx1_pixel", 1642 .ops = &clk_regmap_gate_ops, 1643 .parent_hws = (const struct clk_hw *[]) { 1644 &a9_hdmitx1_pixel_sel.hw 1645 }, 1646 .num_parents = 1, 1647 .flags = CLK_SET_RATE_PARENT, 1648 }, 1649 }; 1650 1651 static struct clk_regmap a9_hdmitx1_fe_sel = { 1652 .data = &(struct clk_regmap_mux_data){ 1653 .offset = HDMI_CLK_CTRL, 1654 .mask = 0xf, 1655 .shift = 28, 1656 .table = a9_vid_parents_val_table, 1657 }, 1658 .hw.init = &(struct clk_init_data){ 1659 .name = "hdmitx1_fe_sel", 1660 .ops = &clk_regmap_mux_ops, 1661 .parent_hws = a9_vid_parents, 1662 .num_parents = ARRAY_SIZE(a9_vid_parents), 1663 }, 1664 }; 1665 1666 static struct clk_regmap a9_hdmitx1_fe = { 1667 .data = &(struct clk_regmap_gate_data){ 1668 .offset = VID_CLK_CTRL2, 1669 .bit_idx = 13, 1670 }, 1671 .hw.init = &(struct clk_init_data) { 1672 .name = "hdmitx1_fe", 1673 .ops = &clk_regmap_gate_ops, 1674 .parent_hws = (const struct clk_hw *[]) { 1675 &a9_hdmitx1_fe_sel.hw 1676 }, 1677 .num_parents = 1, 1678 .flags = CLK_SET_RATE_PARENT, 1679 }, 1680 }; 1681 1682 static const struct clk_parent_data a9_csi_phy_parents[] = { 1683 { .fw_name = "fdiv2p5", }, 1684 { .fw_name = "fdiv3", }, 1685 { .fw_name = "fdiv4", }, 1686 { .fw_name = "fdiv5", }, 1687 { .fw_name = "gp0", }, 1688 { .fw_name = "hifi0", }, 1689 { .fw_name = "fdiv2", }, 1690 { .fw_name = "xtal", } 1691 }; 1692 1693 static A9_COMP_SEL(csi_phy, MIPI_CSI_PHY_CLK_CTRL, 9, 0x7, a9_csi_phy_parents, NULL); 1694 static A9_COMP_DIV(csi_phy, MIPI_CSI_PHY_CLK_CTRL, 0, 7); 1695 static A9_COMP_GATE(csi_phy, MIPI_CSI_PHY_CLK_CTRL, 8, 0); 1696 1697 static const struct clk_parent_data a9_dsi_meas_parents[] = { 1698 { .fw_name = "xtal", }, 1699 { .fw_name = "fdiv4", }, 1700 { .fw_name = "fdiv3", }, 1701 { .fw_name = "fdiv5", }, 1702 { .hw = &a9_vid_pll.hw }, 1703 { .fw_name = "gp0", }, 1704 { .fw_name = "vid1", }, 1705 { .fw_name = "vid2", } 1706 }; 1707 1708 static A9_COMP_SEL(dsi0_meas, DSI_MEAS_CLK_CTRL, 9, 0x7, a9_dsi_meas_parents, NULL); 1709 static A9_COMP_DIV(dsi0_meas, DSI_MEAS_CLK_CTRL, 0, 7); 1710 static A9_COMP_GATE(dsi0_meas, DSI_MEAS_CLK_CTRL, 8, 0); 1711 1712 static A9_COMP_SEL(dsi1_meas, DSI_MEAS_CLK_CTRL, 25, 0x7, a9_dsi_meas_parents, NULL); 1713 static A9_COMP_DIV(dsi1_meas, DSI_MEAS_CLK_CTRL, 16, 7); 1714 static A9_COMP_GATE(dsi1_meas, DSI_MEAS_CLK_CTRL, 24, 0); 1715 1716 static struct clk_hw *a9_peripherals_hw_clks[] = { 1717 [CLKID_SYS_AM_AXI] = &a9_sys_am_axi.hw, 1718 [CLKID_SYS_DOS] = &a9_sys_dos.hw, 1719 [CLKID_SYS_MIPI_DSI0] = &a9_sys_mipi_dsi0.hw, 1720 [CLKID_SYS_ETH_PHY] = &a9_sys_eth_phy.hw, 1721 [CLKID_SYS_AMFC] = &a9_sys_amfc.hw, 1722 [CLKID_SYS_MALI] = &a9_sys_mali.hw, 1723 [CLKID_SYS_NNA] = &a9_sys_nna.hw, 1724 [CLKID_SYS_ETH_AXI] = &a9_sys_eth_axi.hw, 1725 [CLKID_SYS_DP_APB] = &a9_sys_dp_apb.hw, 1726 [CLKID_SYS_EDPTX_APB] = &a9_sys_edptx_apb.hw, 1727 [CLKID_SYS_U3HSG] = &a9_sys_u3hsg.hw, 1728 [CLKID_SYS_AUCPU] = &a9_sys_aucpu.hw, 1729 [CLKID_SYS_GLB] = &a9_sys_glb.hw, 1730 [CLKID_SYS_COMBO_DPHY_APB] = &a9_sys_combo_dphy_apb.hw, 1731 [CLKID_SYS_HDMIRX_APB] = &a9_sys_hdmirx_apb.hw, 1732 [CLKID_SYS_HDMIRX_PCLK] = &a9_sys_hdmirx_pclk.hw, 1733 [CLKID_SYS_MIPI_DSI0_PHY] = &a9_sys_mipi_dsi0_phy.hw, 1734 [CLKID_SYS_CAN0] = &a9_sys_can0.hw, 1735 [CLKID_SYS_CAN1] = &a9_sys_can1.hw, 1736 [CLKID_SYS_SD_EMMC_A] = &a9_sys_sd_emmc_a.hw, 1737 [CLKID_SYS_SD_EMMC_B] = &a9_sys_sd_emmc_b.hw, 1738 [CLKID_SYS_SD_EMMC_C] = &a9_sys_sd_emmc_c.hw, 1739 [CLKID_SYS_SC] = &a9_sys_sc.hw, 1740 [CLKID_SYS_ACODEC] = &a9_sys_acodec.hw, 1741 [CLKID_SYS_MIPI_ISP] = &a9_sys_mipi_isp.hw, 1742 [CLKID_SYS_MSR] = &a9_sys_msr.hw, 1743 [CLKID_SYS_AUDIO] = &a9_sys_audio.hw, 1744 [CLKID_SYS_MIPI_DSI1] = &a9_sys_mipi_dsi1.hw, 1745 [CLKID_SYS_MIPI_DSI1_PHY] = &a9_sys_mipi_dsi1_phy.hw, 1746 [CLKID_SYS_ETH] = &a9_sys_eth.hw, 1747 [CLKID_SYS_ETH_1G_MAC] = &a9_sys_eth_1g_mac.hw, 1748 [CLKID_SYS_UART_A] = &a9_sys_uart_a.hw, 1749 [CLKID_SYS_UART_F] = &a9_sys_uart_f.hw, 1750 [CLKID_SYS_TS_A55] = &a9_sys_ts_a55.hw, 1751 [CLKID_SYS_ETH_1G_AXI] = &a9_sys_eth_1g_axi.hw, 1752 [CLKID_SYS_TS_DOS] = &a9_sys_ts_dos.hw, 1753 [CLKID_SYS_U3DRD_B] = &a9_sys_u3drd_b.hw, 1754 [CLKID_SYS_TS_CORE] = &a9_sys_ts_core.hw, 1755 [CLKID_SYS_TS_PLL] = &a9_sys_ts_pll.hw, 1756 [CLKID_SYS_CSI_DIG_CLKIN] = &a9_sys_csi_dig_clkin.hw, 1757 [CLKID_SYS_CVE] = &a9_sys_cve.hw, 1758 [CLKID_SYS_GE2D] = &a9_sys_ge2d.hw, 1759 [CLKID_SYS_SPISG] = &a9_sys_spisg.hw, 1760 [CLKID_SYS_U2H] = &a9_sys_u2h.hw, 1761 [CLKID_SYS_PCIE_MAC_A] = &a9_sys_pcie_mac_a.hw, 1762 [CLKID_SYS_U3DRD_A] = &a9_sys_u3drd_a.hw, 1763 [CLKID_SYS_U2DRD] = &a9_sys_u2drd.hw, 1764 [CLKID_SYS_PCIE_PHY] = &a9_sys_pcie_phy.hw, 1765 [CLKID_SYS_PCIE_MAC_B] = &a9_sys_pcie_mac_b.hw, 1766 [CLKID_SYS_PERIPH] = &a9_sys_periph.hw, 1767 [CLKID_SYS_PIO] = &a9_sys_pio.hw, 1768 [CLKID_SYS_I3C] = &a9_sys_i3c.hw, 1769 [CLKID_SYS_I2C_M_E] = &a9_sys_i2c_m_e.hw, 1770 [CLKID_SYS_I2C_M_F] = &a9_sys_i2c_m_f.hw, 1771 [CLKID_SYS_HDMITX_APB] = &a9_sys_hdmitx_apb.hw, 1772 [CLKID_SYS_I2C_M_I] = &a9_sys_i2c_m_i.hw, 1773 [CLKID_SYS_I2C_M_G] = &a9_sys_i2c_m_g.hw, 1774 [CLKID_SYS_I2C_M_H] = &a9_sys_i2c_m_h.hw, 1775 [CLKID_SYS_HDMI20_AES] = &a9_sys_hdmi20_aes.hw, 1776 [CLKID_SYS_CSI2_HOST] = &a9_sys_csi2_host.hw, 1777 [CLKID_SYS_CSI2_ADAPT] = &a9_sys_csi2_adapt.hw, 1778 [CLKID_SYS_DSPA] = &a9_sys_dspa.hw, 1779 [CLKID_SYS_PP_DMA] = &a9_sys_pp_dma.hw, 1780 [CLKID_SYS_PP_WRAPPER] = &a9_sys_pp_wrapper.hw, 1781 [CLKID_SYS_VPU_INTR] = &a9_sys_vpu_intr.hw, 1782 [CLKID_SYS_CSI2_PHY] = &a9_sys_csi2_phy.hw, 1783 [CLKID_SYS_SARADC] = &a9_sys_saradc.hw, 1784 [CLKID_SYS_PWM_J] = &a9_sys_pwm_j.hw, 1785 [CLKID_SYS_PWM_I] = &a9_sys_pwm_i.hw, 1786 [CLKID_SYS_PWM_H] = &a9_sys_pwm_h.hw, 1787 [CLKID_SYS_PWM_N] = &a9_sys_pwm_n.hw, 1788 [CLKID_SYS_PWM_M] = &a9_sys_pwm_m.hw, 1789 [CLKID_SYS_PWM_L] = &a9_sys_pwm_l.hw, 1790 [CLKID_SYS_PWM_K] = &a9_sys_pwm_k.hw, 1791 [CLKID_SD_EMMC_A_SEL] = &a9_sd_emmc_a_sel.hw, 1792 [CLKID_SD_EMMC_A_DIV] = &a9_sd_emmc_a_div.hw, 1793 [CLKID_SD_EMMC_A] = &a9_sd_emmc_a.hw, 1794 [CLKID_SD_EMMC_B_SEL] = &a9_sd_emmc_b_sel.hw, 1795 [CLKID_SD_EMMC_B_DIV] = &a9_sd_emmc_b_div.hw, 1796 [CLKID_SD_EMMC_B] = &a9_sd_emmc_b.hw, 1797 [CLKID_SD_EMMC_C_SEL] = &a9_sd_emmc_c_sel.hw, 1798 [CLKID_SD_EMMC_C_DIV] = &a9_sd_emmc_c_div.hw, 1799 [CLKID_SD_EMMC_C] = &a9_sd_emmc_c.hw, 1800 [CLKID_PWM_H_SEL] = &a9_pwm_h_sel.hw, 1801 [CLKID_PWM_H_DIV] = &a9_pwm_h_div.hw, 1802 [CLKID_PWM_H] = &a9_pwm_h.hw, 1803 [CLKID_PWM_I_SEL] = &a9_pwm_i_sel.hw, 1804 [CLKID_PWM_I_DIV] = &a9_pwm_i_div.hw, 1805 [CLKID_PWM_I] = &a9_pwm_i.hw, 1806 [CLKID_PWM_J_SEL] = &a9_pwm_j_sel.hw, 1807 [CLKID_PWM_J_DIV] = &a9_pwm_j_div.hw, 1808 [CLKID_PWM_J] = &a9_pwm_j.hw, 1809 [CLKID_PWM_K_SEL] = &a9_pwm_k_sel.hw, 1810 [CLKID_PWM_K_DIV] = &a9_pwm_k_div.hw, 1811 [CLKID_PWM_K] = &a9_pwm_k.hw, 1812 [CLKID_PWM_L_SEL] = &a9_pwm_l_sel.hw, 1813 [CLKID_PWM_L_DIV] = &a9_pwm_l_div.hw, 1814 [CLKID_PWM_L] = &a9_pwm_l.hw, 1815 [CLKID_PWM_M_SEL] = &a9_pwm_m_sel.hw, 1816 [CLKID_PWM_M_DIV] = &a9_pwm_m_div.hw, 1817 [CLKID_PWM_M] = &a9_pwm_m.hw, 1818 [CLKID_PWM_N_SEL] = &a9_pwm_n_sel.hw, 1819 [CLKID_PWM_N_DIV] = &a9_pwm_n_div.hw, 1820 [CLKID_PWM_N] = &a9_pwm_n.hw, 1821 [CLKID_SPISG0_SEL] = &a9_spisg0_sel.hw, 1822 [CLKID_SPISG0_DIV] = &a9_spisg0_div.hw, 1823 [CLKID_SPISG0] = &a9_spisg0.hw, 1824 [CLKID_SPISG1_SEL] = &a9_spisg1_sel.hw, 1825 [CLKID_SPISG1_DIV] = &a9_spisg1_div.hw, 1826 [CLKID_SPISG1] = &a9_spisg1.hw, 1827 [CLKID_SPISG2_SEL] = &a9_spisg2_sel.hw, 1828 [CLKID_SPISG2_DIV] = &a9_spisg2_div.hw, 1829 [CLKID_SPISG2] = &a9_spisg2.hw, 1830 [CLKID_SARADC_SEL] = &a9_saradc_sel.hw, 1831 [CLKID_SARADC_DIV] = &a9_saradc_div.hw, 1832 [CLKID_SARADC] = &a9_saradc.hw, 1833 [CLKID_AMFC_SEL] = &a9_amfc_sel.hw, 1834 [CLKID_AMFC_DIV] = &a9_amfc_div.hw, 1835 [CLKID_AMFC] = &a9_amfc.hw, 1836 [CLKID_NNA_SEL] = &a9_nna_sel.hw, 1837 [CLKID_NNA_DIV] = &a9_nna_div.hw, 1838 [CLKID_NNA] = &a9_nna.hw, 1839 [CLKID_USB_250M_SEL] = &a9_usb_250m_sel.hw, 1840 [CLKID_USB_250M_DIV] = &a9_usb_250m_div.hw, 1841 [CLKID_USB_250M] = &a9_usb_250m.hw, 1842 [CLKID_USB_48M_PRE_SEL] = &a9_usb_48m_pre_sel.hw, 1843 [CLKID_USB_48M_PRE_DIV] = &a9_usb_48m_pre_div.hw, 1844 [CLKID_USB_48M_PRE] = &a9_usb_48m_pre.hw, 1845 [CLKID_PCIE0_TL_SEL] = &a9_pcie0_tl_sel.hw, 1846 [CLKID_PCIE0_TL_DIV] = &a9_pcie0_tl_div.hw, 1847 [CLKID_PCIE0_TL] = &a9_pcie0_tl.hw, 1848 [CLKID_PCIE1_TL_SEL] = &a9_pcie1_tl_sel.hw, 1849 [CLKID_PCIE1_TL_DIV] = &a9_pcie1_tl_div.hw, 1850 [CLKID_PCIE1_TL] = &a9_pcie1_tl.hw, 1851 [CLKID_CMPR_SEL] = &a9_cmpr_sel.hw, 1852 [CLKID_CMPR_DIV] = &a9_cmpr_div.hw, 1853 [CLKID_CMPR] = &a9_cmpr.hw, 1854 [CLKID_DEWARPA_SEL] = &a9_dewarpa_sel.hw, 1855 [CLKID_DEWARPA_DIV] = &a9_dewarpa_div.hw, 1856 [CLKID_DEWARPA] = &a9_dewarpa.hw, 1857 [CLKID_SC_PRE_SEL] = &a9_sc_pre_sel.hw, 1858 [CLKID_SC_PRE_DIV] = &a9_sc_pre_div.hw, 1859 [CLKID_SC_PRE] = &a9_sc_pre.hw, 1860 [CLKID_SC] = &a9_sc.hw, 1861 [CLKID_DPTX_APB2_SEL] = &a9_dptx_apb2_sel.hw, 1862 [CLKID_DPTX_APB2_DIV] = &a9_dptx_apb2_div.hw, 1863 [CLKID_DPTX_APB2] = &a9_dptx_apb2.hw, 1864 [CLKID_DPTX_AUD_SEL] = &a9_dptx_aud_sel.hw, 1865 [CLKID_DPTX_AUD_DIV] = &a9_dptx_aud_div.hw, 1866 [CLKID_DPTX_AUD] = &a9_dptx_aud.hw, 1867 [CLKID_ISP_SEL] = &a9_isp_sel.hw, 1868 [CLKID_ISP_DIV] = &a9_isp_div.hw, 1869 [CLKID_ISP] = &a9_isp.hw, 1870 [CLKID_CVE_SEL] = &a9_cve_sel.hw, 1871 [CLKID_CVE_DIV] = &a9_cve_div.hw, 1872 [CLKID_CVE] = &a9_cve.hw, 1873 [CLKID_VGE_SEL] = &a9_vge_sel.hw, 1874 [CLKID_VGE_DIV] = &a9_vge_div.hw, 1875 [CLKID_VGE] = &a9_vge.hw, 1876 [CLKID_PP_SEL] = &a9_pp_sel.hw, 1877 [CLKID_PP_DIV] = &a9_pp_div.hw, 1878 [CLKID_PP] = &a9_pp.hw, 1879 [CLKID_GLB_SEL] = &a9_glb_sel.hw, 1880 [CLKID_GLB_DIV] = &a9_glb_div.hw, 1881 [CLKID_GLB] = &a9_glb.hw, 1882 [CLKID_USB_48M_DUALDIV_IN] = &a9_usb_48m_dualdiv_in.hw, 1883 [CLKID_USB_48M_DUALDIV_DIV] = &a9_usb_48m_dualdiv_div.hw, 1884 [CLKID_USB_48M_DUALDIV_SEL] = &a9_usb_48m_dualdiv_sel.hw, 1885 [CLKID_USB_48M_DUALDIV] = &a9_usb_48m_dualdiv.hw, 1886 [CLKID_USB_48M] = &a9_usb_48m.hw, 1887 [CLKID_CAN0_PE_SEL] = &a9_can0_pe_sel.hw, 1888 [CLKID_CAN0_PE_DIV] = &a9_can0_pe_div.hw, 1889 [CLKID_CAN0_PE] = &a9_can0_pe.hw, 1890 [CLKID_CAN1_PE_SEL] = &a9_can1_pe_sel.hw, 1891 [CLKID_CAN1_PE_DIV] = &a9_can1_pe_div.hw, 1892 [CLKID_CAN1_PE] = &a9_can1_pe.hw, 1893 [CLKID_CAN0_FILTER_SEL] = &a9_can0_filter_sel.hw, 1894 [CLKID_CAN0_FILTER_DIV] = &a9_can0_filter_div.hw, 1895 [CLKID_CAN0_FILTER] = &a9_can0_filter.hw, 1896 [CLKID_CAN1_FILTER_SEL] = &a9_can1_filter_sel.hw, 1897 [CLKID_CAN1_FILTER_DIV] = &a9_can1_filter_div.hw, 1898 [CLKID_CAN1_FILTER] = &a9_can1_filter.hw, 1899 [CLKID_I3C_SEL] = &a9_i3c_sel.hw, 1900 [CLKID_I3C_DIV] = &a9_i3c_div.hw, 1901 [CLKID_I3C] = &a9_i3c.hw, 1902 [CLKID_TS_DIV] = &a9_ts_div.hw, 1903 [CLKID_TS] = &a9_ts.hw, 1904 [CLKID_ETH_125M_DIV] = &a9_eth_125m_div.hw, 1905 [CLKID_ETH_125M] = &a9_eth_125m.hw, 1906 [CLKID_ETH_RMII_SEL] = &a9_eth_rmii_sel.hw, 1907 [CLKID_ETH_RMII_DIV] = &a9_eth_rmii_div.hw, 1908 [CLKID_ETH_RMII] = &a9_eth_rmii.hw, 1909 [CLKID_GEN_SEL] = &a9_gen_sel.hw, 1910 [CLKID_GEN_DIV] = &a9_gen_div.hw, 1911 [CLKID_GEN] = &a9_gen.hw, 1912 [CLKID_CLK24M_IN] = &a9_24m_in.hw, 1913 [CLKID_CLK12_24M] = &a9_12_24m.hw, 1914 [CLKID_MALI_0_SEL] = &a9_mali_0_sel.hw, 1915 [CLKID_MALI_0_DIV] = &a9_mali_0_div.hw, 1916 [CLKID_MALI_0] = &a9_mali_0.hw, 1917 [CLKID_MALI_1_SEL] = &a9_mali_1_sel.hw, 1918 [CLKID_MALI_1_DIV] = &a9_mali_1_div.hw, 1919 [CLKID_MALI_1] = &a9_mali_1.hw, 1920 [CLKID_MALI] = &a9_mali.hw, 1921 [CLKID_MALI_STACK_0_SEL] = &a9_mali_stack_0_sel.hw, 1922 [CLKID_MALI_STACK_0_DIV] = &a9_mali_stack_0_div.hw, 1923 [CLKID_MALI_STACK_0] = &a9_mali_stack_0.hw, 1924 [CLKID_MALI_STACK_1_SEL] = &a9_mali_stack_1_sel.hw, 1925 [CLKID_MALI_STACK_1_DIV] = &a9_mali_stack_1_div.hw, 1926 [CLKID_MALI_STACK_1] = &a9_mali_stack_1.hw, 1927 [CLKID_MALI_STACK] = &a9_mali_stack.hw, 1928 [CLKID_DSPA_0_SEL] = &a9_dspa_0_sel.hw, 1929 [CLKID_DSPA_0_DIV] = &a9_dspa_0_div.hw, 1930 [CLKID_DSPA_0] = &a9_dspa_0.hw, 1931 [CLKID_DSPA_1_SEL] = &a9_dspa_1_sel.hw, 1932 [CLKID_DSPA_1_DIV] = &a9_dspa_1_div.hw, 1933 [CLKID_DSPA_1] = &a9_dspa_1.hw, 1934 [CLKID_DSPA] = &a9_dspa.hw, 1935 [CLKID_HEVCF_0_SEL] = &a9_hevcf_0_sel.hw, 1936 [CLKID_HEVCF_0_DIV] = &a9_hevcf_0_div.hw, 1937 [CLKID_HEVCF_0] = &a9_hevcf_0.hw, 1938 [CLKID_HEVCF_1_SEL] = &a9_hevcf_1_sel.hw, 1939 [CLKID_HEVCF_1_DIV] = &a9_hevcf_1_div.hw, 1940 [CLKID_HEVCF_1] = &a9_hevcf_1.hw, 1941 [CLKID_HEVCF] = &a9_hevcf.hw, 1942 [CLKID_HCODEC_0_SEL] = &a9_hcodec_0_sel.hw, 1943 [CLKID_HCODEC_0_DIV] = &a9_hcodec_0_div.hw, 1944 [CLKID_HCODEC_0] = &a9_hcodec_0.hw, 1945 [CLKID_HCODEC_1_SEL] = &a9_hcodec_1_sel.hw, 1946 [CLKID_HCODEC_1_DIV] = &a9_hcodec_1_div.hw, 1947 [CLKID_HCODEC_1] = &a9_hcodec_1.hw, 1948 [CLKID_HCODEC] = &a9_hcodec.hw, 1949 [CLKID_VPU_0_SEL] = &a9_vpu_0_sel.hw, 1950 [CLKID_VPU_0_DIV] = &a9_vpu_0_div.hw, 1951 [CLKID_VPU_0] = &a9_vpu_0.hw, 1952 [CLKID_VPU_1_SEL] = &a9_vpu_1_sel.hw, 1953 [CLKID_VPU_1_DIV] = &a9_vpu_1_div.hw, 1954 [CLKID_VPU_1] = &a9_vpu_1.hw, 1955 [CLKID_VPU] = &a9_vpu.hw, 1956 [CLKID_VAPB_0_SEL] = &a9_vapb_0_sel.hw, 1957 [CLKID_VAPB_0_DIV] = &a9_vapb_0_div.hw, 1958 [CLKID_VAPB_0] = &a9_vapb_0.hw, 1959 [CLKID_VAPB_1_SEL] = &a9_vapb_1_sel.hw, 1960 [CLKID_VAPB_1_DIV] = &a9_vapb_1_div.hw, 1961 [CLKID_VAPB_1] = &a9_vapb_1.hw, 1962 [CLKID_VAPB] = &a9_vapb.hw, 1963 [CLKID_GE2D] = &a9_ge2d.hw, 1964 [CLKID_VPU_CLKB_TMP_SEL] = &a9_vpu_clkb_tmp_sel.hw, 1965 [CLKID_VPU_CLKB_TMP_DIV] = &a9_vpu_clkb_tmp_div.hw, 1966 [CLKID_VPU_CLKB_TMP] = &a9_vpu_clkb_tmp.hw, 1967 [CLKID_VPU_CLKB_DIV] = &a9_vpu_clkb_div.hw, 1968 [CLKID_VPU_CLKB] = &a9_vpu_clkb.hw, 1969 [CLKID_HDMITX_SYS_SEL] = &a9_hdmitx_sys_sel.hw, 1970 [CLKID_HDMITX_SYS_DIV] = &a9_hdmitx_sys_div.hw, 1971 [CLKID_HDMITX_SYS] = &a9_hdmitx_sys.hw, 1972 [CLKID_HDMITX_PRIF_SEL] = &a9_hdmitx_prif_sel.hw, 1973 [CLKID_HDMITX_PRIF_DIV] = &a9_hdmitx_prif_div.hw, 1974 [CLKID_HDMITX_PRIF] = &a9_hdmitx_prif.hw, 1975 [CLKID_HDMITX_200M_SEL] = &a9_hdmitx_200m_sel.hw, 1976 [CLKID_HDMITX_200M_DIV] = &a9_hdmitx_200m_div.hw, 1977 [CLKID_HDMITX_200M] = &a9_hdmitx_200m.hw, 1978 [CLKID_HDMITX_AUD_SEL] = &a9_hdmitx_aud_sel.hw, 1979 [CLKID_HDMITX_AUD_DIV] = &a9_hdmitx_aud_div.hw, 1980 [CLKID_HDMITX_AUD] = &a9_hdmitx_aud.hw, 1981 [CLKID_HDMIRX_5M_SEL] = &a9_hdmirx_5m_sel.hw, 1982 [CLKID_HDMIRX_5M_DIV] = &a9_hdmirx_5m_div.hw, 1983 [CLKID_HDMIRX_5M] = &a9_hdmirx_5m.hw, 1984 [CLKID_HDMIRX_2M_SEL] = &a9_hdmirx_2m_sel.hw, 1985 [CLKID_HDMIRX_2M_DIV] = &a9_hdmirx_2m_div.hw, 1986 [CLKID_HDMIRX_2M] = &a9_hdmirx_2m.hw, 1987 [CLKID_HDMIRX_CFG_SEL] = &a9_hdmirx_cfg_sel.hw, 1988 [CLKID_HDMIRX_CFG_DIV] = &a9_hdmirx_cfg_div.hw, 1989 [CLKID_HDMIRX_CFG] = &a9_hdmirx_cfg.hw, 1990 [CLKID_HDMIRX_HDCP2X_SEL] = &a9_hdmirx_hdcp2x_sel.hw, 1991 [CLKID_HDMIRX_HDCP2X_DIV] = &a9_hdmirx_hdcp2x_div.hw, 1992 [CLKID_HDMIRX_HDCP2X] = &a9_hdmirx_hdcp2x.hw, 1993 [CLKID_HDMIRX_ACR_REF_SEL] = &a9_hdmirx_acr_ref_sel.hw, 1994 [CLKID_HDMIRX_ACR_REF_DIV] = &a9_hdmirx_acr_ref_div.hw, 1995 [CLKID_HDMIRX_ACR_REF] = &a9_hdmirx_acr_ref.hw, 1996 [CLKID_HDMIRX_METER_SEL] = &a9_hdmirx_meter_sel.hw, 1997 [CLKID_HDMIRX_METER_DIV] = &a9_hdmirx_meter_div.hw, 1998 [CLKID_HDMIRX_METER] = &a9_hdmirx_meter.hw, 1999 [CLKID_VID_LOCK_SEL] = &a9_vid_lock_sel.hw, 2000 [CLKID_VID_LOCK_DIV] = &a9_vid_lock_div.hw, 2001 [CLKID_VID_LOCK] = &a9_vid_lock.hw, 2002 [CLKID_VDIN_MEAS_SEL] = &a9_vdin_meas_sel.hw, 2003 [CLKID_VDIN_MEAS_DIV] = &a9_vdin_meas_div.hw, 2004 [CLKID_VDIN_MEAS] = &a9_vdin_meas.hw, 2005 [CLKID_VID_PLL_DIV] = &a9_vid_pll_div.hw, 2006 [CLKID_VID_PLL_SEL] = &a9_vid_pll_sel.hw, 2007 [CLKID_VID_PLL] = &a9_vid_pll.hw, 2008 [CLKID_VID_PLL_VCLK] = &a9_vid_pll_vclk.hw, 2009 [CLKID_VCLK0_SEL] = &a9_vclk0_sel.hw, 2010 [CLKID_VCLK0_IN] = &a9_vclk0_in.hw, 2011 [CLKID_VCLK0_DIV] = &a9_vclk0_div.hw, 2012 [CLKID_VCLK0] = &a9_vclk0.hw, 2013 [CLKID_VCLK0_DIV1_EN] = &a9_vclk0_div1_en.hw, 2014 [CLKID_VCLK0_DIV2_EN] = &a9_vclk0_div2_en.hw, 2015 [CLKID_VCLK0_DIV2] = &a9_vclk0_div2.hw, 2016 [CLKID_VCLK0_DIV4_EN] = &a9_vclk0_div4_en.hw, 2017 [CLKID_VCLK0_DIV4] = &a9_vclk0_div4.hw, 2018 [CLKID_VCLK0_DIV6_EN] = &a9_vclk0_div6_en.hw, 2019 [CLKID_VCLK0_DIV6] = &a9_vclk0_div6.hw, 2020 [CLKID_VCLK0_DIV12_EN] = &a9_vclk0_div12_en.hw, 2021 [CLKID_VCLK0_DIV12] = &a9_vclk0_div12.hw, 2022 [CLKID_VCLK1_SEL] = &a9_vclk1_sel.hw, 2023 [CLKID_VCLK1_IN] = &a9_vclk1_in.hw, 2024 [CLKID_VCLK1_DIV] = &a9_vclk1_div.hw, 2025 [CLKID_VCLK1] = &a9_vclk1.hw, 2026 [CLKID_VCLK1_DIV1_EN] = &a9_vclk1_div1_en.hw, 2027 [CLKID_VCLK1_DIV2_EN] = &a9_vclk1_div2_en.hw, 2028 [CLKID_VCLK1_DIV2] = &a9_vclk1_div2.hw, 2029 [CLKID_VCLK1_DIV4_EN] = &a9_vclk1_div4_en.hw, 2030 [CLKID_VCLK1_DIV4] = &a9_vclk1_div4.hw, 2031 [CLKID_VCLK1_DIV6_EN] = &a9_vclk1_div6_en.hw, 2032 [CLKID_VCLK1_DIV6] = &a9_vclk1_div6.hw, 2033 [CLKID_VCLK1_DIV12_EN] = &a9_vclk1_div12_en.hw, 2034 [CLKID_VCLK1_DIV12] = &a9_vclk1_div12.hw, 2035 [CLKID_VDAC_SEL] = &a9_vdac_sel.hw, 2036 [CLKID_VDAC] = &a9_vdac.hw, 2037 [CLKID_ENCODER0_SEL] = &a9_encoder0_sel.hw, 2038 [CLKID_ENCODER0] = &a9_encoder0.hw, 2039 [CLKID_ENCODER1_SEL] = &a9_encoder1_sel.hw, 2040 [CLKID_ENCODER1] = &a9_encoder1.hw, 2041 [CLKID_HDMITX0_PIXEL_SEL] = &a9_hdmitx0_pixel_sel.hw, 2042 [CLKID_HDMITX0_PIXEL] = &a9_hdmitx0_pixel.hw, 2043 [CLKID_HDMITX0_FE_SEL] = &a9_hdmitx0_fe_sel.hw, 2044 [CLKID_HDMITX0_FE] = &a9_hdmitx0_fe.hw, 2045 [CLKID_HDMITX1_PIXEL_SEL] = &a9_hdmitx1_pixel_sel.hw, 2046 [CLKID_HDMITX1_PIXEL] = &a9_hdmitx1_pixel.hw, 2047 [CLKID_HDMITX1_FE_SEL] = &a9_hdmitx1_fe_sel.hw, 2048 [CLKID_HDMITX1_FE] = &a9_hdmitx1_fe.hw, 2049 [CLKID_CSI_PHY_SEL] = &a9_csi_phy_sel.hw, 2050 [CLKID_CSI_PHY_DIV] = &a9_csi_phy_div.hw, 2051 [CLKID_CSI_PHY] = &a9_csi_phy.hw, 2052 [CLKID_DSI0_MEAS_SEL] = &a9_dsi0_meas_sel.hw, 2053 [CLKID_DSI0_MEAS_DIV] = &a9_dsi0_meas_div.hw, 2054 [CLKID_DSI0_MEAS] = &a9_dsi0_meas.hw, 2055 [CLKID_DSI1_MEAS_SEL] = &a9_dsi1_meas_sel.hw, 2056 [CLKID_DSI1_MEAS_DIV] = &a9_dsi1_meas_div.hw, 2057 [CLKID_DSI1_MEAS] = &a9_dsi1_meas.hw, 2058 }; 2059 2060 static const struct meson_clkc_data a9_peripherals_clkc_data = { 2061 .hw_clks = { 2062 .hws = a9_peripherals_hw_clks, 2063 .num = ARRAY_SIZE(a9_peripherals_hw_clks), 2064 }, 2065 }; 2066 2067 static const struct of_device_id a9_peripherals_clkc_match_table[] = { 2068 { 2069 .compatible = "amlogic,a9-peripherals-clkc", 2070 .data = &a9_peripherals_clkc_data, 2071 }, 2072 { /* sentinel */ } 2073 }; 2074 2075 MODULE_DEVICE_TABLE(of, a9_peripherals_clkc_match_table); 2076 2077 static struct platform_driver a9_peripherals_clkc_driver = { 2078 .probe = meson_clkc_mmio_probe, 2079 .driver = { 2080 .name = "a9-peripherals-clkc", 2081 .of_match_table = a9_peripherals_clkc_match_table, 2082 }, 2083 }; 2084 module_platform_driver(a9_peripherals_clkc_driver); 2085 2086 MODULE_DESCRIPTION("Amlogic A9 Peripherals Clock Controller driver"); 2087 MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); 2088 MODULE_LICENSE("GPL"); 2089 MODULE_IMPORT_NS("CLK_MESON"); 2090