1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CPU_CACHE_ALIASING 10 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 11 select ARCH_HAS_CURRENT_STACK_POINTER 12 select ARCH_HAS_DEBUG_VIRTUAL if MMU 13 select ARCH_HAS_DMA_ALLOC if MMU 14 select ARCH_HAS_DMA_OPS 15 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 16 select ARCH_HAS_ELF_RANDOMIZE 17 select ARCH_HAS_FORTIFY_SOURCE 18 select ARCH_HAS_KEEPINITRD 19 select ARCH_HAS_KCOV 20 select ARCH_HAS_MEMBARRIER_SYNC_CORE 21 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 22 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 23 select ARCH_HAS_SETUP_DMA_OPS 24 select ARCH_HAS_SET_MEMORY 25 select ARCH_STACKWALK 26 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 27 select ARCH_HAS_STRICT_MODULE_RWX if MMU 28 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 29 select ARCH_HAS_SYNC_DMA_FOR_CPU 30 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 31 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 32 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 33 select ARCH_HAS_GCOV_PROFILE_ALL 34 select ARCH_KEEP_MEMBLOCK 35 select ARCH_HAS_UBSAN 36 select ARCH_MIGHT_HAVE_PC_PARPORT 37 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 38 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 39 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 40 select ARCH_SUPPORTS_ATOMIC_RMW 41 select ARCH_SUPPORTS_CFI 42 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 43 select ARCH_SUPPORTS_PER_VMA_LOCK 44 select ARCH_USE_BUILTIN_BSWAP 45 select ARCH_USE_CMPXCHG_LOCKREF 46 select ARCH_USE_MEMTEST 47 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 48 select ARCH_WANT_GENERAL_HUGETLB 49 select ARCH_WANT_IPC_PARSE_VERSION 50 select ARCH_WANT_LD_ORPHAN_WARN 51 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 52 select BUILDTIME_TABLE_SORT if MMU 53 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 54 select CLONE_BACKWARDS 55 select CPU_PM if SUSPEND || CPU_IDLE 56 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 57 select DMA_DECLARE_COHERENT 58 select DMA_GLOBAL_POOL if !MMU 59 select DMA_NONCOHERENT_MMAP if MMU 60 select EDAC_SUPPORT 61 select EDAC_ATOMIC_SCRUB 62 select GENERIC_ALLOCATOR 63 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 64 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 65 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 66 select GENERIC_IRQ_IPI if SMP 67 select GENERIC_CPU_AUTOPROBE 68 select GENERIC_CPU_DEVICES 69 select GENERIC_EARLY_IOREMAP 70 select GENERIC_IDLE_POLL_SETUP 71 select GENERIC_IRQ_MULTI_HANDLER 72 select GENERIC_IRQ_PROBE 73 select GENERIC_IRQ_SHOW 74 select GENERIC_IRQ_SHOW_LEVEL 75 select GENERIC_LIB_DEVMEM_IS_ALLOWED 76 select GENERIC_PCI_IOMAP 77 select GENERIC_SCHED_CLOCK 78 select GENERIC_SMP_IDLE_THREAD 79 select HARDIRQS_SW_RESEND 80 select HAS_IOPORT 81 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 83 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 84 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 85 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 86 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 87 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 88 select HAVE_ARCH_KSTACK_ERASE 89 select HAVE_ARCH_MMAP_RND_BITS if MMU 90 select HAVE_ARCH_PFN_VALID 91 select HAVE_ARCH_SECCOMP 92 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 93 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 94 select HAVE_ARCH_TRACEHOOK 95 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 96 select HAVE_ARM_SMCCC if CPU_V7 97 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 98 select HAVE_CONTEXT_TRACKING_USER 99 select HAVE_C_RECORDMCOUNT 100 select HAVE_BUILDTIME_MCOUNT_SORT 101 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 102 select HAVE_DMA_CONTIGUOUS if MMU 103 select HAVE_EXTRA_IPI_TRACEPOINTS 104 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 105 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 106 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 107 select HAVE_EXIT_THREAD 108 select HAVE_GUP_FAST if ARM_LPAE 109 select HAVE_FUNCTION_ERROR_INJECTION 110 select HAVE_FUNCTION_GRAPH_TRACER 111 select HAVE_FUNCTION_GRAPH_FREGS 112 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 113 select HAVE_GCC_PLUGINS 114 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 115 select HAVE_IRQ_TIME_ACCOUNTING 116 select HAVE_KERNEL_GZIP 117 select HAVE_KERNEL_LZ4 118 select HAVE_KERNEL_LZMA 119 select HAVE_KERNEL_LZO 120 select HAVE_KERNEL_XZ 121 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 122 select HAVE_KRETPROBES if HAVE_KPROBES 123 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY 124 select HAVE_MOD_ARCH_SPECIFIC 125 select HAVE_NMI 126 select HAVE_OPTPROBES if !THUMB2_KERNEL 127 select HAVE_PAGE_SIZE_4KB 128 select HAVE_PCI if MMU 129 select HAVE_PERF_EVENTS 130 select HAVE_PERF_REGS 131 select HAVE_PERF_USER_STACK_DUMP 132 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 133 select HAVE_REGS_AND_STACK_ACCESS_API 134 select HAVE_RSEQ 135 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 136 select HAVE_STACKPROTECTOR 137 select HAVE_SYSCALL_TRACEPOINTS 138 select HAVE_UID16 139 select HAVE_VIRT_CPU_ACCOUNTING_GEN 140 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 141 select IRQ_FORCED_THREADING 142 select LOCK_MM_AND_FIND_VMA 143 select MODULES_USE_ELF_REL 144 select NEED_DMA_MAP_STATE 145 select OF_EARLY_FLATTREE if OF 146 select OLD_SIGACTION 147 select OLD_SIGSUSPEND3 148 select PCI_DOMAINS_GENERIC if PCI 149 select PCI_SYSCALL if PCI 150 select PERF_USE_VMALLOC 151 select RTC_LIB 152 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 153 select SYS_SUPPORTS_APM_EMULATION 154 select THREAD_INFO_IN_TASK 155 select TIMER_OF if OF 156 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 157 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 158 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 159 # Above selects are sorted alphabetically; please add new ones 160 # according to that. Thanks. 161 help 162 The ARM series is a line of low-power-consumption RISC chip designs 163 licensed by ARM Ltd and targeted at embedded applications and 164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 165 manufactured, but legacy ARM-based PC hardware remains popular in 166 Europe. There is an ARM Linux project with a web page at 167 <http://www.arm.linux.org.uk/>. 168 169config ARM_HAS_GROUP_RELOCS 170 def_bool !COMPILE_TEST 171 help 172 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 173 relocations. The combined range is -/+ 256 MiB, which is usually 174 sufficient, but not for allyesconfig, so we disable this feature 175 when doing compile testing. 176 177config ARM_DMA_USE_IOMMU 178 bool 179 select NEED_SG_DMA_LENGTH 180 181if ARM_DMA_USE_IOMMU 182 183config ARM_DMA_IOMMU_ALIGNMENT 184 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 185 range 4 9 186 default 8 187 help 188 DMA mapping framework by default aligns all buffers to the smallest 189 PAGE_SIZE order which is greater than or equal to the requested buffer 190 size. This works well for buffers up to a few hundreds kilobytes, but 191 for larger buffers it just a waste of address space. Drivers which has 192 relatively small addressing window (like 64Mib) might run out of 193 virtual space with just a few allocations. 194 195 With this parameter you can specify the maximum PAGE_SIZE order for 196 DMA IOMMU buffers. Larger buffers will be aligned only to this 197 specified order. The order is expressed as a power of two multiplied 198 by the PAGE_SIZE. 199 200endif 201 202config SYS_SUPPORTS_APM_EMULATION 203 bool 204 205config HAVE_TCM 206 bool 207 select GENERIC_ALLOCATOR 208 209config HAVE_PROC_CPU 210 bool 211 212config NO_IOPORT_MAP 213 bool 214 215config SBUS 216 bool 217 218config STACKTRACE_SUPPORT 219 bool 220 default y 221 222config LOCKDEP_SUPPORT 223 bool 224 default y 225 226config ARCH_HAS_ILOG2_U32 227 bool 228 229config ARCH_HAS_ILOG2_U64 230 bool 231 232config ARCH_HAS_BANDGAP 233 bool 234 235config FIX_EARLYCON_MEM 236 def_bool y if MMU 237 238config GENERIC_HWEIGHT 239 bool 240 default y 241 242config GENERIC_CALIBRATE_DELAY 243 bool 244 default y 245 246config ARCH_MAY_HAVE_PC_FDC 247 bool 248 249config ARCH_SUPPORTS_UPROBES 250 def_bool y 251 252config GENERIC_ISA_DMA 253 bool 254 255config FIQ 256 bool 257 258config ARCH_MTD_XIP 259 bool 260 261config ARM_PATCH_PHYS_VIRT 262 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 263 default y 264 depends on MMU 265 help 266 Patch phys-to-virt and virt-to-phys translation functions at 267 boot and module load time according to the position of the 268 kernel in system memory. 269 270 This can only be used with non-XIP MMU kernels where the base 271 of physical memory is at a 2 MiB boundary. 272 273 Only disable this option if you know that you do not require 274 this feature (eg, building a kernel for a single machine) and 275 you need to shrink the kernel to the minimal size. 276 277config NEED_MACH_IO_H 278 bool 279 help 280 Select this when mach/io.h is required to provide special 281 definitions for this platform. The need for mach/io.h should 282 be avoided when possible. 283 284config NEED_MACH_MEMORY_H 285 bool 286 help 287 Select this when mach/memory.h is required to provide special 288 definitions for this platform. The need for mach/memory.h should 289 be avoided when possible. 290 291config PHYS_OFFSET 292 hex "Physical address of main memory" if MMU 293 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 294 default DRAM_BASE if !MMU 295 default 0x00000000 if ARCH_FOOTBRIDGE 296 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 297 default 0xa0000000 if ARCH_PXA 298 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 299 default 0 300 help 301 Please provide the physical address corresponding to the 302 location of main memory in your system. 303 304config GENERIC_BUG 305 def_bool y 306 depends on BUG 307 308config PGTABLE_LEVELS 309 int 310 default 3 if ARM_LPAE 311 default 2 312 313menu "System Type" 314 315config MMU 316 bool "MMU-based Paged Memory Management Support" 317 default y 318 help 319 Select if you want MMU-based virtualised addressing space 320 support by paged memory management. If unsure, say 'Y'. 321 322config ARM_SINGLE_ARMV7M 323 def_bool !MMU 324 select ARM_NVIC 325 select CPU_V7M 326 select NO_IOPORT_MAP 327 328config ARCH_MMAP_RND_BITS_MIN 329 default 8 330 331config ARCH_MMAP_RND_BITS_MAX 332 default 14 if PAGE_OFFSET=0x40000000 333 default 15 if PAGE_OFFSET=0x80000000 334 default 16 335 336config ARCH_MULTIPLATFORM 337 bool "Require kernel to be portable to multiple machines" if EXPERT 338 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 339 default y 340 help 341 In general, all Arm machines can be supported in a single 342 kernel image, covering either Armv4/v5 or Armv6/v7. 343 344 However, some configuration options require hardcoding machine 345 specific physical addresses or enable errata workarounds that may 346 break other machines. 347 348 Selecting N here allows using those options, including 349 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 350 351source "arch/arm/Kconfig.platforms" 352 353# 354# This is sorted alphabetically by mach-* pathname. However, plat-* 355# Kconfigs may be included either alphabetically (according to the 356# plat- suffix) or along side the corresponding mach-* source. 357# 358source "arch/arm/mach-actions/Kconfig" 359 360source "arch/arm/mach-alpine/Kconfig" 361 362source "arch/arm/mach-artpec/Kconfig" 363 364source "arch/arm/mach-aspeed/Kconfig" 365 366source "arch/arm/mach-at91/Kconfig" 367 368source "arch/arm/mach-axxia/Kconfig" 369 370source "arch/arm/mach-bcm/Kconfig" 371 372source "arch/arm/mach-berlin/Kconfig" 373 374source "arch/arm/mach-clps711x/Kconfig" 375 376source "arch/arm/mach-davinci/Kconfig" 377 378source "arch/arm/mach-digicolor/Kconfig" 379 380source "arch/arm/mach-dove/Kconfig" 381 382source "arch/arm/mach-ep93xx/Kconfig" 383 384source "arch/arm/mach-exynos/Kconfig" 385 386source "arch/arm/mach-footbridge/Kconfig" 387 388source "arch/arm/mach-gemini/Kconfig" 389 390source "arch/arm/mach-highbank/Kconfig" 391 392source "arch/arm/mach-hisi/Kconfig" 393 394source "arch/arm/mach-imx/Kconfig" 395 396source "arch/arm/mach-ixp4xx/Kconfig" 397 398source "arch/arm/mach-keystone/Kconfig" 399 400source "arch/arm/mach-lpc32xx/Kconfig" 401 402source "arch/arm/mach-mediatek/Kconfig" 403 404source "arch/arm/mach-meson/Kconfig" 405 406source "arch/arm/mach-milbeaut/Kconfig" 407 408source "arch/arm/mach-mmp/Kconfig" 409 410source "arch/arm/mach-mstar/Kconfig" 411 412source "arch/arm/mach-mv78xx0/Kconfig" 413 414source "arch/arm/mach-mvebu/Kconfig" 415 416source "arch/arm/mach-mxs/Kconfig" 417 418source "arch/arm/mach-nomadik/Kconfig" 419 420source "arch/arm/mach-npcm/Kconfig" 421 422source "arch/arm/mach-omap1/Kconfig" 423 424source "arch/arm/mach-omap2/Kconfig" 425 426source "arch/arm/mach-orion5x/Kconfig" 427 428source "arch/arm/mach-pxa/Kconfig" 429 430source "arch/arm/mach-qcom/Kconfig" 431 432source "arch/arm/mach-realtek/Kconfig" 433 434source "arch/arm/mach-rpc/Kconfig" 435 436source "arch/arm/mach-rockchip/Kconfig" 437 438source "arch/arm/mach-s3c/Kconfig" 439 440source "arch/arm/mach-s5pv210/Kconfig" 441 442source "arch/arm/mach-sa1100/Kconfig" 443 444source "arch/arm/mach-shmobile/Kconfig" 445 446source "arch/arm/mach-socfpga/Kconfig" 447 448source "arch/arm/mach-spear/Kconfig" 449 450source "arch/arm/mach-sti/Kconfig" 451 452source "arch/arm/mach-stm32/Kconfig" 453 454source "arch/arm/mach-sunxi/Kconfig" 455 456source "arch/arm/mach-tegra/Kconfig" 457 458source "arch/arm/mach-ux500/Kconfig" 459 460source "arch/arm/mach-versatile/Kconfig" 461 462source "arch/arm/mach-vt8500/Kconfig" 463 464source "arch/arm/mach-zynq/Kconfig" 465 466# ARMv7-M architecture 467config ARCH_LPC18XX 468 bool "NXP LPC18xx/LPC43xx" 469 depends on ARM_SINGLE_ARMV7M 470 select ARCH_HAS_RESET_CONTROLLER 471 select ARM_AMBA 472 select CLKSRC_LPC32XX 473 select PINCTRL 474 help 475 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 476 high performance microcontrollers. 477 478config ARCH_MPS2 479 bool "ARM MPS2 platform" 480 depends on ARM_SINGLE_ARMV7M 481 select ARM_AMBA 482 select CLKSRC_MPS2 483 help 484 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 485 with a range of available cores like Cortex-M3/M4/M7. 486 487 Please, note that depends which Application Note is used memory map 488 for the platform may vary, so adjustment of RAM base might be needed. 489 490# Definitions to make life easier 491config ARCH_ACORN 492 bool 493 494config PLAT_ORION 495 bool 496 select CLKSRC_MMIO 497 select GENERIC_IRQ_CHIP 498 select IRQ_DOMAIN 499 500config PLAT_ORION_LEGACY 501 bool 502 select PLAT_ORION 503 504config PLAT_VERSATILE 505 bool 506 507source "arch/arm/mm/Kconfig" 508 509config IWMMXT 510 bool "Enable iWMMXt support" 511 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 512 default y if PXA27x || PXA3xx || ARCH_MMP 513 help 514 Enable support for iWMMXt context switching at run time if 515 running on a CPU that supports it. 516 517if !MMU 518source "arch/arm/Kconfig-nommu" 519endif 520 521config PJ4B_ERRATA_4742 522 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 523 depends on CPU_PJ4B && MACH_ARMADA_370 524 default y 525 help 526 When coming out of either a Wait for Interrupt (WFI) or a Wait for 527 Event (WFE) IDLE states, a specific timing sensitivity exists between 528 the retiring WFI/WFE instructions and the newly issued subsequent 529 instructions. This sensitivity can result in a CPU hang scenario. 530 Workaround: 531 The software must insert either a Data Synchronization Barrier (DSB) 532 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 533 instruction 534 535config ARM_ERRATA_326103 536 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 537 depends on CPU_V6 538 help 539 Executing a SWP instruction to read-only memory does not set bit 11 540 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 541 treat the access as a read, preventing a COW from occurring and 542 causing the faulting task to livelock. 543 544config ARM_ERRATA_411920 545 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 546 depends on CPU_V6 || CPU_V6K 547 help 548 Invalidation of the Instruction Cache operation can 549 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 550 It does not affect the MPCore. This option enables the ARM Ltd. 551 recommended workaround. 552 553config ARM_ERRATA_430973 554 bool "ARM errata: Stale prediction on replaced interworking branch" 555 depends on CPU_V7 556 help 557 This option enables the workaround for the 430973 Cortex-A8 558 r1p* erratum. If a code sequence containing an ARM/Thumb 559 interworking branch is replaced with another code sequence at the 560 same virtual address, whether due to self-modifying code or virtual 561 to physical address re-mapping, Cortex-A8 does not recover from the 562 stale interworking branch prediction. This results in Cortex-A8 563 executing the new code sequence in the incorrect ARM or Thumb state. 564 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 565 and also flushes the branch target cache at every context switch. 566 Note that setting specific bits in the ACTLR register may not be 567 available in non-secure mode. 568 569config ARM_ERRATA_458693 570 bool "ARM errata: Processor deadlock when a false hazard is created" 571 depends on CPU_V7 572 depends on !ARCH_MULTIPLATFORM 573 help 574 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 575 erratum. For very specific sequences of memory operations, it is 576 possible for a hazard condition intended for a cache line to instead 577 be incorrectly associated with a different cache line. This false 578 hazard might then cause a processor deadlock. The workaround enables 579 the L1 caching of the NEON accesses and disables the PLD instruction 580 in the ACTLR register. Note that setting specific bits in the ACTLR 581 register may not be available in non-secure mode and thus is not 582 available on a multiplatform kernel. This should be applied by the 583 bootloader instead. 584 585config ARM_ERRATA_460075 586 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 587 depends on CPU_V7 588 depends on !ARCH_MULTIPLATFORM 589 help 590 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 591 erratum. Any asynchronous access to the L2 cache may encounter a 592 situation in which recent store transactions to the L2 cache are lost 593 and overwritten with stale memory contents from external memory. The 594 workaround disables the write-allocate mode for the L2 cache via the 595 ACTLR register. Note that setting specific bits in the ACTLR register 596 may not be available in non-secure mode and thus is not available on 597 a multiplatform kernel. This should be applied by the bootloader 598 instead. 599 600config ARM_ERRATA_742230 601 bool "ARM errata: DMB operation may be faulty" 602 depends on CPU_V7 && SMP 603 depends on !ARCH_MULTIPLATFORM 604 help 605 This option enables the workaround for the 742230 Cortex-A9 606 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 607 between two write operations may not ensure the correct visibility 608 ordering of the two writes. This workaround sets a specific bit in 609 the diagnostic register of the Cortex-A9 which causes the DMB 610 instruction to behave as a DSB, ensuring the correct behaviour of 611 the two writes. Note that setting specific bits in the diagnostics 612 register may not be available in non-secure mode and thus is not 613 available on a multiplatform kernel. This should be applied by the 614 bootloader instead. 615 616config ARM_ERRATA_742231 617 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 618 depends on CPU_V7 && SMP 619 depends on !ARCH_MULTIPLATFORM 620 help 621 This option enables the workaround for the 742231 Cortex-A9 622 (r2p0..r2p2) erratum. Under certain conditions, specific to the 623 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 624 accessing some data located in the same cache line, may get corrupted 625 data due to bad handling of the address hazard when the line gets 626 replaced from one of the CPUs at the same time as another CPU is 627 accessing it. This workaround sets specific bits in the diagnostic 628 register of the Cortex-A9 which reduces the linefill issuing 629 capabilities of the processor. Note that setting specific bits in the 630 diagnostics register may not be available in non-secure mode and thus 631 is not available on a multiplatform kernel. This should be applied by 632 the bootloader instead. 633 634config ARM_ERRATA_643719 635 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 636 depends on CPU_V7 && SMP 637 default y 638 help 639 This option enables the workaround for the 643719 Cortex-A9 (prior to 640 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 641 register returns zero when it should return one. The workaround 642 corrects this value, ensuring cache maintenance operations which use 643 it behave as intended and avoiding data corruption. 644 645config ARM_ERRATA_720789 646 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 647 depends on CPU_V7 648 help 649 This option enables the workaround for the 720789 Cortex-A9 (prior to 650 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 651 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 652 As a consequence of this erratum, some TLB entries which should be 653 invalidated are not, resulting in an incoherency in the system page 654 tables. The workaround changes the TLB flushing routines to invalidate 655 entries regardless of the ASID. 656 657config ARM_ERRATA_743622 658 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 659 depends on CPU_V7 660 depends on !ARCH_MULTIPLATFORM 661 help 662 This option enables the workaround for the 743622 Cortex-A9 663 (r2p*) erratum. Under very rare conditions, a faulty 664 optimisation in the Cortex-A9 Store Buffer may lead to data 665 corruption. This workaround sets a specific bit in the diagnostic 666 register of the Cortex-A9 which disables the Store Buffer 667 optimisation, preventing the defect from occurring. This has no 668 visible impact on the overall performance or power consumption of the 669 processor. Note that setting specific bits in the diagnostics register 670 may not be available in non-secure mode and thus is not available on a 671 multiplatform kernel. This should be applied by the bootloader instead. 672 673config ARM_ERRATA_751472 674 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 675 depends on CPU_V7 676 depends on !ARCH_MULTIPLATFORM 677 help 678 This option enables the workaround for the 751472 Cortex-A9 (prior 679 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 680 completion of a following broadcasted operation if the second 681 operation is received by a CPU before the ICIALLUIS has completed, 682 potentially leading to corrupted entries in the cache or TLB. 683 Note that setting specific bits in the diagnostics register may 684 not be available in non-secure mode and thus is not available on 685 a multiplatform kernel. This should be applied by the bootloader 686 instead. 687 688config ARM_ERRATA_754322 689 bool "ARM errata: possible faulty MMU translations following an ASID switch" 690 depends on CPU_V7 691 help 692 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 693 r3p*) erratum. A speculative memory access may cause a page table walk 694 which starts prior to an ASID switch but completes afterwards. This 695 can populate the micro-TLB with a stale entry which may be hit with 696 the new ASID. This workaround places two dsb instructions in the mm 697 switching code so that no page table walks can cross the ASID switch. 698 699config ARM_ERRATA_754327 700 bool "ARM errata: no automatic Store Buffer drain" 701 depends on CPU_V7 && SMP 702 help 703 This option enables the workaround for the 754327 Cortex-A9 (prior to 704 r2p0) erratum. The Store Buffer does not have any automatic draining 705 mechanism and therefore a livelock may occur if an external agent 706 continuously polls a memory location waiting to observe an update. 707 This workaround defines cpu_relax() as smp_mb(), preventing correctly 708 written polling loops from denying visibility of updates to memory. 709 710config ARM_ERRATA_364296 711 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 712 depends on CPU_V6 713 help 714 This options enables the workaround for the 364296 ARM1136 715 r0p2 erratum (possible cache data corruption with 716 hit-under-miss enabled). It sets the undocumented bit 31 in 717 the auxiliary control register and the FI bit in the control 718 register, thus disabling hit-under-miss without putting the 719 processor into full low interrupt latency mode. ARM11MPCore 720 is not affected. 721 722config ARM_ERRATA_764369 723 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 724 depends on CPU_V7 && SMP 725 help 726 This option enables the workaround for erratum 764369 727 affecting Cortex-A9 MPCore with two or more processors (all 728 current revisions). Under certain timing circumstances, a data 729 cache line maintenance operation by MVA targeting an Inner 730 Shareable memory region may fail to proceed up to either the 731 Point of Coherency or to the Point of Unification of the 732 system. This workaround adds a DSB instruction before the 733 relevant cache maintenance functions and sets a specific bit 734 in the diagnostic control register of the SCU. 735 736config ARM_ERRATA_764319 737 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 738 depends on CPU_V7 739 help 740 This option enables the workaround for the 764319 Cortex-A9 erratum. 741 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 742 unexpected Undefined Instruction exception when the DBGSWENABLE 743 external pin is set to 0, even when the CP14 accesses are performed 744 from a privileged mode. This work around catches the exception in a 745 way the kernel does not stop execution. 746 747config ARM_ERRATA_775420 748 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 749 depends on CPU_V7 750 help 751 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 752 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 753 operation aborts with MMU exception, it might cause the processor 754 to deadlock. This workaround puts DSB before executing ISB if 755 an abort may occur on cache maintenance. 756 757config ARM_ERRATA_798181 758 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 759 depends on CPU_V7 && SMP 760 help 761 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 762 adequately shooting down all use of the old entries. This 763 option enables the Linux kernel workaround for this erratum 764 which sends an IPI to the CPUs that are running the same ASID 765 as the one being invalidated. 766 767config ARM_ERRATA_773022 768 bool "ARM errata: incorrect instructions may be executed from loop buffer" 769 depends on CPU_V7 770 help 771 This option enables the workaround for the 773022 Cortex-A15 772 (up to r0p4) erratum. In certain rare sequences of code, the 773 loop buffer may deliver incorrect instructions. This 774 workaround disables the loop buffer to avoid the erratum. 775 776config ARM_ERRATA_818325_852422 777 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 778 depends on CPU_V7 779 help 780 This option enables the workaround for: 781 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 782 instruction might deadlock. Fixed in r0p1. 783 - Cortex-A12 852422: Execution of a sequence of instructions might 784 lead to either a data corruption or a CPU deadlock. Not fixed in 785 any Cortex-A12 cores yet. 786 This workaround for all both errata involves setting bit[12] of the 787 Feature Register. This bit disables an optimisation applied to a 788 sequence of 2 instructions that use opposing condition codes. 789 790config ARM_ERRATA_821420 791 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 792 depends on CPU_V7 793 help 794 This option enables the workaround for the 821420 Cortex-A12 795 (all revs) erratum. In very rare timing conditions, a sequence 796 of VMOV to Core registers instructions, for which the second 797 one is in the shadow of a branch or abort, can lead to a 798 deadlock when the VMOV instructions are issued out-of-order. 799 800config ARM_ERRATA_825619 801 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 802 depends on CPU_V7 803 help 804 This option enables the workaround for the 825619 Cortex-A12 805 (all revs) erratum. Within rare timing constraints, executing a 806 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 807 and Device/Strongly-Ordered loads and stores might cause deadlock 808 809config ARM_ERRATA_857271 810 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 811 depends on CPU_V7 812 help 813 This option enables the workaround for the 857271 Cortex-A12 814 (all revs) erratum. Under very rare timing conditions, the CPU might 815 hang. The workaround is expected to have a < 1% performance impact. 816 817config ARM_ERRATA_852421 818 bool "ARM errata: A17: DMB ST might fail to create order between stores" 819 depends on CPU_V7 820 help 821 This option enables the workaround for the 852421 Cortex-A17 822 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 823 execution of a DMB ST instruction might fail to properly order 824 stores from GroupA and stores from GroupB. 825 826config ARM_ERRATA_852423 827 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 828 depends on CPU_V7 829 help 830 This option enables the workaround for: 831 - Cortex-A17 852423: Execution of a sequence of instructions might 832 lead to either a data corruption or a CPU deadlock. Not fixed in 833 any Cortex-A17 cores yet. 834 This is identical to Cortex-A12 erratum 852422. It is a separate 835 config option from the A12 erratum due to the way errata are checked 836 for and handled. 837 838config ARM_ERRATA_857272 839 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 840 depends on CPU_V7 841 help 842 This option enables the workaround for the 857272 Cortex-A17 erratum. 843 This erratum is not known to be fixed in any A17 revision. 844 This is identical to Cortex-A12 erratum 857271. It is a separate 845 config option from the A12 erratum due to the way errata are checked 846 for and handled. 847 848endmenu 849 850source "arch/arm/common/Kconfig" 851 852menu "Bus support" 853 854config ISA 855 bool 856 help 857 Find out whether you have ISA slots on your motherboard. ISA is the 858 name of a bus system, i.e. the way the CPU talks to the other stuff 859 inside your box. Other bus systems are PCI, EISA, MicroChannel 860 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 861 newer boards don't support it. If you have ISA, say Y, otherwise N. 862 863# Select ISA DMA interface 864config ISA_DMA_API 865 bool 866 867config ARM_ERRATA_814220 868 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 869 depends on CPU_V7 870 help 871 The v7 ARM states that all cache and branch predictor maintenance 872 operations that do not specify an address execute, relative to 873 each other, in program order. 874 However, because of this erratum, an L2 set/way cache maintenance 875 operation can overtake an L1 set/way cache maintenance operation. 876 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 877 r0p4, r0p5. 878 879endmenu 880 881menu "Kernel Features" 882 883config HAVE_SMP 884 bool 885 help 886 This option should be selected by machines which have an SMP- 887 capable CPU. 888 889 The only effect of this option is to make the SMP-related 890 options available to the user for configuration. 891 892config SMP 893 bool "Symmetric Multi-Processing" 894 depends on CPU_V6K || CPU_V7 895 depends on HAVE_SMP 896 depends on MMU || ARM_MPU 897 select IRQ_WORK 898 help 899 This enables support for systems with more than one CPU. If you have 900 a system with only one CPU, say N. If you have a system with more 901 than one CPU, say Y. 902 903 If you say N here, the kernel will run on uni- and multiprocessor 904 machines, but will use only one CPU of a multiprocessor machine. If 905 you say Y here, the kernel will run on many, but not all, 906 uniprocessor machines. On a uniprocessor machine, the kernel 907 will run faster if you say N here. 908 909 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 910 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 911 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 912 913 If you don't know what to do here, say N. 914 915config SMP_ON_UP 916 bool "Allow booting SMP kernel on uniprocessor systems" 917 depends on SMP && MMU 918 default y 919 help 920 SMP kernels contain instructions which fail on non-SMP processors. 921 Enabling this option allows the kernel to modify itself to make 922 these instructions safe. Disabling it allows about 1K of space 923 savings. 924 925 If you don't know what to do here, say Y. 926 927 928config CURRENT_POINTER_IN_TPIDRURO 929 def_bool y 930 depends on CPU_32v6K && !CPU_V6 931 932config IRQSTACKS 933 def_bool y 934 select HAVE_IRQ_EXIT_ON_IRQ_STACK 935 select HAVE_SOFTIRQ_ON_OWN_STACK 936 937config ARM_CPU_TOPOLOGY 938 bool "Support cpu topology definition" 939 depends on SMP && CPU_V7 940 select ARCH_SUPPORTS_SCHED_MC 941 select ARCH_SUPPORTS_SCHED_SMT 942 default y 943 help 944 Support ARM cpu topology definition. The MPIDR register defines 945 affinity between processors which is then used to describe the cpu 946 topology of an ARM System. 947 948config HAVE_ARM_SCU 949 bool 950 help 951 This option enables support for the ARM snoop control unit 952 953config HAVE_ARM_ARCH_TIMER 954 bool "Architected timer support" 955 depends on CPU_V7 956 select ARM_ARCH_TIMER 957 help 958 This option enables support for the ARM architected timer 959 960config HAVE_ARM_TWD 961 bool 962 help 963 This options enables support for the ARM timer and watchdog unit 964 965config MCPM 966 bool "Multi-Cluster Power Management" 967 depends on CPU_V7 && SMP 968 help 969 This option provides the common power management infrastructure 970 for (multi-)cluster based systems, such as big.LITTLE based 971 systems. 972 973config MCPM_QUAD_CLUSTER 974 bool 975 depends on MCPM 976 help 977 To avoid wasting resources unnecessarily, MCPM only supports up 978 to 2 clusters by default. 979 Platforms with 3 or 4 clusters that use MCPM must select this 980 option to allow the additional clusters to be managed. 981 982config BIG_LITTLE 983 bool "big.LITTLE support (Experimental)" 984 depends on CPU_V7 && SMP 985 select MCPM 986 help 987 This option enables support selections for the big.LITTLE 988 system architecture. 989 990config BL_SWITCHER 991 bool "big.LITTLE switcher support" 992 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 993 select CPU_PM 994 help 995 The big.LITTLE "switcher" provides the core functionality to 996 transparently handle transition between a cluster of A15's 997 and a cluster of A7's in a big.LITTLE system. 998 999config BL_SWITCHER_DUMMY_IF 1000 tristate "Simple big.LITTLE switcher user interface" 1001 depends on BL_SWITCHER && DEBUG_KERNEL 1002 help 1003 This is a simple and dummy char dev interface to control 1004 the big.LITTLE switcher core code. It is meant for 1005 debugging purposes only. 1006 1007choice 1008 prompt "Memory split" 1009 depends on MMU 1010 default VMSPLIT_3G 1011 help 1012 Select the desired split between kernel and user memory. 1013 1014 If you are not absolutely sure what you are doing, leave this 1015 option alone! 1016 1017 config VMSPLIT_3G 1018 bool "3G/1G user/kernel split" 1019 config VMSPLIT_3G_OPT 1020 depends on !ARM_LPAE 1021 bool "3G/1G user/kernel split (for full 1G low memory)" 1022 config VMSPLIT_2G 1023 bool "2G/2G user/kernel split" 1024 config VMSPLIT_1G 1025 bool "1G/3G user/kernel split" 1026endchoice 1027 1028config PAGE_OFFSET 1029 hex 1030 default PHYS_OFFSET if !MMU 1031 default 0x40000000 if VMSPLIT_1G 1032 default 0x80000000 if VMSPLIT_2G 1033 default 0xB0000000 if VMSPLIT_3G_OPT 1034 default 0xC0000000 1035 1036config KASAN_SHADOW_OFFSET 1037 hex 1038 depends on KASAN 1039 default 0x1f000000 if PAGE_OFFSET=0x40000000 1040 default 0x5f000000 if PAGE_OFFSET=0x80000000 1041 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1042 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1043 default 0xffffffff 1044 1045config NR_CPUS 1046 int "Maximum number of CPUs (2-32)" 1047 range 2 16 if DEBUG_KMAP_LOCAL 1048 range 2 32 if !DEBUG_KMAP_LOCAL 1049 depends on SMP 1050 default "4" 1051 help 1052 The maximum number of CPUs that the kernel can support. 1053 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1054 debugging is enabled, which uses half of the per-CPU fixmap 1055 slots as guard regions. 1056 1057config HOTPLUG_CPU 1058 bool "Support for hot-pluggable CPUs" 1059 depends on SMP 1060 select GENERIC_IRQ_MIGRATION 1061 help 1062 Say Y here to experiment with turning CPUs off and on. CPUs 1063 can be controlled through /sys/devices/system/cpu. 1064 1065config ARM_PSCI 1066 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1067 depends on HAVE_ARM_SMCCC 1068 select ARM_PSCI_FW 1069 help 1070 Say Y here if you want Linux to communicate with system firmware 1071 implementing the PSCI specification for CPU-centric power 1072 management operations described in ARM document number ARM DEN 1073 0022A ("Power State Coordination Interface System Software on 1074 ARM processors"). 1075 1076config HZ_FIXED 1077 int 1078 default 128 if SOC_AT91RM9200 1079 default 0 1080 1081choice 1082 depends on HZ_FIXED = 0 1083 prompt "Timer frequency" 1084 1085config HZ_100 1086 bool "100 Hz" 1087 1088config HZ_200 1089 bool "200 Hz" 1090 1091config HZ_250 1092 bool "250 Hz" 1093 1094config HZ_300 1095 bool "300 Hz" 1096 1097config HZ_500 1098 bool "500 Hz" 1099 1100config HZ_1000 1101 bool "1000 Hz" 1102 1103endchoice 1104 1105config HZ 1106 int 1107 default HZ_FIXED if HZ_FIXED != 0 1108 default 100 if HZ_100 1109 default 200 if HZ_200 1110 default 250 if HZ_250 1111 default 300 if HZ_300 1112 default 500 if HZ_500 1113 default 1000 1114 1115config SCHED_HRTICK 1116 def_bool HIGH_RES_TIMERS 1117 1118config THUMB2_KERNEL 1119 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1120 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1121 default y if CPU_THUMBONLY 1122 select ARM_UNWIND 1123 help 1124 By enabling this option, the kernel will be compiled in 1125 Thumb-2 mode. 1126 1127 If unsure, say N. 1128 1129config ARM_PATCH_IDIV 1130 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1131 depends on CPU_32v7 1132 default y 1133 help 1134 The ARM compiler inserts calls to __aeabi_idiv() and 1135 __aeabi_uidiv() when it needs to perform division on signed 1136 and unsigned integers. Some v7 CPUs have support for the sdiv 1137 and udiv instructions that can be used to implement those 1138 functions. 1139 1140 Enabling this option allows the kernel to modify itself to 1141 replace the first two instructions of these library functions 1142 with the sdiv or udiv plus "bx lr" instructions when the CPU 1143 it is running on supports them. Typically this will be faster 1144 and less power intensive than running the original library 1145 code to do integer division. 1146 1147config AEABI 1148 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1149 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1150 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1151 help 1152 This option allows for the kernel to be compiled using the latest 1153 ARM ABI (aka EABI). This is only useful if you are using a user 1154 space environment that is also compiled with EABI. 1155 1156 Since there are major incompatibilities between the legacy ABI and 1157 EABI, especially with regard to structure member alignment, this 1158 option also changes the kernel syscall calling convention to 1159 disambiguate both ABIs and allow for backward compatibility support 1160 (selected with CONFIG_OABI_COMPAT). 1161 1162 To use this you need GCC version 4.0.0 or later. 1163 1164config OABI_COMPAT 1165 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1166 depends on AEABI && !THUMB2_KERNEL 1167 help 1168 This option preserves the old syscall interface along with the 1169 new (ARM EABI) one. It also provides a compatibility layer to 1170 intercept syscalls that have structure arguments which layout 1171 in memory differs between the legacy ABI and the new ARM EABI 1172 (only for non "thumb" binaries). This option adds a tiny 1173 overhead to all syscalls and produces a slightly larger kernel. 1174 1175 The seccomp filter system will not be available when this is 1176 selected, since there is no way yet to sensibly distinguish 1177 between calling conventions during filtering. 1178 1179 If you know you'll be using only pure EABI user space then you 1180 can say N here. If this option is not selected and you attempt 1181 to execute a legacy ABI binary then the result will be 1182 UNPREDICTABLE (in fact it can be predicted that it won't work 1183 at all). If in doubt say N. 1184 1185config ARCH_SELECT_MEMORY_MODEL 1186 def_bool y 1187 1188config ARCH_FLATMEM_ENABLE 1189 def_bool !(ARCH_RPC || ARCH_SA1100) 1190 1191config ARCH_SPARSEMEM_ENABLE 1192 def_bool !ARCH_FOOTBRIDGE 1193 select SPARSEMEM_STATIC if SPARSEMEM 1194 1195config HIGHMEM 1196 bool "High Memory Support" 1197 depends on MMU 1198 select KMAP_LOCAL 1199 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1200 help 1201 The address space of ARM processors is only 4 Gigabytes large 1202 and it has to accommodate user address space, kernel address 1203 space as well as some memory mapped IO. That means that, if you 1204 have a large amount of physical memory and/or IO, not all of the 1205 memory can be "permanently mapped" by the kernel. The physical 1206 memory that is not permanently mapped is called "high memory". 1207 1208 Depending on the selected kernel/user memory split, minimum 1209 vmalloc space and actual amount of RAM, you may not need this 1210 option which should result in a slightly faster kernel. 1211 1212 If unsure, say n. 1213 1214config HIGHPTE 1215 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1216 depends on HIGHMEM 1217 default y 1218 help 1219 The VM uses one page of physical memory for each page table. 1220 For systems with a lot of processes, this can use a lot of 1221 precious low memory, eventually leading to low memory being 1222 consumed by page tables. Setting this option will allow 1223 user-space 2nd level page tables to reside in high memory. 1224 1225config ARM_PAN 1226 bool "Enable privileged no-access" 1227 depends on MMU 1228 default y 1229 help 1230 Increase kernel security by ensuring that normal kernel accesses 1231 are unable to access userspace addresses. This can help prevent 1232 use-after-free bugs becoming an exploitable privilege escalation 1233 by ensuring that magic values (such as LIST_POISON) will always 1234 fault when dereferenced. 1235 1236 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1237 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1238 1239config CPU_SW_DOMAIN_PAN 1240 def_bool y 1241 depends on ARM_PAN && !ARM_LPAE 1242 help 1243 Enable use of CPU domains to implement privileged no-access. 1244 1245 CPUs with low-vector mappings use a best-efforts implementation. 1246 Their lower 1MB needs to remain accessible for the vectors, but 1247 the remainder of userspace will become appropriately inaccessible. 1248 1249config CPU_TTBR0_PAN 1250 def_bool y 1251 depends on ARM_PAN && ARM_LPAE 1252 help 1253 Enable privileged no-access by disabling TTBR0 page table walks when 1254 running in kernel mode. 1255 1256config HW_PERF_EVENTS 1257 def_bool y 1258 depends on ARM_PMU 1259 1260config ARM_MODULE_PLTS 1261 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1262 depends on MODULES 1263 select KASAN_VMALLOC if KASAN 1264 default y 1265 help 1266 Allocate PLTs when loading modules so that jumps and calls whose 1267 targets are too far away for their relative offsets to be encoded 1268 in the instructions themselves can be bounced via veneers in the 1269 module's PLT. This allows modules to be allocated in the generic 1270 vmalloc area after the dedicated module memory area has been 1271 exhausted. The modules will use slightly more memory, but after 1272 rounding up to page size, the actual memory footprint is usually 1273 the same. 1274 1275 Disabling this is usually safe for small single-platform 1276 configurations. If unsure, say y. 1277 1278config ARCH_FORCE_MAX_ORDER 1279 int "Order of maximal physically contiguous allocations" 1280 default "11" if SOC_AM33XX 1281 default "8" if SA1111 1282 default "10" 1283 help 1284 The kernel page allocator limits the size of maximal physically 1285 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1286 defines the maximal power of two of number of pages that can be 1287 allocated as a single contiguous block. This option allows 1288 overriding the default setting when ability to allocate very 1289 large blocks of physically contiguous memory is required. 1290 1291 Don't change if unsure. 1292 1293config ALIGNMENT_TRAP 1294 def_bool CPU_CP15_MMU 1295 select HAVE_PROC_CPU if PROC_FS 1296 help 1297 ARM processors cannot fetch/store information which is not 1298 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1299 address divisible by 4. On 32-bit ARM processors, these non-aligned 1300 fetch/store instructions will be emulated in software if you say 1301 here, which has a severe performance impact. This is necessary for 1302 correct operation of some network protocols. With an IP-only 1303 configuration it is safe to say N, otherwise say Y. 1304 1305config UACCESS_WITH_MEMCPY 1306 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1307 depends on MMU 1308 default y if CPU_FEROCEON 1309 help 1310 Implement faster copy_to_user and clear_user methods for CPU 1311 cores where a 8-word STM instruction give significantly higher 1312 memory write throughput than a sequence of individual 32bit stores. 1313 1314 A possible side effect is a slight increase in scheduling latency 1315 between threads sharing the same address space if they invoke 1316 such copy operations with large buffers. 1317 1318 However, if the CPU data cache is using a write-allocate mode, 1319 this option is unlikely to provide any performance gain. 1320 1321config PARAVIRT 1322 bool "Enable paravirtualization code" 1323 help 1324 This changes the kernel so it can modify itself when it is run 1325 under a hypervisor, potentially improving performance significantly 1326 over full virtualization. 1327 1328config PARAVIRT_TIME_ACCOUNTING 1329 bool "Paravirtual steal time accounting" 1330 select PARAVIRT 1331 help 1332 Select this option to enable fine granularity task steal time 1333 accounting. Time spent executing other tasks in parallel with 1334 the current vCPU is discounted from the vCPU power. To account for 1335 that, there can be a small performance impact. 1336 1337 If in doubt, say N here. 1338 1339config XEN_DOM0 1340 def_bool y 1341 depends on XEN 1342 1343config XEN 1344 bool "Xen guest support on ARM" 1345 depends on ARM && AEABI && OF 1346 depends on CPU_V7 && !CPU_V6 1347 depends on !GENERIC_ATOMIC64 1348 depends on MMU 1349 select ARCH_DMA_ADDR_T_64BIT 1350 select ARM_PSCI 1351 select SWIOTLB 1352 select SWIOTLB_XEN 1353 select PARAVIRT 1354 help 1355 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1356 1357config CC_HAVE_STACKPROTECTOR_TLS 1358 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1359 1360config STACKPROTECTOR_PER_TASK 1361 bool "Use a unique stack canary value for each task" 1362 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1363 depends on CC_HAVE_STACKPROTECTOR_TLS 1364 default y 1365 help 1366 Due to the fact that GCC uses an ordinary symbol reference from 1367 which to load the value of the stack canary, this value can only 1368 change at reboot time on SMP systems, and all tasks running in the 1369 kernel's address space are forced to use the same canary value for 1370 the entire duration that the system is up. 1371 1372 Enable this option to switch to a different method that uses a 1373 different canary value for each task. 1374 1375endmenu 1376 1377menu "Boot options" 1378 1379config USE_OF 1380 bool "Flattened Device Tree support" 1381 select IRQ_DOMAIN 1382 select OF 1383 help 1384 Include support for flattened device tree machine descriptions. 1385 1386config ARCH_WANT_FLAT_DTB_INSTALL 1387 def_bool y 1388 1389config ATAGS 1390 bool "Support for the traditional ATAGS boot data passing" 1391 default y 1392 help 1393 This is the traditional way of passing data to the kernel at boot 1394 time. If you are solely relying on the flattened device tree (or 1395 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1396 to remove ATAGS support from your kernel binary. 1397 1398config DEPRECATED_PARAM_STRUCT 1399 bool "Provide old way to pass kernel parameters" 1400 depends on ATAGS 1401 help 1402 This was deprecated in 2001 and announced to live on for 5 years. 1403 Some old boot loaders still use this way. 1404 1405# Compressed boot loader in ROM. Yes, we really want to ask about 1406# TEXT and BSS so we preserve their values in the config files. 1407config ZBOOT_ROM_TEXT 1408 hex "Compressed ROM boot loader base address" 1409 default 0x0 1410 help 1411 The physical address at which the ROM-able zImage is to be 1412 placed in the target. Platforms which normally make use of 1413 ROM-able zImage formats normally set this to a suitable 1414 value in their defconfig file. 1415 1416 If ZBOOT_ROM is not enabled, this has no effect. 1417 1418config ZBOOT_ROM_BSS 1419 hex "Compressed ROM boot loader BSS address" 1420 default 0x0 1421 help 1422 The base address of an area of read/write memory in the target 1423 for the ROM-able zImage which must be available while the 1424 decompressor is running. It must be large enough to hold the 1425 entire decompressed kernel plus an additional 128 KiB. 1426 Platforms which normally make use of ROM-able zImage formats 1427 normally set this to a suitable value in their defconfig file. 1428 1429 If ZBOOT_ROM is not enabled, this has no effect. 1430 1431config ZBOOT_ROM 1432 bool "Compressed boot loader in ROM/flash" 1433 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1434 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1435 help 1436 Say Y here if you intend to execute your compressed kernel image 1437 (zImage) directly from ROM or flash. If unsure, say N. 1438 1439config ARM_APPENDED_DTB 1440 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1441 depends on OF 1442 help 1443 With this option, the boot code will look for a device tree binary 1444 (DTB) appended to zImage 1445 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1446 1447 This is meant as a backward compatibility convenience for those 1448 systems with a bootloader that can't be upgraded to accommodate 1449 the documented boot protocol using a device tree. 1450 1451 Beware that there is very little in terms of protection against 1452 this option being confused by leftover garbage in memory that might 1453 look like a DTB header after a reboot if no actual DTB is appended 1454 to zImage. Do not leave this option active in a production kernel 1455 if you don't intend to always append a DTB. Proper passing of the 1456 location into r2 of a bootloader provided DTB is always preferable 1457 to this option. 1458 1459config ARM_ATAG_DTB_COMPAT 1460 bool "Supplement the appended DTB with traditional ATAG information" 1461 depends on ARM_APPENDED_DTB 1462 help 1463 Some old bootloaders can't be updated to a DTB capable one, yet 1464 they provide ATAGs with memory configuration, the ramdisk address, 1465 the kernel cmdline string, etc. Such information is dynamically 1466 provided by the bootloader and can't always be stored in a static 1467 DTB. To allow a device tree enabled kernel to be used with such 1468 bootloaders, this option allows zImage to extract the information 1469 from the ATAG list and store it at run time into the appended DTB. 1470 1471choice 1472 prompt "Kernel command line type" 1473 depends on ARM_ATAG_DTB_COMPAT 1474 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1475 1476config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1477 bool "Use bootloader kernel arguments if available" 1478 help 1479 Uses the command-line options passed by the boot loader instead of 1480 the device tree bootargs property. If the boot loader doesn't provide 1481 any, the device tree bootargs property will be used. 1482 1483config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1484 bool "Extend with bootloader kernel arguments" 1485 help 1486 The command-line arguments provided by the boot loader will be 1487 appended to the the device tree bootargs property. 1488 1489endchoice 1490 1491config CMDLINE 1492 string "Default kernel command string" 1493 default "" 1494 help 1495 On some architectures (e.g. CATS), there is currently no way 1496 for the boot loader to pass arguments to the kernel. For these 1497 architectures, you should supply some command-line options at build 1498 time by entering them here. As a minimum, you should specify the 1499 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1500 1501choice 1502 prompt "Kernel command line type" 1503 depends on CMDLINE != "" 1504 default CMDLINE_FROM_BOOTLOADER 1505 1506config CMDLINE_FROM_BOOTLOADER 1507 bool "Use bootloader kernel arguments if available" 1508 help 1509 Uses the command-line options passed by the boot loader. If 1510 the boot loader doesn't provide any, the default kernel command 1511 string provided in CMDLINE will be used. 1512 1513config CMDLINE_EXTEND 1514 bool "Extend bootloader kernel arguments" 1515 help 1516 The command-line arguments provided by the boot loader will be 1517 appended to the default kernel command string. 1518 1519config CMDLINE_FORCE 1520 bool "Always use the default kernel command string" 1521 help 1522 Always use the default kernel command string, even if the boot 1523 loader passes other arguments to the kernel. 1524 This is useful if you cannot or don't want to change the 1525 command-line options your boot loader passes to the kernel. 1526endchoice 1527 1528config XIP_KERNEL 1529 bool "Kernel Execute-In-Place from ROM" 1530 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1531 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1532 help 1533 Execute-In-Place allows the kernel to run from non-volatile storage 1534 directly addressable by the CPU, such as NOR flash. This saves RAM 1535 space since the text section of the kernel is not loaded from flash 1536 to RAM. Read-write sections, such as the data section and stack, 1537 are still copied to RAM. The XIP kernel is not compressed since 1538 it has to run directly from flash, so it will take more space to 1539 store it. The flash address used to link the kernel object files, 1540 and for storing it, is configuration dependent. Therefore, if you 1541 say Y here, you must know the proper physical address where to 1542 store the kernel image depending on your own flash memory usage. 1543 1544 Also note that the make target becomes "make xipImage" rather than 1545 "make zImage" or "make Image". The final kernel binary to put in 1546 ROM memory will be arch/arm/boot/xipImage. 1547 1548 If unsure, say N. 1549 1550config XIP_PHYS_ADDR 1551 hex "XIP Kernel Physical Location" 1552 depends on XIP_KERNEL 1553 default "0x00080000" 1554 help 1555 This is the physical address in your flash memory the kernel will 1556 be linked for and stored to. This address is dependent on your 1557 own flash usage. 1558 1559config XIP_DEFLATED_DATA 1560 bool "Store kernel .data section compressed in ROM" 1561 depends on XIP_KERNEL 1562 select ZLIB_INFLATE 1563 help 1564 Before the kernel is actually executed, its .data section has to be 1565 copied to RAM from ROM. This option allows for storing that data 1566 in compressed form and decompressed to RAM rather than merely being 1567 copied, saving some precious ROM space. A possible drawback is a 1568 slightly longer boot delay. 1569 1570config ARCH_SUPPORTS_KEXEC 1571 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1572 1573config ATAGS_PROC 1574 bool "Export atags in procfs" 1575 depends on ATAGS && KEXEC 1576 default y 1577 help 1578 Should the atags used to boot the kernel be exported in an "atags" 1579 file in procfs. Useful with kexec. 1580 1581config ARCH_SUPPORTS_CRASH_DUMP 1582 def_bool y 1583 1584config ARCH_DEFAULT_CRASH_DUMP 1585 def_bool y 1586 1587config AUTO_ZRELADDR 1588 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1589 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1590 help 1591 ZRELADDR is the physical address where the decompressed kernel 1592 image will be placed. If AUTO_ZRELADDR is selected, the address 1593 will be determined at run-time, either by masking the current IP 1594 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1595 This assumes the zImage being placed in the first 128MB from 1596 start of memory. 1597 1598config EFI_STUB 1599 bool 1600 1601config EFI 1602 bool "UEFI runtime support" 1603 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1604 select UCS2_STRING 1605 select EFI_PARAMS_FROM_FDT 1606 select EFI_STUB 1607 select EFI_GENERIC_STUB 1608 select EFI_RUNTIME_WRAPPERS 1609 help 1610 This option provides support for runtime services provided 1611 by UEFI firmware (such as non-volatile variables, realtime 1612 clock, and platform reset). A UEFI stub is also provided to 1613 allow the kernel to be booted as an EFI application. This 1614 is only useful for kernels that may run on systems that have 1615 UEFI firmware. 1616 1617config DMI 1618 bool "Enable support for SMBIOS (DMI) tables" 1619 depends on EFI 1620 default y 1621 help 1622 This enables SMBIOS/DMI feature for systems. 1623 1624 This option is only useful on systems that have UEFI firmware. 1625 However, even with this option, the resultant kernel should 1626 continue to boot on existing non-UEFI platforms. 1627 1628 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1629 i.e., the the practice of identifying the platform via DMI to 1630 decide whether certain workarounds for buggy hardware and/or 1631 firmware need to be enabled. This would require the DMI subsystem 1632 to be enabled much earlier than we do on ARM, which is non-trivial. 1633 1634endmenu 1635 1636menu "CPU Power Management" 1637 1638source "drivers/cpufreq/Kconfig" 1639 1640source "drivers/cpuidle/Kconfig" 1641 1642endmenu 1643 1644menu "Floating point emulation" 1645 1646comment "At least one emulation must be selected" 1647 1648config FPE_NWFPE 1649 bool "NWFPE math emulation" 1650 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1651 help 1652 Say Y to include the NWFPE floating point emulator in the kernel. 1653 This is necessary to run most binaries. Linux does not currently 1654 support floating point hardware so you need to say Y here even if 1655 your machine has an FPA or floating point co-processor podule. 1656 1657 You may say N here if you are going to load the Acorn FPEmulator 1658 early in the bootup. 1659 1660config FPE_NWFPE_XP 1661 bool "Support extended precision" 1662 depends on FPE_NWFPE 1663 help 1664 Say Y to include 80-bit support in the kernel floating-point 1665 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1666 Note that gcc does not generate 80-bit operations by default, 1667 so in most cases this option only enlarges the size of the 1668 floating point emulator without any good reason. 1669 1670 You almost surely want to say N here. 1671 1672config FPE_FASTFPE 1673 bool "FastFPE math emulation (EXPERIMENTAL)" 1674 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1675 help 1676 Say Y here to include the FAST floating point emulator in the kernel. 1677 This is an experimental much faster emulator which now also has full 1678 precision for the mantissa. It does not support any exceptions. 1679 It is very simple, and approximately 3-6 times faster than NWFPE. 1680 1681 It should be sufficient for most programs. It may be not suitable 1682 for scientific calculations, but you have to check this for yourself. 1683 If you do not feel you need a faster FP emulation you should better 1684 choose NWFPE. 1685 1686config VFP 1687 bool "VFP-format floating point maths" 1688 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1689 help 1690 Say Y to include VFP support code in the kernel. This is needed 1691 if your hardware includes a VFP unit. 1692 1693 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1694 release notes and additional status information. 1695 1696 Say N if your target does not have VFP hardware. 1697 1698config VFPv3 1699 bool 1700 depends on VFP 1701 default y if CPU_V7 1702 1703config NEON 1704 bool "Advanced SIMD (NEON) Extension support" 1705 depends on VFPv3 && CPU_V7 1706 help 1707 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1708 Extension. 1709 1710config KERNEL_MODE_NEON 1711 bool "Support for NEON in kernel mode" 1712 depends on NEON && AEABI 1713 help 1714 Say Y to include support for NEON in kernel mode. 1715 1716endmenu 1717 1718menu "Power management options" 1719 1720source "kernel/power/Kconfig" 1721 1722config ARCH_SUSPEND_POSSIBLE 1723 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1724 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1725 def_bool y 1726 1727config ARM_CPU_SUSPEND 1728 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1729 depends on ARCH_SUSPEND_POSSIBLE 1730 1731config ARCH_HIBERNATION_POSSIBLE 1732 bool 1733 depends on MMU 1734 default y if ARCH_SUSPEND_POSSIBLE 1735 1736endmenu 1737