1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 32config GIC_NON_BANKED 33 bool 34 35config ARM_GIC_V3 36 bool 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 42config ARM_GIC_V3_ITS 43 bool 44 select GENERIC_MSI_IRQ 45 select IRQ_MSI_LIB 46 default ARM_GIC_V3 47 48config ARM_GIC_V3_ITS_FSL_MC 49 bool 50 depends on ARM_GIC_V3_ITS 51 depends on FSL_MC_BUS 52 default ARM_GIC_V3_ITS 53 54config ARM_NVIC 55 bool 56 select IRQ_DOMAIN_HIERARCHY 57 select GENERIC_IRQ_CHIP 58 59config ARM_VIC 60 bool 61 select IRQ_DOMAIN 62 63config ARM_VIC_NR 64 int 65 default 4 if ARCH_S5PV210 66 default 2 67 depends on ARM_VIC 68 help 69 The maximum number of VICs available in the system, for 70 power management. 71 72config IRQ_MSI_LIB 73 bool 74 75config ARMADA_370_XP_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select PCI_MSI if PCI 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 80 81config ALPINE_MSI 82 bool 83 depends on PCI 84 select PCI_MSI 85 select GENERIC_IRQ_CHIP 86 87config AL_FIC 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 89 depends on OF 90 depends on HAS_IOMEM 91 select GENERIC_IRQ_CHIP 92 select IRQ_DOMAIN 93 help 94 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 95 96config ATMEL_AIC_IRQ 97 bool 98 select GENERIC_IRQ_CHIP 99 select IRQ_DOMAIN 100 select SPARSE_IRQ 101 102config ATMEL_AIC5_IRQ 103 bool 104 select GENERIC_IRQ_CHIP 105 select IRQ_DOMAIN 106 select SPARSE_IRQ 107 108config I8259 109 bool 110 select IRQ_DOMAIN 111 112config BCM6345_L1_IRQ 113 bool 114 select GENERIC_IRQ_CHIP 115 select IRQ_DOMAIN 116 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 117 118config BCM7038_L1_IRQ 119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 120 depends on ARCH_BRCMSTB || BMIPS_GENERIC 121 default ARCH_BRCMSTB || BMIPS_GENERIC 122 select GENERIC_IRQ_CHIP 123 select IRQ_DOMAIN 124 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 125 126config BCM7120_L2_IRQ 127 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 128 depends on ARCH_BRCMSTB || BMIPS_GENERIC 129 default ARCH_BRCMSTB || BMIPS_GENERIC 130 select GENERIC_IRQ_CHIP 131 select IRQ_DOMAIN 132 133config BRCMSTB_L2_IRQ 134 tristate "Broadcom STB generic L2 interrupt controller driver" 135 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 136 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 137 select GENERIC_IRQ_CHIP 138 select IRQ_DOMAIN 139 140config DAVINCI_CP_INTC 141 bool 142 select GENERIC_IRQ_CHIP 143 select IRQ_DOMAIN 144 145config DW_APB_ICTL 146 bool 147 select GENERIC_IRQ_CHIP 148 select IRQ_DOMAIN_HIERARCHY 149 150config FARADAY_FTINTC010 151 bool 152 select IRQ_DOMAIN 153 select SPARSE_IRQ 154 155config HISILICON_IRQ_MBIGEN 156 bool 157 select ARM_GIC_V3 158 select ARM_GIC_V3_ITS 159 160config IMGPDC_IRQ 161 bool 162 select GENERIC_IRQ_CHIP 163 select IRQ_DOMAIN 164 165config IXP4XX_IRQ 166 bool 167 select IRQ_DOMAIN 168 select SPARSE_IRQ 169 170config LAN966X_OIC 171 tristate "Microchip LAN966x OIC Support" 172 select GENERIC_IRQ_CHIP 173 select IRQ_DOMAIN 174 help 175 Enable support for the LAN966x Outbound Interrupt Controller. 176 This controller is present on the Microchip LAN966x PCI device and 177 maps the internal interrupts sources to PCIe interrupt. 178 179 To compile this driver as a module, choose M here: the module 180 will be called irq-lan966x-oic. 181 182config MADERA_IRQ 183 tristate 184 185config IRQ_MIPS_CPU 186 bool 187 select GENERIC_IRQ_CHIP 188 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 189 select IRQ_DOMAIN 190 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 191 192config CLPS711X_IRQCHIP 193 bool 194 depends on ARCH_CLPS711X 195 select IRQ_DOMAIN 196 select SPARSE_IRQ 197 default y 198 199config OMPIC 200 bool 201 202config OR1K_PIC 203 bool 204 select IRQ_DOMAIN 205 206config OMAP_IRQCHIP 207 bool 208 select GENERIC_IRQ_CHIP 209 select IRQ_DOMAIN 210 211config ORION_IRQCHIP 212 bool 213 select IRQ_DOMAIN 214 215config PIC32_EVIC 216 bool 217 select GENERIC_IRQ_CHIP 218 select IRQ_DOMAIN 219 220config JCORE_AIC 221 bool "J-Core integrated AIC" if COMPILE_TEST 222 depends on OF 223 select IRQ_DOMAIN 224 help 225 Support for the J-Core integrated AIC. 226 227config RDA_INTC 228 bool 229 select IRQ_DOMAIN 230 231config RENESAS_INTC_IRQPIN 232 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 233 select IRQ_DOMAIN 234 help 235 Enable support for the Renesas Interrupt Controller for external 236 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 237 238config RENESAS_IRQC 239 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 240 select GENERIC_IRQ_CHIP 241 select IRQ_DOMAIN 242 help 243 Enable support for the Renesas Interrupt Controller for external 244 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 245 246config RENESAS_RZA1_IRQC 247 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 248 select IRQ_DOMAIN_HIERARCHY 249 help 250 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 251 to 8 external interrupts with configurable sense select. 252 253config RENESAS_RZG2L_IRQC 254 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 255 select GENERIC_IRQ_CHIP 256 select IRQ_DOMAIN_HIERARCHY 257 help 258 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 259 for external devices. 260 261config SL28CPLD_INTC 262 bool "Kontron sl28cpld IRQ controller" 263 depends on MFD_SL28CPLD=y || COMPILE_TEST 264 select REGMAP_IRQ 265 help 266 Interrupt controller driver for the board management controller 267 found on the Kontron sl28 CPLD. 268 269config ST_IRQCHIP 270 bool 271 select REGMAP 272 select MFD_SYSCON 273 help 274 Enables SysCfg Controlled IRQs on STi based platforms. 275 276config SUN4I_INTC 277 bool 278 279config SUN6I_R_INTC 280 bool 281 select IRQ_DOMAIN_HIERARCHY 282 select IRQ_FASTEOI_HIERARCHY_HANDLERS 283 284config SUNXI_NMI_INTC 285 bool 286 select GENERIC_IRQ_CHIP 287 288config TB10X_IRQC 289 bool 290 select IRQ_DOMAIN 291 select GENERIC_IRQ_CHIP 292 293config TS4800_IRQ 294 tristate "TS-4800 IRQ controller" 295 select IRQ_DOMAIN 296 depends on HAS_IOMEM 297 depends on SOC_IMX51 || COMPILE_TEST 298 help 299 Support for the TS-4800 FPGA IRQ controller 300 301config VERSATILE_FPGA_IRQ 302 bool 303 select IRQ_DOMAIN 304 305config VERSATILE_FPGA_IRQ_NR 306 int 307 default 4 308 depends on VERSATILE_FPGA_IRQ 309 310config XTENSA_MX 311 bool 312 select IRQ_DOMAIN 313 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 314 315config XILINX_INTC 316 bool "Xilinx Interrupt Controller IP" 317 depends on OF_ADDRESS 318 select IRQ_DOMAIN 319 help 320 Support for the Xilinx Interrupt Controller IP core. 321 This is used as a primary controller with MicroBlaze and can also 322 be used as a secondary chained controller on other platforms. 323 324config IRQ_CROSSBAR 325 bool 326 help 327 Support for a CROSSBAR ip that precedes the main interrupt controller. 328 The primary irqchip invokes the crossbar's callback which inturn allocates 329 a free irq and configures the IP. Thus the peripheral interrupts are 330 routed to one of the free irqchip interrupt lines. 331 332config KEYSTONE_IRQ 333 tristate "Keystone 2 IRQ controller IP" 334 depends on ARCH_KEYSTONE 335 help 336 Support for Texas Instruments Keystone 2 IRQ controller IP which 337 is part of the Keystone 2 IPC mechanism 338 339config MIPS_GIC 340 bool 341 select GENERIC_IRQ_IPI if SMP 342 select IRQ_DOMAIN_HIERARCHY 343 select MIPS_CM 344 345config INGENIC_IRQ 346 bool 347 depends on MACH_INGENIC 348 default y 349 350config INGENIC_TCU_IRQ 351 bool "Ingenic JZ47xx TCU interrupt controller" 352 default MACH_INGENIC 353 depends on MIPS || COMPILE_TEST 354 select MFD_SYSCON 355 select GENERIC_IRQ_CHIP 356 help 357 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 358 JZ47xx SoCs. 359 360 If unsure, say N. 361 362config IMX_GPCV2 363 bool 364 select IRQ_DOMAIN 365 help 366 Enables the wakeup IRQs for IMX platforms with GPCv2 block 367 368config IRQ_MXS 369 def_bool y if MACH_ASM9260 || ARCH_MXS 370 select IRQ_DOMAIN 371 select STMP_DEVICE 372 373config MSCC_OCELOT_IRQ 374 bool 375 select IRQ_DOMAIN 376 select GENERIC_IRQ_CHIP 377 378config MVEBU_GICP 379 select IRQ_MSI_LIB 380 bool 381 382config MVEBU_ICU 383 bool 384 385config MVEBU_ODMI 386 bool 387 select IRQ_MSI_LIB 388 select GENERIC_MSI_IRQ 389 390config MVEBU_PIC 391 bool 392 393config MVEBU_SEI 394 bool 395 396config LS_EXTIRQ 397 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 398 select MFD_SYSCON 399 400config LS_SCFG_MSI 401 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 402 depends on PCI_MSI 403 404config PARTITION_PERCPU 405 bool 406 407config STM32MP_EXTI 408 tristate "STM32MP extended interrupts and event controller" 409 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 410 default y 411 select IRQ_DOMAIN_HIERARCHY 412 select GENERIC_IRQ_CHIP 413 help 414 Support STM32MP EXTI (extended interrupts and event) controller. 415 416config STM32_EXTI 417 bool 418 select IRQ_DOMAIN 419 select GENERIC_IRQ_CHIP 420 421config QCOM_IRQ_COMBINER 422 bool "QCOM IRQ combiner support" 423 depends on ARCH_QCOM && ACPI 424 select IRQ_DOMAIN_HIERARCHY 425 help 426 Say yes here to add support for the IRQ combiner devices embedded 427 in Qualcomm Technologies chips. 428 429config IRQ_UNIPHIER_AIDET 430 bool "UniPhier AIDET support" if COMPILE_TEST 431 depends on ARCH_UNIPHIER || COMPILE_TEST 432 default ARCH_UNIPHIER 433 select IRQ_DOMAIN_HIERARCHY 434 help 435 Support for the UniPhier AIDET (ARM Interrupt Detector). 436 437config MESON_IRQ_GPIO 438 tristate "Meson GPIO Interrupt Multiplexer" 439 depends on ARCH_MESON || COMPILE_TEST 440 default ARCH_MESON 441 select IRQ_DOMAIN_HIERARCHY 442 help 443 Support Meson SoC Family GPIO Interrupt Multiplexer 444 445config GOLDFISH_PIC 446 bool "Goldfish programmable interrupt controller" 447 depends on MIPS && (GOLDFISH || COMPILE_TEST) 448 select GENERIC_IRQ_CHIP 449 select IRQ_DOMAIN 450 help 451 Say yes here to enable Goldfish interrupt controller driver used 452 for Goldfish based virtual platforms. 453 454config QCOM_PDC 455 tristate "QCOM PDC" 456 depends on ARCH_QCOM 457 select IRQ_DOMAIN_HIERARCHY 458 help 459 Power Domain Controller driver to manage and configure wakeup 460 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 461 462config QCOM_MPM 463 tristate "QCOM MPM" 464 depends on ARCH_QCOM 465 depends on MAILBOX 466 select IRQ_DOMAIN_HIERARCHY 467 help 468 MSM Power Manager driver to manage and configure wakeup 469 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 470 471config CSKY_MPINTC 472 bool 473 depends on CSKY 474 help 475 Say yes here to enable C-SKY SMP interrupt controller driver used 476 for C-SKY SMP system. 477 In fact it's not mmio map in hardware and it uses ld/st to visit the 478 controller's register inside CPU. 479 480config CSKY_APB_INTC 481 bool "C-SKY APB Interrupt Controller" 482 depends on CSKY 483 help 484 Say yes here to enable C-SKY APB interrupt controller driver used 485 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 486 the controller's register. 487 488config IMX_IRQSTEER 489 bool "i.MX IRQSTEER support" 490 depends on ARCH_MXC || COMPILE_TEST 491 default ARCH_MXC 492 select IRQ_DOMAIN 493 help 494 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 495 496config IMX_INTMUX 497 bool "i.MX INTMUX support" if COMPILE_TEST 498 default y if ARCH_MXC 499 select IRQ_DOMAIN 500 help 501 Support for the i.MX INTMUX interrupt multiplexer. 502 503config IMX_MU_MSI 504 tristate "i.MX MU used as MSI controller" 505 depends on OF && HAS_IOMEM 506 depends on ARCH_MXC || COMPILE_TEST 507 default m if ARCH_MXC 508 select IRQ_DOMAIN 509 select IRQ_DOMAIN_HIERARCHY 510 select GENERIC_MSI_IRQ 511 select IRQ_MSI_LIB 512 help 513 Provide a driver for the i.MX Messaging Unit block used as a 514 CPU-to-CPU MSI controller. This requires a specially crafted DT 515 to make use of this driver. 516 517 If unsure, say N 518 519config LS1X_IRQ 520 bool "Loongson-1 Interrupt Controller" 521 depends on MACH_LOONGSON32 522 default y 523 select IRQ_DOMAIN 524 select GENERIC_IRQ_CHIP 525 help 526 Support for the Loongson-1 platform Interrupt Controller. 527 528config TI_SCI_INTR_IRQCHIP 529 bool 530 depends on TI_SCI_PROTOCOL 531 select IRQ_DOMAIN_HIERARCHY 532 help 533 This enables the irqchip driver support for K3 Interrupt router 534 over TI System Control Interface available on some new TI's SoCs. 535 If you wish to use interrupt router irq resources managed by the 536 TI System Controller, say Y here. Otherwise, say N. 537 538config TI_SCI_INTA_IRQCHIP 539 bool 540 depends on TI_SCI_PROTOCOL 541 select IRQ_DOMAIN_HIERARCHY 542 select TI_SCI_INTA_MSI_DOMAIN 543 help 544 This enables the irqchip driver support for K3 Interrupt aggregator 545 over TI System Control Interface available on some new TI's SoCs. 546 If you wish to use interrupt aggregator irq resources managed by the 547 TI System Controller, say Y here. Otherwise, say N. 548 549config TI_PRUSS_INTC 550 tristate 551 depends on TI_PRUSS 552 default TI_PRUSS 553 select IRQ_DOMAIN 554 help 555 This enables support for the PRU-ICSS Local Interrupt Controller 556 present within a PRU-ICSS subsystem present on various TI SoCs. 557 The PRUSS INTC enables various interrupts to be routed to multiple 558 different processors within the SoC. 559 560config RISCV_INTC 561 bool 562 depends on RISCV 563 select IRQ_DOMAIN_HIERARCHY 564 565config RISCV_APLIC 566 bool 567 depends on RISCV 568 select IRQ_DOMAIN_HIERARCHY 569 570config RISCV_APLIC_MSI 571 bool 572 depends on RISCV_APLIC 573 select GENERIC_MSI_IRQ 574 default RISCV_APLIC 575 576config RISCV_IMSIC 577 bool 578 depends on RISCV 579 select IRQ_DOMAIN_HIERARCHY 580 select GENERIC_IRQ_MATRIX_ALLOCATOR 581 select GENERIC_MSI_IRQ 582 583config RISCV_IMSIC_PCI 584 bool 585 depends on RISCV_IMSIC 586 depends on PCI 587 depends on PCI_MSI 588 default RISCV_IMSIC 589 590config SIFIVE_PLIC 591 bool 592 depends on RISCV 593 select IRQ_DOMAIN_HIERARCHY 594 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 595 596config STARFIVE_JH8100_INTC 597 bool "StarFive JH8100 External Interrupt Controller" 598 depends on ARCH_STARFIVE || COMPILE_TEST 599 default ARCH_STARFIVE 600 select IRQ_DOMAIN_HIERARCHY 601 help 602 This enables support for the INTC chip found in StarFive JH8100 603 SoC. 604 605 If you don't know what to do here, say Y. 606 607config EXYNOS_IRQ_COMBINER 608 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 609 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 610 help 611 Say yes here to add support for the IRQ combiner devices embedded 612 in Samsung Exynos chips. 613 614config IRQ_LOONGARCH_CPU 615 bool 616 select GENERIC_IRQ_CHIP 617 select IRQ_DOMAIN 618 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 619 select LOONGSON_HTVEC 620 select LOONGSON_LIOINTC 621 select LOONGSON_EIOINTC 622 select LOONGSON_PCH_PIC 623 select LOONGSON_PCH_MSI 624 select LOONGSON_PCH_LPC 625 help 626 Support for the LoongArch CPU Interrupt Controller. For details of 627 irq chip hierarchy on LoongArch platforms please read the document 628 Documentation/arch/loongarch/irq-chip-model.rst. 629 630config LOONGSON_LIOINTC 631 bool "Loongson Local I/O Interrupt Controller" 632 depends on MACH_LOONGSON64 633 default y 634 select IRQ_DOMAIN 635 select GENERIC_IRQ_CHIP 636 help 637 Support for the Loongson Local I/O Interrupt Controller. 638 639config LOONGSON_EIOINTC 640 bool "Loongson Extend I/O Interrupt Controller" 641 depends on LOONGARCH 642 depends on MACH_LOONGSON64 643 default MACH_LOONGSON64 644 select IRQ_DOMAIN_HIERARCHY 645 select GENERIC_IRQ_CHIP 646 help 647 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 648 649config LOONGSON_HTPIC 650 bool "Loongson3 HyperTransport PIC Controller" 651 depends on MACH_LOONGSON64 && MIPS 652 default y 653 select IRQ_DOMAIN 654 select GENERIC_IRQ_CHIP 655 help 656 Support for the Loongson-3 HyperTransport PIC Controller. 657 658config LOONGSON_HTVEC 659 bool "Loongson HyperTransport Interrupt Vector Controller" 660 depends on MACH_LOONGSON64 661 default MACH_LOONGSON64 662 select IRQ_DOMAIN_HIERARCHY 663 help 664 Support for the Loongson HyperTransport Interrupt Vector Controller. 665 666config LOONGSON_PCH_PIC 667 bool "Loongson PCH PIC Controller" 668 depends on MACH_LOONGSON64 669 default MACH_LOONGSON64 670 select IRQ_DOMAIN_HIERARCHY 671 select IRQ_FASTEOI_HIERARCHY_HANDLERS 672 help 673 Support for the Loongson PCH PIC Controller. 674 675config LOONGSON_PCH_MSI 676 bool "Loongson PCH MSI Controller" 677 depends on MACH_LOONGSON64 678 depends on PCI 679 default MACH_LOONGSON64 680 select IRQ_DOMAIN_HIERARCHY 681 select IRQ_MSI_LIB 682 select PCI_MSI 683 help 684 Support for the Loongson PCH MSI Controller. 685 686config LOONGSON_PCH_LPC 687 bool "Loongson PCH LPC Controller" 688 depends on LOONGARCH 689 depends on MACH_LOONGSON64 690 default MACH_LOONGSON64 691 select IRQ_DOMAIN_HIERARCHY 692 help 693 Support for the Loongson PCH LPC Controller. 694 695config MST_IRQ 696 bool "MStar Interrupt Controller" 697 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 698 default ARCH_MEDIATEK 699 select IRQ_DOMAIN 700 select IRQ_DOMAIN_HIERARCHY 701 help 702 Support MStar Interrupt Controller. 703 704config WPCM450_AIC 705 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 706 depends on ARCH_WPCM450 707 help 708 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 709 710config IRQ_IDT3243X 711 bool 712 select GENERIC_IRQ_CHIP 713 select IRQ_DOMAIN 714 715config APPLE_AIC 716 bool "Apple Interrupt Controller (AIC)" 717 depends on ARM64 718 depends on ARCH_APPLE || COMPILE_TEST 719 select GENERIC_IRQ_IPI_MUX 720 help 721 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 722 such as the M1. 723 724config MCHP_EIC 725 bool "Microchip External Interrupt Controller" 726 depends on ARCH_AT91 || COMPILE_TEST 727 select IRQ_DOMAIN 728 select IRQ_DOMAIN_HIERARCHY 729 help 730 Support for Microchip External Interrupt Controller. 731 732config SUNPLUS_SP7021_INTC 733 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 734 default SOC_SP7021 735 help 736 Support for the Sunplus SP7021 Interrupt Controller IP core. 737 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 738 chained controller, routing all interrupt source in P-Chip to 739 the primary controller on C-Chip. 740 741endmenu 742