1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select PARTITION_PERCPU 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 41 select HAVE_ARM_SMCCC_DISCOVERY 42 select IRQ_MSI_IOMMU 43 44config ARM_GIC_V3_ITS 45 bool 46 select GENERIC_MSI_IRQ 47 select IRQ_MSI_LIB 48 default ARM_GIC_V3 49 select IRQ_MSI_IOMMU 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config IRQ_MSI_LIB 76 bool 77 select GENERIC_MSI_IRQ 78 79config ARMADA_370_XP_IRQ 80 bool 81 select GENERIC_IRQ_CHIP 82 select PCI_MSI if PCI 83 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 84 85config ALPINE_MSI 86 bool 87 depends on PCI 88 select PCI_MSI 89 select GENERIC_IRQ_CHIP 90 91config AL_FIC 92 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 93 depends on OF 94 depends on HAS_IOMEM 95 select GENERIC_IRQ_CHIP 96 select IRQ_DOMAIN 97 help 98 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 99 100config ATMEL_AIC_IRQ 101 bool 102 select GENERIC_IRQ_CHIP 103 select IRQ_DOMAIN 104 select SPARSE_IRQ 105 106config ATMEL_AIC5_IRQ 107 bool 108 select GENERIC_IRQ_CHIP 109 select IRQ_DOMAIN 110 select SPARSE_IRQ 111 112config I8259 113 bool 114 select IRQ_DOMAIN 115 116config BCM2712_MIP 117 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 118 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 119 default m if ARCH_BRCMSTB || ARCH_BCM2835 120 depends on ARM_GIC 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN_HIERARCHY 123 select GENERIC_MSI_IRQ 124 select IRQ_MSI_LIB 125 help 126 Enable support for the Broadcom BCM2712 MSI-X target peripheral 127 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 128 Raspberry Pi 5. 129 130 If unsure say n. 131 132config BCM6345_L1_IRQ 133 bool 134 select GENERIC_IRQ_CHIP 135 select IRQ_DOMAIN 136 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 137 138config BCM7038_L1_IRQ 139 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 140 depends on ARCH_BRCMSTB || BMIPS_GENERIC 141 default ARCH_BRCMSTB || BMIPS_GENERIC 142 select GENERIC_IRQ_CHIP 143 select IRQ_DOMAIN 144 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 145 146config BCM7120_L2_IRQ 147 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 148 depends on ARCH_BRCMSTB || BMIPS_GENERIC 149 default ARCH_BRCMSTB || BMIPS_GENERIC 150 select GENERIC_IRQ_CHIP 151 select IRQ_DOMAIN 152 153config BRCMSTB_L2_IRQ 154 tristate "Broadcom STB generic L2 interrupt controller driver" 155 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 156 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 157 select GENERIC_IRQ_CHIP 158 select IRQ_DOMAIN 159 160config DAVINCI_CP_INTC 161 bool 162 select GENERIC_IRQ_CHIP 163 select IRQ_DOMAIN 164 165config DW_APB_ICTL 166 bool 167 select GENERIC_IRQ_CHIP 168 select IRQ_DOMAIN_HIERARCHY 169 170config ECONET_EN751221_INTC 171 bool 172 select GENERIC_IRQ_CHIP 173 select IRQ_DOMAIN 174 175config FARADAY_FTINTC010 176 bool 177 select IRQ_DOMAIN 178 select SPARSE_IRQ 179 180config HISILICON_IRQ_MBIGEN 181 bool 182 select ARM_GIC_V3 183 select ARM_GIC_V3_ITS 184 185config IMGPDC_IRQ 186 bool 187 select GENERIC_IRQ_CHIP 188 select IRQ_DOMAIN 189 190config IXP4XX_IRQ 191 bool 192 select IRQ_DOMAIN 193 select SPARSE_IRQ 194 195config LAN966X_OIC 196 tristate "Microchip LAN966x OIC Support" 197 depends on MCHP_LAN966X_PCI || COMPILE_TEST 198 select GENERIC_IRQ_CHIP 199 select IRQ_DOMAIN 200 help 201 Enable support for the LAN966x Outbound Interrupt Controller. 202 This controller is present on the Microchip LAN966x PCI device and 203 maps the internal interrupts sources to PCIe interrupt. 204 205 To compile this driver as a module, choose M here: the module 206 will be called irq-lan966x-oic. 207 208config MADERA_IRQ 209 tristate 210 211config IRQ_MIPS_CPU 212 bool 213 select GENERIC_IRQ_CHIP 214 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 215 select IRQ_DOMAIN 216 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 217 218config CLPS711X_IRQCHIP 219 bool 220 depends on ARCH_CLPS711X 221 select IRQ_DOMAIN 222 select SPARSE_IRQ 223 default y 224 225config OMPIC 226 bool 227 228config OR1K_PIC 229 bool 230 select IRQ_DOMAIN 231 232config OMAP_IRQCHIP 233 bool 234 select GENERIC_IRQ_CHIP 235 select IRQ_DOMAIN 236 237config ORION_IRQCHIP 238 bool 239 select IRQ_DOMAIN 240 241config PIC32_EVIC 242 bool 243 select GENERIC_IRQ_CHIP 244 select IRQ_DOMAIN 245 246config JCORE_AIC 247 bool "J-Core integrated AIC" if COMPILE_TEST 248 depends on OF 249 select IRQ_DOMAIN 250 help 251 Support for the J-Core integrated AIC. 252 253config RDA_INTC 254 bool 255 select IRQ_DOMAIN 256 257config RENESAS_INTC_IRQPIN 258 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 259 select IRQ_DOMAIN 260 help 261 Enable support for the Renesas Interrupt Controller for external 262 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 263 264config RENESAS_IRQC 265 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 266 select GENERIC_IRQ_CHIP 267 select IRQ_DOMAIN 268 help 269 Enable support for the Renesas Interrupt Controller for external 270 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 271 272config RENESAS_RZA1_IRQC 273 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 274 select IRQ_DOMAIN_HIERARCHY 275 help 276 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 277 to 8 external interrupts with configurable sense select. 278 279config RENESAS_RZG2L_IRQC 280 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 281 select GENERIC_IRQ_CHIP 282 select IRQ_DOMAIN_HIERARCHY 283 help 284 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 285 for external devices. 286 287config RENESAS_RZV2H_ICU 288 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 289 select GENERIC_IRQ_CHIP 290 select IRQ_DOMAIN_HIERARCHY 291 help 292 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 293 294config SL28CPLD_INTC 295 bool "Kontron sl28cpld IRQ controller" 296 depends on MFD_SL28CPLD=y || COMPILE_TEST 297 select REGMAP_IRQ 298 help 299 Interrupt controller driver for the board management controller 300 found on the Kontron sl28 CPLD. 301 302config ST_IRQCHIP 303 bool 304 select REGMAP 305 select MFD_SYSCON 306 help 307 Enables SysCfg Controlled IRQs on STi based platforms. 308 309config SUN4I_INTC 310 bool 311 312config SUN6I_R_INTC 313 bool 314 select IRQ_DOMAIN_HIERARCHY 315 select IRQ_FASTEOI_HIERARCHY_HANDLERS 316 317config SUNXI_NMI_INTC 318 bool 319 select GENERIC_IRQ_CHIP 320 321config TB10X_IRQC 322 bool 323 select IRQ_DOMAIN 324 select GENERIC_IRQ_CHIP 325 326config TS4800_IRQ 327 tristate "TS-4800 IRQ controller" 328 select IRQ_DOMAIN 329 depends on HAS_IOMEM 330 depends on SOC_IMX51 || COMPILE_TEST 331 help 332 Support for the TS-4800 FPGA IRQ controller 333 334config VERSATILE_FPGA_IRQ 335 bool 336 select IRQ_DOMAIN 337 338config VERSATILE_FPGA_IRQ_NR 339 int 340 default 4 341 depends on VERSATILE_FPGA_IRQ 342 343config XTENSA_MX 344 bool 345 select IRQ_DOMAIN 346 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 347 348config XILINX_INTC 349 bool "Xilinx Interrupt Controller IP" 350 depends on OF_ADDRESS 351 select IRQ_DOMAIN 352 help 353 Support for the Xilinx Interrupt Controller IP core. 354 This is used as a primary controller with MicroBlaze and can also 355 be used as a secondary chained controller on other platforms. 356 357config IRQ_CROSSBAR 358 bool 359 help 360 Support for a CROSSBAR ip that precedes the main interrupt controller. 361 The primary irqchip invokes the crossbar's callback which inturn allocates 362 a free irq and configures the IP. Thus the peripheral interrupts are 363 routed to one of the free irqchip interrupt lines. 364 365config KEYSTONE_IRQ 366 tristate "Keystone 2 IRQ controller IP" 367 depends on ARCH_KEYSTONE 368 help 369 Support for Texas Instruments Keystone 2 IRQ controller IP which 370 is part of the Keystone 2 IPC mechanism 371 372config MIPS_GIC 373 bool 374 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 375 select GENERIC_IRQ_IPI if SMP 376 select IRQ_DOMAIN_HIERARCHY 377 select MIPS_CM 378 379config INGENIC_IRQ 380 bool 381 depends on MACH_INGENIC 382 default y 383 384config INGENIC_TCU_IRQ 385 bool "Ingenic JZ47xx TCU interrupt controller" 386 default MACH_INGENIC 387 depends on MIPS || COMPILE_TEST 388 select MFD_SYSCON 389 select GENERIC_IRQ_CHIP 390 help 391 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 392 JZ47xx SoCs. 393 394 If unsure, say N. 395 396config IMX_GPCV2 397 bool 398 select IRQ_DOMAIN 399 help 400 Enables the wakeup IRQs for IMX platforms with GPCv2 block 401 402config IRQ_MXS 403 def_bool y if MACH_ASM9260 || ARCH_MXS 404 select IRQ_DOMAIN 405 select STMP_DEVICE 406 407config MSCC_OCELOT_IRQ 408 bool 409 select IRQ_DOMAIN 410 select GENERIC_IRQ_CHIP 411 412config MVEBU_GICP 413 select IRQ_MSI_LIB 414 bool 415 416config MVEBU_ICU 417 bool 418 419config MVEBU_ODMI 420 bool 421 select IRQ_MSI_LIB 422 select GENERIC_MSI_IRQ 423 424config MVEBU_PIC 425 bool 426 427config MVEBU_SEI 428 bool 429 430config LS_EXTIRQ 431 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 432 select MFD_SYSCON 433 434config LS_SCFG_MSI 435 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 436 select IRQ_MSI_IOMMU 437 depends on PCI_MSI 438 439config PARTITION_PERCPU 440 bool 441 442config STM32MP_EXTI 443 tristate "STM32MP extended interrupts and event controller" 444 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 445 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 446 select IRQ_DOMAIN_HIERARCHY 447 select GENERIC_IRQ_CHIP 448 help 449 Support STM32MP EXTI (extended interrupts and event) controller. 450 451config STM32_EXTI 452 bool 453 select IRQ_DOMAIN 454 select GENERIC_IRQ_CHIP 455 456config QCOM_IRQ_COMBINER 457 bool "QCOM IRQ combiner support" 458 depends on ARCH_QCOM && ACPI 459 select IRQ_DOMAIN_HIERARCHY 460 help 461 Say yes here to add support for the IRQ combiner devices embedded 462 in Qualcomm Technologies chips. 463 464config IRQ_UNIPHIER_AIDET 465 bool "UniPhier AIDET support" if COMPILE_TEST 466 depends on ARCH_UNIPHIER || COMPILE_TEST 467 default ARCH_UNIPHIER 468 select IRQ_DOMAIN_HIERARCHY 469 help 470 Support for the UniPhier AIDET (ARM Interrupt Detector). 471 472config MESON_IRQ_GPIO 473 tristate "Meson GPIO Interrupt Multiplexer" 474 depends on ARCH_MESON || COMPILE_TEST 475 default ARCH_MESON 476 select IRQ_DOMAIN_HIERARCHY 477 help 478 Support Meson SoC Family GPIO Interrupt Multiplexer 479 480config GOLDFISH_PIC 481 bool "Goldfish programmable interrupt controller" 482 depends on MIPS && (GOLDFISH || COMPILE_TEST) 483 select GENERIC_IRQ_CHIP 484 select IRQ_DOMAIN 485 help 486 Say yes here to enable Goldfish interrupt controller driver used 487 for Goldfish based virtual platforms. 488 489config QCOM_PDC 490 tristate "QCOM PDC" 491 depends on ARCH_QCOM 492 select IRQ_DOMAIN_HIERARCHY 493 help 494 Power Domain Controller driver to manage and configure wakeup 495 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 496 497config QCOM_MPM 498 tristate "QCOM MPM" 499 depends on ARCH_QCOM 500 depends on MAILBOX 501 select IRQ_DOMAIN_HIERARCHY 502 help 503 MSM Power Manager driver to manage and configure wakeup 504 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 505 506config CSKY_MPINTC 507 bool 508 depends on CSKY 509 help 510 Say yes here to enable C-SKY SMP interrupt controller driver used 511 for C-SKY SMP system. 512 In fact it's not mmio map in hardware and it uses ld/st to visit the 513 controller's register inside CPU. 514 515config CSKY_APB_INTC 516 bool "C-SKY APB Interrupt Controller" 517 depends on CSKY 518 help 519 Say yes here to enable C-SKY APB interrupt controller driver used 520 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 521 the controller's register. 522 523config IMX_IRQSTEER 524 bool "i.MX IRQSTEER support" 525 depends on ARCH_MXC || COMPILE_TEST 526 default ARCH_MXC 527 select IRQ_DOMAIN 528 help 529 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 530 531config IMX_INTMUX 532 bool "i.MX INTMUX support" if COMPILE_TEST 533 default y if ARCH_MXC 534 select IRQ_DOMAIN 535 help 536 Support for the i.MX INTMUX interrupt multiplexer. 537 538config IMX_MU_MSI 539 tristate "i.MX MU used as MSI controller" 540 depends on OF && HAS_IOMEM 541 depends on ARCH_MXC || COMPILE_TEST 542 default m if ARCH_MXC 543 select IRQ_DOMAIN 544 select IRQ_DOMAIN_HIERARCHY 545 select GENERIC_MSI_IRQ 546 select IRQ_MSI_LIB 547 help 548 Provide a driver for the i.MX Messaging Unit block used as a 549 CPU-to-CPU MSI controller. This requires a specially crafted DT 550 to make use of this driver. 551 552 If unsure, say N 553 554config LS1X_IRQ 555 bool "Loongson-1 Interrupt Controller" 556 depends on MACH_LOONGSON32 557 default y 558 select IRQ_DOMAIN 559 select GENERIC_IRQ_CHIP 560 help 561 Support for the Loongson-1 platform Interrupt Controller. 562 563config TI_SCI_INTR_IRQCHIP 564 tristate "TI SCI INTR Interrupt Controller" 565 depends on TI_SCI_PROTOCOL 566 depends on ARCH_K3 || COMPILE_TEST 567 select IRQ_DOMAIN_HIERARCHY 568 help 569 This enables the irqchip driver support for K3 Interrupt router 570 over TI System Control Interface available on some new TI's SoCs. 571 If you wish to use interrupt router irq resources managed by the 572 TI System Controller, say Y here. Otherwise, say N. 573 574config TI_SCI_INTA_IRQCHIP 575 tristate "TI SCI INTA Interrupt Controller" 576 depends on TI_SCI_PROTOCOL 577 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 578 select IRQ_DOMAIN_HIERARCHY 579 select TI_SCI_INTA_MSI_DOMAIN 580 help 581 This enables the irqchip driver support for K3 Interrupt aggregator 582 over TI System Control Interface available on some new TI's SoCs. 583 If you wish to use interrupt aggregator irq resources managed by the 584 TI System Controller, say Y here. Otherwise, say N. 585 586config TI_PRUSS_INTC 587 tristate 588 depends on TI_PRUSS 589 default TI_PRUSS 590 select IRQ_DOMAIN 591 help 592 This enables support for the PRU-ICSS Local Interrupt Controller 593 present within a PRU-ICSS subsystem present on various TI SoCs. 594 The PRUSS INTC enables various interrupts to be routed to multiple 595 different processors within the SoC. 596 597config RISCV_INTC 598 bool 599 depends on RISCV 600 select IRQ_DOMAIN_HIERARCHY 601 602config RISCV_APLIC 603 bool 604 depends on RISCV 605 select IRQ_DOMAIN_HIERARCHY 606 607config RISCV_APLIC_MSI 608 bool 609 depends on RISCV_APLIC 610 select GENERIC_MSI_IRQ 611 default RISCV_APLIC 612 613config RISCV_IMSIC 614 bool 615 depends on RISCV 616 select IRQ_DOMAIN_HIERARCHY 617 select GENERIC_IRQ_MATRIX_ALLOCATOR 618 select GENERIC_MSI_IRQ 619 select IRQ_MSI_LIB 620 621config SIFIVE_PLIC 622 bool 623 depends on RISCV 624 select IRQ_DOMAIN_HIERARCHY 625 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 626 627config STARFIVE_JH8100_INTC 628 bool "StarFive JH8100 External Interrupt Controller" 629 depends on ARCH_STARFIVE || COMPILE_TEST 630 default ARCH_STARFIVE 631 select IRQ_DOMAIN_HIERARCHY 632 help 633 This enables support for the INTC chip found in StarFive JH8100 634 SoC. 635 636 If you don't know what to do here, say Y. 637 638config THEAD_C900_ACLINT_SSWI 639 bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 640 depends on RISCV 641 depends on SMP 642 select IRQ_DOMAIN_HIERARCHY 643 select GENERIC_IRQ_IPI_MUX 644 help 645 This enables support for T-HEAD specific ACLINT SSWI device 646 support. 647 648 If you don't know what to do here, say Y. 649 650config EXYNOS_IRQ_COMBINER 651 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 652 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 653 help 654 Say yes here to add support for the IRQ combiner devices embedded 655 in Samsung Exynos chips. 656 657config IRQ_LOONGARCH_CPU 658 bool 659 select GENERIC_IRQ_CHIP 660 select IRQ_DOMAIN 661 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 662 select LOONGSON_HTVEC 663 select LOONGSON_LIOINTC 664 select LOONGSON_EIOINTC 665 select LOONGSON_PCH_PIC 666 select LOONGSON_PCH_MSI 667 select LOONGSON_PCH_LPC 668 help 669 Support for the LoongArch CPU Interrupt Controller. For details of 670 irq chip hierarchy on LoongArch platforms please read the document 671 Documentation/arch/loongarch/irq-chip-model.rst. 672 673config LOONGSON_LIOINTC 674 bool "Loongson Local I/O Interrupt Controller" 675 depends on MACH_LOONGSON64 676 default y 677 select IRQ_DOMAIN 678 select GENERIC_IRQ_CHIP 679 help 680 Support for the Loongson Local I/O Interrupt Controller. 681 682config LOONGSON_EIOINTC 683 bool "Loongson Extend I/O Interrupt Controller" 684 depends on LOONGARCH 685 depends on MACH_LOONGSON64 686 default MACH_LOONGSON64 687 select IRQ_DOMAIN_HIERARCHY 688 select GENERIC_IRQ_CHIP 689 help 690 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 691 692config LOONGSON_HTPIC 693 bool "Loongson3 HyperTransport PIC Controller" 694 depends on MACH_LOONGSON64 && MIPS 695 default y 696 select IRQ_DOMAIN 697 select GENERIC_IRQ_CHIP 698 help 699 Support for the Loongson-3 HyperTransport PIC Controller. 700 701config LOONGSON_HTVEC 702 bool "Loongson HyperTransport Interrupt Vector Controller" 703 depends on MACH_LOONGSON64 704 default MACH_LOONGSON64 705 select IRQ_DOMAIN_HIERARCHY 706 help 707 Support for the Loongson HyperTransport Interrupt Vector Controller. 708 709config LOONGSON_PCH_PIC 710 bool "Loongson PCH PIC Controller" 711 depends on MACH_LOONGSON64 712 default MACH_LOONGSON64 713 select IRQ_DOMAIN_HIERARCHY 714 select IRQ_FASTEOI_HIERARCHY_HANDLERS 715 help 716 Support for the Loongson PCH PIC Controller. 717 718config LOONGSON_PCH_MSI 719 bool "Loongson PCH MSI Controller" 720 depends on MACH_LOONGSON64 721 depends on PCI 722 default MACH_LOONGSON64 723 select IRQ_DOMAIN_HIERARCHY 724 select IRQ_MSI_LIB 725 select PCI_MSI 726 help 727 Support for the Loongson PCH MSI Controller. 728 729config LOONGSON_PCH_LPC 730 bool "Loongson PCH LPC Controller" 731 depends on LOONGARCH 732 depends on MACH_LOONGSON64 733 default MACH_LOONGSON64 734 select IRQ_DOMAIN_HIERARCHY 735 help 736 Support for the Loongson PCH LPC Controller. 737 738config MST_IRQ 739 bool "MStar Interrupt Controller" 740 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 741 default ARCH_MEDIATEK 742 select IRQ_DOMAIN 743 select IRQ_DOMAIN_HIERARCHY 744 help 745 Support MStar Interrupt Controller. 746 747config WPCM450_AIC 748 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 749 depends on ARCH_WPCM450 750 help 751 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 752 753config IRQ_IDT3243X 754 bool 755 select GENERIC_IRQ_CHIP 756 select IRQ_DOMAIN 757 758config APPLE_AIC 759 bool "Apple Interrupt Controller (AIC)" 760 depends on ARM64 761 depends on ARCH_APPLE || COMPILE_TEST 762 select GENERIC_IRQ_IPI_MUX 763 help 764 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 765 such as the M1. 766 767config MCHP_EIC 768 bool "Microchip External Interrupt Controller" 769 depends on ARCH_AT91 || COMPILE_TEST 770 select IRQ_DOMAIN 771 select IRQ_DOMAIN_HIERARCHY 772 help 773 Support for Microchip External Interrupt Controller. 774 775config SOPHGO_SG2042_MSI 776 bool "Sophgo SG2042 MSI Controller" 777 depends on ARCH_SOPHGO || COMPILE_TEST 778 depends on PCI 779 select IRQ_DOMAIN_HIERARCHY 780 select IRQ_MSI_LIB 781 select PCI_MSI 782 help 783 Support for the Sophgo SG2042 MSI Controller. 784 This on-chip interrupt controller enables MSI sources to be 785 routed to the primary PLIC controller on SoC. 786 787config SUNPLUS_SP7021_INTC 788 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 789 default SOC_SP7021 790 help 791 Support for the Sunplus SP7021 Interrupt Controller IP core. 792 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 793 chained controller, routing all interrupt source in P-Chip to 794 the primary controller on C-Chip. 795 796endmenu 797