1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CPU_CACHE_ALIASING 10 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 11 select ARCH_HAS_CURRENT_STACK_POINTER 12 select ARCH_HAS_DEBUG_VIRTUAL if MMU 13 select ARCH_HAS_DMA_ALLOC if MMU 14 select ARCH_HAS_DMA_OPS 15 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 16 select ARCH_HAS_ELF_RANDOMIZE 17 select ARCH_HAS_FORTIFY_SOURCE 18 select ARCH_HAS_KEEPINITRD 19 select ARCH_HAS_KCOV 20 select ARCH_HAS_MEMBARRIER_SYNC_CORE 21 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 22 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 23 select ARCH_HAS_SETUP_DMA_OPS 24 select ARCH_HAS_SET_MEMORY 25 select ARCH_STACKWALK 26 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 27 select ARCH_HAS_STRICT_MODULE_RWX if MMU 28 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 29 select ARCH_HAS_SYNC_DMA_FOR_CPU 30 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 31 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 32 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 33 select ARCH_HAS_GCOV_PROFILE_ALL 34 select ARCH_KEEP_MEMBLOCK 35 select ARCH_HAS_UBSAN 36 select ARCH_MIGHT_HAVE_PC_PARPORT 37 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 38 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 39 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 40 select ARCH_SUPPORTS_ATOMIC_RMW 41 select ARCH_SUPPORTS_CFI 42 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 43 select ARCH_SUPPORTS_PER_VMA_LOCK 44 select ARCH_USE_BUILTIN_BSWAP 45 select ARCH_USE_CMPXCHG_LOCKREF 46 select ARCH_USE_MEMTEST 47 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de 48 select ARCH_USES_CFI_GENERIC_LLVM_PASS if CLANG_VERSION < 220000 49 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 50 select ARCH_WANT_GENERAL_HUGETLB 51 select ARCH_WANT_IPC_PARSE_VERSION 52 select ARCH_WANT_LD_ORPHAN_WARN 53 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 54 select BUILDTIME_TABLE_SORT if MMU 55 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 56 select CLONE_BACKWARDS 57 select CPU_PM if SUSPEND || CPU_IDLE 58 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 59 select DMA_DECLARE_COHERENT 60 select DMA_GLOBAL_POOL if !MMU 61 select DMA_NONCOHERENT_MMAP if MMU 62 select EDAC_SUPPORT 63 select EDAC_ATOMIC_SCRUB 64 select GENERIC_ALLOCATOR 65 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 66 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 67 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 68 select GENERIC_IRQ_IPI if SMP 69 select GENERIC_CPU_AUTOPROBE 70 select GENERIC_CPU_DEVICES 71 select GENERIC_EARLY_IOREMAP 72 select GENERIC_IDLE_POLL_SETUP 73 select GENERIC_IRQ_MULTI_HANDLER 74 select GENERIC_IRQ_PROBE 75 select GENERIC_IRQ_SHOW 76 select GENERIC_IRQ_SHOW_LEVEL 77 select GENERIC_LIB_DEVMEM_IS_ALLOWED 78 select GENERIC_PCI_IOMAP 79 select GENERIC_SCHED_CLOCK 80 select GENERIC_SMP_IDLE_THREAD 81 select HARDIRQS_SW_RESEND 82 select HAS_IOPORT 83 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 84 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 85 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 86 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 87 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 88 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 89 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 90 select HAVE_ARCH_KSTACK_ERASE 91 select HAVE_ARCH_MMAP_RND_BITS if MMU 92 select HAVE_ARCH_PFN_VALID 93 select HAVE_ARCH_SECCOMP 94 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 95 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 96 select HAVE_ARCH_TRACEHOOK 97 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 98 select HAVE_ARM_SMCCC if CPU_V7 99 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 100 select HAVE_CONTEXT_TRACKING_USER 101 select HAVE_C_RECORDMCOUNT 102 select HAVE_BUILDTIME_MCOUNT_SORT 103 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 104 select HAVE_DMA_CONTIGUOUS if MMU 105 select HAVE_EXTRA_IPI_TRACEPOINTS 106 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 107 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 108 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 109 select HAVE_EXIT_THREAD 110 select HAVE_GUP_FAST if ARM_LPAE 111 select HAVE_FUNCTION_ERROR_INJECTION 112 select HAVE_FUNCTION_GRAPH_TRACER 113 select HAVE_FUNCTION_GRAPH_FREGS 114 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 115 select HAVE_GCC_PLUGINS 116 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 117 select HAVE_IRQ_TIME_ACCOUNTING 118 select HAVE_KERNEL_GZIP 119 select HAVE_KERNEL_LZ4 120 select HAVE_KERNEL_LZMA 121 select HAVE_KERNEL_LZO 122 select HAVE_KERNEL_XZ 123 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 124 select HAVE_KRETPROBES if HAVE_KPROBES 125 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY 126 select HAVE_MOD_ARCH_SPECIFIC 127 select HAVE_NMI 128 select HAVE_OPTPROBES if !THUMB2_KERNEL 129 select HAVE_PAGE_SIZE_4KB 130 select HAVE_PCI if MMU 131 select HAVE_PERF_EVENTS 132 select HAVE_PERF_REGS 133 select HAVE_PERF_USER_STACK_DUMP 134 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 135 select HAVE_REGS_AND_STACK_ACCESS_API 136 select HAVE_RSEQ 137 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 138 select HAVE_STACKPROTECTOR 139 select HAVE_SYSCALL_TRACEPOINTS 140 select HAVE_UID16 141 select HAVE_VIRT_CPU_ACCOUNTING_GEN 142 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 143 select IRQ_FORCED_THREADING 144 select LOCK_MM_AND_FIND_VMA 145 select MODULES_USE_ELF_REL 146 select NEED_DMA_MAP_STATE 147 select OF_EARLY_FLATTREE if OF 148 select OLD_SIGACTION 149 select OLD_SIGSUSPEND3 150 select PCI_DOMAINS_GENERIC if PCI 151 select PCI_SYSCALL if PCI 152 select PERF_USE_VMALLOC 153 select RTC_LIB 154 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 155 select SYS_SUPPORTS_APM_EMULATION 156 select THREAD_INFO_IN_TASK 157 select TIMER_OF if OF 158 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 159 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 160 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 161 # Above selects are sorted alphabetically; please add new ones 162 # according to that. Thanks. 163 help 164 The ARM series is a line of low-power-consumption RISC chip designs 165 licensed by ARM Ltd and targeted at embedded applications and 166 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 167 manufactured, but legacy ARM-based PC hardware remains popular in 168 Europe. There is an ARM Linux project with a web page at 169 <http://www.arm.linux.org.uk/>. 170 171config ARM_HAS_GROUP_RELOCS 172 def_bool !COMPILE_TEST 173 help 174 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 175 relocations. The combined range is -/+ 256 MiB, which is usually 176 sufficient, but not for allyesconfig, so we disable this feature 177 when doing compile testing. 178 179config ARM_DMA_USE_IOMMU 180 bool 181 select NEED_SG_DMA_LENGTH 182 183if ARM_DMA_USE_IOMMU 184 185config ARM_DMA_IOMMU_ALIGNMENT 186 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 187 range 4 9 188 default 8 189 help 190 DMA mapping framework by default aligns all buffers to the smallest 191 PAGE_SIZE order which is greater than or equal to the requested buffer 192 size. This works well for buffers up to a few hundreds kilobytes, but 193 for larger buffers it just a waste of address space. Drivers which has 194 relatively small addressing window (like 64Mib) might run out of 195 virtual space with just a few allocations. 196 197 With this parameter you can specify the maximum PAGE_SIZE order for 198 DMA IOMMU buffers. Larger buffers will be aligned only to this 199 specified order. The order is expressed as a power of two multiplied 200 by the PAGE_SIZE. 201 202endif 203 204config SYS_SUPPORTS_APM_EMULATION 205 bool 206 207config HAVE_TCM 208 bool 209 select GENERIC_ALLOCATOR 210 211config HAVE_PROC_CPU 212 bool 213 214config NO_IOPORT_MAP 215 bool 216 217config SBUS 218 bool 219 220config STACKTRACE_SUPPORT 221 bool 222 default y 223 224config LOCKDEP_SUPPORT 225 bool 226 default y 227 228config ARCH_HAS_ILOG2_U32 229 bool 230 231config ARCH_HAS_ILOG2_U64 232 bool 233 234config ARCH_HAS_BANDGAP 235 bool 236 237config FIX_EARLYCON_MEM 238 def_bool y if MMU 239 240config GENERIC_HWEIGHT 241 bool 242 default y 243 244config GENERIC_CALIBRATE_DELAY 245 bool 246 default y 247 248config ARCH_MAY_HAVE_PC_FDC 249 bool 250 251config ARCH_SUPPORTS_UPROBES 252 def_bool y 253 254config GENERIC_ISA_DMA 255 bool 256 257config FIQ 258 bool 259 260config ARCH_MTD_XIP 261 bool 262 263config ARM_PATCH_PHYS_VIRT 264 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 265 default y 266 depends on MMU 267 help 268 Patch phys-to-virt and virt-to-phys translation functions at 269 boot and module load time according to the position of the 270 kernel in system memory. 271 272 This can only be used with non-XIP MMU kernels where the base 273 of physical memory is at a 2 MiB boundary. 274 275 Only disable this option if you know that you do not require 276 this feature (eg, building a kernel for a single machine) and 277 you need to shrink the kernel to the minimal size. 278 279config NEED_MACH_IO_H 280 bool 281 help 282 Select this when mach/io.h is required to provide special 283 definitions for this platform. The need for mach/io.h should 284 be avoided when possible. 285 286config NEED_MACH_MEMORY_H 287 bool 288 help 289 Select this when mach/memory.h is required to provide special 290 definitions for this platform. The need for mach/memory.h should 291 be avoided when possible. 292 293config PHYS_OFFSET 294 hex "Physical address of main memory" if MMU 295 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 296 default DRAM_BASE if !MMU 297 default 0x00000000 if ARCH_FOOTBRIDGE 298 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 299 default 0xa0000000 if ARCH_PXA 300 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 301 default 0 302 help 303 Please provide the physical address corresponding to the 304 location of main memory in your system. 305 306config GENERIC_BUG 307 def_bool y 308 depends on BUG 309 310config PGTABLE_LEVELS 311 int 312 default 3 if ARM_LPAE 313 default 2 314 315menu "System Type" 316 317config MMU 318 bool "MMU-based Paged Memory Management Support" 319 default y 320 help 321 Select if you want MMU-based virtualised addressing space 322 support by paged memory management. If unsure, say 'Y'. 323 324config ARM_SINGLE_ARMV7M 325 def_bool !MMU 326 select ARM_NVIC 327 select CPU_V7M 328 select NO_IOPORT_MAP 329 330config ARCH_MMAP_RND_BITS_MIN 331 default 8 332 333config ARCH_MMAP_RND_BITS_MAX 334 default 14 if PAGE_OFFSET=0x40000000 335 default 15 if PAGE_OFFSET=0x80000000 336 default 16 337 338config ARCH_MULTIPLATFORM 339 bool "Require kernel to be portable to multiple machines" if EXPERT 340 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 341 default y 342 help 343 In general, all Arm machines can be supported in a single 344 kernel image, covering either Armv4/v5 or Armv6/v7. 345 346 However, some configuration options require hardcoding machine 347 specific physical addresses or enable errata workarounds that may 348 break other machines. 349 350 Selecting N here allows using those options, including 351 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 352 353source "arch/arm/Kconfig.platforms" 354 355# 356# This is sorted alphabetically by mach-* pathname. However, plat-* 357# Kconfigs may be included either alphabetically (according to the 358# plat- suffix) or along side the corresponding mach-* source. 359# 360source "arch/arm/mach-actions/Kconfig" 361 362source "arch/arm/mach-alpine/Kconfig" 363 364source "arch/arm/mach-artpec/Kconfig" 365 366source "arch/arm/mach-aspeed/Kconfig" 367 368source "arch/arm/mach-at91/Kconfig" 369 370source "arch/arm/mach-axxia/Kconfig" 371 372source "arch/arm/mach-bcm/Kconfig" 373 374source "arch/arm/mach-berlin/Kconfig" 375 376source "arch/arm/mach-clps711x/Kconfig" 377 378source "arch/arm/mach-davinci/Kconfig" 379 380source "arch/arm/mach-digicolor/Kconfig" 381 382source "arch/arm/mach-dove/Kconfig" 383 384source "arch/arm/mach-ep93xx/Kconfig" 385 386source "arch/arm/mach-exynos/Kconfig" 387 388source "arch/arm/mach-footbridge/Kconfig" 389 390source "arch/arm/mach-gemini/Kconfig" 391 392source "arch/arm/mach-highbank/Kconfig" 393 394source "arch/arm/mach-hisi/Kconfig" 395 396source "arch/arm/mach-imx/Kconfig" 397 398source "arch/arm/mach-ixp4xx/Kconfig" 399 400source "arch/arm/mach-keystone/Kconfig" 401 402source "arch/arm/mach-lpc32xx/Kconfig" 403 404source "arch/arm/mach-mediatek/Kconfig" 405 406source "arch/arm/mach-meson/Kconfig" 407 408source "arch/arm/mach-milbeaut/Kconfig" 409 410source "arch/arm/mach-mmp/Kconfig" 411 412source "arch/arm/mach-mstar/Kconfig" 413 414source "arch/arm/mach-mv78xx0/Kconfig" 415 416source "arch/arm/mach-mvebu/Kconfig" 417 418source "arch/arm/mach-mxs/Kconfig" 419 420source "arch/arm/mach-nomadik/Kconfig" 421 422source "arch/arm/mach-npcm/Kconfig" 423 424source "arch/arm/mach-omap1/Kconfig" 425 426source "arch/arm/mach-omap2/Kconfig" 427 428source "arch/arm/mach-orion5x/Kconfig" 429 430source "arch/arm/mach-pxa/Kconfig" 431 432source "arch/arm/mach-qcom/Kconfig" 433 434source "arch/arm/mach-realtek/Kconfig" 435 436source "arch/arm/mach-rpc/Kconfig" 437 438source "arch/arm/mach-rockchip/Kconfig" 439 440source "arch/arm/mach-s3c/Kconfig" 441 442source "arch/arm/mach-s5pv210/Kconfig" 443 444source "arch/arm/mach-sa1100/Kconfig" 445 446source "arch/arm/mach-shmobile/Kconfig" 447 448source "arch/arm/mach-socfpga/Kconfig" 449 450source "arch/arm/mach-spear/Kconfig" 451 452source "arch/arm/mach-sti/Kconfig" 453 454source "arch/arm/mach-stm32/Kconfig" 455 456source "arch/arm/mach-sunxi/Kconfig" 457 458source "arch/arm/mach-tegra/Kconfig" 459 460source "arch/arm/mach-ux500/Kconfig" 461 462source "arch/arm/mach-versatile/Kconfig" 463 464source "arch/arm/mach-vt8500/Kconfig" 465 466source "arch/arm/mach-zynq/Kconfig" 467 468# ARMv7-M architecture 469config ARCH_LPC18XX 470 bool "NXP LPC18xx/LPC43xx" 471 depends on ARM_SINGLE_ARMV7M 472 select ARCH_HAS_RESET_CONTROLLER 473 select ARM_AMBA 474 select CLKSRC_LPC32XX 475 select PINCTRL 476 help 477 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 478 high performance microcontrollers. 479 480config ARCH_MPS2 481 bool "ARM MPS2 platform" 482 depends on ARM_SINGLE_ARMV7M 483 select ARM_AMBA 484 select CLKSRC_MPS2 485 help 486 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 487 with a range of available cores like Cortex-M3/M4/M7. 488 489 Please, note that depends which Application Note is used memory map 490 for the platform may vary, so adjustment of RAM base might be needed. 491 492# Definitions to make life easier 493config ARCH_ACORN 494 bool 495 496config PLAT_ORION 497 bool 498 select CLKSRC_MMIO 499 select GENERIC_IRQ_CHIP 500 select IRQ_DOMAIN 501 502config PLAT_ORION_LEGACY 503 bool 504 select PLAT_ORION 505 506config PLAT_VERSATILE 507 bool 508 509source "arch/arm/mm/Kconfig" 510 511config IWMMXT 512 bool "Enable iWMMXt support" 513 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 514 default y if PXA27x || PXA3xx || ARCH_MMP 515 help 516 Enable support for iWMMXt context switching at run time if 517 running on a CPU that supports it. 518 519if !MMU 520source "arch/arm/Kconfig-nommu" 521endif 522 523config PJ4B_ERRATA_4742 524 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 525 depends on CPU_PJ4B && MACH_ARMADA_370 526 default y 527 help 528 When coming out of either a Wait for Interrupt (WFI) or a Wait for 529 Event (WFE) IDLE states, a specific timing sensitivity exists between 530 the retiring WFI/WFE instructions and the newly issued subsequent 531 instructions. This sensitivity can result in a CPU hang scenario. 532 Workaround: 533 The software must insert either a Data Synchronization Barrier (DSB) 534 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 535 instruction 536 537config ARM_ERRATA_326103 538 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 539 depends on CPU_V6 540 help 541 Executing a SWP instruction to read-only memory does not set bit 11 542 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 543 treat the access as a read, preventing a COW from occurring and 544 causing the faulting task to livelock. 545 546config ARM_ERRATA_411920 547 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 548 depends on CPU_V6 || CPU_V6K 549 help 550 Invalidation of the Instruction Cache operation can 551 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 552 It does not affect the MPCore. This option enables the ARM Ltd. 553 recommended workaround. 554 555config ARM_ERRATA_430973 556 bool "ARM errata: Stale prediction on replaced interworking branch" 557 depends on CPU_V7 558 help 559 This option enables the workaround for the 430973 Cortex-A8 560 r1p* erratum. If a code sequence containing an ARM/Thumb 561 interworking branch is replaced with another code sequence at the 562 same virtual address, whether due to self-modifying code or virtual 563 to physical address re-mapping, Cortex-A8 does not recover from the 564 stale interworking branch prediction. This results in Cortex-A8 565 executing the new code sequence in the incorrect ARM or Thumb state. 566 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 567 and also flushes the branch target cache at every context switch. 568 Note that setting specific bits in the ACTLR register may not be 569 available in non-secure mode. 570 571config ARM_ERRATA_458693 572 bool "ARM errata: Processor deadlock when a false hazard is created" 573 depends on CPU_V7 574 depends on !ARCH_MULTIPLATFORM 575 help 576 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 577 erratum. For very specific sequences of memory operations, it is 578 possible for a hazard condition intended for a cache line to instead 579 be incorrectly associated with a different cache line. This false 580 hazard might then cause a processor deadlock. The workaround enables 581 the L1 caching of the NEON accesses and disables the PLD instruction 582 in the ACTLR register. Note that setting specific bits in the ACTLR 583 register may not be available in non-secure mode and thus is not 584 available on a multiplatform kernel. This should be applied by the 585 bootloader instead. 586 587config ARM_ERRATA_460075 588 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 589 depends on CPU_V7 590 depends on !ARCH_MULTIPLATFORM 591 help 592 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 593 erratum. Any asynchronous access to the L2 cache may encounter a 594 situation in which recent store transactions to the L2 cache are lost 595 and overwritten with stale memory contents from external memory. The 596 workaround disables the write-allocate mode for the L2 cache via the 597 ACTLR register. Note that setting specific bits in the ACTLR register 598 may not be available in non-secure mode and thus is not available on 599 a multiplatform kernel. This should be applied by the bootloader 600 instead. 601 602config ARM_ERRATA_742230 603 bool "ARM errata: DMB operation may be faulty" 604 depends on CPU_V7 && SMP 605 depends on !ARCH_MULTIPLATFORM 606 help 607 This option enables the workaround for the 742230 Cortex-A9 608 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 609 between two write operations may not ensure the correct visibility 610 ordering of the two writes. This workaround sets a specific bit in 611 the diagnostic register of the Cortex-A9 which causes the DMB 612 instruction to behave as a DSB, ensuring the correct behaviour of 613 the two writes. Note that setting specific bits in the diagnostics 614 register may not be available in non-secure mode and thus is not 615 available on a multiplatform kernel. This should be applied by the 616 bootloader instead. 617 618config ARM_ERRATA_742231 619 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 620 depends on CPU_V7 && SMP 621 depends on !ARCH_MULTIPLATFORM 622 help 623 This option enables the workaround for the 742231 Cortex-A9 624 (r2p0..r2p2) erratum. Under certain conditions, specific to the 625 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 626 accessing some data located in the same cache line, may get corrupted 627 data due to bad handling of the address hazard when the line gets 628 replaced from one of the CPUs at the same time as another CPU is 629 accessing it. This workaround sets specific bits in the diagnostic 630 register of the Cortex-A9 which reduces the linefill issuing 631 capabilities of the processor. Note that setting specific bits in the 632 diagnostics register may not be available in non-secure mode and thus 633 is not available on a multiplatform kernel. This should be applied by 634 the bootloader instead. 635 636config ARM_ERRATA_643719 637 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 638 depends on CPU_V7 && SMP 639 default y 640 help 641 This option enables the workaround for the 643719 Cortex-A9 (prior to 642 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 643 register returns zero when it should return one. The workaround 644 corrects this value, ensuring cache maintenance operations which use 645 it behave as intended and avoiding data corruption. 646 647config ARM_ERRATA_720789 648 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 649 depends on CPU_V7 650 help 651 This option enables the workaround for the 720789 Cortex-A9 (prior to 652 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 653 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 654 As a consequence of this erratum, some TLB entries which should be 655 invalidated are not, resulting in an incoherency in the system page 656 tables. The workaround changes the TLB flushing routines to invalidate 657 entries regardless of the ASID. 658 659config ARM_ERRATA_743622 660 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 661 depends on CPU_V7 662 depends on !ARCH_MULTIPLATFORM 663 help 664 This option enables the workaround for the 743622 Cortex-A9 665 (r2p*) erratum. Under very rare conditions, a faulty 666 optimisation in the Cortex-A9 Store Buffer may lead to data 667 corruption. This workaround sets a specific bit in the diagnostic 668 register of the Cortex-A9 which disables the Store Buffer 669 optimisation, preventing the defect from occurring. This has no 670 visible impact on the overall performance or power consumption of the 671 processor. Note that setting specific bits in the diagnostics register 672 may not be available in non-secure mode and thus is not available on a 673 multiplatform kernel. This should be applied by the bootloader instead. 674 675config ARM_ERRATA_751472 676 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 677 depends on CPU_V7 678 depends on !ARCH_MULTIPLATFORM 679 help 680 This option enables the workaround for the 751472 Cortex-A9 (prior 681 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 682 completion of a following broadcasted operation if the second 683 operation is received by a CPU before the ICIALLUIS has completed, 684 potentially leading to corrupted entries in the cache or TLB. 685 Note that setting specific bits in the diagnostics register may 686 not be available in non-secure mode and thus is not available on 687 a multiplatform kernel. This should be applied by the bootloader 688 instead. 689 690config ARM_ERRATA_754322 691 bool "ARM errata: possible faulty MMU translations following an ASID switch" 692 depends on CPU_V7 693 help 694 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 695 r3p*) erratum. A speculative memory access may cause a page table walk 696 which starts prior to an ASID switch but completes afterwards. This 697 can populate the micro-TLB with a stale entry which may be hit with 698 the new ASID. This workaround places two dsb instructions in the mm 699 switching code so that no page table walks can cross the ASID switch. 700 701config ARM_ERRATA_754327 702 bool "ARM errata: no automatic Store Buffer drain" 703 depends on CPU_V7 && SMP 704 help 705 This option enables the workaround for the 754327 Cortex-A9 (prior to 706 r2p0) erratum. The Store Buffer does not have any automatic draining 707 mechanism and therefore a livelock may occur if an external agent 708 continuously polls a memory location waiting to observe an update. 709 This workaround defines cpu_relax() as smp_mb(), preventing correctly 710 written polling loops from denying visibility of updates to memory. 711 712config ARM_ERRATA_364296 713 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 714 depends on CPU_V6 715 help 716 This options enables the workaround for the 364296 ARM1136 717 r0p2 erratum (possible cache data corruption with 718 hit-under-miss enabled). It sets the undocumented bit 31 in 719 the auxiliary control register and the FI bit in the control 720 register, thus disabling hit-under-miss without putting the 721 processor into full low interrupt latency mode. ARM11MPCore 722 is not affected. 723 724config ARM_ERRATA_764369 725 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 726 depends on CPU_V7 && SMP 727 help 728 This option enables the workaround for erratum 764369 729 affecting Cortex-A9 MPCore with two or more processors (all 730 current revisions). Under certain timing circumstances, a data 731 cache line maintenance operation by MVA targeting an Inner 732 Shareable memory region may fail to proceed up to either the 733 Point of Coherency or to the Point of Unification of the 734 system. This workaround adds a DSB instruction before the 735 relevant cache maintenance functions and sets a specific bit 736 in the diagnostic control register of the SCU. 737 738config ARM_ERRATA_764319 739 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 740 depends on CPU_V7 741 help 742 This option enables the workaround for the 764319 Cortex-A9 erratum. 743 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 744 unexpected Undefined Instruction exception when the DBGSWENABLE 745 external pin is set to 0, even when the CP14 accesses are performed 746 from a privileged mode. This work around catches the exception in a 747 way the kernel does not stop execution. 748 749config ARM_ERRATA_775420 750 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 751 depends on CPU_V7 752 help 753 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 754 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 755 operation aborts with MMU exception, it might cause the processor 756 to deadlock. This workaround puts DSB before executing ISB if 757 an abort may occur on cache maintenance. 758 759config ARM_ERRATA_798181 760 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 761 depends on CPU_V7 && SMP 762 help 763 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 764 adequately shooting down all use of the old entries. This 765 option enables the Linux kernel workaround for this erratum 766 which sends an IPI to the CPUs that are running the same ASID 767 as the one being invalidated. 768 769config ARM_ERRATA_773022 770 bool "ARM errata: incorrect instructions may be executed from loop buffer" 771 depends on CPU_V7 772 help 773 This option enables the workaround for the 773022 Cortex-A15 774 (up to r0p4) erratum. In certain rare sequences of code, the 775 loop buffer may deliver incorrect instructions. This 776 workaround disables the loop buffer to avoid the erratum. 777 778config ARM_ERRATA_818325_852422 779 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 780 depends on CPU_V7 781 help 782 This option enables the workaround for: 783 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 784 instruction might deadlock. Fixed in r0p1. 785 - Cortex-A12 852422: Execution of a sequence of instructions might 786 lead to either a data corruption or a CPU deadlock. Not fixed in 787 any Cortex-A12 cores yet. 788 This workaround for all both errata involves setting bit[12] of the 789 Feature Register. This bit disables an optimisation applied to a 790 sequence of 2 instructions that use opposing condition codes. 791 792config ARM_ERRATA_821420 793 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 794 depends on CPU_V7 795 help 796 This option enables the workaround for the 821420 Cortex-A12 797 (all revs) erratum. In very rare timing conditions, a sequence 798 of VMOV to Core registers instructions, for which the second 799 one is in the shadow of a branch or abort, can lead to a 800 deadlock when the VMOV instructions are issued out-of-order. 801 802config ARM_ERRATA_825619 803 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 804 depends on CPU_V7 805 help 806 This option enables the workaround for the 825619 Cortex-A12 807 (all revs) erratum. Within rare timing constraints, executing a 808 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 809 and Device/Strongly-Ordered loads and stores might cause deadlock 810 811config ARM_ERRATA_857271 812 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 813 depends on CPU_V7 814 help 815 This option enables the workaround for the 857271 Cortex-A12 816 (all revs) erratum. Under very rare timing conditions, the CPU might 817 hang. The workaround is expected to have a < 1% performance impact. 818 819config ARM_ERRATA_852421 820 bool "ARM errata: A17: DMB ST might fail to create order between stores" 821 depends on CPU_V7 822 help 823 This option enables the workaround for the 852421 Cortex-A17 824 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 825 execution of a DMB ST instruction might fail to properly order 826 stores from GroupA and stores from GroupB. 827 828config ARM_ERRATA_852423 829 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 830 depends on CPU_V7 831 help 832 This option enables the workaround for: 833 - Cortex-A17 852423: Execution of a sequence of instructions might 834 lead to either a data corruption or a CPU deadlock. Not fixed in 835 any Cortex-A17 cores yet. 836 This is identical to Cortex-A12 erratum 852422. It is a separate 837 config option from the A12 erratum due to the way errata are checked 838 for and handled. 839 840config ARM_ERRATA_857272 841 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 842 depends on CPU_V7 843 help 844 This option enables the workaround for the 857272 Cortex-A17 erratum. 845 This erratum is not known to be fixed in any A17 revision. 846 This is identical to Cortex-A12 erratum 857271. It is a separate 847 config option from the A12 erratum due to the way errata are checked 848 for and handled. 849 850endmenu 851 852source "arch/arm/common/Kconfig" 853 854menu "Bus support" 855 856config ISA 857 bool 858 help 859 Find out whether you have ISA slots on your motherboard. ISA is the 860 name of a bus system, i.e. the way the CPU talks to the other stuff 861 inside your box. Other bus systems are PCI, EISA, MicroChannel 862 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 863 newer boards don't support it. If you have ISA, say Y, otherwise N. 864 865# Select ISA DMA interface 866config ISA_DMA_API 867 bool 868 869config ARM_ERRATA_814220 870 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 871 depends on CPU_V7 872 help 873 The v7 ARM states that all cache and branch predictor maintenance 874 operations that do not specify an address execute, relative to 875 each other, in program order. 876 However, because of this erratum, an L2 set/way cache maintenance 877 operation can overtake an L1 set/way cache maintenance operation. 878 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 879 r0p4, r0p5. 880 881endmenu 882 883menu "Kernel Features" 884 885config HAVE_SMP 886 bool 887 help 888 This option should be selected by machines which have an SMP- 889 capable CPU. 890 891 The only effect of this option is to make the SMP-related 892 options available to the user for configuration. 893 894config SMP 895 bool "Symmetric Multi-Processing" 896 depends on CPU_V6K || CPU_V7 897 depends on HAVE_SMP 898 depends on MMU || ARM_MPU 899 select IRQ_WORK 900 help 901 This enables support for systems with more than one CPU. If you have 902 a system with only one CPU, say N. If you have a system with more 903 than one CPU, say Y. 904 905 If you say N here, the kernel will run on uni- and multiprocessor 906 machines, but will use only one CPU of a multiprocessor machine. If 907 you say Y here, the kernel will run on many, but not all, 908 uniprocessor machines. On a uniprocessor machine, the kernel 909 will run faster if you say N here. 910 911 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 912 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 913 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 914 915 If you don't know what to do here, say N. 916 917config SMP_ON_UP 918 bool "Allow booting SMP kernel on uniprocessor systems" 919 depends on SMP && MMU 920 default y 921 help 922 SMP kernels contain instructions which fail on non-SMP processors. 923 Enabling this option allows the kernel to modify itself to make 924 these instructions safe. Disabling it allows about 1K of space 925 savings. 926 927 If you don't know what to do here, say Y. 928 929 930config CURRENT_POINTER_IN_TPIDRURO 931 def_bool y 932 depends on CPU_32v6K && !CPU_V6 933 934config IRQSTACKS 935 def_bool y 936 select HAVE_IRQ_EXIT_ON_IRQ_STACK 937 select HAVE_SOFTIRQ_ON_OWN_STACK 938 939config ARM_CPU_TOPOLOGY 940 bool "Support cpu topology definition" 941 depends on SMP && CPU_V7 942 select ARCH_SUPPORTS_SCHED_MC 943 select ARCH_SUPPORTS_SCHED_SMT 944 default y 945 help 946 Support ARM cpu topology definition. The MPIDR register defines 947 affinity between processors which is then used to describe the cpu 948 topology of an ARM System. 949 950config HAVE_ARM_SCU 951 bool 952 help 953 This option enables support for the ARM snoop control unit 954 955config HAVE_ARM_ARCH_TIMER 956 bool "Architected timer support" 957 depends on CPU_V7 958 select ARM_ARCH_TIMER 959 help 960 This option enables support for the ARM architected timer 961 962config HAVE_ARM_TWD 963 bool 964 help 965 This options enables support for the ARM timer and watchdog unit 966 967config MCPM 968 bool "Multi-Cluster Power Management" 969 depends on CPU_V7 && SMP 970 help 971 This option provides the common power management infrastructure 972 for (multi-)cluster based systems, such as big.LITTLE based 973 systems. 974 975config MCPM_QUAD_CLUSTER 976 bool 977 depends on MCPM 978 help 979 To avoid wasting resources unnecessarily, MCPM only supports up 980 to 2 clusters by default. 981 Platforms with 3 or 4 clusters that use MCPM must select this 982 option to allow the additional clusters to be managed. 983 984config BIG_LITTLE 985 bool "big.LITTLE support (Experimental)" 986 depends on CPU_V7 && SMP 987 select MCPM 988 help 989 This option enables support selections for the big.LITTLE 990 system architecture. 991 992config BL_SWITCHER 993 bool "big.LITTLE switcher support" 994 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 995 select CPU_PM 996 help 997 The big.LITTLE "switcher" provides the core functionality to 998 transparently handle transition between a cluster of A15's 999 and a cluster of A7's in a big.LITTLE system. 1000 1001config BL_SWITCHER_DUMMY_IF 1002 tristate "Simple big.LITTLE switcher user interface" 1003 depends on BL_SWITCHER && DEBUG_KERNEL 1004 help 1005 This is a simple and dummy char dev interface to control 1006 the big.LITTLE switcher core code. It is meant for 1007 debugging purposes only. 1008 1009choice 1010 prompt "Memory split" 1011 depends on MMU 1012 default VMSPLIT_3G 1013 help 1014 Select the desired split between kernel and user memory. 1015 1016 If you are not absolutely sure what you are doing, leave this 1017 option alone! 1018 1019 config VMSPLIT_3G 1020 bool "3G/1G user/kernel split" 1021 config VMSPLIT_3G_OPT 1022 depends on !ARM_LPAE 1023 bool "3G/1G user/kernel split (for full 1G low memory)" 1024 config VMSPLIT_2G 1025 bool "2G/2G user/kernel split" 1026 config VMSPLIT_1G 1027 bool "1G/3G user/kernel split" 1028endchoice 1029 1030config PAGE_OFFSET 1031 hex 1032 default PHYS_OFFSET if !MMU 1033 default 0x40000000 if VMSPLIT_1G 1034 default 0x80000000 if VMSPLIT_2G 1035 default 0xB0000000 if VMSPLIT_3G_OPT 1036 default 0xC0000000 1037 1038config KASAN_SHADOW_OFFSET 1039 hex 1040 depends on KASAN 1041 default 0x1f000000 if PAGE_OFFSET=0x40000000 1042 default 0x5f000000 if PAGE_OFFSET=0x80000000 1043 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1044 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1045 default 0xffffffff 1046 1047config NR_CPUS 1048 int "Maximum number of CPUs (2-32)" 1049 range 2 16 if DEBUG_KMAP_LOCAL 1050 range 2 32 if !DEBUG_KMAP_LOCAL 1051 depends on SMP 1052 default "4" 1053 help 1054 The maximum number of CPUs that the kernel can support. 1055 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1056 debugging is enabled, which uses half of the per-CPU fixmap 1057 slots as guard regions. 1058 1059config HOTPLUG_CPU 1060 bool "Support for hot-pluggable CPUs" 1061 depends on SMP 1062 select GENERIC_IRQ_MIGRATION 1063 help 1064 Say Y here to experiment with turning CPUs off and on. CPUs 1065 can be controlled through /sys/devices/system/cpu. 1066 1067config ARM_PSCI 1068 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1069 depends on HAVE_ARM_SMCCC 1070 select ARM_PSCI_FW 1071 help 1072 Say Y here if you want Linux to communicate with system firmware 1073 implementing the PSCI specification for CPU-centric power 1074 management operations described in ARM document number ARM DEN 1075 0022A ("Power State Coordination Interface System Software on 1076 ARM processors"). 1077 1078config HZ_FIXED 1079 int 1080 default 128 if SOC_AT91RM9200 1081 default 0 1082 1083choice 1084 depends on HZ_FIXED = 0 1085 prompt "Timer frequency" 1086 1087config HZ_100 1088 bool "100 Hz" 1089 1090config HZ_200 1091 bool "200 Hz" 1092 1093config HZ_250 1094 bool "250 Hz" 1095 1096config HZ_300 1097 bool "300 Hz" 1098 1099config HZ_500 1100 bool "500 Hz" 1101 1102config HZ_1000 1103 bool "1000 Hz" 1104 1105endchoice 1106 1107config HZ 1108 int 1109 default HZ_FIXED if HZ_FIXED != 0 1110 default 100 if HZ_100 1111 default 200 if HZ_200 1112 default 250 if HZ_250 1113 default 300 if HZ_300 1114 default 500 if HZ_500 1115 default 1000 1116 1117config SCHED_HRTICK 1118 def_bool HIGH_RES_TIMERS 1119 1120config THUMB2_KERNEL 1121 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1122 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1123 default y if CPU_THUMBONLY 1124 select ARM_UNWIND 1125 help 1126 By enabling this option, the kernel will be compiled in 1127 Thumb-2 mode. 1128 1129 If unsure, say N. 1130 1131config ARM_PATCH_IDIV 1132 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1133 depends on CPU_32v7 1134 default y 1135 help 1136 The ARM compiler inserts calls to __aeabi_idiv() and 1137 __aeabi_uidiv() when it needs to perform division on signed 1138 and unsigned integers. Some v7 CPUs have support for the sdiv 1139 and udiv instructions that can be used to implement those 1140 functions. 1141 1142 Enabling this option allows the kernel to modify itself to 1143 replace the first two instructions of these library functions 1144 with the sdiv or udiv plus "bx lr" instructions when the CPU 1145 it is running on supports them. Typically this will be faster 1146 and less power intensive than running the original library 1147 code to do integer division. 1148 1149config AEABI 1150 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1151 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1152 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1153 help 1154 This option allows for the kernel to be compiled using the latest 1155 ARM ABI (aka EABI). This is only useful if you are using a user 1156 space environment that is also compiled with EABI. 1157 1158 Since there are major incompatibilities between the legacy ABI and 1159 EABI, especially with regard to structure member alignment, this 1160 option also changes the kernel syscall calling convention to 1161 disambiguate both ABIs and allow for backward compatibility support 1162 (selected with CONFIG_OABI_COMPAT). 1163 1164config OABI_COMPAT 1165 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1166 depends on AEABI && !THUMB2_KERNEL 1167 help 1168 This option preserves the old syscall interface along with the 1169 new (ARM EABI) one. It also provides a compatibility layer to 1170 intercept syscalls that have structure arguments which layout 1171 in memory differs between the legacy ABI and the new ARM EABI 1172 (only for non "thumb" binaries). This option adds a tiny 1173 overhead to all syscalls and produces a slightly larger kernel. 1174 1175 The seccomp filter system will not be available when this is 1176 selected, since there is no way yet to sensibly distinguish 1177 between calling conventions during filtering. 1178 1179 If you know you'll be using only pure EABI user space then you 1180 can say N here. If this option is not selected and you attempt 1181 to execute a legacy ABI binary then the result will be 1182 UNPREDICTABLE (in fact it can be predicted that it won't work 1183 at all). If in doubt say N. 1184 1185config ARCH_SELECT_MEMORY_MODEL 1186 def_bool y 1187 1188config ARCH_FLATMEM_ENABLE 1189 def_bool !(ARCH_RPC || ARCH_SA1100) 1190 1191config ARCH_SPARSEMEM_ENABLE 1192 def_bool !ARCH_FOOTBRIDGE 1193 select SPARSEMEM_STATIC if SPARSEMEM 1194 1195config HIGHMEM 1196 bool "High Memory Support" 1197 depends on MMU 1198 select KMAP_LOCAL 1199 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1200 help 1201 The address space of ARM processors is only 4 Gigabytes large 1202 and it has to accommodate user address space, kernel address 1203 space as well as some memory mapped IO. That means that, if you 1204 have a large amount of physical memory and/or IO, not all of the 1205 memory can be "permanently mapped" by the kernel. The physical 1206 memory that is not permanently mapped is called "high memory". 1207 1208 Depending on the selected kernel/user memory split, minimum 1209 vmalloc space and actual amount of RAM, you may not need this 1210 option which should result in a slightly faster kernel. 1211 1212 If unsure, say n. 1213 1214config HIGHPTE 1215 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1216 depends on HIGHMEM 1217 default y 1218 help 1219 The VM uses one page of physical memory for each page table. 1220 For systems with a lot of processes, this can use a lot of 1221 precious low memory, eventually leading to low memory being 1222 consumed by page tables. Setting this option will allow 1223 user-space 2nd level page tables to reside in high memory. 1224 1225config ARM_PAN 1226 bool "Enable privileged no-access" 1227 depends on MMU 1228 default y 1229 help 1230 Increase kernel security by ensuring that normal kernel accesses 1231 are unable to access userspace addresses. This can help prevent 1232 use-after-free bugs becoming an exploitable privilege escalation 1233 by ensuring that magic values (such as LIST_POISON) will always 1234 fault when dereferenced. 1235 1236 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1237 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1238 1239config CPU_SW_DOMAIN_PAN 1240 def_bool y 1241 depends on ARM_PAN && !ARM_LPAE 1242 help 1243 Enable use of CPU domains to implement privileged no-access. 1244 1245 CPUs with low-vector mappings use a best-efforts implementation. 1246 Their lower 1MB needs to remain accessible for the vectors, but 1247 the remainder of userspace will become appropriately inaccessible. 1248 1249config CPU_TTBR0_PAN 1250 def_bool y 1251 depends on ARM_PAN && ARM_LPAE 1252 help 1253 Enable privileged no-access by disabling TTBR0 page table walks when 1254 running in kernel mode. 1255 1256config HW_PERF_EVENTS 1257 def_bool y 1258 depends on ARM_PMU 1259 1260config ARM_MODULE_PLTS 1261 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1262 depends on MODULES 1263 select KASAN_VMALLOC if KASAN 1264 default y 1265 help 1266 Allocate PLTs when loading modules so that jumps and calls whose 1267 targets are too far away for their relative offsets to be encoded 1268 in the instructions themselves can be bounced via veneers in the 1269 module's PLT. This allows modules to be allocated in the generic 1270 vmalloc area after the dedicated module memory area has been 1271 exhausted. The modules will use slightly more memory, but after 1272 rounding up to page size, the actual memory footprint is usually 1273 the same. 1274 1275 Disabling this is usually safe for small single-platform 1276 configurations. If unsure, say y. 1277 1278config ARCH_FORCE_MAX_ORDER 1279 int "Order of maximal physically contiguous allocations" 1280 default "11" if SOC_AM33XX 1281 default "8" if SA1111 1282 default "10" 1283 help 1284 The kernel page allocator limits the size of maximal physically 1285 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1286 defines the maximal power of two of number of pages that can be 1287 allocated as a single contiguous block. This option allows 1288 overriding the default setting when ability to allocate very 1289 large blocks of physically contiguous memory is required. 1290 1291 Don't change if unsure. 1292 1293config ALIGNMENT_TRAP 1294 def_bool CPU_CP15_MMU 1295 select HAVE_PROC_CPU if PROC_FS 1296 help 1297 ARM processors cannot fetch/store information which is not 1298 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1299 address divisible by 4. On 32-bit ARM processors, these non-aligned 1300 fetch/store instructions will be emulated in software if you say 1301 here, which has a severe performance impact. This is necessary for 1302 correct operation of some network protocols. With an IP-only 1303 configuration it is safe to say N, otherwise say Y. 1304 1305config UACCESS_WITH_MEMCPY 1306 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1307 depends on MMU 1308 default y if CPU_FEROCEON 1309 help 1310 Implement faster copy_to_user and clear_user methods for CPU 1311 cores where a 8-word STM instruction give significantly higher 1312 memory write throughput than a sequence of individual 32bit stores. 1313 1314 A possible side effect is a slight increase in scheduling latency 1315 between threads sharing the same address space if they invoke 1316 such copy operations with large buffers. 1317 1318 However, if the CPU data cache is using a write-allocate mode, 1319 this option is unlikely to provide any performance gain. 1320 1321config PARAVIRT 1322 bool "Enable paravirtualization code" 1323 help 1324 This changes the kernel so it can modify itself when it is run 1325 under a hypervisor, potentially improving performance significantly 1326 over full virtualization. 1327 1328config PARAVIRT_TIME_ACCOUNTING 1329 bool "Paravirtual steal time accounting" 1330 select PARAVIRT 1331 help 1332 Select this option to enable fine granularity task steal time 1333 accounting. Time spent executing other tasks in parallel with 1334 the current vCPU is discounted from the vCPU power. To account for 1335 that, there can be a small performance impact. 1336 1337 If in doubt, say N here. 1338 1339config XEN_DOM0 1340 def_bool y 1341 depends on XEN 1342 1343config XEN 1344 bool "Xen guest support on ARM" 1345 depends on ARM && AEABI && OF 1346 depends on CPU_V7 && !CPU_V6 1347 depends on !GENERIC_ATOMIC64 1348 depends on MMU 1349 select ARCH_DMA_ADDR_T_64BIT 1350 select ARM_PSCI 1351 select SWIOTLB 1352 select SWIOTLB_XEN 1353 select PARAVIRT 1354 help 1355 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1356 1357config CC_HAVE_STACKPROTECTOR_TLS 1358 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1359 1360config STACKPROTECTOR_PER_TASK 1361 bool "Use a unique stack canary value for each task" 1362 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1363 depends on CC_HAVE_STACKPROTECTOR_TLS 1364 default y 1365 help 1366 Due to the fact that GCC uses an ordinary symbol reference from 1367 which to load the value of the stack canary, this value can only 1368 change at reboot time on SMP systems, and all tasks running in the 1369 kernel's address space are forced to use the same canary value for 1370 the entire duration that the system is up. 1371 1372 Enable this option to switch to a different method that uses a 1373 different canary value for each task. 1374 1375endmenu 1376 1377menu "Boot options" 1378 1379config USE_OF 1380 bool "Flattened Device Tree support" 1381 select IRQ_DOMAIN 1382 select OF 1383 help 1384 Include support for flattened device tree machine descriptions. 1385 1386config ARCH_WANT_FLAT_DTB_INSTALL 1387 def_bool y 1388 1389config ATAGS 1390 bool "Support for the traditional ATAGS boot data passing" 1391 default y 1392 help 1393 This is the traditional way of passing data to the kernel at boot 1394 time. If you are solely relying on the flattened device tree (or 1395 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1396 to remove ATAGS support from your kernel binary. 1397 1398config DEPRECATED_PARAM_STRUCT 1399 bool "Provide old way to pass kernel parameters" 1400 depends on ATAGS 1401 help 1402 This was deprecated in 2001 and announced to live on for 5 years. 1403 Some old boot loaders still use this way. 1404 1405# Compressed boot loader in ROM. Yes, we really want to ask about 1406# TEXT and BSS so we preserve their values in the config files. 1407config ZBOOT_ROM_TEXT 1408 hex "Compressed ROM boot loader base address" 1409 default 0x0 1410 help 1411 The physical address at which the ROM-able zImage is to be 1412 placed in the target. Platforms which normally make use of 1413 ROM-able zImage formats normally set this to a suitable 1414 value in their defconfig file. 1415 1416 If ZBOOT_ROM is not enabled, this has no effect. 1417 1418config ZBOOT_ROM_BSS 1419 hex "Compressed ROM boot loader BSS address" 1420 default 0x0 1421 help 1422 The base address of an area of read/write memory in the target 1423 for the ROM-able zImage which must be available while the 1424 decompressor is running. It must be large enough to hold the 1425 entire decompressed kernel plus an additional 128 KiB. 1426 Platforms which normally make use of ROM-able zImage formats 1427 normally set this to a suitable value in their defconfig file. 1428 1429 If ZBOOT_ROM is not enabled, this has no effect. 1430 1431config ZBOOT_ROM 1432 bool "Compressed boot loader in ROM/flash" 1433 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1434 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1435 help 1436 Say Y here if you intend to execute your compressed kernel image 1437 (zImage) directly from ROM or flash. If unsure, say N. 1438 1439config ARM_APPENDED_DTB 1440 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1441 depends on OF 1442 help 1443 With this option, the boot code will look for a device tree binary 1444 (DTB) appended to zImage 1445 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1446 1447 This is meant as a backward compatibility convenience for those 1448 systems with a bootloader that can't be upgraded to accommodate 1449 the documented boot protocol using a device tree. 1450 1451 Beware that there is very little in terms of protection against 1452 this option being confused by leftover garbage in memory that might 1453 look like a DTB header after a reboot if no actual DTB is appended 1454 to zImage. Do not leave this option active in a production kernel 1455 if you don't intend to always append a DTB. Proper passing of the 1456 location into r2 of a bootloader provided DTB is always preferable 1457 to this option. 1458 1459config ARM_ATAG_DTB_COMPAT 1460 bool "Supplement the appended DTB with traditional ATAG information" 1461 depends on ARM_APPENDED_DTB 1462 help 1463 Some old bootloaders can't be updated to a DTB capable one, yet 1464 they provide ATAGs with memory configuration, the ramdisk address, 1465 the kernel cmdline string, etc. Such information is dynamically 1466 provided by the bootloader and can't always be stored in a static 1467 DTB. To allow a device tree enabled kernel to be used with such 1468 bootloaders, this option allows zImage to extract the information 1469 from the ATAG list and store it at run time into the appended DTB. 1470 1471choice 1472 prompt "Kernel command line type" 1473 depends on ARM_ATAG_DTB_COMPAT 1474 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1475 1476config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1477 bool "Use bootloader kernel arguments if available" 1478 help 1479 Uses the command-line options passed by the boot loader instead of 1480 the device tree bootargs property. If the boot loader doesn't provide 1481 any, the device tree bootargs property will be used. 1482 1483config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1484 bool "Extend with bootloader kernel arguments" 1485 help 1486 The command-line arguments provided by the boot loader will be 1487 appended to the the device tree bootargs property. 1488 1489endchoice 1490 1491config CMDLINE 1492 string "Default kernel command string" 1493 default "" 1494 help 1495 On some architectures (e.g. CATS), there is currently no way 1496 for the boot loader to pass arguments to the kernel. For these 1497 architectures, you should supply some command-line options at build 1498 time by entering them here. As a minimum, you should specify the 1499 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1500 1501choice 1502 prompt "Kernel command line type" 1503 depends on CMDLINE != "" 1504 default CMDLINE_FROM_BOOTLOADER 1505 1506config CMDLINE_FROM_BOOTLOADER 1507 bool "Use bootloader kernel arguments if available" 1508 help 1509 Uses the command-line options passed by the boot loader. If 1510 the boot loader doesn't provide any, the default kernel command 1511 string provided in CMDLINE will be used. 1512 1513config CMDLINE_EXTEND 1514 bool "Extend bootloader kernel arguments" 1515 help 1516 The command-line arguments provided by the boot loader will be 1517 appended to the default kernel command string. 1518 1519config CMDLINE_FORCE 1520 bool "Always use the default kernel command string" 1521 help 1522 Always use the default kernel command string, even if the boot 1523 loader passes other arguments to the kernel. 1524 This is useful if you cannot or don't want to change the 1525 command-line options your boot loader passes to the kernel. 1526endchoice 1527 1528config XIP_KERNEL 1529 bool "Kernel Execute-In-Place from ROM" 1530 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1531 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1532 help 1533 Execute-In-Place allows the kernel to run from non-volatile storage 1534 directly addressable by the CPU, such as NOR flash. This saves RAM 1535 space since the text section of the kernel is not loaded from flash 1536 to RAM. Read-write sections, such as the data section and stack, 1537 are still copied to RAM. The XIP kernel is not compressed since 1538 it has to run directly from flash, so it will take more space to 1539 store it. The flash address used to link the kernel object files, 1540 and for storing it, is configuration dependent. Therefore, if you 1541 say Y here, you must know the proper physical address where to 1542 store the kernel image depending on your own flash memory usage. 1543 1544 Also note that the make target becomes "make xipImage" rather than 1545 "make zImage" or "make Image". The final kernel binary to put in 1546 ROM memory will be arch/arm/boot/xipImage. 1547 1548 If unsure, say N. 1549 1550config XIP_PHYS_ADDR 1551 hex "XIP Kernel Physical Location" 1552 depends on XIP_KERNEL 1553 default "0x00080000" 1554 help 1555 This is the physical address in your flash memory the kernel will 1556 be linked for and stored to. This address is dependent on your 1557 own flash usage. 1558 1559config XIP_DEFLATED_DATA 1560 bool "Store kernel .data section compressed in ROM" 1561 depends on XIP_KERNEL 1562 select ZLIB_INFLATE 1563 help 1564 Before the kernel is actually executed, its .data section has to be 1565 copied to RAM from ROM. This option allows for storing that data 1566 in compressed form and decompressed to RAM rather than merely being 1567 copied, saving some precious ROM space. A possible drawback is a 1568 slightly longer boot delay. 1569 1570config ARCH_SUPPORTS_KEXEC 1571 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1572 1573config ATAGS_PROC 1574 bool "Export atags in procfs" 1575 depends on ATAGS && KEXEC 1576 default y 1577 help 1578 Should the atags used to boot the kernel be exported in an "atags" 1579 file in procfs. Useful with kexec. 1580 1581config ARCH_SUPPORTS_CRASH_DUMP 1582 def_bool y 1583 1584config ARCH_DEFAULT_CRASH_DUMP 1585 def_bool y 1586 1587config AUTO_ZRELADDR 1588 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1589 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1590 help 1591 ZRELADDR is the physical address where the decompressed kernel 1592 image will be placed. If AUTO_ZRELADDR is selected, the address 1593 will be determined at run-time, either by masking the current IP 1594 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1595 This assumes the zImage being placed in the first 128MB from 1596 start of memory. 1597 1598config EFI_STUB 1599 bool 1600 1601config EFI 1602 bool "UEFI runtime support" 1603 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1604 select UCS2_STRING 1605 select EFI_PARAMS_FROM_FDT 1606 select EFI_STUB 1607 select EFI_GENERIC_STUB 1608 select EFI_RUNTIME_WRAPPERS 1609 help 1610 This option provides support for runtime services provided 1611 by UEFI firmware (such as non-volatile variables, realtime 1612 clock, and platform reset). A UEFI stub is also provided to 1613 allow the kernel to be booted as an EFI application. This 1614 is only useful for kernels that may run on systems that have 1615 UEFI firmware. 1616 1617config DMI 1618 bool "Enable support for SMBIOS (DMI) tables" 1619 depends on EFI 1620 default y 1621 help 1622 This enables SMBIOS/DMI feature for systems. 1623 1624 This option is only useful on systems that have UEFI firmware. 1625 However, even with this option, the resultant kernel should 1626 continue to boot on existing non-UEFI platforms. 1627 1628 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1629 i.e., the the practice of identifying the platform via DMI to 1630 decide whether certain workarounds for buggy hardware and/or 1631 firmware need to be enabled. This would require the DMI subsystem 1632 to be enabled much earlier than we do on ARM, which is non-trivial. 1633 1634endmenu 1635 1636menu "CPU Power Management" 1637 1638source "drivers/cpufreq/Kconfig" 1639 1640source "drivers/cpuidle/Kconfig" 1641 1642endmenu 1643 1644menu "Floating point emulation" 1645 1646comment "At least one emulation must be selected" 1647 1648config FPE_NWFPE 1649 bool "NWFPE math emulation" 1650 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1651 help 1652 Say Y to include the NWFPE floating point emulator in the kernel. 1653 This is necessary to run most binaries. Linux does not currently 1654 support floating point hardware so you need to say Y here even if 1655 your machine has an FPA or floating point co-processor podule. 1656 1657 You may say N here if you are going to load the Acorn FPEmulator 1658 early in the bootup. 1659 1660config FPE_NWFPE_XP 1661 bool "Support extended precision" 1662 depends on FPE_NWFPE 1663 help 1664 Say Y to include 80-bit support in the kernel floating-point 1665 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1666 Note that gcc does not generate 80-bit operations by default, 1667 so in most cases this option only enlarges the size of the 1668 floating point emulator without any good reason. 1669 1670 You almost surely want to say N here. 1671 1672config FPE_FASTFPE 1673 bool "FastFPE math emulation (EXPERIMENTAL)" 1674 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1675 help 1676 Say Y here to include the FAST floating point emulator in the kernel. 1677 This is an experimental much faster emulator which now also has full 1678 precision for the mantissa. It does not support any exceptions. 1679 It is very simple, and approximately 3-6 times faster than NWFPE. 1680 1681 It should be sufficient for most programs. It may be not suitable 1682 for scientific calculations, but you have to check this for yourself. 1683 If you do not feel you need a faster FP emulation you should better 1684 choose NWFPE. 1685 1686config VFP 1687 bool "VFP-format floating point maths" 1688 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1689 help 1690 Say Y to include VFP support code in the kernel. This is needed 1691 if your hardware includes a VFP unit. 1692 1693 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1694 release notes and additional status information. 1695 1696 Say N if your target does not have VFP hardware. 1697 1698config VFPv3 1699 bool 1700 depends on VFP 1701 default y if CPU_V7 1702 1703config NEON 1704 bool "Advanced SIMD (NEON) Extension support" 1705 depends on VFPv3 && CPU_V7 1706 help 1707 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1708 Extension. 1709 1710config KERNEL_MODE_NEON 1711 bool "Support for NEON in kernel mode" 1712 depends on NEON && AEABI 1713 help 1714 Say Y to include support for NEON in kernel mode. 1715 1716endmenu 1717 1718menu "Power management options" 1719 1720source "kernel/power/Kconfig" 1721 1722config ARCH_SUSPEND_POSSIBLE 1723 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1724 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1725 def_bool y 1726 1727config ARM_CPU_SUSPEND 1728 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1729 depends on ARCH_SUSPEND_POSSIBLE 1730 1731config ARCH_HIBERNATION_POSSIBLE 1732 bool 1733 depends on MMU 1734 default y if ARCH_SUSPEND_POSSIBLE 1735 1736endmenu 1737