1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 32config GIC_NON_BANKED 33 bool 34 35config ARM_GIC_V3 36 bool 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 42config ARM_GIC_V3_ITS 43 bool 44 select GENERIC_MSI_IRQ 45 select IRQ_MSI_LIB 46 default ARM_GIC_V3 47 48config ARM_GIC_V3_ITS_FSL_MC 49 bool 50 depends on ARM_GIC_V3_ITS 51 depends on FSL_MC_BUS 52 default ARM_GIC_V3_ITS 53 54config ARM_NVIC 55 bool 56 select IRQ_DOMAIN_HIERARCHY 57 select GENERIC_IRQ_CHIP 58 59config ARM_VIC 60 bool 61 select IRQ_DOMAIN 62 63config ARM_VIC_NR 64 int 65 default 4 if ARCH_S5PV210 66 default 2 67 depends on ARM_VIC 68 help 69 The maximum number of VICs available in the system, for 70 power management. 71 72config IRQ_MSI_LIB 73 bool 74 75config ARMADA_370_XP_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select PCI_MSI if PCI 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 80 81config ALPINE_MSI 82 bool 83 depends on PCI 84 select PCI_MSI 85 select GENERIC_IRQ_CHIP 86 87config AL_FIC 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 89 depends on OF 90 depends on HAS_IOMEM 91 select GENERIC_IRQ_CHIP 92 select IRQ_DOMAIN 93 help 94 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 95 96config ATMEL_AIC_IRQ 97 bool 98 select GENERIC_IRQ_CHIP 99 select IRQ_DOMAIN 100 select SPARSE_IRQ 101 102config ATMEL_AIC5_IRQ 103 bool 104 select GENERIC_IRQ_CHIP 105 select IRQ_DOMAIN 106 select SPARSE_IRQ 107 108config I8259 109 bool 110 select IRQ_DOMAIN 111 112config BCM6345_L1_IRQ 113 bool 114 select GENERIC_IRQ_CHIP 115 select IRQ_DOMAIN 116 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 117 118config BCM7038_L1_IRQ 119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 120 depends on ARCH_BRCMSTB || BMIPS_GENERIC 121 default ARCH_BRCMSTB || BMIPS_GENERIC 122 select GENERIC_IRQ_CHIP 123 select IRQ_DOMAIN 124 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 125 126config BCM7120_L2_IRQ 127 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 128 depends on ARCH_BRCMSTB || BMIPS_GENERIC 129 default ARCH_BRCMSTB || BMIPS_GENERIC 130 select GENERIC_IRQ_CHIP 131 select IRQ_DOMAIN 132 133config BRCMSTB_L2_IRQ 134 tristate "Broadcom STB generic L2 interrupt controller driver" 135 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 136 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 137 select GENERIC_IRQ_CHIP 138 select IRQ_DOMAIN 139 140config DAVINCI_CP_INTC 141 bool 142 select GENERIC_IRQ_CHIP 143 select IRQ_DOMAIN 144 145config DW_APB_ICTL 146 bool 147 select GENERIC_IRQ_CHIP 148 select IRQ_DOMAIN_HIERARCHY 149 150config FARADAY_FTINTC010 151 bool 152 select IRQ_DOMAIN 153 select SPARSE_IRQ 154 155config HISILICON_IRQ_MBIGEN 156 bool 157 select ARM_GIC_V3 158 select ARM_GIC_V3_ITS 159 160config IMGPDC_IRQ 161 bool 162 select GENERIC_IRQ_CHIP 163 select IRQ_DOMAIN 164 165config IXP4XX_IRQ 166 bool 167 select IRQ_DOMAIN 168 select SPARSE_IRQ 169 170config LAN966X_OIC 171 tristate "Microchip LAN966x OIC Support" 172 depends on MCHP_LAN966X_PCI || COMPILE_TEST 173 select GENERIC_IRQ_CHIP 174 select IRQ_DOMAIN 175 help 176 Enable support for the LAN966x Outbound Interrupt Controller. 177 This controller is present on the Microchip LAN966x PCI device and 178 maps the internal interrupts sources to PCIe interrupt. 179 180 To compile this driver as a module, choose M here: the module 181 will be called irq-lan966x-oic. 182 183config MADERA_IRQ 184 tristate 185 186config IRQ_MIPS_CPU 187 bool 188 select GENERIC_IRQ_CHIP 189 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 190 select IRQ_DOMAIN 191 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 192 193config CLPS711X_IRQCHIP 194 bool 195 depends on ARCH_CLPS711X 196 select IRQ_DOMAIN 197 select SPARSE_IRQ 198 default y 199 200config OMPIC 201 bool 202 203config OR1K_PIC 204 bool 205 select IRQ_DOMAIN 206 207config OMAP_IRQCHIP 208 bool 209 select GENERIC_IRQ_CHIP 210 select IRQ_DOMAIN 211 212config ORION_IRQCHIP 213 bool 214 select IRQ_DOMAIN 215 216config PIC32_EVIC 217 bool 218 select GENERIC_IRQ_CHIP 219 select IRQ_DOMAIN 220 221config JCORE_AIC 222 bool "J-Core integrated AIC" if COMPILE_TEST 223 depends on OF 224 select IRQ_DOMAIN 225 help 226 Support for the J-Core integrated AIC. 227 228config RDA_INTC 229 bool 230 select IRQ_DOMAIN 231 232config RENESAS_INTC_IRQPIN 233 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 234 select IRQ_DOMAIN 235 help 236 Enable support for the Renesas Interrupt Controller for external 237 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 238 239config RENESAS_IRQC 240 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 241 select GENERIC_IRQ_CHIP 242 select IRQ_DOMAIN 243 help 244 Enable support for the Renesas Interrupt Controller for external 245 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 246 247config RENESAS_RZA1_IRQC 248 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 249 select IRQ_DOMAIN_HIERARCHY 250 help 251 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 252 to 8 external interrupts with configurable sense select. 253 254config RENESAS_RZG2L_IRQC 255 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 256 select GENERIC_IRQ_CHIP 257 select IRQ_DOMAIN_HIERARCHY 258 help 259 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 260 for external devices. 261 262config RENESAS_RZV2H_ICU 263 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 264 select GENERIC_IRQ_CHIP 265 select IRQ_DOMAIN_HIERARCHY 266 help 267 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 268 269config SL28CPLD_INTC 270 bool "Kontron sl28cpld IRQ controller" 271 depends on MFD_SL28CPLD=y || COMPILE_TEST 272 select REGMAP_IRQ 273 help 274 Interrupt controller driver for the board management controller 275 found on the Kontron sl28 CPLD. 276 277config ST_IRQCHIP 278 bool 279 select REGMAP 280 select MFD_SYSCON 281 help 282 Enables SysCfg Controlled IRQs on STi based platforms. 283 284config SUN4I_INTC 285 bool 286 287config SUN6I_R_INTC 288 bool 289 select IRQ_DOMAIN_HIERARCHY 290 select IRQ_FASTEOI_HIERARCHY_HANDLERS 291 292config SUNXI_NMI_INTC 293 bool 294 select GENERIC_IRQ_CHIP 295 296config TB10X_IRQC 297 bool 298 select IRQ_DOMAIN 299 select GENERIC_IRQ_CHIP 300 301config TS4800_IRQ 302 tristate "TS-4800 IRQ controller" 303 select IRQ_DOMAIN 304 depends on HAS_IOMEM 305 depends on SOC_IMX51 || COMPILE_TEST 306 help 307 Support for the TS-4800 FPGA IRQ controller 308 309config VERSATILE_FPGA_IRQ 310 bool 311 select IRQ_DOMAIN 312 313config VERSATILE_FPGA_IRQ_NR 314 int 315 default 4 316 depends on VERSATILE_FPGA_IRQ 317 318config XTENSA_MX 319 bool 320 select IRQ_DOMAIN 321 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 322 323config XILINX_INTC 324 bool "Xilinx Interrupt Controller IP" 325 depends on OF_ADDRESS 326 select IRQ_DOMAIN 327 help 328 Support for the Xilinx Interrupt Controller IP core. 329 This is used as a primary controller with MicroBlaze and can also 330 be used as a secondary chained controller on other platforms. 331 332config IRQ_CROSSBAR 333 bool 334 help 335 Support for a CROSSBAR ip that precedes the main interrupt controller. 336 The primary irqchip invokes the crossbar's callback which inturn allocates 337 a free irq and configures the IP. Thus the peripheral interrupts are 338 routed to one of the free irqchip interrupt lines. 339 340config KEYSTONE_IRQ 341 tristate "Keystone 2 IRQ controller IP" 342 depends on ARCH_KEYSTONE 343 help 344 Support for Texas Instruments Keystone 2 IRQ controller IP which 345 is part of the Keystone 2 IPC mechanism 346 347config MIPS_GIC 348 bool 349 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 350 select GENERIC_IRQ_IPI if SMP 351 select IRQ_DOMAIN_HIERARCHY 352 select MIPS_CM 353 354config INGENIC_IRQ 355 bool 356 depends on MACH_INGENIC 357 default y 358 359config INGENIC_TCU_IRQ 360 bool "Ingenic JZ47xx TCU interrupt controller" 361 default MACH_INGENIC 362 depends on MIPS || COMPILE_TEST 363 select MFD_SYSCON 364 select GENERIC_IRQ_CHIP 365 help 366 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 367 JZ47xx SoCs. 368 369 If unsure, say N. 370 371config IMX_GPCV2 372 bool 373 select IRQ_DOMAIN 374 help 375 Enables the wakeup IRQs for IMX platforms with GPCv2 block 376 377config IRQ_MXS 378 def_bool y if MACH_ASM9260 || ARCH_MXS 379 select IRQ_DOMAIN 380 select STMP_DEVICE 381 382config MSCC_OCELOT_IRQ 383 bool 384 select IRQ_DOMAIN 385 select GENERIC_IRQ_CHIP 386 387config MVEBU_GICP 388 select IRQ_MSI_LIB 389 bool 390 391config MVEBU_ICU 392 bool 393 394config MVEBU_ODMI 395 bool 396 select IRQ_MSI_LIB 397 select GENERIC_MSI_IRQ 398 399config MVEBU_PIC 400 bool 401 402config MVEBU_SEI 403 bool 404 405config LS_EXTIRQ 406 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 407 select MFD_SYSCON 408 409config LS_SCFG_MSI 410 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 411 depends on PCI_MSI 412 413config PARTITION_PERCPU 414 bool 415 416config STM32MP_EXTI 417 tristate "STM32MP extended interrupts and event controller" 418 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 419 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 420 select IRQ_DOMAIN_HIERARCHY 421 select GENERIC_IRQ_CHIP 422 help 423 Support STM32MP EXTI (extended interrupts and event) controller. 424 425config STM32_EXTI 426 bool 427 select IRQ_DOMAIN 428 select GENERIC_IRQ_CHIP 429 430config QCOM_IRQ_COMBINER 431 bool "QCOM IRQ combiner support" 432 depends on ARCH_QCOM && ACPI 433 select IRQ_DOMAIN_HIERARCHY 434 help 435 Say yes here to add support for the IRQ combiner devices embedded 436 in Qualcomm Technologies chips. 437 438config IRQ_UNIPHIER_AIDET 439 bool "UniPhier AIDET support" if COMPILE_TEST 440 depends on ARCH_UNIPHIER || COMPILE_TEST 441 default ARCH_UNIPHIER 442 select IRQ_DOMAIN_HIERARCHY 443 help 444 Support for the UniPhier AIDET (ARM Interrupt Detector). 445 446config MESON_IRQ_GPIO 447 tristate "Meson GPIO Interrupt Multiplexer" 448 depends on ARCH_MESON || COMPILE_TEST 449 default ARCH_MESON 450 select IRQ_DOMAIN_HIERARCHY 451 help 452 Support Meson SoC Family GPIO Interrupt Multiplexer 453 454config GOLDFISH_PIC 455 bool "Goldfish programmable interrupt controller" 456 depends on MIPS && (GOLDFISH || COMPILE_TEST) 457 select GENERIC_IRQ_CHIP 458 select IRQ_DOMAIN 459 help 460 Say yes here to enable Goldfish interrupt controller driver used 461 for Goldfish based virtual platforms. 462 463config QCOM_PDC 464 tristate "QCOM PDC" 465 depends on ARCH_QCOM 466 select IRQ_DOMAIN_HIERARCHY 467 help 468 Power Domain Controller driver to manage and configure wakeup 469 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 470 471config QCOM_MPM 472 tristate "QCOM MPM" 473 depends on ARCH_QCOM 474 depends on MAILBOX 475 select IRQ_DOMAIN_HIERARCHY 476 help 477 MSM Power Manager driver to manage and configure wakeup 478 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 479 480config CSKY_MPINTC 481 bool 482 depends on CSKY 483 help 484 Say yes here to enable C-SKY SMP interrupt controller driver used 485 for C-SKY SMP system. 486 In fact it's not mmio map in hardware and it uses ld/st to visit the 487 controller's register inside CPU. 488 489config CSKY_APB_INTC 490 bool "C-SKY APB Interrupt Controller" 491 depends on CSKY 492 help 493 Say yes here to enable C-SKY APB interrupt controller driver used 494 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 495 the controller's register. 496 497config IMX_IRQSTEER 498 bool "i.MX IRQSTEER support" 499 depends on ARCH_MXC || COMPILE_TEST 500 default ARCH_MXC 501 select IRQ_DOMAIN 502 help 503 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 504 505config IMX_INTMUX 506 bool "i.MX INTMUX support" if COMPILE_TEST 507 default y if ARCH_MXC 508 select IRQ_DOMAIN 509 help 510 Support for the i.MX INTMUX interrupt multiplexer. 511 512config IMX_MU_MSI 513 tristate "i.MX MU used as MSI controller" 514 depends on OF && HAS_IOMEM 515 depends on ARCH_MXC || COMPILE_TEST 516 default m if ARCH_MXC 517 select IRQ_DOMAIN 518 select IRQ_DOMAIN_HIERARCHY 519 select GENERIC_MSI_IRQ 520 select IRQ_MSI_LIB 521 help 522 Provide a driver for the i.MX Messaging Unit block used as a 523 CPU-to-CPU MSI controller. This requires a specially crafted DT 524 to make use of this driver. 525 526 If unsure, say N 527 528config LS1X_IRQ 529 bool "Loongson-1 Interrupt Controller" 530 depends on MACH_LOONGSON32 531 default y 532 select IRQ_DOMAIN 533 select GENERIC_IRQ_CHIP 534 help 535 Support for the Loongson-1 platform Interrupt Controller. 536 537config TI_SCI_INTR_IRQCHIP 538 tristate "TI SCI INTR Interrupt Controller" 539 depends on TI_SCI_PROTOCOL 540 depends on ARCH_K3 || COMPILE_TEST 541 select IRQ_DOMAIN_HIERARCHY 542 help 543 This enables the irqchip driver support for K3 Interrupt router 544 over TI System Control Interface available on some new TI's SoCs. 545 If you wish to use interrupt router irq resources managed by the 546 TI System Controller, say Y here. Otherwise, say N. 547 548config TI_SCI_INTA_IRQCHIP 549 tristate "TI SCI INTA Interrupt Controller" 550 depends on TI_SCI_PROTOCOL 551 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 552 select IRQ_DOMAIN_HIERARCHY 553 select TI_SCI_INTA_MSI_DOMAIN 554 help 555 This enables the irqchip driver support for K3 Interrupt aggregator 556 over TI System Control Interface available on some new TI's SoCs. 557 If you wish to use interrupt aggregator irq resources managed by the 558 TI System Controller, say Y here. Otherwise, say N. 559 560config TI_PRUSS_INTC 561 tristate 562 depends on TI_PRUSS 563 default TI_PRUSS 564 select IRQ_DOMAIN 565 help 566 This enables support for the PRU-ICSS Local Interrupt Controller 567 present within a PRU-ICSS subsystem present on various TI SoCs. 568 The PRUSS INTC enables various interrupts to be routed to multiple 569 different processors within the SoC. 570 571config RISCV_INTC 572 bool 573 depends on RISCV 574 select IRQ_DOMAIN_HIERARCHY 575 576config RISCV_APLIC 577 bool 578 depends on RISCV 579 select IRQ_DOMAIN_HIERARCHY 580 581config RISCV_APLIC_MSI 582 bool 583 depends on RISCV_APLIC 584 select GENERIC_MSI_IRQ 585 default RISCV_APLIC 586 587config RISCV_IMSIC 588 bool 589 depends on RISCV 590 select IRQ_DOMAIN_HIERARCHY 591 select GENERIC_IRQ_MATRIX_ALLOCATOR 592 select GENERIC_MSI_IRQ 593 594config RISCV_IMSIC_PCI 595 bool 596 depends on RISCV_IMSIC 597 depends on PCI 598 depends on PCI_MSI 599 default RISCV_IMSIC 600 601config SIFIVE_PLIC 602 bool 603 depends on RISCV 604 select IRQ_DOMAIN_HIERARCHY 605 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 606 607config STARFIVE_JH8100_INTC 608 bool "StarFive JH8100 External Interrupt Controller" 609 depends on ARCH_STARFIVE || COMPILE_TEST 610 default ARCH_STARFIVE 611 select IRQ_DOMAIN_HIERARCHY 612 help 613 This enables support for the INTC chip found in StarFive JH8100 614 SoC. 615 616 If you don't know what to do here, say Y. 617 618config THEAD_C900_ACLINT_SSWI 619 bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 620 depends on RISCV 621 depends on SMP 622 select IRQ_DOMAIN_HIERARCHY 623 select GENERIC_IRQ_IPI_MUX 624 help 625 This enables support for T-HEAD specific ACLINT SSWI device 626 support. 627 628 If you don't know what to do here, say Y. 629 630config EXYNOS_IRQ_COMBINER 631 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 632 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 633 help 634 Say yes here to add support for the IRQ combiner devices embedded 635 in Samsung Exynos chips. 636 637config IRQ_LOONGARCH_CPU 638 bool 639 select GENERIC_IRQ_CHIP 640 select IRQ_DOMAIN 641 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 642 select LOONGSON_HTVEC 643 select LOONGSON_LIOINTC 644 select LOONGSON_EIOINTC 645 select LOONGSON_PCH_PIC 646 select LOONGSON_PCH_MSI 647 select LOONGSON_PCH_LPC 648 help 649 Support for the LoongArch CPU Interrupt Controller. For details of 650 irq chip hierarchy on LoongArch platforms please read the document 651 Documentation/arch/loongarch/irq-chip-model.rst. 652 653config LOONGSON_LIOINTC 654 bool "Loongson Local I/O Interrupt Controller" 655 depends on MACH_LOONGSON64 656 default y 657 select IRQ_DOMAIN 658 select GENERIC_IRQ_CHIP 659 help 660 Support for the Loongson Local I/O Interrupt Controller. 661 662config LOONGSON_EIOINTC 663 bool "Loongson Extend I/O Interrupt Controller" 664 depends on LOONGARCH 665 depends on MACH_LOONGSON64 666 default MACH_LOONGSON64 667 select IRQ_DOMAIN_HIERARCHY 668 select GENERIC_IRQ_CHIP 669 help 670 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 671 672config LOONGSON_HTPIC 673 bool "Loongson3 HyperTransport PIC Controller" 674 depends on MACH_LOONGSON64 && MIPS 675 default y 676 select IRQ_DOMAIN 677 select GENERIC_IRQ_CHIP 678 help 679 Support for the Loongson-3 HyperTransport PIC Controller. 680 681config LOONGSON_HTVEC 682 bool "Loongson HyperTransport Interrupt Vector Controller" 683 depends on MACH_LOONGSON64 684 default MACH_LOONGSON64 685 select IRQ_DOMAIN_HIERARCHY 686 help 687 Support for the Loongson HyperTransport Interrupt Vector Controller. 688 689config LOONGSON_PCH_PIC 690 bool "Loongson PCH PIC Controller" 691 depends on MACH_LOONGSON64 692 default MACH_LOONGSON64 693 select IRQ_DOMAIN_HIERARCHY 694 select IRQ_FASTEOI_HIERARCHY_HANDLERS 695 help 696 Support for the Loongson PCH PIC Controller. 697 698config LOONGSON_PCH_MSI 699 bool "Loongson PCH MSI Controller" 700 depends on MACH_LOONGSON64 701 depends on PCI 702 default MACH_LOONGSON64 703 select IRQ_DOMAIN_HIERARCHY 704 select IRQ_MSI_LIB 705 select PCI_MSI 706 help 707 Support for the Loongson PCH MSI Controller. 708 709config LOONGSON_PCH_LPC 710 bool "Loongson PCH LPC Controller" 711 depends on LOONGARCH 712 depends on MACH_LOONGSON64 713 default MACH_LOONGSON64 714 select IRQ_DOMAIN_HIERARCHY 715 help 716 Support for the Loongson PCH LPC Controller. 717 718config MST_IRQ 719 bool "MStar Interrupt Controller" 720 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 721 default ARCH_MEDIATEK 722 select IRQ_DOMAIN 723 select IRQ_DOMAIN_HIERARCHY 724 help 725 Support MStar Interrupt Controller. 726 727config WPCM450_AIC 728 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 729 depends on ARCH_WPCM450 730 help 731 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 732 733config IRQ_IDT3243X 734 bool 735 select GENERIC_IRQ_CHIP 736 select IRQ_DOMAIN 737 738config APPLE_AIC 739 bool "Apple Interrupt Controller (AIC)" 740 depends on ARM64 741 depends on ARCH_APPLE || COMPILE_TEST 742 select GENERIC_IRQ_IPI_MUX 743 help 744 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 745 such as the M1. 746 747config MCHP_EIC 748 bool "Microchip External Interrupt Controller" 749 depends on ARCH_AT91 || COMPILE_TEST 750 select IRQ_DOMAIN 751 select IRQ_DOMAIN_HIERARCHY 752 help 753 Support for Microchip External Interrupt Controller. 754 755config SUNPLUS_SP7021_INTC 756 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 757 default SOC_SP7021 758 help 759 Support for the Sunplus SP7021 Interrupt Controller IP core. 760 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 761 chained controller, routing all interrupt source in P-Chip to 762 the primary controller on C-Chip. 763 764endmenu 765