1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CRC32 25 select ARCH_HAS_CRC_T10DIF if KERNEL_MODE_NEON 26 select ARCH_HAS_CURRENT_STACK_POINTER 27 select ARCH_HAS_DEBUG_VIRTUAL 28 select ARCH_HAS_DEBUG_VM_PGTABLE 29 select ARCH_HAS_DMA_OPS if XEN 30 select ARCH_HAS_DMA_PREP_COHERENT 31 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 32 select ARCH_HAS_FAST_MULTIPLIER 33 select ARCH_HAS_FORTIFY_SOURCE 34 select ARCH_HAS_GCOV_PROFILE_ALL 35 select ARCH_HAS_GIGANTIC_PAGE 36 select ARCH_HAS_KCOV 37 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 38 select ARCH_HAS_KEEPINITRD 39 select ARCH_HAS_MEMBARRIER_SYNC_CORE 40 select ARCH_HAS_MEM_ENCRYPT 41 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 42 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 43 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 44 select ARCH_HAS_PTE_DEVMAP 45 select ARCH_HAS_PTE_SPECIAL 46 select ARCH_HAS_HW_PTE_YOUNG 47 select ARCH_HAS_SETUP_DMA_OPS 48 select ARCH_HAS_SET_DIRECT_MAP 49 select ARCH_HAS_SET_MEMORY 50 select ARCH_HAS_MEM_ENCRYPT 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_SYSCALL_WRAPPER 58 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 59 select ARCH_HAS_ZONE_DMA_SET if EXPERT 60 select ARCH_HAVE_ELF_PROT 61 select ARCH_HAVE_NMI_SAFE_CMPXCHG 62 select ARCH_HAVE_TRACE_MMIO_ACCESS 63 select ARCH_INLINE_READ_LOCK if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 65 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 70 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 73 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 74 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 77 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 78 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 79 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 83 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 84 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 87 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 88 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 89 select ARCH_KEEP_MEMBLOCK 90 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 91 select ARCH_USE_CMPXCHG_LOCKREF 92 select ARCH_USE_GNU_PROPERTY 93 select ARCH_USE_MEMTEST 94 select ARCH_USE_QUEUED_RWLOCKS 95 select ARCH_USE_QUEUED_SPINLOCKS 96 select ARCH_USE_SYM_ANNOTATIONS 97 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 98 select ARCH_SUPPORTS_HUGETLBFS 99 select ARCH_SUPPORTS_MEMORY_FAILURE 100 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 101 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 102 select ARCH_SUPPORTS_LTO_CLANG_THIN 103 select ARCH_SUPPORTS_CFI_CLANG 104 select ARCH_SUPPORTS_ATOMIC_RMW 105 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 106 select ARCH_SUPPORTS_NUMA_BALANCING 107 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 108 select ARCH_SUPPORTS_PER_VMA_LOCK 109 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 110 select ARCH_SUPPORTS_RT 111 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 112 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 113 select ARCH_WANT_DEFAULT_BPF_JIT 114 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 115 select ARCH_WANT_FRAME_POINTERS 116 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 117 select ARCH_WANT_LD_ORPHAN_WARN 118 select ARCH_WANTS_EXECMEM_LATE 119 select ARCH_WANTS_NO_INSTR 120 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 121 select ARCH_HAS_UBSAN 122 select ARM_AMBA 123 select ARM_ARCH_TIMER 124 select ARM_GIC 125 select AUDIT_ARCH_COMPAT_GENERIC 126 select ARM_GIC_V2M if PCI 127 select ARM_GIC_V3 128 select ARM_GIC_V3_ITS if PCI 129 select ARM_PSCI_FW 130 select BUILDTIME_TABLE_SORT 131 select CLONE_BACKWARDS 132 select COMMON_CLK 133 select CPU_PM if (SUSPEND || CPU_IDLE) 134 select CPUMASK_OFFSTACK if NR_CPUS > 256 135 select CRC32 136 select DCACHE_WORD_ACCESS 137 select DYNAMIC_FTRACE if FUNCTION_TRACER 138 select DMA_BOUNCE_UNALIGNED_KMALLOC 139 select DMA_DIRECT_REMAP 140 select EDAC_SUPPORT 141 select FRAME_POINTER 142 select FUNCTION_ALIGNMENT_4B 143 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 144 select GENERIC_ALLOCATOR 145 select GENERIC_ARCH_TOPOLOGY 146 select GENERIC_CLOCKEVENTS_BROADCAST 147 select GENERIC_CPU_AUTOPROBE 148 select GENERIC_CPU_DEVICES 149 select GENERIC_CPU_VULNERABILITIES 150 select GENERIC_EARLY_IOREMAP 151 select GENERIC_IDLE_POLL_SETUP 152 select GENERIC_IOREMAP 153 select GENERIC_IRQ_IPI 154 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 155 select GENERIC_IRQ_PROBE 156 select GENERIC_IRQ_SHOW 157 select GENERIC_IRQ_SHOW_LEVEL 158 select GENERIC_LIB_DEVMEM_IS_ALLOWED 159 select GENERIC_PCI_IOMAP 160 select GENERIC_PTDUMP 161 select GENERIC_SCHED_CLOCK 162 select GENERIC_SMP_IDLE_THREAD 163 select GENERIC_TIME_VSYSCALL 164 select GENERIC_GETTIMEOFDAY 165 select GENERIC_VDSO_DATA_STORE 166 select GENERIC_VDSO_TIME_NS 167 select HARDIRQS_SW_RESEND 168 select HAS_IOPORT 169 select HAVE_MOVE_PMD 170 select HAVE_MOVE_PUD 171 select HAVE_PCI 172 select HAVE_ACPI_APEI if (ACPI && EFI) 173 select HAVE_ALIGNED_STRUCT_PAGE 174 select HAVE_ARCH_AUDITSYSCALL 175 select HAVE_ARCH_BITREVERSE 176 select HAVE_ARCH_COMPILER_H 177 select HAVE_ARCH_HUGE_VMALLOC 178 select HAVE_ARCH_HUGE_VMAP 179 select HAVE_ARCH_JUMP_LABEL 180 select HAVE_ARCH_JUMP_LABEL_RELATIVE 181 select HAVE_ARCH_KASAN 182 select HAVE_ARCH_KASAN_VMALLOC 183 select HAVE_ARCH_KASAN_SW_TAGS 184 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 185 # Some instrumentation may be unsound, hence EXPERT 186 select HAVE_ARCH_KCSAN if EXPERT 187 select HAVE_ARCH_KFENCE 188 select HAVE_ARCH_KGDB 189 select HAVE_ARCH_MMAP_RND_BITS 190 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 191 select HAVE_ARCH_PREL32_RELOCATIONS 192 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 193 select HAVE_ARCH_SECCOMP_FILTER 194 select HAVE_ARCH_STACKLEAK 195 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 196 select HAVE_ARCH_TRACEHOOK 197 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 198 select HAVE_ARCH_VMAP_STACK 199 select HAVE_ARM_SMCCC 200 select HAVE_ASM_MODVERSIONS 201 select HAVE_EBPF_JIT 202 select HAVE_C_RECORDMCOUNT 203 select HAVE_CMPXCHG_DOUBLE 204 select HAVE_CMPXCHG_LOCAL 205 select HAVE_CONTEXT_TRACKING_USER 206 select HAVE_DEBUG_KMEMLEAK 207 select HAVE_DMA_CONTIGUOUS 208 select HAVE_DYNAMIC_FTRACE 209 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 210 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 211 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 212 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 213 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 214 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 215 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 216 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 217 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 218 if DYNAMIC_FTRACE_WITH_ARGS 219 select HAVE_SAMPLE_FTRACE_DIRECT 220 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 221 select HAVE_BUILDTIME_MCOUNT_SORT 222 select HAVE_EFFICIENT_UNALIGNED_ACCESS 223 select HAVE_GUP_FAST 224 select HAVE_FTRACE_GRAPH_FUNC 225 select HAVE_FTRACE_MCOUNT_RECORD 226 select HAVE_FUNCTION_TRACER 227 select HAVE_FUNCTION_ERROR_INJECTION 228 select HAVE_FUNCTION_GRAPH_FREGS 229 select HAVE_FUNCTION_GRAPH_TRACER 230 select HAVE_GCC_PLUGINS 231 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 232 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 233 select HAVE_HW_BREAKPOINT if PERF_EVENTS 234 select HAVE_IOREMAP_PROT 235 select HAVE_IRQ_TIME_ACCOUNTING 236 select HAVE_MOD_ARCH_SPECIFIC 237 select HAVE_NMI 238 select HAVE_PERF_EVENTS 239 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 240 select HAVE_PERF_REGS 241 select HAVE_PERF_USER_STACK_DUMP 242 select HAVE_PREEMPT_DYNAMIC_KEY 243 select HAVE_REGS_AND_STACK_ACCESS_API 244 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 245 select HAVE_FUNCTION_ARG_ACCESS_API 246 select MMU_GATHER_RCU_TABLE_FREE 247 select HAVE_RSEQ 248 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 249 select HAVE_STACKPROTECTOR 250 select HAVE_SYSCALL_TRACEPOINTS 251 select HAVE_KPROBES 252 select HAVE_KRETPROBES 253 select HAVE_GENERIC_VDSO 254 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 255 select HOTPLUG_SMT if HOTPLUG_CPU 256 select IRQ_DOMAIN 257 select IRQ_FORCED_THREADING 258 select KASAN_VMALLOC if KASAN 259 select LOCK_MM_AND_FIND_VMA 260 select MODULES_USE_ELF_RELA 261 select NEED_DMA_MAP_STATE 262 select NEED_SG_DMA_LENGTH 263 select OF 264 select OF_EARLY_FLATTREE 265 select PCI_DOMAINS_GENERIC if PCI 266 select PCI_ECAM if (ACPI && PCI) 267 select PCI_SYSCALL if PCI 268 select POWER_RESET 269 select POWER_SUPPLY 270 select SPARSE_IRQ 271 select SWIOTLB 272 select SYSCTL_EXCEPTION_TRACE 273 select THREAD_INFO_IN_TASK 274 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 275 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 276 select TRACE_IRQFLAGS_SUPPORT 277 select TRACE_IRQFLAGS_NMI_SUPPORT 278 select HAVE_SOFTIRQ_ON_OWN_STACK 279 select USER_STACKTRACE_SUPPORT 280 select VDSO_GETRANDOM 281 help 282 ARM 64-bit (AArch64) Linux support. 283 284config RUSTC_SUPPORTS_ARM64 285 def_bool y 286 depends on CPU_LITTLE_ENDIAN 287 # Shadow call stack is only supported on certain rustc versions. 288 # 289 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 290 # required due to use of the -Zfixed-x18 flag. 291 # 292 # Otherwise, rustc version 1.82+ is required due to use of the 293 # -Zsanitizer=shadow-call-stack flag. 294 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 295 296config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 297 def_bool CC_IS_CLANG 298 # https://github.com/ClangBuiltLinux/linux/issues/1507 299 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 300 301config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 302 def_bool CC_IS_GCC 303 depends on $(cc-option,-fpatchable-function-entry=2) 304 305config 64BIT 306 def_bool y 307 308config MMU 309 def_bool y 310 311config ARM64_CONT_PTE_SHIFT 312 int 313 default 5 if PAGE_SIZE_64KB 314 default 7 if PAGE_SIZE_16KB 315 default 4 316 317config ARM64_CONT_PMD_SHIFT 318 int 319 default 5 if PAGE_SIZE_64KB 320 default 5 if PAGE_SIZE_16KB 321 default 4 322 323config ARCH_MMAP_RND_BITS_MIN 324 default 14 if PAGE_SIZE_64KB 325 default 16 if PAGE_SIZE_16KB 326 default 18 327 328# max bits determined by the following formula: 329# VA_BITS - PTDESC_TABLE_SHIFT 330config ARCH_MMAP_RND_BITS_MAX 331 default 19 if ARM64_VA_BITS=36 332 default 24 if ARM64_VA_BITS=39 333 default 27 if ARM64_VA_BITS=42 334 default 30 if ARM64_VA_BITS=47 335 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 336 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 337 default 33 if ARM64_VA_BITS=48 338 default 14 if ARM64_64K_PAGES 339 default 16 if ARM64_16K_PAGES 340 default 18 341 342config ARCH_MMAP_RND_COMPAT_BITS_MIN 343 default 7 if ARM64_64K_PAGES 344 default 9 if ARM64_16K_PAGES 345 default 11 346 347config ARCH_MMAP_RND_COMPAT_BITS_MAX 348 default 16 349 350config NO_IOPORT_MAP 351 def_bool y if !PCI 352 353config STACKTRACE_SUPPORT 354 def_bool y 355 356config ILLEGAL_POINTER_VALUE 357 hex 358 default 0xdead000000000000 359 360config LOCKDEP_SUPPORT 361 def_bool y 362 363config GENERIC_BUG 364 def_bool y 365 depends on BUG 366 367config GENERIC_BUG_RELATIVE_POINTERS 368 def_bool y 369 depends on GENERIC_BUG 370 371config GENERIC_HWEIGHT 372 def_bool y 373 374config GENERIC_CSUM 375 def_bool y 376 377config GENERIC_CALIBRATE_DELAY 378 def_bool y 379 380config SMP 381 def_bool y 382 383config KERNEL_MODE_NEON 384 def_bool y 385 386config FIX_EARLYCON_MEM 387 def_bool y 388 389config PGTABLE_LEVELS 390 int 391 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 392 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 393 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 394 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 395 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 396 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 397 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 398 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 399 400config ARCH_SUPPORTS_UPROBES 401 def_bool y 402 403config ARCH_PROC_KCORE_TEXT 404 def_bool y 405 406config BROKEN_GAS_INST 407 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 408 409config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 410 bool 411 # Clang's __builtin_return_address() strips the PAC since 12.0.0 412 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 413 default y if CC_IS_CLANG 414 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 415 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 416 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 417 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 418 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 419 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 420 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 421 default n 422 423config KASAN_SHADOW_OFFSET 424 hex 425 depends on KASAN_GENERIC || KASAN_SW_TAGS 426 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 427 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 428 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 429 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 430 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 431 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 432 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 433 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 434 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 435 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 436 default 0xffffffffffffffff 437 438config UNWIND_TABLES 439 bool 440 441source "arch/arm64/Kconfig.platforms" 442 443menu "Kernel Features" 444 445menu "ARM errata workarounds via the alternatives framework" 446 447config AMPERE_ERRATUM_AC03_CPU_38 448 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 449 default y 450 help 451 This option adds an alternative code sequence to work around Ampere 452 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 453 454 The affected design reports FEAT_HAFDBS as not implemented in 455 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 456 as required by the architecture. The unadvertised HAFDBS 457 implementation suffers from an additional erratum where hardware 458 A/D updates can occur after a PTE has been marked invalid. 459 460 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 461 which avoids enabling unadvertised hardware Access Flag management 462 at stage-2. 463 464 If unsure, say Y. 465 466config ARM64_WORKAROUND_CLEAN_CACHE 467 bool 468 469config ARM64_ERRATUM_826319 470 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 471 default y 472 select ARM64_WORKAROUND_CLEAN_CACHE 473 help 474 This option adds an alternative code sequence to work around ARM 475 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 476 AXI master interface and an L2 cache. 477 478 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 479 and is unable to accept a certain write via this interface, it will 480 not progress on read data presented on the read data channel and the 481 system can deadlock. 482 483 The workaround promotes data cache clean instructions to 484 data cache clean-and-invalidate. 485 Please note that this does not necessarily enable the workaround, 486 as it depends on the alternative framework, which will only patch 487 the kernel if an affected CPU is detected. 488 489 If unsure, say Y. 490 491config ARM64_ERRATUM_827319 492 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 493 default y 494 select ARM64_WORKAROUND_CLEAN_CACHE 495 help 496 This option adds an alternative code sequence to work around ARM 497 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 498 master interface and an L2 cache. 499 500 Under certain conditions this erratum can cause a clean line eviction 501 to occur at the same time as another transaction to the same address 502 on the AMBA 5 CHI interface, which can cause data corruption if the 503 interconnect reorders the two transactions. 504 505 The workaround promotes data cache clean instructions to 506 data cache clean-and-invalidate. 507 Please note that this does not necessarily enable the workaround, 508 as it depends on the alternative framework, which will only patch 509 the kernel if an affected CPU is detected. 510 511 If unsure, say Y. 512 513config ARM64_ERRATUM_824069 514 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 515 default y 516 select ARM64_WORKAROUND_CLEAN_CACHE 517 help 518 This option adds an alternative code sequence to work around ARM 519 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 520 to a coherent interconnect. 521 522 If a Cortex-A53 processor is executing a store or prefetch for 523 write instruction at the same time as a processor in another 524 cluster is executing a cache maintenance operation to the same 525 address, then this erratum might cause a clean cache line to be 526 incorrectly marked as dirty. 527 528 The workaround promotes data cache clean instructions to 529 data cache clean-and-invalidate. 530 Please note that this option does not necessarily enable the 531 workaround, as it depends on the alternative framework, which will 532 only patch the kernel if an affected CPU is detected. 533 534 If unsure, say Y. 535 536config ARM64_ERRATUM_819472 537 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 538 default y 539 select ARM64_WORKAROUND_CLEAN_CACHE 540 help 541 This option adds an alternative code sequence to work around ARM 542 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 543 present when it is connected to a coherent interconnect. 544 545 If the processor is executing a load and store exclusive sequence at 546 the same time as a processor in another cluster is executing a cache 547 maintenance operation to the same address, then this erratum might 548 cause data corruption. 549 550 The workaround promotes data cache clean instructions to 551 data cache clean-and-invalidate. 552 Please note that this does not necessarily enable the workaround, 553 as it depends on the alternative framework, which will only patch 554 the kernel if an affected CPU is detected. 555 556 If unsure, say Y. 557 558config ARM64_ERRATUM_832075 559 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 560 default y 561 help 562 This option adds an alternative code sequence to work around ARM 563 erratum 832075 on Cortex-A57 parts up to r1p2. 564 565 Affected Cortex-A57 parts might deadlock when exclusive load/store 566 instructions to Write-Back memory are mixed with Device loads. 567 568 The workaround is to promote device loads to use Load-Acquire 569 semantics. 570 Please note that this does not necessarily enable the workaround, 571 as it depends on the alternative framework, which will only patch 572 the kernel if an affected CPU is detected. 573 574 If unsure, say Y. 575 576config ARM64_ERRATUM_834220 577 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 578 depends on KVM 579 help 580 This option adds an alternative code sequence to work around ARM 581 erratum 834220 on Cortex-A57 parts up to r1p2. 582 583 Affected Cortex-A57 parts might report a Stage 2 translation 584 fault as the result of a Stage 1 fault for load crossing a 585 page boundary when there is a permission or device memory 586 alignment fault at Stage 1 and a translation fault at Stage 2. 587 588 The workaround is to verify that the Stage 1 translation 589 doesn't generate a fault before handling the Stage 2 fault. 590 Please note that this does not necessarily enable the workaround, 591 as it depends on the alternative framework, which will only patch 592 the kernel if an affected CPU is detected. 593 594 If unsure, say N. 595 596config ARM64_ERRATUM_1742098 597 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 598 depends on COMPAT 599 default y 600 help 601 This option removes the AES hwcap for aarch32 user-space to 602 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 603 604 Affected parts may corrupt the AES state if an interrupt is 605 taken between a pair of AES instructions. These instructions 606 are only present if the cryptography extensions are present. 607 All software should have a fallback implementation for CPUs 608 that don't implement the cryptography extensions. 609 610 If unsure, say Y. 611 612config ARM64_ERRATUM_845719 613 bool "Cortex-A53: 845719: a load might read incorrect data" 614 depends on COMPAT 615 default y 616 help 617 This option adds an alternative code sequence to work around ARM 618 erratum 845719 on Cortex-A53 parts up to r0p4. 619 620 When running a compat (AArch32) userspace on an affected Cortex-A53 621 part, a load at EL0 from a virtual address that matches the bottom 32 622 bits of the virtual address used by a recent load at (AArch64) EL1 623 might return incorrect data. 624 625 The workaround is to write the contextidr_el1 register on exception 626 return to a 32-bit task. 627 Please note that this does not necessarily enable the workaround, 628 as it depends on the alternative framework, which will only patch 629 the kernel if an affected CPU is detected. 630 631 If unsure, say Y. 632 633config ARM64_ERRATUM_843419 634 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 635 default y 636 help 637 This option links the kernel with '--fix-cortex-a53-843419' and 638 enables PLT support to replace certain ADRP instructions, which can 639 cause subsequent memory accesses to use an incorrect address on 640 Cortex-A53 parts up to r0p4. 641 642 If unsure, say Y. 643 644config ARM64_LD_HAS_FIX_ERRATUM_843419 645 def_bool $(ld-option,--fix-cortex-a53-843419) 646 647config ARM64_ERRATUM_1024718 648 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 649 default y 650 help 651 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 652 653 Affected Cortex-A55 cores (all revisions) could cause incorrect 654 update of the hardware dirty bit when the DBM/AP bits are updated 655 without a break-before-make. The workaround is to disable the usage 656 of hardware DBM locally on the affected cores. CPUs not affected by 657 this erratum will continue to use the feature. 658 659 If unsure, say Y. 660 661config ARM64_ERRATUM_1418040 662 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 663 default y 664 depends on COMPAT 665 help 666 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 667 errata 1188873 and 1418040. 668 669 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 670 cause register corruption when accessing the timer registers 671 from AArch32 userspace. 672 673 If unsure, say Y. 674 675config ARM64_WORKAROUND_SPECULATIVE_AT 676 bool 677 678config ARM64_ERRATUM_1165522 679 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 680 default y 681 select ARM64_WORKAROUND_SPECULATIVE_AT 682 help 683 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 684 685 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 686 corrupted TLBs by speculating an AT instruction during a guest 687 context switch. 688 689 If unsure, say Y. 690 691config ARM64_ERRATUM_1319367 692 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 693 default y 694 select ARM64_WORKAROUND_SPECULATIVE_AT 695 help 696 This option adds work arounds for ARM Cortex-A57 erratum 1319537 697 and A72 erratum 1319367 698 699 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 700 speculating an AT instruction during a guest context switch. 701 702 If unsure, say Y. 703 704config ARM64_ERRATUM_1530923 705 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 706 default y 707 select ARM64_WORKAROUND_SPECULATIVE_AT 708 help 709 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 710 711 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 712 corrupted TLBs by speculating an AT instruction during a guest 713 context switch. 714 715 If unsure, say Y. 716 717config ARM64_WORKAROUND_REPEAT_TLBI 718 bool 719 720config ARM64_ERRATUM_2441007 721 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 722 select ARM64_WORKAROUND_REPEAT_TLBI 723 help 724 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 725 726 Under very rare circumstances, affected Cortex-A55 CPUs 727 may not handle a race between a break-before-make sequence on one 728 CPU, and another CPU accessing the same page. This could allow a 729 store to a page that has been unmapped. 730 731 Work around this by adding the affected CPUs to the list that needs 732 TLB sequences to be done twice. 733 734 If unsure, say N. 735 736config ARM64_ERRATUM_1286807 737 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 738 select ARM64_WORKAROUND_REPEAT_TLBI 739 help 740 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 741 742 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 743 address for a cacheable mapping of a location is being 744 accessed by a core while another core is remapping the virtual 745 address to a new physical page using the recommended 746 break-before-make sequence, then under very rare circumstances 747 TLBI+DSB completes before a read using the translation being 748 invalidated has been observed by other observers. The 749 workaround repeats the TLBI+DSB operation. 750 751 If unsure, say N. 752 753config ARM64_ERRATUM_1463225 754 bool "Cortex-A76: Software Step might prevent interrupt recognition" 755 default y 756 help 757 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 758 759 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 760 of a system call instruction (SVC) can prevent recognition of 761 subsequent interrupts when software stepping is disabled in the 762 exception handler of the system call and either kernel debugging 763 is enabled or VHE is in use. 764 765 Work around the erratum by triggering a dummy step exception 766 when handling a system call from a task that is being stepped 767 in a VHE configuration of the kernel. 768 769 If unsure, say Y. 770 771config ARM64_ERRATUM_1542419 772 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 773 help 774 This option adds a workaround for ARM Neoverse-N1 erratum 775 1542419. 776 777 Affected Neoverse-N1 cores could execute a stale instruction when 778 modified by another CPU. The workaround depends on a firmware 779 counterpart. 780 781 Workaround the issue by hiding the DIC feature from EL0. This 782 forces user-space to perform cache maintenance. 783 784 If unsure, say N. 785 786config ARM64_ERRATUM_1508412 787 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 788 default y 789 help 790 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 791 792 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 793 of a store-exclusive or read of PAR_EL1 and a load with device or 794 non-cacheable memory attributes. The workaround depends on a firmware 795 counterpart. 796 797 KVM guests must also have the workaround implemented or they can 798 deadlock the system. 799 800 Work around the issue by inserting DMB SY barriers around PAR_EL1 801 register reads and warning KVM users. The DMB barrier is sufficient 802 to prevent a speculative PAR_EL1 read. 803 804 If unsure, say Y. 805 806config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 807 bool 808 809config ARM64_ERRATUM_2051678 810 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 811 default y 812 help 813 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 814 Affected Cortex-A510 might not respect the ordering rules for 815 hardware update of the page table's dirty bit. The workaround 816 is to not enable the feature on affected CPUs. 817 818 If unsure, say Y. 819 820config ARM64_ERRATUM_2077057 821 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 822 default y 823 help 824 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 825 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 826 expected, but a Pointer Authentication trap is taken instead. The 827 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 828 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 829 830 This can only happen when EL2 is stepping EL1. 831 832 When these conditions occur, the SPSR_EL2 value is unchanged from the 833 previous guest entry, and can be restored from the in-memory copy. 834 835 If unsure, say Y. 836 837config ARM64_ERRATUM_2658417 838 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 839 default y 840 help 841 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 842 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 843 BFMMLA or VMMLA instructions in rare circumstances when a pair of 844 A510 CPUs are using shared neon hardware. As the sharing is not 845 discoverable by the kernel, hide the BF16 HWCAP to indicate that 846 user-space should not be using these instructions. 847 848 If unsure, say Y. 849 850config ARM64_ERRATUM_2119858 851 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 852 default y 853 depends on CORESIGHT_TRBE 854 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 855 help 856 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 857 858 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 859 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 860 the event of a WRAP event. 861 862 Work around the issue by always making sure we move the TRBPTR_EL1 by 863 256 bytes before enabling the buffer and filling the first 256 bytes of 864 the buffer with ETM ignore packets upon disabling. 865 866 If unsure, say Y. 867 868config ARM64_ERRATUM_2139208 869 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 870 default y 871 depends on CORESIGHT_TRBE 872 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 873 help 874 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 875 876 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 877 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 878 the event of a WRAP event. 879 880 Work around the issue by always making sure we move the TRBPTR_EL1 by 881 256 bytes before enabling the buffer and filling the first 256 bytes of 882 the buffer with ETM ignore packets upon disabling. 883 884 If unsure, say Y. 885 886config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 887 bool 888 889config ARM64_ERRATUM_2054223 890 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 891 default y 892 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 893 help 894 Enable workaround for ARM Cortex-A710 erratum 2054223 895 896 Affected cores may fail to flush the trace data on a TSB instruction, when 897 the PE is in trace prohibited state. This will cause losing a few bytes 898 of the trace cached. 899 900 Workaround is to issue two TSB consecutively on affected cores. 901 902 If unsure, say Y. 903 904config ARM64_ERRATUM_2067961 905 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 906 default y 907 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 908 help 909 Enable workaround for ARM Neoverse-N2 erratum 2067961 910 911 Affected cores may fail to flush the trace data on a TSB instruction, when 912 the PE is in trace prohibited state. This will cause losing a few bytes 913 of the trace cached. 914 915 Workaround is to issue two TSB consecutively on affected cores. 916 917 If unsure, say Y. 918 919config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 920 bool 921 922config ARM64_ERRATUM_2253138 923 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 924 depends on CORESIGHT_TRBE 925 default y 926 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 927 help 928 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 929 930 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 931 for TRBE. Under some conditions, the TRBE might generate a write to the next 932 virtually addressed page following the last page of the TRBE address space 933 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 934 935 Work around this in the driver by always making sure that there is a 936 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 937 938 If unsure, say Y. 939 940config ARM64_ERRATUM_2224489 941 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 942 depends on CORESIGHT_TRBE 943 default y 944 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 945 help 946 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 947 948 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 949 for TRBE. Under some conditions, the TRBE might generate a write to the next 950 virtually addressed page following the last page of the TRBE address space 951 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 952 953 Work around this in the driver by always making sure that there is a 954 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 955 956 If unsure, say Y. 957 958config ARM64_ERRATUM_2441009 959 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 960 select ARM64_WORKAROUND_REPEAT_TLBI 961 help 962 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 963 964 Under very rare circumstances, affected Cortex-A510 CPUs 965 may not handle a race between a break-before-make sequence on one 966 CPU, and another CPU accessing the same page. This could allow a 967 store to a page that has been unmapped. 968 969 Work around this by adding the affected CPUs to the list that needs 970 TLB sequences to be done twice. 971 972 If unsure, say N. 973 974config ARM64_ERRATUM_2064142 975 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 976 depends on CORESIGHT_TRBE 977 default y 978 help 979 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 980 981 Affected Cortex-A510 core might fail to write into system registers after the 982 TRBE has been disabled. Under some conditions after the TRBE has been disabled 983 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 984 and TRBTRG_EL1 will be ignored and will not be effected. 985 986 Work around this in the driver by executing TSB CSYNC and DSB after collection 987 is stopped and before performing a system register write to one of the affected 988 registers. 989 990 If unsure, say Y. 991 992config ARM64_ERRATUM_2038923 993 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 994 depends on CORESIGHT_TRBE 995 default y 996 help 997 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 998 999 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 1000 prohibited within the CPU. As a result, the trace buffer or trace buffer state 1001 might be corrupted. This happens after TRBE buffer has been enabled by setting 1002 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 1003 execution changes from a context, in which trace is prohibited to one where it 1004 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1005 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1006 the trace buffer state might be corrupted. 1007 1008 Work around this in the driver by preventing an inconsistent view of whether the 1009 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1010 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1011 two ISB instructions if no ERET is to take place. 1012 1013 If unsure, say Y. 1014 1015config ARM64_ERRATUM_1902691 1016 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1017 depends on CORESIGHT_TRBE 1018 default y 1019 help 1020 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1021 1022 Affected Cortex-A510 core might cause trace data corruption, when being written 1023 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1024 trace data. 1025 1026 Work around this problem in the driver by just preventing TRBE initialization on 1027 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1028 on such implementations. This will cover the kernel for any firmware that doesn't 1029 do this already. 1030 1031 If unsure, say Y. 1032 1033config ARM64_ERRATUM_2457168 1034 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1035 depends on ARM64_AMU_EXTN 1036 default y 1037 help 1038 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1039 1040 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1041 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1042 incorrectly giving a significantly higher output value. 1043 1044 Work around this problem by returning 0 when reading the affected counter in 1045 key locations that results in disabling all users of this counter. This effect 1046 is the same to firmware disabling affected counters. 1047 1048 If unsure, say Y. 1049 1050config ARM64_ERRATUM_2645198 1051 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1052 default y 1053 help 1054 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1055 1056 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1057 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1058 next instruction abort caused by permission fault. 1059 1060 Only user-space does executable to non-executable permission transition via 1061 mprotect() system call. Workaround the problem by doing a break-before-make 1062 TLB invalidation, for all changes to executable user space mappings. 1063 1064 If unsure, say Y. 1065 1066config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1067 bool 1068 1069config ARM64_ERRATUM_2966298 1070 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1071 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1072 default y 1073 help 1074 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1075 1076 On an affected Cortex-A520 core, a speculatively executed unprivileged 1077 load might leak data from a privileged level via a cache side channel. 1078 1079 Work around this problem by executing a TLBI before returning to EL0. 1080 1081 If unsure, say Y. 1082 1083config ARM64_ERRATUM_3117295 1084 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1085 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1086 default y 1087 help 1088 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1089 1090 On an affected Cortex-A510 core, a speculatively executed unprivileged 1091 load might leak data from a privileged level via a cache side channel. 1092 1093 Work around this problem by executing a TLBI before returning to EL0. 1094 1095 If unsure, say Y. 1096 1097config ARM64_ERRATUM_3194386 1098 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1099 default y 1100 help 1101 This option adds the workaround for the following errata: 1102 1103 * ARM Cortex-A76 erratum 3324349 1104 * ARM Cortex-A77 erratum 3324348 1105 * ARM Cortex-A78 erratum 3324344 1106 * ARM Cortex-A78C erratum 3324346 1107 * ARM Cortex-A78C erratum 3324347 1108 * ARM Cortex-A710 erratam 3324338 1109 * ARM Cortex-A715 errartum 3456084 1110 * ARM Cortex-A720 erratum 3456091 1111 * ARM Cortex-A725 erratum 3456106 1112 * ARM Cortex-X1 erratum 3324344 1113 * ARM Cortex-X1C erratum 3324346 1114 * ARM Cortex-X2 erratum 3324338 1115 * ARM Cortex-X3 erratum 3324335 1116 * ARM Cortex-X4 erratum 3194386 1117 * ARM Cortex-X925 erratum 3324334 1118 * ARM Neoverse-N1 erratum 3324349 1119 * ARM Neoverse N2 erratum 3324339 1120 * ARM Neoverse-N3 erratum 3456111 1121 * ARM Neoverse-V1 erratum 3324341 1122 * ARM Neoverse V2 erratum 3324336 1123 * ARM Neoverse-V3 erratum 3312417 1124 1125 On affected cores "MSR SSBS, #0" instructions may not affect 1126 subsequent speculative instructions, which may permit unexepected 1127 speculative store bypassing. 1128 1129 Work around this problem by placing a Speculation Barrier (SB) or 1130 Instruction Synchronization Barrier (ISB) after kernel changes to 1131 SSBS. The presence of the SSBS special-purpose register is hidden 1132 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1133 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1134 1135 If unsure, say Y. 1136 1137config CAVIUM_ERRATUM_22375 1138 bool "Cavium erratum 22375, 24313" 1139 default y 1140 help 1141 Enable workaround for errata 22375 and 24313. 1142 1143 This implements two gicv3-its errata workarounds for ThunderX. Both 1144 with a small impact affecting only ITS table allocation. 1145 1146 erratum 22375: only alloc 8MB table size 1147 erratum 24313: ignore memory access type 1148 1149 The fixes are in ITS initialization and basically ignore memory access 1150 type and table size provided by the TYPER and BASER registers. 1151 1152 If unsure, say Y. 1153 1154config CAVIUM_ERRATUM_23144 1155 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1156 depends on NUMA 1157 default y 1158 help 1159 ITS SYNC command hang for cross node io and collections/cpu mapping. 1160 1161 If unsure, say Y. 1162 1163config CAVIUM_ERRATUM_23154 1164 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1165 default y 1166 help 1167 The ThunderX GICv3 implementation requires a modified version for 1168 reading the IAR status to ensure data synchronization 1169 (access to icc_iar1_el1 is not sync'ed before and after). 1170 1171 It also suffers from erratum 38545 (also present on Marvell's 1172 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1173 spuriously presented to the CPU interface. 1174 1175 If unsure, say Y. 1176 1177config CAVIUM_ERRATUM_27456 1178 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1179 default y 1180 help 1181 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1182 instructions may cause the icache to become corrupted if it 1183 contains data for a non-current ASID. The fix is to 1184 invalidate the icache when changing the mm context. 1185 1186 If unsure, say Y. 1187 1188config CAVIUM_ERRATUM_30115 1189 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1190 default y 1191 help 1192 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1193 1.2, and T83 Pass 1.0, KVM guest execution may disable 1194 interrupts in host. Trapping both GICv3 group-0 and group-1 1195 accesses sidesteps the issue. 1196 1197 If unsure, say Y. 1198 1199config CAVIUM_TX2_ERRATUM_219 1200 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1201 default y 1202 help 1203 On Cavium ThunderX2, a load, store or prefetch instruction between a 1204 TTBR update and the corresponding context synchronizing operation can 1205 cause a spurious Data Abort to be delivered to any hardware thread in 1206 the CPU core. 1207 1208 Work around the issue by avoiding the problematic code sequence and 1209 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1210 trap handler performs the corresponding register access, skips the 1211 instruction and ensures context synchronization by virtue of the 1212 exception return. 1213 1214 If unsure, say Y. 1215 1216config FUJITSU_ERRATUM_010001 1217 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1218 default y 1219 help 1220 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1221 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1222 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1223 This fault occurs under a specific hardware condition when a 1224 load/store instruction performs an address translation using: 1225 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1226 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1227 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1228 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1229 1230 The workaround is to ensure these bits are clear in TCR_ELx. 1231 The workaround only affects the Fujitsu-A64FX. 1232 1233 If unsure, say Y. 1234 1235config HISILICON_ERRATUM_161600802 1236 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1237 default y 1238 help 1239 The HiSilicon Hip07 SoC uses the wrong redistributor base 1240 when issued ITS commands such as VMOVP and VMAPP, and requires 1241 a 128kB offset to be applied to the target address in this commands. 1242 1243 If unsure, say Y. 1244 1245config HISILICON_ERRATUM_162100801 1246 bool "Hip09 162100801 erratum support" 1247 default y 1248 help 1249 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1250 during unmapping operation, which will cause some vSGIs lost. 1251 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1252 after VMOVP. 1253 1254 If unsure, say Y. 1255 1256config QCOM_FALKOR_ERRATUM_1003 1257 bool "Falkor E1003: Incorrect translation due to ASID change" 1258 default y 1259 help 1260 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1261 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1262 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1263 then only for entries in the walk cache, since the leaf translation 1264 is unchanged. Work around the erratum by invalidating the walk cache 1265 entries for the trampoline before entering the kernel proper. 1266 1267config QCOM_FALKOR_ERRATUM_1009 1268 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1269 default y 1270 select ARM64_WORKAROUND_REPEAT_TLBI 1271 help 1272 On Falkor v1, the CPU may prematurely complete a DSB following a 1273 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1274 one more time to fix the issue. 1275 1276 If unsure, say Y. 1277 1278config QCOM_QDF2400_ERRATUM_0065 1279 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1280 default y 1281 help 1282 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1283 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1284 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1285 1286 If unsure, say Y. 1287 1288config QCOM_FALKOR_ERRATUM_E1041 1289 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1290 default y 1291 help 1292 Falkor CPU may speculatively fetch instructions from an improper 1293 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1294 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1295 1296 If unsure, say Y. 1297 1298config NVIDIA_CARMEL_CNP_ERRATUM 1299 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1300 default y 1301 help 1302 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1303 invalidate shared TLB entries installed by a different core, as it would 1304 on standard ARM cores. 1305 1306 If unsure, say Y. 1307 1308config ROCKCHIP_ERRATUM_3568002 1309 bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" 1310 default y 1311 help 1312 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI 1313 addressing limited to the first 32bit of physical address space. 1314 1315 If unsure, say Y. 1316 1317config ROCKCHIP_ERRATUM_3588001 1318 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1319 default y 1320 help 1321 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1322 This means, that its sharability feature may not be used, even though it 1323 is supported by the IP itself. 1324 1325 If unsure, say Y. 1326 1327config SOCIONEXT_SYNQUACER_PREITS 1328 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1329 default y 1330 help 1331 Socionext Synquacer SoCs implement a separate h/w block to generate 1332 MSI doorbell writes with non-zero values for the device ID. 1333 1334 If unsure, say Y. 1335 1336endmenu # "ARM errata workarounds via the alternatives framework" 1337 1338choice 1339 prompt "Page size" 1340 default ARM64_4K_PAGES 1341 help 1342 Page size (translation granule) configuration. 1343 1344config ARM64_4K_PAGES 1345 bool "4KB" 1346 select HAVE_PAGE_SIZE_4KB 1347 help 1348 This feature enables 4KB pages support. 1349 1350config ARM64_16K_PAGES 1351 bool "16KB" 1352 select HAVE_PAGE_SIZE_16KB 1353 help 1354 The system will use 16KB pages support. AArch32 emulation 1355 requires applications compiled with 16K (or a multiple of 16K) 1356 aligned segments. 1357 1358config ARM64_64K_PAGES 1359 bool "64KB" 1360 select HAVE_PAGE_SIZE_64KB 1361 help 1362 This feature enables 64KB pages support (4KB by default) 1363 allowing only two levels of page tables and faster TLB 1364 look-up. AArch32 emulation requires applications compiled 1365 with 64K aligned segments. 1366 1367endchoice 1368 1369choice 1370 prompt "Virtual address space size" 1371 default ARM64_VA_BITS_52 1372 help 1373 Allows choosing one of multiple possible virtual address 1374 space sizes. The level of translation table is determined by 1375 a combination of page size and virtual address space size. 1376 1377config ARM64_VA_BITS_36 1378 bool "36-bit" if EXPERT 1379 depends on PAGE_SIZE_16KB 1380 1381config ARM64_VA_BITS_39 1382 bool "39-bit" 1383 depends on PAGE_SIZE_4KB 1384 1385config ARM64_VA_BITS_42 1386 bool "42-bit" 1387 depends on PAGE_SIZE_64KB 1388 1389config ARM64_VA_BITS_47 1390 bool "47-bit" 1391 depends on PAGE_SIZE_16KB 1392 1393config ARM64_VA_BITS_48 1394 bool "48-bit" 1395 1396config ARM64_VA_BITS_52 1397 bool "52-bit" 1398 help 1399 Enable 52-bit virtual addressing for userspace when explicitly 1400 requested via a hint to mmap(). The kernel will also use 52-bit 1401 virtual addresses for its own mappings (provided HW support for 1402 this feature is available, otherwise it reverts to 48-bit). 1403 1404 NOTE: Enabling 52-bit virtual addressing in conjunction with 1405 ARMv8.3 Pointer Authentication will result in the PAC being 1406 reduced from 7 bits to 3 bits, which may have a significant 1407 impact on its susceptibility to brute-force attacks. 1408 1409 If unsure, select 48-bit virtual addressing instead. 1410 1411endchoice 1412 1413config ARM64_FORCE_52BIT 1414 bool "Force 52-bit virtual addresses for userspace" 1415 depends on ARM64_VA_BITS_52 && EXPERT 1416 help 1417 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1418 to maintain compatibility with older software by providing 48-bit VAs 1419 unless a hint is supplied to mmap. 1420 1421 This configuration option disables the 48-bit compatibility logic, and 1422 forces all userspace addresses to be 52-bit on HW that supports it. One 1423 should only enable this configuration option for stress testing userspace 1424 memory management code. If unsure say N here. 1425 1426config ARM64_VA_BITS 1427 int 1428 default 36 if ARM64_VA_BITS_36 1429 default 39 if ARM64_VA_BITS_39 1430 default 42 if ARM64_VA_BITS_42 1431 default 47 if ARM64_VA_BITS_47 1432 default 48 if ARM64_VA_BITS_48 1433 default 52 if ARM64_VA_BITS_52 1434 1435choice 1436 prompt "Physical address space size" 1437 default ARM64_PA_BITS_48 1438 help 1439 Choose the maximum physical address range that the kernel will 1440 support. 1441 1442config ARM64_PA_BITS_48 1443 bool "48-bit" 1444 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1445 1446config ARM64_PA_BITS_52 1447 bool "52-bit" 1448 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1449 help 1450 Enable support for a 52-bit physical address space, introduced as 1451 part of the ARMv8.2-LPA extension. 1452 1453 With this enabled, the kernel will also continue to work on CPUs that 1454 do not support ARMv8.2-LPA, but with some added memory overhead (and 1455 minor performance overhead). 1456 1457endchoice 1458 1459config ARM64_PA_BITS 1460 int 1461 default 48 if ARM64_PA_BITS_48 1462 default 52 if ARM64_PA_BITS_52 1463 1464config ARM64_LPA2 1465 def_bool y 1466 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1467 1468choice 1469 prompt "Endianness" 1470 default CPU_LITTLE_ENDIAN 1471 help 1472 Select the endianness of data accesses performed by the CPU. Userspace 1473 applications will need to be compiled and linked for the endianness 1474 that is selected here. 1475 1476config CPU_BIG_ENDIAN 1477 bool "Build big-endian kernel" 1478 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1479 depends on AS_IS_GNU || AS_VERSION >= 150000 1480 help 1481 Say Y if you plan on running a kernel with a big-endian userspace. 1482 1483config CPU_LITTLE_ENDIAN 1484 bool "Build little-endian kernel" 1485 help 1486 Say Y if you plan on running a kernel with a little-endian userspace. 1487 This is usually the case for distributions targeting arm64. 1488 1489endchoice 1490 1491config SCHED_MC 1492 bool "Multi-core scheduler support" 1493 help 1494 Multi-core scheduler support improves the CPU scheduler's decision 1495 making when dealing with multi-core CPU chips at a cost of slightly 1496 increased overhead in some places. If unsure say N here. 1497 1498config SCHED_CLUSTER 1499 bool "Cluster scheduler support" 1500 help 1501 Cluster scheduler support improves the CPU scheduler's decision 1502 making when dealing with machines that have clusters of CPUs. 1503 Cluster usually means a couple of CPUs which are placed closely 1504 by sharing mid-level caches, last-level cache tags or internal 1505 busses. 1506 1507config SCHED_SMT 1508 bool "SMT scheduler support" 1509 help 1510 Improves the CPU scheduler's decision making when dealing with 1511 MultiThreading at a cost of slightly increased overhead in some 1512 places. If unsure say N here. 1513 1514config NR_CPUS 1515 int "Maximum number of CPUs (2-4096)" 1516 range 2 4096 1517 default "512" 1518 1519config HOTPLUG_CPU 1520 bool "Support for hot-pluggable CPUs" 1521 select GENERIC_IRQ_MIGRATION 1522 help 1523 Say Y here to experiment with turning CPUs off and on. CPUs 1524 can be controlled through /sys/devices/system/cpu. 1525 1526# Common NUMA Features 1527config NUMA 1528 bool "NUMA Memory Allocation and Scheduler Support" 1529 select GENERIC_ARCH_NUMA 1530 select OF_NUMA 1531 select HAVE_SETUP_PER_CPU_AREA 1532 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1533 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1534 select USE_PERCPU_NUMA_NODE_ID 1535 help 1536 Enable NUMA (Non-Uniform Memory Access) support. 1537 1538 The kernel will try to allocate memory used by a CPU on the 1539 local memory of the CPU and add some more 1540 NUMA awareness to the kernel. 1541 1542config NODES_SHIFT 1543 int "Maximum NUMA Nodes (as a power of 2)" 1544 range 1 10 1545 default "4" 1546 depends on NUMA 1547 help 1548 Specify the maximum number of NUMA Nodes available on the target 1549 system. Increases memory reserved to accommodate various tables. 1550 1551source "kernel/Kconfig.hz" 1552 1553config ARCH_SPARSEMEM_ENABLE 1554 def_bool y 1555 select SPARSEMEM_VMEMMAP_ENABLE 1556 select SPARSEMEM_VMEMMAP 1557 1558config HW_PERF_EVENTS 1559 def_bool y 1560 depends on ARM_PMU 1561 1562# Supported by clang >= 7.0 or GCC >= 12.0.0 1563config CC_HAVE_SHADOW_CALL_STACK 1564 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1565 1566config PARAVIRT 1567 bool "Enable paravirtualization code" 1568 help 1569 This changes the kernel so it can modify itself when it is run 1570 under a hypervisor, potentially improving performance significantly 1571 over full virtualization. 1572 1573config PARAVIRT_TIME_ACCOUNTING 1574 bool "Paravirtual steal time accounting" 1575 select PARAVIRT 1576 help 1577 Select this option to enable fine granularity task steal time 1578 accounting. Time spent executing other tasks in parallel with 1579 the current vCPU is discounted from the vCPU power. To account for 1580 that, there can be a small performance impact. 1581 1582 If in doubt, say N here. 1583 1584config ARCH_SUPPORTS_KEXEC 1585 def_bool PM_SLEEP_SMP 1586 1587config ARCH_SUPPORTS_KEXEC_FILE 1588 def_bool y 1589 1590config ARCH_SELECTS_KEXEC_FILE 1591 def_bool y 1592 depends on KEXEC_FILE 1593 select HAVE_IMA_KEXEC if IMA 1594 1595config ARCH_SUPPORTS_KEXEC_SIG 1596 def_bool y 1597 1598config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1599 def_bool y 1600 1601config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1602 def_bool y 1603 1604config ARCH_SUPPORTS_CRASH_DUMP 1605 def_bool y 1606 1607config ARCH_DEFAULT_CRASH_DUMP 1608 def_bool y 1609 1610config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1611 def_bool CRASH_RESERVE 1612 1613config TRANS_TABLE 1614 def_bool y 1615 depends on HIBERNATION || KEXEC_CORE 1616 1617config XEN_DOM0 1618 def_bool y 1619 depends on XEN 1620 1621config XEN 1622 bool "Xen guest support on ARM64" 1623 depends on ARM64 && OF 1624 select SWIOTLB_XEN 1625 select PARAVIRT 1626 help 1627 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1628 1629# include/linux/mmzone.h requires the following to be true: 1630# 1631# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1632# 1633# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1634# 1635# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1636# ----+-------------------+--------------+----------------------+-------------------------+ 1637# 4K | 27 | 12 | 15 | 10 | 1638# 16K | 27 | 14 | 13 | 11 | 1639# 64K | 29 | 16 | 13 | 13 | 1640config ARCH_FORCE_MAX_ORDER 1641 int 1642 default "13" if ARM64_64K_PAGES 1643 default "11" if ARM64_16K_PAGES 1644 default "10" 1645 help 1646 The kernel page allocator limits the size of maximal physically 1647 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1648 defines the maximal power of two of number of pages that can be 1649 allocated as a single contiguous block. This option allows 1650 overriding the default setting when ability to allocate very 1651 large blocks of physically contiguous memory is required. 1652 1653 The maximal size of allocation cannot exceed the size of the 1654 section, so the value of MAX_PAGE_ORDER should satisfy 1655 1656 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1657 1658 Don't change if unsure. 1659 1660config UNMAP_KERNEL_AT_EL0 1661 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1662 default y 1663 help 1664 Speculation attacks against some high-performance processors can 1665 be used to bypass MMU permission checks and leak kernel data to 1666 userspace. This can be defended against by unmapping the kernel 1667 when running in userspace, mapping it back in on exception entry 1668 via a trampoline page in the vector table. 1669 1670 If unsure, say Y. 1671 1672config MITIGATE_SPECTRE_BRANCH_HISTORY 1673 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1674 default y 1675 help 1676 Speculation attacks against some high-performance processors can 1677 make use of branch history to influence future speculation. 1678 When taking an exception from user-space, a sequence of branches 1679 or a firmware call overwrites the branch history. 1680 1681config RODATA_FULL_DEFAULT_ENABLED 1682 bool "Apply r/o permissions of VM areas also to their linear aliases" 1683 default y 1684 help 1685 Apply read-only attributes of VM areas to the linear alias of 1686 the backing pages as well. This prevents code or read-only data 1687 from being modified (inadvertently or intentionally) via another 1688 mapping of the same memory page. This additional enhancement can 1689 be turned off at runtime by passing rodata=[off|on] (and turned on 1690 with rodata=full if this option is set to 'n') 1691 1692 This requires the linear region to be mapped down to pages, 1693 which may adversely affect performance in some cases. 1694 1695config ARM64_SW_TTBR0_PAN 1696 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1697 depends on !KCSAN 1698 select ARM64_PAN 1699 help 1700 Enabling this option prevents the kernel from accessing 1701 user-space memory directly by pointing TTBR0_EL1 to a reserved 1702 zeroed area and reserved ASID. The user access routines 1703 restore the valid TTBR0_EL1 temporarily. 1704 1705config ARM64_TAGGED_ADDR_ABI 1706 bool "Enable the tagged user addresses syscall ABI" 1707 default y 1708 help 1709 When this option is enabled, user applications can opt in to a 1710 relaxed ABI via prctl() allowing tagged addresses to be passed 1711 to system calls as pointer arguments. For details, see 1712 Documentation/arch/arm64/tagged-address-abi.rst. 1713 1714menuconfig COMPAT 1715 bool "Kernel support for 32-bit EL0" 1716 depends on ARM64_4K_PAGES || EXPERT 1717 select HAVE_UID16 1718 select OLD_SIGSUSPEND3 1719 select COMPAT_OLD_SIGACTION 1720 help 1721 This option enables support for a 32-bit EL0 running under a 64-bit 1722 kernel at EL1. AArch32-specific components such as system calls, 1723 the user helper functions, VFP support and the ptrace interface are 1724 handled appropriately by the kernel. 1725 1726 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1727 that you will only be able to execute AArch32 binaries that were compiled 1728 with page size aligned segments. 1729 1730 If you want to execute 32-bit userspace applications, say Y. 1731 1732if COMPAT 1733 1734config KUSER_HELPERS 1735 bool "Enable kuser helpers page for 32-bit applications" 1736 default y 1737 help 1738 Warning: disabling this option may break 32-bit user programs. 1739 1740 Provide kuser helpers to compat tasks. The kernel provides 1741 helper code to userspace in read only form at a fixed location 1742 to allow userspace to be independent of the CPU type fitted to 1743 the system. This permits binaries to be run on ARMv4 through 1744 to ARMv8 without modification. 1745 1746 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1747 1748 However, the fixed address nature of these helpers can be used 1749 by ROP (return orientated programming) authors when creating 1750 exploits. 1751 1752 If all of the binaries and libraries which run on your platform 1753 are built specifically for your platform, and make no use of 1754 these helpers, then you can turn this option off to hinder 1755 such exploits. However, in that case, if a binary or library 1756 relying on those helpers is run, it will not function correctly. 1757 1758 Say N here only if you are absolutely certain that you do not 1759 need these helpers; otherwise, the safe option is to say Y. 1760 1761config COMPAT_VDSO 1762 bool "Enable vDSO for 32-bit applications" 1763 depends on !CPU_BIG_ENDIAN 1764 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1765 select GENERIC_COMPAT_VDSO 1766 default y 1767 help 1768 Place in the process address space of 32-bit applications an 1769 ELF shared object providing fast implementations of gettimeofday 1770 and clock_gettime. 1771 1772 You must have a 32-bit build of glibc 2.22 or later for programs 1773 to seamlessly take advantage of this. 1774 1775config THUMB2_COMPAT_VDSO 1776 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1777 depends on COMPAT_VDSO 1778 default y 1779 help 1780 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1781 otherwise with '-marm'. 1782 1783config COMPAT_ALIGNMENT_FIXUPS 1784 bool "Fix up misaligned multi-word loads and stores in user space" 1785 1786menuconfig ARMV8_DEPRECATED 1787 bool "Emulate deprecated/obsolete ARMv8 instructions" 1788 depends on SYSCTL 1789 help 1790 Legacy software support may require certain instructions 1791 that have been deprecated or obsoleted in the architecture. 1792 1793 Enable this config to enable selective emulation of these 1794 features. 1795 1796 If unsure, say Y 1797 1798if ARMV8_DEPRECATED 1799 1800config SWP_EMULATION 1801 bool "Emulate SWP/SWPB instructions" 1802 help 1803 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1804 they are always undefined. Say Y here to enable software 1805 emulation of these instructions for userspace using LDXR/STXR. 1806 This feature can be controlled at runtime with the abi.swp 1807 sysctl which is disabled by default. 1808 1809 In some older versions of glibc [<=2.8] SWP is used during futex 1810 trylock() operations with the assumption that the code will not 1811 be preempted. This invalid assumption may be more likely to fail 1812 with SWP emulation enabled, leading to deadlock of the user 1813 application. 1814 1815 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1816 on an external transaction monitoring block called a global 1817 monitor to maintain update atomicity. If your system does not 1818 implement a global monitor, this option can cause programs that 1819 perform SWP operations to uncached memory to deadlock. 1820 1821 If unsure, say Y 1822 1823config CP15_BARRIER_EMULATION 1824 bool "Emulate CP15 Barrier instructions" 1825 help 1826 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1827 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1828 strongly recommended to use the ISB, DSB, and DMB 1829 instructions instead. 1830 1831 Say Y here to enable software emulation of these 1832 instructions for AArch32 userspace code. When this option is 1833 enabled, CP15 barrier usage is traced which can help 1834 identify software that needs updating. This feature can be 1835 controlled at runtime with the abi.cp15_barrier sysctl. 1836 1837 If unsure, say Y 1838 1839config SETEND_EMULATION 1840 bool "Emulate SETEND instruction" 1841 help 1842 The SETEND instruction alters the data-endianness of the 1843 AArch32 EL0, and is deprecated in ARMv8. 1844 1845 Say Y here to enable software emulation of the instruction 1846 for AArch32 userspace code. This feature can be controlled 1847 at runtime with the abi.setend sysctl. 1848 1849 Note: All the cpus on the system must have mixed endian support at EL0 1850 for this feature to be enabled. If a new CPU - which doesn't support mixed 1851 endian - is hotplugged in after this feature has been enabled, there could 1852 be unexpected results in the applications. 1853 1854 If unsure, say Y 1855endif # ARMV8_DEPRECATED 1856 1857endif # COMPAT 1858 1859menu "ARMv8.1 architectural features" 1860 1861config ARM64_HW_AFDBM 1862 bool "Support for hardware updates of the Access and Dirty page flags" 1863 default y 1864 help 1865 The ARMv8.1 architecture extensions introduce support for 1866 hardware updates of the access and dirty information in page 1867 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1868 capable processors, accesses to pages with PTE_AF cleared will 1869 set this bit instead of raising an access flag fault. 1870 Similarly, writes to read-only pages with the DBM bit set will 1871 clear the read-only bit (AP[2]) instead of raising a 1872 permission fault. 1873 1874 Kernels built with this configuration option enabled continue 1875 to work on pre-ARMv8.1 hardware and the performance impact is 1876 minimal. If unsure, say Y. 1877 1878config ARM64_PAN 1879 bool "Enable support for Privileged Access Never (PAN)" 1880 default y 1881 help 1882 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1883 prevents the kernel or hypervisor from accessing user-space (EL0) 1884 memory directly. 1885 1886 Choosing this option will cause any unprotected (not using 1887 copy_to_user et al) memory access to fail with a permission fault. 1888 1889 The feature is detected at runtime, and will remain as a 'nop' 1890 instruction if the cpu does not implement the feature. 1891 1892config AS_HAS_LSE_ATOMICS 1893 def_bool $(as-instr,.arch_extension lse) 1894 1895config ARM64_LSE_ATOMICS 1896 bool 1897 default ARM64_USE_LSE_ATOMICS 1898 depends on AS_HAS_LSE_ATOMICS 1899 1900config ARM64_USE_LSE_ATOMICS 1901 bool "Atomic instructions" 1902 default y 1903 help 1904 As part of the Large System Extensions, ARMv8.1 introduces new 1905 atomic instructions that are designed specifically to scale in 1906 very large systems. 1907 1908 Say Y here to make use of these instructions for the in-kernel 1909 atomic routines. This incurs a small overhead on CPUs that do 1910 not support these instructions and requires the kernel to be 1911 built with binutils >= 2.25 in order for the new instructions 1912 to be used. 1913 1914endmenu # "ARMv8.1 architectural features" 1915 1916menu "ARMv8.2 architectural features" 1917 1918config AS_HAS_ARMV8_2 1919 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1920 1921config AS_HAS_SHA3 1922 def_bool $(as-instr,.arch armv8.2-a+sha3) 1923 1924config ARM64_PMEM 1925 bool "Enable support for persistent memory" 1926 select ARCH_HAS_PMEM_API 1927 select ARCH_HAS_UACCESS_FLUSHCACHE 1928 help 1929 Say Y to enable support for the persistent memory API based on the 1930 ARMv8.2 DCPoP feature. 1931 1932 The feature is detected at runtime, and the kernel will use DC CVAC 1933 operations if DC CVAP is not supported (following the behaviour of 1934 DC CVAP itself if the system does not define a point of persistence). 1935 1936config ARM64_RAS_EXTN 1937 bool "Enable support for RAS CPU Extensions" 1938 default y 1939 help 1940 CPUs that support the Reliability, Availability and Serviceability 1941 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1942 errors, classify them and report them to software. 1943 1944 On CPUs with these extensions system software can use additional 1945 barriers to determine if faults are pending and read the 1946 classification from a new set of registers. 1947 1948 Selecting this feature will allow the kernel to use these barriers 1949 and access the new registers if the system supports the extension. 1950 Platform RAS features may additionally depend on firmware support. 1951 1952config ARM64_CNP 1953 bool "Enable support for Common Not Private (CNP) translations" 1954 default y 1955 help 1956 Common Not Private (CNP) allows translation table entries to 1957 be shared between different PEs in the same inner shareable 1958 domain, so the hardware can use this fact to optimise the 1959 caching of such entries in the TLB. 1960 1961 Selecting this option allows the CNP feature to be detected 1962 at runtime, and does not affect PEs that do not implement 1963 this feature. 1964 1965endmenu # "ARMv8.2 architectural features" 1966 1967menu "ARMv8.3 architectural features" 1968 1969config ARM64_PTR_AUTH 1970 bool "Enable support for pointer authentication" 1971 default y 1972 help 1973 Pointer authentication (part of the ARMv8.3 Extensions) provides 1974 instructions for signing and authenticating pointers against secret 1975 keys, which can be used to mitigate Return Oriented Programming (ROP) 1976 and other attacks. 1977 1978 This option enables these instructions at EL0 (i.e. for userspace). 1979 Choosing this option will cause the kernel to initialise secret keys 1980 for each process at exec() time, with these keys being 1981 context-switched along with the process. 1982 1983 The feature is detected at runtime. If the feature is not present in 1984 hardware it will not be advertised to userspace/KVM guest nor will it 1985 be enabled. 1986 1987 If the feature is present on the boot CPU but not on a late CPU, then 1988 the late CPU will be parked. Also, if the boot CPU does not have 1989 address auth and the late CPU has then the late CPU will still boot 1990 but with the feature disabled. On such a system, this option should 1991 not be selected. 1992 1993config ARM64_PTR_AUTH_KERNEL 1994 bool "Use pointer authentication for kernel" 1995 default y 1996 depends on ARM64_PTR_AUTH 1997 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1998 # Modern compilers insert a .note.gnu.property section note for PAC 1999 # which is only understood by binutils starting with version 2.33.1. 2000 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 2001 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 2002 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2003 help 2004 If the compiler supports the -mbranch-protection or 2005 -msign-return-address flag (e.g. GCC 7 or later), then this option 2006 will cause the kernel itself to be compiled with return address 2007 protection. In this case, and if the target hardware is known to 2008 support pointer authentication, then CONFIG_STACKPROTECTOR can be 2009 disabled with minimal loss of protection. 2010 2011 This feature works with FUNCTION_GRAPH_TRACER option only if 2012 DYNAMIC_FTRACE_WITH_ARGS is enabled. 2013 2014config CC_HAS_BRANCH_PROT_PAC_RET 2015 # GCC 9 or later, clang 8 or later 2016 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 2017 2018config CC_HAS_SIGN_RETURN_ADDRESS 2019 # GCC 7, 8 2020 def_bool $(cc-option,-msign-return-address=all) 2021 2022config AS_HAS_ARMV8_3 2023 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 2024 2025config AS_HAS_CFI_NEGATE_RA_STATE 2026 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2027 2028config AS_HAS_LDAPR 2029 def_bool $(as-instr,.arch_extension rcpc) 2030 2031endmenu # "ARMv8.3 architectural features" 2032 2033menu "ARMv8.4 architectural features" 2034 2035config ARM64_AMU_EXTN 2036 bool "Enable support for the Activity Monitors Unit CPU extension" 2037 default y 2038 help 2039 The activity monitors extension is an optional extension introduced 2040 by the ARMv8.4 CPU architecture. This enables support for version 1 2041 of the activity monitors architecture, AMUv1. 2042 2043 To enable the use of this extension on CPUs that implement it, say Y. 2044 2045 Note that for architectural reasons, firmware _must_ implement AMU 2046 support when running on CPUs that present the activity monitors 2047 extension. The required support is present in: 2048 * Version 1.5 and later of the ARM Trusted Firmware 2049 2050 For kernels that have this configuration enabled but boot with broken 2051 firmware, you may need to say N here until the firmware is fixed. 2052 Otherwise you may experience firmware panics or lockups when 2053 accessing the counter registers. Even if you are not observing these 2054 symptoms, the values returned by the register reads might not 2055 correctly reflect reality. Most commonly, the value read will be 0, 2056 indicating that the counter is not enabled. 2057 2058config AS_HAS_ARMV8_4 2059 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2060 2061config ARM64_TLB_RANGE 2062 bool "Enable support for tlbi range feature" 2063 default y 2064 depends on AS_HAS_ARMV8_4 2065 help 2066 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2067 range of input addresses. 2068 2069 The feature introduces new assembly instructions, and they were 2070 support when binutils >= 2.30. 2071 2072endmenu # "ARMv8.4 architectural features" 2073 2074menu "ARMv8.5 architectural features" 2075 2076config AS_HAS_ARMV8_5 2077 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2078 2079config ARM64_BTI 2080 bool "Branch Target Identification support" 2081 default y 2082 help 2083 Branch Target Identification (part of the ARMv8.5 Extensions) 2084 provides a mechanism to limit the set of locations to which computed 2085 branch instructions such as BR or BLR can jump. 2086 2087 To make use of BTI on CPUs that support it, say Y. 2088 2089 BTI is intended to provide complementary protection to other control 2090 flow integrity protection mechanisms, such as the Pointer 2091 authentication mechanism provided as part of the ARMv8.3 Extensions. 2092 For this reason, it does not make sense to enable this option without 2093 also enabling support for pointer authentication. Thus, when 2094 enabling this option you should also select ARM64_PTR_AUTH=y. 2095 2096 Userspace binaries must also be specifically compiled to make use of 2097 this mechanism. If you say N here or the hardware does not support 2098 BTI, such binaries can still run, but you get no additional 2099 enforcement of branch destinations. 2100 2101config ARM64_BTI_KERNEL 2102 bool "Use Branch Target Identification for kernel" 2103 default y 2104 depends on ARM64_BTI 2105 depends on ARM64_PTR_AUTH_KERNEL 2106 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2107 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2108 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2109 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2110 depends on !CC_IS_GCC 2111 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2112 help 2113 Build the kernel with Branch Target Identification annotations 2114 and enable enforcement of this for kernel code. When this option 2115 is enabled and the system supports BTI all kernel code including 2116 modular code must have BTI enabled. 2117 2118config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2119 # GCC 9 or later, clang 8 or later 2120 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2121 2122config ARM64_E0PD 2123 bool "Enable support for E0PD" 2124 default y 2125 help 2126 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2127 that EL0 accesses made via TTBR1 always fault in constant time, 2128 providing similar benefits to KASLR as those provided by KPTI, but 2129 with lower overhead and without disrupting legitimate access to 2130 kernel memory such as SPE. 2131 2132 This option enables E0PD for TTBR1 where available. 2133 2134config ARM64_AS_HAS_MTE 2135 # Initial support for MTE went in binutils 2.32.0, checked with 2136 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2137 # as a late addition to the final architecture spec (LDGM/STGM) 2138 # is only supported in the newer 2.32.x and 2.33 binutils 2139 # versions, hence the extra "stgm" instruction check below. 2140 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2141 2142config ARM64_MTE 2143 bool "Memory Tagging Extension support" 2144 default y 2145 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2146 depends on AS_HAS_ARMV8_5 2147 depends on AS_HAS_LSE_ATOMICS 2148 # Required for tag checking in the uaccess routines 2149 select ARM64_PAN 2150 select ARCH_HAS_SUBPAGE_FAULTS 2151 select ARCH_USES_HIGH_VMA_FLAGS 2152 select ARCH_USES_PG_ARCH_2 2153 select ARCH_USES_PG_ARCH_3 2154 help 2155 Memory Tagging (part of the ARMv8.5 Extensions) provides 2156 architectural support for run-time, always-on detection of 2157 various classes of memory error to aid with software debugging 2158 to eliminate vulnerabilities arising from memory-unsafe 2159 languages. 2160 2161 This option enables the support for the Memory Tagging 2162 Extension at EL0 (i.e. for userspace). 2163 2164 Selecting this option allows the feature to be detected at 2165 runtime. Any secondary CPU not implementing this feature will 2166 not be allowed a late bring-up. 2167 2168 Userspace binaries that want to use this feature must 2169 explicitly opt in. The mechanism for the userspace is 2170 described in: 2171 2172 Documentation/arch/arm64/memory-tagging-extension.rst. 2173 2174endmenu # "ARMv8.5 architectural features" 2175 2176menu "ARMv8.7 architectural features" 2177 2178config ARM64_EPAN 2179 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2180 default y 2181 depends on ARM64_PAN 2182 help 2183 Enhanced Privileged Access Never (EPAN) allows Privileged 2184 Access Never to be used with Execute-only mappings. 2185 2186 The feature is detected at runtime, and will remain disabled 2187 if the cpu does not implement the feature. 2188endmenu # "ARMv8.7 architectural features" 2189 2190config AS_HAS_MOPS 2191 def_bool $(as-instr,.arch_extension mops) 2192 2193menu "ARMv8.9 architectural features" 2194 2195config ARM64_POE 2196 prompt "Permission Overlay Extension" 2197 def_bool y 2198 select ARCH_USES_HIGH_VMA_FLAGS 2199 select ARCH_HAS_PKEYS 2200 help 2201 The Permission Overlay Extension is used to implement Memory 2202 Protection Keys. Memory Protection Keys provides a mechanism for 2203 enforcing page-based protections, but without requiring modification 2204 of the page tables when an application changes protection domains. 2205 2206 For details, see Documentation/core-api/protection-keys.rst 2207 2208 If unsure, say y. 2209 2210config ARCH_PKEY_BITS 2211 int 2212 default 3 2213 2214config ARM64_HAFT 2215 bool "Support for Hardware managed Access Flag for Table Descriptors" 2216 depends on ARM64_HW_AFDBM 2217 default y 2218 help 2219 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2220 Flag for Table descriptors. When enabled an architectural executed 2221 memory access will update the Access Flag in each Table descriptor 2222 which is accessed during the translation table walk and for which 2223 the Access Flag is 0. The Access Flag of the Table descriptor use 2224 the same bit of PTE_AF. 2225 2226 The feature will only be enabled if all the CPUs in the system 2227 support this feature. If unsure, say Y. 2228 2229endmenu # "ARMv8.9 architectural features" 2230 2231menu "v9.4 architectural features" 2232 2233config ARM64_GCS 2234 bool "Enable support for Guarded Control Stack (GCS)" 2235 default y 2236 select ARCH_HAS_USER_SHADOW_STACK 2237 select ARCH_USES_HIGH_VMA_FLAGS 2238 depends on !UPROBES 2239 help 2240 Guarded Control Stack (GCS) provides support for a separate 2241 stack with restricted access which contains only return 2242 addresses. This can be used to harden against some attacks 2243 by comparing return address used by the program with what is 2244 stored in the GCS, and may also be used to efficiently obtain 2245 the call stack for applications such as profiling. 2246 2247 The feature is detected at runtime, and will remain disabled 2248 if the system does not implement the feature. 2249 2250endmenu # "v9.4 architectural features" 2251 2252config ARM64_SVE 2253 bool "ARM Scalable Vector Extension support" 2254 default y 2255 help 2256 The Scalable Vector Extension (SVE) is an extension to the AArch64 2257 execution state which complements and extends the SIMD functionality 2258 of the base architecture to support much larger vectors and to enable 2259 additional vectorisation opportunities. 2260 2261 To enable use of this extension on CPUs that implement it, say Y. 2262 2263 On CPUs that support the SVE2 extensions, this option will enable 2264 those too. 2265 2266 Note that for architectural reasons, firmware _must_ implement SVE 2267 support when running on SVE capable hardware. The required support 2268 is present in: 2269 2270 * version 1.5 and later of the ARM Trusted Firmware 2271 * the AArch64 boot wrapper since commit 5e1261e08abf 2272 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2273 2274 For other firmware implementations, consult the firmware documentation 2275 or vendor. 2276 2277 If you need the kernel to boot on SVE-capable hardware with broken 2278 firmware, you may need to say N here until you get your firmware 2279 fixed. Otherwise, you may experience firmware panics or lockups when 2280 booting the kernel. If unsure and you are not observing these 2281 symptoms, you should assume that it is safe to say Y. 2282 2283config ARM64_SME 2284 bool "ARM Scalable Matrix Extension support" 2285 default y 2286 depends on ARM64_SVE 2287 depends on BROKEN 2288 help 2289 The Scalable Matrix Extension (SME) is an extension to the AArch64 2290 execution state which utilises a substantial subset of the SVE 2291 instruction set, together with the addition of new architectural 2292 register state capable of holding two dimensional matrix tiles to 2293 enable various matrix operations. 2294 2295config ARM64_PSEUDO_NMI 2296 bool "Support for NMI-like interrupts" 2297 select ARM_GIC_V3 2298 help 2299 Adds support for mimicking Non-Maskable Interrupts through the use of 2300 GIC interrupt priority. This support requires version 3 or later of 2301 ARM GIC. 2302 2303 This high priority configuration for interrupts needs to be 2304 explicitly enabled by setting the kernel parameter 2305 "irqchip.gicv3_pseudo_nmi" to 1. 2306 2307 If unsure, say N 2308 2309if ARM64_PSEUDO_NMI 2310config ARM64_DEBUG_PRIORITY_MASKING 2311 bool "Debug interrupt priority masking" 2312 help 2313 This adds runtime checks to functions enabling/disabling 2314 interrupts when using priority masking. The additional checks verify 2315 the validity of ICC_PMR_EL1 when calling concerned functions. 2316 2317 If unsure, say N 2318endif # ARM64_PSEUDO_NMI 2319 2320config RELOCATABLE 2321 bool "Build a relocatable kernel image" if EXPERT 2322 select ARCH_HAS_RELR 2323 default y 2324 help 2325 This builds the kernel as a Position Independent Executable (PIE), 2326 which retains all relocation metadata required to relocate the 2327 kernel binary at runtime to a different virtual address than the 2328 address it was linked at. 2329 Since AArch64 uses the RELA relocation format, this requires a 2330 relocation pass at runtime even if the kernel is loaded at the 2331 same address it was linked at. 2332 2333config RANDOMIZE_BASE 2334 bool "Randomize the address of the kernel image" 2335 select RELOCATABLE 2336 help 2337 Randomizes the virtual address at which the kernel image is 2338 loaded, as a security feature that deters exploit attempts 2339 relying on knowledge of the location of kernel internals. 2340 2341 It is the bootloader's job to provide entropy, by passing a 2342 random u64 value in /chosen/kaslr-seed at kernel entry. 2343 2344 When booting via the UEFI stub, it will invoke the firmware's 2345 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2346 to the kernel proper. In addition, it will randomise the physical 2347 location of the kernel Image as well. 2348 2349 If unsure, say N. 2350 2351config RANDOMIZE_MODULE_REGION_FULL 2352 bool "Randomize the module region over a 2 GB range" 2353 depends on RANDOMIZE_BASE 2354 default y 2355 help 2356 Randomizes the location of the module region inside a 2 GB window 2357 covering the core kernel. This way, it is less likely for modules 2358 to leak information about the location of core kernel data structures 2359 but it does imply that function calls between modules and the core 2360 kernel will need to be resolved via veneers in the module PLT. 2361 2362 When this option is not set, the module region will be randomized over 2363 a limited range that contains the [_stext, _etext] interval of the 2364 core kernel, so branch relocations are almost always in range unless 2365 the region is exhausted. In this particular case of region 2366 exhaustion, modules might be able to fall back to a larger 2GB area. 2367 2368config CC_HAVE_STACKPROTECTOR_SYSREG 2369 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2370 2371config STACKPROTECTOR_PER_TASK 2372 def_bool y 2373 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2374 2375config UNWIND_PATCH_PAC_INTO_SCS 2376 bool "Enable shadow call stack dynamically using code patching" 2377 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2378 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2379 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2380 depends on SHADOW_CALL_STACK 2381 select UNWIND_TABLES 2382 select DYNAMIC_SCS 2383 2384config ARM64_CONTPTE 2385 bool "Contiguous PTE mappings for user memory" if EXPERT 2386 depends on TRANSPARENT_HUGEPAGE 2387 default y 2388 help 2389 When enabled, user mappings are configured using the PTE contiguous 2390 bit, for any mappings that meet the size and alignment requirements. 2391 This reduces TLB pressure and improves performance. 2392 2393endmenu # "Kernel Features" 2394 2395menu "Boot options" 2396 2397config ARM64_ACPI_PARKING_PROTOCOL 2398 bool "Enable support for the ARM64 ACPI parking protocol" 2399 depends on ACPI 2400 help 2401 Enable support for the ARM64 ACPI parking protocol. If disabled 2402 the kernel will not allow booting through the ARM64 ACPI parking 2403 protocol even if the corresponding data is present in the ACPI 2404 MADT table. 2405 2406config CMDLINE 2407 string "Default kernel command string" 2408 default "" 2409 help 2410 Provide a set of default command-line options at build time by 2411 entering them here. As a minimum, you should specify the the 2412 root device (e.g. root=/dev/nfs). 2413 2414choice 2415 prompt "Kernel command line type" 2416 depends on CMDLINE != "" 2417 default CMDLINE_FROM_BOOTLOADER 2418 help 2419 Choose how the kernel will handle the provided default kernel 2420 command line string. 2421 2422config CMDLINE_FROM_BOOTLOADER 2423 bool "Use bootloader kernel arguments if available" 2424 help 2425 Uses the command-line options passed by the boot loader. If 2426 the boot loader doesn't provide any, the default kernel command 2427 string provided in CMDLINE will be used. 2428 2429config CMDLINE_FORCE 2430 bool "Always use the default kernel command string" 2431 help 2432 Always use the default kernel command string, even if the boot 2433 loader passes other arguments to the kernel. 2434 This is useful if you cannot or don't want to change the 2435 command-line options your boot loader passes to the kernel. 2436 2437endchoice 2438 2439config EFI_STUB 2440 bool 2441 2442config EFI 2443 bool "UEFI runtime support" 2444 depends on OF && !CPU_BIG_ENDIAN 2445 depends on KERNEL_MODE_NEON 2446 select ARCH_SUPPORTS_ACPI 2447 select LIBFDT 2448 select UCS2_STRING 2449 select EFI_PARAMS_FROM_FDT 2450 select EFI_RUNTIME_WRAPPERS 2451 select EFI_STUB 2452 select EFI_GENERIC_STUB 2453 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2454 default y 2455 help 2456 This option provides support for runtime services provided 2457 by UEFI firmware (such as non-volatile variables, realtime 2458 clock, and platform reset). A UEFI stub is also provided to 2459 allow the kernel to be booted as an EFI application. This 2460 is only useful on systems that have UEFI firmware. 2461 2462config COMPRESSED_INSTALL 2463 bool "Install compressed image by default" 2464 help 2465 This makes the regular "make install" install the compressed 2466 image we built, not the legacy uncompressed one. 2467 2468 You can check that a compressed image works for you by doing 2469 "make zinstall" first, and verifying that everything is fine 2470 in your environment before making "make install" do this for 2471 you. 2472 2473config DMI 2474 bool "Enable support for SMBIOS (DMI) tables" 2475 depends on EFI 2476 default y 2477 help 2478 This enables SMBIOS/DMI feature for systems. 2479 2480 This option is only useful on systems that have UEFI firmware. 2481 However, even with this option, the resultant kernel should 2482 continue to boot on existing non-UEFI platforms. 2483 2484endmenu # "Boot options" 2485 2486menu "Power management options" 2487 2488source "kernel/power/Kconfig" 2489 2490config ARCH_HIBERNATION_POSSIBLE 2491 def_bool y 2492 depends on CPU_PM 2493 2494config ARCH_HIBERNATION_HEADER 2495 def_bool y 2496 depends on HIBERNATION 2497 2498config ARCH_SUSPEND_POSSIBLE 2499 def_bool y 2500 2501endmenu # "Power management options" 2502 2503menu "CPU Power Management" 2504 2505source "drivers/cpuidle/Kconfig" 2506 2507source "drivers/cpufreq/Kconfig" 2508 2509endmenu # "CPU Power Management" 2510 2511source "drivers/acpi/Kconfig" 2512 2513source "arch/arm64/kvm/Kconfig" 2514 2515