1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED 11 select ARCH_HAS_DMA_CLEAR_UNCACHED 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13 select GENERIC_BUILTIN_DTB 14 select COMMON_CLK 15 select OF 16 select OF_EARLY_FLATTREE 17 select IRQ_DOMAIN 18 select GPIOLIB 19 select HAVE_ARCH_TRACEHOOK 20 select SPARSE_IRQ 21 select GENERIC_IRQ_CHIP 22 select GENERIC_IRQ_PROBE 23 select GENERIC_IRQ_SHOW 24 select GENERIC_PCI_IOMAP 25 select GENERIC_IOREMAP 26 select GENERIC_CPU_DEVICES 27 select HAVE_ARCH_JUMP_LABEL 28 select HAVE_ARCH_JUMP_LABEL_RELATIVE 29 select HAVE_PCI 30 select HAVE_UID16 31 select HAVE_PAGE_SIZE_8KB 32 select HAVE_REGS_AND_STACK_ACCESS_API 33 select HAVE_RSEQ 34 select GENERIC_ATOMIC64 35 select GENERIC_CLOCKEVENTS_BROADCAST 36 select GENERIC_SMP_IDLE_THREAD 37 select MODULES_USE_ELF_RELA 38 select HAVE_DEBUG_STACKOVERFLOW 39 select OR1K_PIC 40 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 41 select ARCH_USE_QUEUED_RWLOCKS 42 select OMPIC if SMP 43 select PCI_DOMAINS_GENERIC if PCI 44 select PCI_MSI if PCI 45 select ARCH_WANT_FRAME_POINTERS 46 select GENERIC_IRQ_MULTI_HANDLER 47 select MMU_GATHER_NO_RANGE if MMU 48 select TRACE_IRQFLAGS_SUPPORT 49 50config CPU_BIG_ENDIAN 51 def_bool y 52 53config MMU 54 def_bool y 55 56config GENERIC_HWEIGHT 57 def_bool y 58 59config NO_IOPORT_MAP 60 def_bool y 61 62# For now, use generic checksum functions 63#These can be reimplemented in assembly later if so inclined 64config GENERIC_CSUM 65 def_bool y 66 67config STACKTRACE_SUPPORT 68 def_bool y 69 70config LOCKDEP_SUPPORT 71 def_bool y 72 73config FIX_EARLYCON_MEM 74 def_bool y 75 76menu "Processor type and features" 77 78choice 79 prompt "Subarchitecture" 80 default OR1K_1200 81 82config OR1K_1200 83 bool "OR1200" 84 help 85 Generic OpenRISC 1200 architecture 86 87endchoice 88 89config DCACHE_WRITETHROUGH 90 bool "Have write through data caches" 91 default n 92 help 93 Select this if your implementation features write through data caches. 94 Selecting 'N' here will allow the kernel to force flushing of data 95 caches at relevant times. Most OpenRISC implementations support write- 96 through data caches. 97 98 If unsure say N here 99 100config BUILTIN_DTB_NAME 101 string "Builtin DTB" 102 default "" 103 104menu "Class II Instructions" 105 106config OPENRISC_HAVE_INST_FF1 107 bool "Have instruction l.ff1" 108 default y 109 help 110 Select this if your implementation has the Class II instruction l.ff1 111 112config OPENRISC_HAVE_INST_FL1 113 bool "Have instruction l.fl1" 114 default y 115 help 116 Select this if your implementation has the Class II instruction l.fl1 117 118config OPENRISC_HAVE_INST_MUL 119 bool "Have instruction l.mul for hardware multiply" 120 default y 121 help 122 Select this if your implementation has a hardware multiply instruction 123 124config OPENRISC_HAVE_INST_DIV 125 bool "Have instruction l.div for hardware divide" 126 default y 127 help 128 Select this if your implementation has a hardware divide instruction 129 130config OPENRISC_HAVE_INST_CMOV 131 bool "Have instruction l.cmov for conditional move" 132 default n 133 help 134 This config enables gcc to generate l.cmov instructions when compiling 135 the kernel which in general will improve performance and reduce the 136 binary size. 137 138 Select this if your implementation has support for the Class II 139 l.cmov conistional move instruction. 140 141 Say N if you are unsure. 142 143config OPENRISC_HAVE_INST_ROR 144 bool "Have instruction l.ror for rotate right" 145 default n 146 help 147 This config enables gcc to generate l.ror instructions when compiling 148 the kernel which in general will improve performance and reduce the 149 binary size. 150 151 Select this if your implementation has support for the Class II 152 l.ror rotate right instruction. 153 154 Say N if you are unsure. 155 156config OPENRISC_HAVE_INST_RORI 157 bool "Have instruction l.rori for rotate right with immediate" 158 default n 159 help 160 This config enables gcc to generate l.rori instructions when compiling 161 the kernel which in general will improve performance and reduce the 162 binary size. 163 164 Select this if your implementation has support for the Class II 165 l.rori rotate right with immediate instruction. 166 167 Say N if you are unsure. 168 169config OPENRISC_HAVE_INST_SEXT 170 bool "Have instructions l.ext* for sign extension" 171 default n 172 help 173 This config enables gcc to generate l.ext* instructions when compiling 174 the kernel which in general will improve performance and reduce the 175 binary size. 176 177 Select this if your implementation has support for the Class II 178 l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 179 180 Say N if you are unsure. 181 182endmenu 183 184config NR_CPUS 185 int "Maximum number of CPUs (2-32)" 186 range 2 32 187 depends on SMP 188 default "2" 189 190config SMP 191 bool "Symmetric Multi-Processing support" 192 help 193 This enables support for systems with more than one CPU. If you have 194 a system with only one CPU, say N. If you have a system with more 195 than one CPU, say Y. 196 197 If you don't know what to do here, say N. 198 199config FPU 200 bool "FPU support" 201 default y 202 help 203 Say N here if you want to disable all floating-point related procedures 204 in the kernel and reduce binary size. 205 206 If you don't know what to do here, say Y. 207 208source "kernel/Kconfig.hz" 209 210config OPENRISC_NO_SPR_SR_DSX 211 bool "use SPR_SR_DSX software emulation" if OR1K_1200 212 default y 213 help 214 SPR_SR_DSX bit is status register bit indicating whether 215 the last exception has happened in delay slot. 216 217 OpenRISC architecture makes it optional to have it implemented 218 in hardware and the OR1200 does not have it. 219 220 Say N here if you know that your OpenRISC processor has 221 SPR_SR_DSX bit implemented. Say Y if you are unsure. 222 223config OPENRISC_HAVE_SHADOW_GPRS 224 bool "Support for shadow gpr files" if !SMP 225 default y if SMP 226 help 227 Say Y here if your OpenRISC processor features shadowed 228 register files. They will in such case be used as a 229 scratch reg storage on exception entry. 230 231 On SMP systems, this feature is mandatory. 232 On a unicore system it's safe to say N here if you are unsure. 233 234config CMDLINE 235 string "Default kernel command string" 236 default "" 237 help 238 On some architectures there is currently no way for the boot loader 239 to pass arguments to the kernel. For these architectures, you should 240 supply some command-line options at build time by entering them 241 here. 242 243menu "Debugging options" 244 245config JUMP_UPON_UNHANDLED_EXCEPTION 246 bool "Try to die gracefully" 247 default y 248 help 249 Now this puts kernel into infinite loop after first oops. Till 250 your kernel crashes this doesn't have any influence. 251 252 Say Y if you are unsure. 253 254config OPENRISC_ESR_EXCEPTION_BUG_CHECK 255 bool "Check for possible ESR exception bug" 256 default n 257 help 258 This option enables some checks that might expose some problems 259 in kernel. 260 261 Say N if you are unsure. 262 263endmenu 264 265endmenu 266