1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION 25 select ARCH_HAS_CURRENT_STACK_POINTER 26 select ARCH_HAS_DEBUG_VIRTUAL 27 select ARCH_HAS_DEBUG_VM_PGTABLE 28 select ARCH_HAS_DMA_OPS if XEN 29 select ARCH_HAS_DMA_PREP_COHERENT 30 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 31 select ARCH_HAS_FAST_MULTIPLIER 32 select ARCH_HAS_FORTIFY_SOURCE 33 select ARCH_HAS_GCOV_PROFILE_ALL 34 select ARCH_HAS_GIGANTIC_PAGE 35 select ARCH_HAS_KCOV 36 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 37 select ARCH_HAS_KEEPINITRD 38 select ARCH_HAS_MEMBARRIER_SYNC_CORE 39 select ARCH_HAS_MEM_ENCRYPT 40 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS 41 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 42 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 43 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 44 select ARCH_HAS_PREEMPT_LAZY 45 select ARCH_HAS_PTDUMP 46 select ARCH_HAS_PTE_SPECIAL 47 select ARCH_HAS_HW_PTE_YOUNG 48 select ARCH_HAS_SETUP_DMA_OPS 49 select ARCH_HAS_SET_DIRECT_MAP 50 select ARCH_HAS_SET_MEMORY 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_SYSCALL_WRAPPER 58 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 59 select ARCH_HAS_ZONE_DMA_SET if EXPERT 60 select ARCH_HAVE_ELF_PROT 61 select ARCH_HAVE_NMI_SAFE_CMPXCHG 62 select ARCH_HAVE_TRACE_MMIO_ACCESS 63 select ARCH_INLINE_READ_LOCK if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 65 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 70 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 73 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 74 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 77 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 78 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 79 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 83 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 84 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 87 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 88 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 89 select ARCH_KEEP_MEMBLOCK 90 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 91 select ARCH_USE_CMPXCHG_LOCKREF 92 select ARCH_USE_GNU_PROPERTY 93 select ARCH_USE_MEMTEST 94 select ARCH_USE_QUEUED_RWLOCKS 95 select ARCH_USE_QUEUED_SPINLOCKS 96 select ARCH_USE_SYM_ANNOTATIONS 97 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 98 select ARCH_SUPPORTS_HUGETLBFS 99 select ARCH_SUPPORTS_MEMORY_FAILURE 100 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 101 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 102 select ARCH_SUPPORTS_LTO_CLANG_THIN 103 select ARCH_SUPPORTS_CFI 104 select ARCH_SUPPORTS_ATOMIC_RMW 105 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 106 select ARCH_SUPPORTS_NUMA_BALANCING 107 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 108 select ARCH_SUPPORTS_PER_VMA_LOCK 109 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 110 select ARCH_SUPPORTS_RT 111 select ARCH_SUPPORTS_SCHED_SMT 112 select ARCH_SUPPORTS_SCHED_CLUSTER 113 select ARCH_SUPPORTS_SCHED_MC 114 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 115 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 116 select ARCH_WANT_DEFAULT_BPF_JIT 117 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 118 select ARCH_WANT_FRAME_POINTERS 119 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 120 select ARCH_WANT_LD_ORPHAN_WARN 121 select ARCH_WANTS_EXECMEM_LATE 122 select ARCH_WANTS_NO_INSTR 123 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 124 select ARCH_HAS_UBSAN 125 select ARM_AMBA 126 select ARM_ARCH_TIMER 127 select ARM_GIC 128 select AUDIT_ARCH_COMPAT_GENERIC 129 select ARM_GIC_V2M if PCI 130 select ARM_GIC_V3 131 select ARM_GIC_V3_ITS if PCI 132 select ARM_GIC_V5 133 select ARM_PSCI_FW 134 select BUILDTIME_TABLE_SORT 135 select CLONE_BACKWARDS 136 select COMMON_CLK 137 select CPU_PM if (SUSPEND || CPU_IDLE) 138 select CPUMASK_OFFSTACK if NR_CPUS > 256 139 select DCACHE_WORD_ACCESS 140 select HAVE_EXTRA_IPI_TRACEPOINTS 141 select DYNAMIC_FTRACE if FUNCTION_TRACER 142 select DMA_BOUNCE_UNALIGNED_KMALLOC 143 select DMA_DIRECT_REMAP 144 select EDAC_SUPPORT 145 select FRAME_POINTER 146 select FUNCTION_ALIGNMENT_4B 147 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 148 select GENERIC_ALLOCATOR 149 select GENERIC_ARCH_TOPOLOGY 150 select GENERIC_CLOCKEVENTS_BROADCAST 151 select GENERIC_CPU_AUTOPROBE 152 select GENERIC_CPU_CACHE_MAINTENANCE 153 select GENERIC_CPU_DEVICES 154 select GENERIC_CPU_VULNERABILITIES 155 select GENERIC_EARLY_IOREMAP 156 select GENERIC_IDLE_POLL_SETUP 157 select GENERIC_IOREMAP 158 select GENERIC_IRQ_ENTRY 159 select GENERIC_IRQ_IPI 160 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 161 select GENERIC_IRQ_PROBE 162 select GENERIC_IRQ_SHOW 163 select GENERIC_IRQ_SHOW_LEVEL 164 select GENERIC_LIB_DEVMEM_IS_ALLOWED 165 select GENERIC_PCI_IOMAP 166 select GENERIC_SCHED_CLOCK 167 select GENERIC_SMP_IDLE_THREAD 168 select GENERIC_TIME_VSYSCALL 169 select GENERIC_GETTIMEOFDAY 170 select HARDIRQS_SW_RESEND 171 select HAS_IOPORT 172 select HAVE_MOVE_PMD 173 select HAVE_MOVE_PUD 174 select HAVE_PCI 175 select HAVE_ACPI_APEI if (ACPI && EFI) 176 select HAVE_ALIGNED_STRUCT_PAGE 177 select HAVE_ARCH_AUDITSYSCALL 178 select HAVE_ARCH_BITREVERSE 179 select HAVE_ARCH_COMPILER_H 180 select HAVE_ARCH_HUGE_VMALLOC 181 select HAVE_ARCH_HUGE_VMAP 182 select HAVE_ARCH_JUMP_LABEL 183 select HAVE_ARCH_JUMP_LABEL_RELATIVE 184 select HAVE_ARCH_KASAN 185 select HAVE_ARCH_KASAN_VMALLOC 186 select HAVE_ARCH_KASAN_SW_TAGS 187 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 188 # Some instrumentation may be unsound, hence EXPERT 189 select HAVE_ARCH_KCSAN if EXPERT 190 select HAVE_ARCH_KFENCE 191 select HAVE_ARCH_KGDB 192 select HAVE_ARCH_KSTACK_ERASE 193 select HAVE_ARCH_MMAP_RND_BITS 194 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 195 select HAVE_ARCH_PREL32_RELOCATIONS 196 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 197 select HAVE_ARCH_SECCOMP_FILTER 198 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 199 select HAVE_ARCH_TRACEHOOK 200 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 201 select HAVE_ARCH_VMAP_STACK 202 select HAVE_ARM_SMCCC 203 select HAVE_ASM_MODVERSIONS 204 select HAVE_EBPF_JIT 205 select HAVE_C_RECORDMCOUNT 206 select HAVE_CMPXCHG_DOUBLE 207 select HAVE_CMPXCHG_LOCAL 208 select HAVE_CONTEXT_TRACKING_USER 209 select HAVE_DEBUG_KMEMLEAK 210 select HAVE_DMA_CONTIGUOUS 211 select HAVE_DYNAMIC_FTRACE 212 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 213 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 214 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 215 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 216 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 217 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 218 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI && \ 219 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 220 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 221 if DYNAMIC_FTRACE_WITH_ARGS 222 select HAVE_SAMPLE_FTRACE_DIRECT 223 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 224 select HAVE_BUILDTIME_MCOUNT_SORT 225 select HAVE_EFFICIENT_UNALIGNED_ACCESS 226 select HAVE_GUP_FAST 227 select HAVE_FTRACE_GRAPH_FUNC 228 select HAVE_FUNCTION_TRACER 229 select HAVE_FUNCTION_ERROR_INJECTION 230 select HAVE_FUNCTION_GRAPH_FREGS 231 select HAVE_FUNCTION_GRAPH_TRACER 232 select HAVE_GCC_PLUGINS 233 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 234 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 235 select HAVE_HW_BREAKPOINT if PERF_EVENTS 236 select HAVE_IOREMAP_PROT 237 select HAVE_IRQ_TIME_ACCOUNTING 238 select HAVE_LIVEPATCH 239 select HAVE_MOD_ARCH_SPECIFIC 240 select HAVE_NMI 241 select HAVE_PERF_EVENTS 242 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 243 select HAVE_PERF_REGS 244 select HAVE_PERF_USER_STACK_DUMP 245 select HAVE_PREEMPT_DYNAMIC_KEY 246 select HAVE_REGS_AND_STACK_ACCESS_API 247 select HAVE_RELIABLE_STACKTRACE 248 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 249 select HAVE_FUNCTION_ARG_ACCESS_API 250 select MMU_GATHER_RCU_TABLE_FREE 251 select HAVE_RSEQ 252 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 253 select HAVE_STACKPROTECTOR 254 select HAVE_SYSCALL_TRACEPOINTS 255 select HAVE_KPROBES 256 select HAVE_KRETPROBES 257 select HAVE_GENERIC_VDSO 258 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 259 select HOTPLUG_SMT if HOTPLUG_CPU 260 select IRQ_DOMAIN 261 select IRQ_FORCED_THREADING 262 select JUMP_LABEL 263 select KASAN_VMALLOC if KASAN 264 select LOCK_MM_AND_FIND_VMA 265 select MODULES_USE_ELF_RELA 266 select NEED_DMA_MAP_STATE 267 select NEED_SG_DMA_LENGTH 268 select OF 269 select OF_EARLY_FLATTREE 270 select PCI_DOMAINS_GENERIC if PCI 271 select PCI_ECAM if (ACPI && PCI) 272 select PCI_SYSCALL if PCI 273 select POWER_RESET 274 select POWER_SUPPLY 275 select SPARSE_IRQ 276 select SWIOTLB 277 select SYSCTL_EXCEPTION_TRACE 278 select THREAD_INFO_IN_TASK 279 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 280 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 281 select TRACE_IRQFLAGS_SUPPORT 282 select TRACE_IRQFLAGS_NMI_SUPPORT 283 select HAVE_SOFTIRQ_ON_OWN_STACK 284 select USER_STACKTRACE_SUPPORT 285 select VDSO_GETRANDOM 286 select VMAP_STACK 287 help 288 ARM 64-bit (AArch64) Linux support. 289 290config RUSTC_SUPPORTS_ARM64 291 def_bool y 292 depends on CPU_LITTLE_ENDIAN 293 # Shadow call stack is only supported on certain rustc versions. 294 # 295 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 296 # required due to use of the -Zfixed-x18 flag. 297 # 298 # Otherwise, rustc version 1.82+ is required due to use of the 299 # -Zsanitizer=shadow-call-stack flag. 300 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 301 302config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 303 def_bool CC_IS_CLANG 304 # https://github.com/ClangBuiltLinux/linux/issues/1507 305 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 306 307config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 308 def_bool CC_IS_GCC 309 depends on $(cc-option,-fpatchable-function-entry=2) 310 311config 64BIT 312 def_bool y 313 314config MMU 315 def_bool y 316 317config ARM64_CONT_PTE_SHIFT 318 int 319 default 5 if PAGE_SIZE_64KB 320 default 7 if PAGE_SIZE_16KB 321 default 4 322 323config ARM64_CONT_PMD_SHIFT 324 int 325 default 5 if PAGE_SIZE_64KB 326 default 5 if PAGE_SIZE_16KB 327 default 4 328 329config ARCH_MMAP_RND_BITS_MIN 330 default 14 if PAGE_SIZE_64KB 331 default 16 if PAGE_SIZE_16KB 332 default 18 333 334# max bits determined by the following formula: 335# VA_BITS - PTDESC_TABLE_SHIFT 336config ARCH_MMAP_RND_BITS_MAX 337 default 19 if ARM64_VA_BITS=36 338 default 24 if ARM64_VA_BITS=39 339 default 27 if ARM64_VA_BITS=42 340 default 30 if ARM64_VA_BITS=47 341 default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES 342 default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES 343 default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) 344 default 14 if ARM64_64K_PAGES 345 default 16 if ARM64_16K_PAGES 346 default 18 347 348config ARCH_MMAP_RND_COMPAT_BITS_MIN 349 default 7 if ARM64_64K_PAGES 350 default 9 if ARM64_16K_PAGES 351 default 11 352 353config ARCH_MMAP_RND_COMPAT_BITS_MAX 354 default 16 355 356config NO_IOPORT_MAP 357 def_bool y if !PCI 358 359config STACKTRACE_SUPPORT 360 def_bool y 361 362config ILLEGAL_POINTER_VALUE 363 hex 364 default 0xdead000000000000 365 366config LOCKDEP_SUPPORT 367 def_bool y 368 369config GENERIC_BUG 370 def_bool y 371 depends on BUG 372 373config GENERIC_BUG_RELATIVE_POINTERS 374 def_bool y 375 depends on GENERIC_BUG 376 377config GENERIC_HWEIGHT 378 def_bool y 379 380config GENERIC_CSUM 381 def_bool y 382 383config GENERIC_CALIBRATE_DELAY 384 def_bool y 385 386config SMP 387 def_bool y 388 389config KERNEL_MODE_NEON 390 def_bool y 391 392config FIX_EARLYCON_MEM 393 def_bool y 394 395config PGTABLE_LEVELS 396 int 397 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 398 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 399 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 400 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 401 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 402 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 403 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 404 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 405 406config ARCH_SUPPORTS_UPROBES 407 def_bool y 408 409config ARCH_PROC_KCORE_TEXT 410 def_bool y 411 412config BROKEN_GAS_INST 413 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 414 415config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 416 bool 417 # Clang's __builtin_return_address() strips the PAC since 12.0.0 418 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 419 default y if CC_IS_CLANG 420 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 421 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 422 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 423 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 424 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 425 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 426 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 427 default n 428 429config KASAN_SHADOW_OFFSET 430 hex 431 depends on KASAN_GENERIC || KASAN_SW_TAGS 432 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 433 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 434 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 435 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 436 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 437 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 438 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 439 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 440 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 441 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 442 default 0xffffffffffffffff 443 444config UNWIND_TABLES 445 bool 446 447source "arch/arm64/Kconfig.platforms" 448 449menu "Kernel Features" 450 451menu "ARM errata workarounds via the alternatives framework" 452 453config AMPERE_ERRATUM_AC03_CPU_38 454 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 455 default y 456 help 457 This option adds an alternative code sequence to work around Ampere 458 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 459 460 The affected design reports FEAT_HAFDBS as not implemented in 461 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 462 as required by the architecture. The unadvertised HAFDBS 463 implementation suffers from an additional erratum where hardware 464 A/D updates can occur after a PTE has been marked invalid. 465 466 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 467 which avoids enabling unadvertised hardware Access Flag management 468 at stage-2. 469 470 If unsure, say Y. 471 472config AMPERE_ERRATUM_AC04_CPU_23 473 bool "AmpereOne: AC04_CPU_23: Failure to synchronize writes to HCR_EL2 may corrupt address translations." 474 default y 475 help 476 This option adds an alternative code sequence to work around Ampere 477 errata AC04_CPU_23 on AmpereOne. 478 479 Updates to HCR_EL2 can rarely corrupt simultaneous translations for 480 data addresses initiated by load/store instructions. Only 481 instruction initiated translations are vulnerable, not translations 482 from prefetches for example. A DSB before the store to HCR_EL2 is 483 sufficient to prevent older instructions from hitting the window 484 for corruption, and an ISB after is sufficient to prevent younger 485 instructions from hitting the window for corruption. 486 487 If unsure, say Y. 488 489config ARM64_WORKAROUND_CLEAN_CACHE 490 bool 491 492config ARM64_ERRATUM_826319 493 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 494 default y 495 select ARM64_WORKAROUND_CLEAN_CACHE 496 help 497 This option adds an alternative code sequence to work around ARM 498 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 499 AXI master interface and an L2 cache. 500 501 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 502 and is unable to accept a certain write via this interface, it will 503 not progress on read data presented on the read data channel and the 504 system can deadlock. 505 506 The workaround promotes data cache clean instructions to 507 data cache clean-and-invalidate. 508 Please note that this does not necessarily enable the workaround, 509 as it depends on the alternative framework, which will only patch 510 the kernel if an affected CPU is detected. 511 512 If unsure, say Y. 513 514config ARM64_ERRATUM_827319 515 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 516 default y 517 select ARM64_WORKAROUND_CLEAN_CACHE 518 help 519 This option adds an alternative code sequence to work around ARM 520 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 521 master interface and an L2 cache. 522 523 Under certain conditions this erratum can cause a clean line eviction 524 to occur at the same time as another transaction to the same address 525 on the AMBA 5 CHI interface, which can cause data corruption if the 526 interconnect reorders the two transactions. 527 528 The workaround promotes data cache clean instructions to 529 data cache clean-and-invalidate. 530 Please note that this does not necessarily enable the workaround, 531 as it depends on the alternative framework, which will only patch 532 the kernel if an affected CPU is detected. 533 534 If unsure, say Y. 535 536config ARM64_ERRATUM_824069 537 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 538 default y 539 select ARM64_WORKAROUND_CLEAN_CACHE 540 help 541 This option adds an alternative code sequence to work around ARM 542 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 543 to a coherent interconnect. 544 545 If a Cortex-A53 processor is executing a store or prefetch for 546 write instruction at the same time as a processor in another 547 cluster is executing a cache maintenance operation to the same 548 address, then this erratum might cause a clean cache line to be 549 incorrectly marked as dirty. 550 551 The workaround promotes data cache clean instructions to 552 data cache clean-and-invalidate. 553 Please note that this option does not necessarily enable the 554 workaround, as it depends on the alternative framework, which will 555 only patch the kernel if an affected CPU is detected. 556 557 If unsure, say Y. 558 559config ARM64_ERRATUM_819472 560 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 561 default y 562 select ARM64_WORKAROUND_CLEAN_CACHE 563 help 564 This option adds an alternative code sequence to work around ARM 565 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 566 present when it is connected to a coherent interconnect. 567 568 If the processor is executing a load and store exclusive sequence at 569 the same time as a processor in another cluster is executing a cache 570 maintenance operation to the same address, then this erratum might 571 cause data corruption. 572 573 The workaround promotes data cache clean instructions to 574 data cache clean-and-invalidate. 575 Please note that this does not necessarily enable the workaround, 576 as it depends on the alternative framework, which will only patch 577 the kernel if an affected CPU is detected. 578 579 If unsure, say Y. 580 581config ARM64_ERRATUM_832075 582 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 583 default y 584 help 585 This option adds an alternative code sequence to work around ARM 586 erratum 832075 on Cortex-A57 parts up to r1p2. 587 588 Affected Cortex-A57 parts might deadlock when exclusive load/store 589 instructions to Write-Back memory are mixed with Device loads. 590 591 The workaround is to promote device loads to use Load-Acquire 592 semantics. 593 Please note that this does not necessarily enable the workaround, 594 as it depends on the alternative framework, which will only patch 595 the kernel if an affected CPU is detected. 596 597 If unsure, say Y. 598 599config ARM64_ERRATUM_834220 600 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 601 depends on KVM 602 help 603 This option adds an alternative code sequence to work around ARM 604 erratum 834220 on Cortex-A57 parts up to r1p2. 605 606 Affected Cortex-A57 parts might report a Stage 2 translation 607 fault as the result of a Stage 1 fault for load crossing a 608 page boundary when there is a permission or device memory 609 alignment fault at Stage 1 and a translation fault at Stage 2. 610 611 The workaround is to verify that the Stage 1 translation 612 doesn't generate a fault before handling the Stage 2 fault. 613 Please note that this does not necessarily enable the workaround, 614 as it depends on the alternative framework, which will only patch 615 the kernel if an affected CPU is detected. 616 617 If unsure, say N. 618 619config ARM64_ERRATUM_1742098 620 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 621 depends on COMPAT 622 default y 623 help 624 This option removes the AES hwcap for aarch32 user-space to 625 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 626 627 Affected parts may corrupt the AES state if an interrupt is 628 taken between a pair of AES instructions. These instructions 629 are only present if the cryptography extensions are present. 630 All software should have a fallback implementation for CPUs 631 that don't implement the cryptography extensions. 632 633 If unsure, say Y. 634 635config ARM64_ERRATUM_845719 636 bool "Cortex-A53: 845719: a load might read incorrect data" 637 depends on COMPAT 638 default y 639 help 640 This option adds an alternative code sequence to work around ARM 641 erratum 845719 on Cortex-A53 parts up to r0p4. 642 643 When running a compat (AArch32) userspace on an affected Cortex-A53 644 part, a load at EL0 from a virtual address that matches the bottom 32 645 bits of the virtual address used by a recent load at (AArch64) EL1 646 might return incorrect data. 647 648 The workaround is to write the contextidr_el1 register on exception 649 return to a 32-bit task. 650 Please note that this does not necessarily enable the workaround, 651 as it depends on the alternative framework, which will only patch 652 the kernel if an affected CPU is detected. 653 654 If unsure, say Y. 655 656config ARM64_ERRATUM_843419 657 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 658 default y 659 help 660 This option links the kernel with '--fix-cortex-a53-843419' and 661 enables PLT support to replace certain ADRP instructions, which can 662 cause subsequent memory accesses to use an incorrect address on 663 Cortex-A53 parts up to r0p4. 664 665 If unsure, say Y. 666 667config ARM64_ERRATUM_1024718 668 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 669 default y 670 help 671 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 672 673 Affected Cortex-A55 cores (all revisions) could cause incorrect 674 update of the hardware dirty bit when the DBM/AP bits are updated 675 without a break-before-make. The workaround is to disable the usage 676 of hardware DBM locally on the affected cores. CPUs not affected by 677 this erratum will continue to use the feature. 678 679 If unsure, say Y. 680 681config ARM64_ERRATUM_1418040 682 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 683 default y 684 depends on COMPAT 685 help 686 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 687 errata 1188873 and 1418040. 688 689 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 690 cause register corruption when accessing the timer registers 691 from AArch32 userspace. 692 693 If unsure, say Y. 694 695config ARM64_WORKAROUND_SPECULATIVE_AT 696 bool 697 698config ARM64_ERRATUM_1165522 699 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 700 default y 701 select ARM64_WORKAROUND_SPECULATIVE_AT 702 help 703 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 704 705 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 706 corrupted TLBs by speculating an AT instruction during a guest 707 context switch. 708 709 If unsure, say Y. 710 711config ARM64_ERRATUM_1319367 712 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 713 default y 714 select ARM64_WORKAROUND_SPECULATIVE_AT 715 help 716 This option adds work arounds for ARM Cortex-A57 erratum 1319537 717 and A72 erratum 1319367 718 719 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 720 speculating an AT instruction during a guest context switch. 721 722 If unsure, say Y. 723 724config ARM64_ERRATUM_1530923 725 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 726 default y 727 select ARM64_WORKAROUND_SPECULATIVE_AT 728 help 729 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 730 731 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 732 corrupted TLBs by speculating an AT instruction during a guest 733 context switch. 734 735 If unsure, say Y. 736 737config ARM64_WORKAROUND_REPEAT_TLBI 738 bool 739 740config ARM64_ERRATUM_2441007 741 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 742 select ARM64_WORKAROUND_REPEAT_TLBI 743 help 744 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 745 746 Under very rare circumstances, affected Cortex-A55 CPUs 747 may not handle a race between a break-before-make sequence on one 748 CPU, and another CPU accessing the same page. This could allow a 749 store to a page that has been unmapped. 750 751 Work around this by adding the affected CPUs to the list that needs 752 TLB sequences to be done twice. 753 754 If unsure, say N. 755 756config ARM64_ERRATUM_1286807 757 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 758 select ARM64_WORKAROUND_REPEAT_TLBI 759 help 760 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 761 762 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 763 address for a cacheable mapping of a location is being 764 accessed by a core while another core is remapping the virtual 765 address to a new physical page using the recommended 766 break-before-make sequence, then under very rare circumstances 767 TLBI+DSB completes before a read using the translation being 768 invalidated has been observed by other observers. The 769 workaround repeats the TLBI+DSB operation. 770 771 If unsure, say N. 772 773config ARM64_ERRATUM_1463225 774 bool "Cortex-A76: Software Step might prevent interrupt recognition" 775 default y 776 help 777 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 778 779 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 780 of a system call instruction (SVC) can prevent recognition of 781 subsequent interrupts when software stepping is disabled in the 782 exception handler of the system call and either kernel debugging 783 is enabled or VHE is in use. 784 785 Work around the erratum by triggering a dummy step exception 786 when handling a system call from a task that is being stepped 787 in a VHE configuration of the kernel. 788 789 If unsure, say Y. 790 791config ARM64_ERRATUM_1542419 792 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 793 help 794 This option adds a workaround for ARM Neoverse-N1 erratum 795 1542419. 796 797 Affected Neoverse-N1 cores could execute a stale instruction when 798 modified by another CPU. The workaround depends on a firmware 799 counterpart. 800 801 Workaround the issue by hiding the DIC feature from EL0. This 802 forces user-space to perform cache maintenance. 803 804 If unsure, say N. 805 806config ARM64_ERRATUM_1508412 807 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 808 default y 809 help 810 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 811 812 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 813 of a store-exclusive or read of PAR_EL1 and a load with device or 814 non-cacheable memory attributes. The workaround depends on a firmware 815 counterpart. 816 817 KVM guests must also have the workaround implemented or they can 818 deadlock the system. 819 820 Work around the issue by inserting DMB SY barriers around PAR_EL1 821 register reads and warning KVM users. The DMB barrier is sufficient 822 to prevent a speculative PAR_EL1 read. 823 824 If unsure, say Y. 825 826config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 827 bool 828 829config ARM64_ERRATUM_2051678 830 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 831 default y 832 help 833 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 834 Affected Cortex-A510 might not respect the ordering rules for 835 hardware update of the page table's dirty bit. The workaround 836 is to not enable the feature on affected CPUs. 837 838 If unsure, say Y. 839 840config ARM64_ERRATUM_2077057 841 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 842 default y 843 help 844 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 845 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 846 expected, but a Pointer Authentication trap is taken instead. The 847 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 848 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 849 850 This can only happen when EL2 is stepping EL1. 851 852 When these conditions occur, the SPSR_EL2 value is unchanged from the 853 previous guest entry, and can be restored from the in-memory copy. 854 855 If unsure, say Y. 856 857config ARM64_ERRATUM_2658417 858 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 859 default y 860 help 861 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 862 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 863 BFMMLA or VMMLA instructions in rare circumstances when a pair of 864 A510 CPUs are using shared neon hardware. As the sharing is not 865 discoverable by the kernel, hide the BF16 HWCAP to indicate that 866 user-space should not be using these instructions. 867 868 If unsure, say Y. 869 870config ARM64_ERRATUM_2119858 871 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 872 default y 873 depends on CORESIGHT_TRBE 874 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 875 help 876 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 877 878 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 879 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 880 the event of a WRAP event. 881 882 Work around the issue by always making sure we move the TRBPTR_EL1 by 883 256 bytes before enabling the buffer and filling the first 256 bytes of 884 the buffer with ETM ignore packets upon disabling. 885 886 If unsure, say Y. 887 888config ARM64_ERRATUM_2139208 889 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 890 default y 891 depends on CORESIGHT_TRBE 892 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 893 help 894 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 895 896 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 897 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 898 the event of a WRAP event. 899 900 Work around the issue by always making sure we move the TRBPTR_EL1 by 901 256 bytes before enabling the buffer and filling the first 256 bytes of 902 the buffer with ETM ignore packets upon disabling. 903 904 If unsure, say Y. 905 906config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 907 bool 908 909config ARM64_ERRATUM_2054223 910 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 911 default y 912 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 913 help 914 Enable workaround for ARM Cortex-A710 erratum 2054223 915 916 Affected cores may fail to flush the trace data on a TSB instruction, when 917 the PE is in trace prohibited state. This will cause losing a few bytes 918 of the trace cached. 919 920 Workaround is to issue two TSB consecutively on affected cores. 921 922 If unsure, say Y. 923 924config ARM64_ERRATUM_2067961 925 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 926 default y 927 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 928 help 929 Enable workaround for ARM Neoverse-N2 erratum 2067961 930 931 Affected cores may fail to flush the trace data on a TSB instruction, when 932 the PE is in trace prohibited state. This will cause losing a few bytes 933 of the trace cached. 934 935 Workaround is to issue two TSB consecutively on affected cores. 936 937 If unsure, say Y. 938 939config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 940 bool 941 942config ARM64_ERRATUM_2253138 943 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 944 depends on CORESIGHT_TRBE 945 default y 946 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 947 help 948 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 949 950 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 951 for TRBE. Under some conditions, the TRBE might generate a write to the next 952 virtually addressed page following the last page of the TRBE address space 953 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 954 955 Work around this in the driver by always making sure that there is a 956 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 957 958 If unsure, say Y. 959 960config ARM64_ERRATUM_2224489 961 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 962 depends on CORESIGHT_TRBE 963 default y 964 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 965 help 966 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 967 968 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 969 for TRBE. Under some conditions, the TRBE might generate a write to the next 970 virtually addressed page following the last page of the TRBE address space 971 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 972 973 Work around this in the driver by always making sure that there is a 974 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 975 976 If unsure, say Y. 977 978config ARM64_ERRATUM_2441009 979 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 980 select ARM64_WORKAROUND_REPEAT_TLBI 981 help 982 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 983 984 Under very rare circumstances, affected Cortex-A510 CPUs 985 may not handle a race between a break-before-make sequence on one 986 CPU, and another CPU accessing the same page. This could allow a 987 store to a page that has been unmapped. 988 989 Work around this by adding the affected CPUs to the list that needs 990 TLB sequences to be done twice. 991 992 If unsure, say N. 993 994config ARM64_ERRATUM_2064142 995 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 996 depends on CORESIGHT_TRBE 997 default y 998 help 999 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 1000 1001 Affected Cortex-A510 core might fail to write into system registers after the 1002 TRBE has been disabled. Under some conditions after the TRBE has been disabled 1003 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 1004 and TRBTRG_EL1 will be ignored and will not be effected. 1005 1006 Work around this in the driver by executing TSB CSYNC and DSB after collection 1007 is stopped and before performing a system register write to one of the affected 1008 registers. 1009 1010 If unsure, say Y. 1011 1012config ARM64_ERRATUM_2038923 1013 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 1014 depends on CORESIGHT_TRBE 1015 default y 1016 help 1017 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 1018 1019 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 1020 prohibited within the CPU. As a result, the trace buffer or trace buffer state 1021 might be corrupted. This happens after TRBE buffer has been enabled by setting 1022 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 1023 execution changes from a context, in which trace is prohibited to one where it 1024 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1025 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1026 the trace buffer state might be corrupted. 1027 1028 Work around this in the driver by preventing an inconsistent view of whether the 1029 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1030 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1031 two ISB instructions if no ERET is to take place. 1032 1033 If unsure, say Y. 1034 1035config ARM64_ERRATUM_1902691 1036 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1037 depends on CORESIGHT_TRBE 1038 default y 1039 help 1040 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1041 1042 Affected Cortex-A510 core might cause trace data corruption, when being written 1043 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1044 trace data. 1045 1046 Work around this problem in the driver by just preventing TRBE initialization on 1047 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1048 on such implementations. This will cover the kernel for any firmware that doesn't 1049 do this already. 1050 1051 If unsure, say Y. 1052 1053config ARM64_ERRATUM_2457168 1054 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1055 depends on ARM64_AMU_EXTN 1056 default y 1057 help 1058 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1059 1060 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1061 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1062 incorrectly giving a significantly higher output value. 1063 1064 Work around this problem by returning 0 when reading the affected counter in 1065 key locations that results in disabling all users of this counter. This effect 1066 is the same to firmware disabling affected counters. 1067 1068 If unsure, say Y. 1069 1070config ARM64_ERRATUM_2645198 1071 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1072 default y 1073 help 1074 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1075 1076 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1077 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1078 next instruction abort caused by permission fault. 1079 1080 Only user-space does executable to non-executable permission transition via 1081 mprotect() system call. Workaround the problem by doing a break-before-make 1082 TLB invalidation, for all changes to executable user space mappings. 1083 1084 If unsure, say Y. 1085 1086config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1087 bool 1088 1089config ARM64_ERRATUM_2966298 1090 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1091 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1092 default y 1093 help 1094 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1095 1096 On an affected Cortex-A520 core, a speculatively executed unprivileged 1097 load might leak data from a privileged level via a cache side channel. 1098 1099 Work around this problem by executing a TLBI before returning to EL0. 1100 1101 If unsure, say Y. 1102 1103config ARM64_ERRATUM_3117295 1104 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1105 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1106 default y 1107 help 1108 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1109 1110 On an affected Cortex-A510 core, a speculatively executed unprivileged 1111 load might leak data from a privileged level via a cache side channel. 1112 1113 Work around this problem by executing a TLBI before returning to EL0. 1114 1115 If unsure, say Y. 1116 1117config ARM64_ERRATUM_3194386 1118 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1119 default y 1120 help 1121 This option adds the workaround for the following errata: 1122 1123 * ARM Cortex-A76 erratum 3324349 1124 * ARM Cortex-A77 erratum 3324348 1125 * ARM Cortex-A78 erratum 3324344 1126 * ARM Cortex-A78C erratum 3324346 1127 * ARM Cortex-A78C erratum 3324347 1128 * ARM Cortex-A710 erratam 3324338 1129 * ARM Cortex-A715 errartum 3456084 1130 * ARM Cortex-A720 erratum 3456091 1131 * ARM Cortex-A725 erratum 3456106 1132 * ARM Cortex-X1 erratum 3324344 1133 * ARM Cortex-X1C erratum 3324346 1134 * ARM Cortex-X2 erratum 3324338 1135 * ARM Cortex-X3 erratum 3324335 1136 * ARM Cortex-X4 erratum 3194386 1137 * ARM Cortex-X925 erratum 3324334 1138 * ARM Neoverse-N1 erratum 3324349 1139 * ARM Neoverse N2 erratum 3324339 1140 * ARM Neoverse-N3 erratum 3456111 1141 * ARM Neoverse-V1 erratum 3324341 1142 * ARM Neoverse V2 erratum 3324336 1143 * ARM Neoverse-V3 erratum 3312417 1144 * ARM Neoverse-V3AE erratum 3312417 1145 1146 On affected cores "MSR SSBS, #0" instructions may not affect 1147 subsequent speculative instructions, which may permit unexepected 1148 speculative store bypassing. 1149 1150 Work around this problem by placing a Speculation Barrier (SB) or 1151 Instruction Synchronization Barrier (ISB) after kernel changes to 1152 SSBS. The presence of the SSBS special-purpose register is hidden 1153 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1154 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1155 1156 If unsure, say Y. 1157 1158config CAVIUM_ERRATUM_22375 1159 bool "Cavium erratum 22375, 24313" 1160 default y 1161 help 1162 Enable workaround for errata 22375 and 24313. 1163 1164 This implements two gicv3-its errata workarounds for ThunderX. Both 1165 with a small impact affecting only ITS table allocation. 1166 1167 erratum 22375: only alloc 8MB table size 1168 erratum 24313: ignore memory access type 1169 1170 The fixes are in ITS initialization and basically ignore memory access 1171 type and table size provided by the TYPER and BASER registers. 1172 1173 If unsure, say Y. 1174 1175config CAVIUM_ERRATUM_23144 1176 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1177 depends on NUMA 1178 default y 1179 help 1180 ITS SYNC command hang for cross node io and collections/cpu mapping. 1181 1182 If unsure, say Y. 1183 1184config CAVIUM_ERRATUM_23154 1185 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1186 default y 1187 help 1188 The ThunderX GICv3 implementation requires a modified version for 1189 reading the IAR status to ensure data synchronization 1190 (access to icc_iar1_el1 is not sync'ed before and after). 1191 1192 It also suffers from erratum 38545 (also present on Marvell's 1193 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1194 spuriously presented to the CPU interface. 1195 1196 If unsure, say Y. 1197 1198config CAVIUM_ERRATUM_27456 1199 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1200 default y 1201 help 1202 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1203 instructions may cause the icache to become corrupted if it 1204 contains data for a non-current ASID. The fix is to 1205 invalidate the icache when changing the mm context. 1206 1207 If unsure, say Y. 1208 1209config CAVIUM_ERRATUM_30115 1210 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1211 default y 1212 help 1213 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1214 1.2, and T83 Pass 1.0, KVM guest execution may disable 1215 interrupts in host. Trapping both GICv3 group-0 and group-1 1216 accesses sidesteps the issue. 1217 1218 If unsure, say Y. 1219 1220config CAVIUM_TX2_ERRATUM_219 1221 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1222 default y 1223 help 1224 On Cavium ThunderX2, a load, store or prefetch instruction between a 1225 TTBR update and the corresponding context synchronizing operation can 1226 cause a spurious Data Abort to be delivered to any hardware thread in 1227 the CPU core. 1228 1229 Work around the issue by avoiding the problematic code sequence and 1230 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1231 trap handler performs the corresponding register access, skips the 1232 instruction and ensures context synchronization by virtue of the 1233 exception return. 1234 1235 If unsure, say Y. 1236 1237config FUJITSU_ERRATUM_010001 1238 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1239 default y 1240 help 1241 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1242 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1243 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1244 This fault occurs under a specific hardware condition when a 1245 load/store instruction performs an address translation using: 1246 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1247 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1248 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1249 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1250 1251 The workaround is to ensure these bits are clear in TCR_ELx. 1252 The workaround only affects the Fujitsu-A64FX. 1253 1254 If unsure, say Y. 1255 1256config HISILICON_ERRATUM_161600802 1257 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1258 default y 1259 help 1260 The HiSilicon Hip07 SoC uses the wrong redistributor base 1261 when issued ITS commands such as VMOVP and VMAPP, and requires 1262 a 128kB offset to be applied to the target address in this commands. 1263 1264 If unsure, say Y. 1265 1266config HISILICON_ERRATUM_162100801 1267 bool "Hip09 162100801 erratum support" 1268 default y 1269 help 1270 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1271 during unmapping operation, which will cause some vSGIs lost. 1272 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1273 after VMOVP. 1274 1275 If unsure, say Y. 1276 1277config QCOM_FALKOR_ERRATUM_1003 1278 bool "Falkor E1003: Incorrect translation due to ASID change" 1279 default y 1280 help 1281 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1282 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1283 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1284 then only for entries in the walk cache, since the leaf translation 1285 is unchanged. Work around the erratum by invalidating the walk cache 1286 entries for the trampoline before entering the kernel proper. 1287 1288config QCOM_FALKOR_ERRATUM_1009 1289 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1290 default y 1291 select ARM64_WORKAROUND_REPEAT_TLBI 1292 help 1293 On Falkor v1, the CPU may prematurely complete a DSB following a 1294 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1295 one more time to fix the issue. 1296 1297 If unsure, say Y. 1298 1299config QCOM_QDF2400_ERRATUM_0065 1300 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1301 default y 1302 help 1303 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1304 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1305 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1306 1307 If unsure, say Y. 1308 1309config QCOM_FALKOR_ERRATUM_E1041 1310 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1311 default y 1312 help 1313 Falkor CPU may speculatively fetch instructions from an improper 1314 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1315 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1316 1317 If unsure, say Y. 1318 1319config NVIDIA_CARMEL_CNP_ERRATUM 1320 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1321 default y 1322 help 1323 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1324 invalidate shared TLB entries installed by a different core, as it would 1325 on standard ARM cores. 1326 1327 If unsure, say Y. 1328 1329config ROCKCHIP_ERRATUM_3568002 1330 bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" 1331 default y 1332 help 1333 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI 1334 addressing limited to the first 32bit of physical address space. 1335 1336 If unsure, say Y. 1337 1338config ROCKCHIP_ERRATUM_3588001 1339 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1340 default y 1341 help 1342 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1343 This means, that its sharability feature may not be used, even though it 1344 is supported by the IP itself. 1345 1346 If unsure, say Y. 1347 1348config SOCIONEXT_SYNQUACER_PREITS 1349 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1350 default y 1351 help 1352 Socionext Synquacer SoCs implement a separate h/w block to generate 1353 MSI doorbell writes with non-zero values for the device ID. 1354 1355 If unsure, say Y. 1356 1357endmenu # "ARM errata workarounds via the alternatives framework" 1358 1359choice 1360 prompt "Page size" 1361 default ARM64_4K_PAGES 1362 help 1363 Page size (translation granule) configuration. 1364 1365config ARM64_4K_PAGES 1366 bool "4KB" 1367 select HAVE_PAGE_SIZE_4KB 1368 help 1369 This feature enables 4KB pages support. 1370 1371config ARM64_16K_PAGES 1372 bool "16KB" 1373 select HAVE_PAGE_SIZE_16KB 1374 help 1375 The system will use 16KB pages support. AArch32 emulation 1376 requires applications compiled with 16K (or a multiple of 16K) 1377 aligned segments. 1378 1379config ARM64_64K_PAGES 1380 bool "64KB" 1381 select HAVE_PAGE_SIZE_64KB 1382 help 1383 This feature enables 64KB pages support (4KB by default) 1384 allowing only two levels of page tables and faster TLB 1385 look-up. AArch32 emulation requires applications compiled 1386 with 64K aligned segments. 1387 1388endchoice 1389 1390choice 1391 prompt "Virtual address space size" 1392 default ARM64_VA_BITS_52 1393 help 1394 Allows choosing one of multiple possible virtual address 1395 space sizes. The level of translation table is determined by 1396 a combination of page size and virtual address space size. 1397 1398config ARM64_VA_BITS_36 1399 bool "36-bit" if EXPERT 1400 depends on PAGE_SIZE_16KB 1401 1402config ARM64_VA_BITS_39 1403 bool "39-bit" 1404 depends on PAGE_SIZE_4KB 1405 1406config ARM64_VA_BITS_42 1407 bool "42-bit" 1408 depends on PAGE_SIZE_64KB 1409 1410config ARM64_VA_BITS_47 1411 bool "47-bit" 1412 depends on PAGE_SIZE_16KB 1413 1414config ARM64_VA_BITS_48 1415 bool "48-bit" 1416 1417config ARM64_VA_BITS_52 1418 bool "52-bit" 1419 help 1420 Enable 52-bit virtual addressing for userspace when explicitly 1421 requested via a hint to mmap(). The kernel will also use 52-bit 1422 virtual addresses for its own mappings (provided HW support for 1423 this feature is available, otherwise it reverts to 48-bit). 1424 1425 NOTE: Enabling 52-bit virtual addressing in conjunction with 1426 ARMv8.3 Pointer Authentication will result in the PAC being 1427 reduced from 7 bits to 3 bits, which may have a significant 1428 impact on its susceptibility to brute-force attacks. 1429 1430 If unsure, select 48-bit virtual addressing instead. 1431 1432endchoice 1433 1434config ARM64_FORCE_52BIT 1435 bool "Force 52-bit virtual addresses for userspace" 1436 depends on ARM64_VA_BITS_52 && EXPERT 1437 help 1438 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1439 to maintain compatibility with older software by providing 48-bit VAs 1440 unless a hint is supplied to mmap. 1441 1442 This configuration option disables the 48-bit compatibility logic, and 1443 forces all userspace addresses to be 52-bit on HW that supports it. One 1444 should only enable this configuration option for stress testing userspace 1445 memory management code. If unsure say N here. 1446 1447config ARM64_VA_BITS 1448 int 1449 default 36 if ARM64_VA_BITS_36 1450 default 39 if ARM64_VA_BITS_39 1451 default 42 if ARM64_VA_BITS_42 1452 default 47 if ARM64_VA_BITS_47 1453 default 48 if ARM64_VA_BITS_48 1454 default 52 if ARM64_VA_BITS_52 1455 1456choice 1457 prompt "Physical address space size" 1458 default ARM64_PA_BITS_48 1459 help 1460 Choose the maximum physical address range that the kernel will 1461 support. 1462 1463config ARM64_PA_BITS_48 1464 bool "48-bit" 1465 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1466 1467config ARM64_PA_BITS_52 1468 bool "52-bit" 1469 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1470 help 1471 Enable support for a 52-bit physical address space, introduced as 1472 part of the ARMv8.2-LPA extension. 1473 1474 With this enabled, the kernel will also continue to work on CPUs that 1475 do not support ARMv8.2-LPA, but with some added memory overhead (and 1476 minor performance overhead). 1477 1478endchoice 1479 1480config ARM64_PA_BITS 1481 int 1482 default 48 if ARM64_PA_BITS_48 1483 default 52 if ARM64_PA_BITS_52 1484 1485config ARM64_LPA2 1486 def_bool y 1487 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1488 1489choice 1490 prompt "Endianness" 1491 default CPU_LITTLE_ENDIAN 1492 help 1493 Select the endianness of data accesses performed by the CPU. Userspace 1494 applications will need to be compiled and linked for the endianness 1495 that is selected here. 1496 1497config CPU_BIG_ENDIAN 1498 bool "Build big-endian kernel" 1499 depends on BROKEN 1500 help 1501 Say Y if you plan on running a kernel with a big-endian userspace. 1502 1503config CPU_LITTLE_ENDIAN 1504 bool "Build little-endian kernel" 1505 help 1506 Say Y if you plan on running a kernel with a little-endian userspace. 1507 This is usually the case for distributions targeting arm64. 1508 1509endchoice 1510 1511config NR_CPUS 1512 int "Maximum number of CPUs (2-4096)" 1513 range 2 4096 1514 default "512" 1515 1516config HOTPLUG_CPU 1517 bool "Support for hot-pluggable CPUs" 1518 select GENERIC_IRQ_MIGRATION 1519 help 1520 Say Y here to experiment with turning CPUs off and on. CPUs 1521 can be controlled through /sys/devices/system/cpu. 1522 1523# Common NUMA Features 1524config NUMA 1525 bool "NUMA Memory Allocation and Scheduler Support" 1526 select GENERIC_ARCH_NUMA 1527 select OF_NUMA 1528 select HAVE_SETUP_PER_CPU_AREA 1529 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1530 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1531 select USE_PERCPU_NUMA_NODE_ID 1532 help 1533 Enable NUMA (Non-Uniform Memory Access) support. 1534 1535 The kernel will try to allocate memory used by a CPU on the 1536 local memory of the CPU and add some more 1537 NUMA awareness to the kernel. 1538 1539config NODES_SHIFT 1540 int "Maximum NUMA Nodes (as a power of 2)" 1541 range 1 10 1542 default "4" 1543 depends on NUMA 1544 help 1545 Specify the maximum number of NUMA Nodes available on the target 1546 system. Increases memory reserved to accommodate various tables. 1547 1548source "kernel/Kconfig.hz" 1549 1550config ARCH_SPARSEMEM_ENABLE 1551 def_bool y 1552 select SPARSEMEM_VMEMMAP_ENABLE 1553 1554config HW_PERF_EVENTS 1555 def_bool y 1556 depends on ARM_PMU 1557 1558# Supported by clang >= 7.0 or GCC >= 12.0.0 1559config CC_HAVE_SHADOW_CALL_STACK 1560 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1561 1562config PARAVIRT 1563 bool "Enable paravirtualization code" 1564 help 1565 This changes the kernel so it can modify itself when it is run 1566 under a hypervisor, potentially improving performance significantly 1567 over full virtualization. 1568 1569config PARAVIRT_TIME_ACCOUNTING 1570 bool "Paravirtual steal time accounting" 1571 select PARAVIRT 1572 help 1573 Select this option to enable fine granularity task steal time 1574 accounting. Time spent executing other tasks in parallel with 1575 the current vCPU is discounted from the vCPU power. To account for 1576 that, there can be a small performance impact. 1577 1578 If in doubt, say N here. 1579 1580config ARCH_SUPPORTS_KEXEC 1581 def_bool PM_SLEEP_SMP 1582 1583config ARCH_SUPPORTS_KEXEC_FILE 1584 def_bool y 1585 1586config ARCH_SELECTS_KEXEC_FILE 1587 def_bool y 1588 depends on KEXEC_FILE 1589 select HAVE_IMA_KEXEC if IMA 1590 1591config ARCH_SUPPORTS_KEXEC_SIG 1592 def_bool y 1593 1594config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1595 def_bool y 1596 1597config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1598 def_bool y 1599 1600config ARCH_SUPPORTS_KEXEC_HANDOVER 1601 def_bool y 1602 1603config ARCH_SUPPORTS_CRASH_DUMP 1604 def_bool y 1605 1606config ARCH_DEFAULT_CRASH_DUMP 1607 def_bool y 1608 1609config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1610 def_bool CRASH_RESERVE 1611 1612config TRANS_TABLE 1613 def_bool y 1614 depends on HIBERNATION || KEXEC_CORE 1615 1616config XEN_DOM0 1617 def_bool y 1618 depends on XEN 1619 1620config XEN 1621 bool "Xen guest support on ARM64" 1622 depends on ARM64 && OF 1623 select SWIOTLB_XEN 1624 select PARAVIRT 1625 help 1626 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1627 1628# include/linux/mmzone.h requires the following to be true: 1629# 1630# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1631# 1632# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1633# 1634# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1635# ----+-------------------+--------------+----------------------+-------------------------+ 1636# 4K | 27 | 12 | 15 | 10 | 1637# 16K | 27 | 14 | 13 | 11 | 1638# 64K | 29 | 16 | 13 | 13 | 1639config ARCH_FORCE_MAX_ORDER 1640 int 1641 default "13" if ARM64_64K_PAGES 1642 default "11" if ARM64_16K_PAGES 1643 default "10" 1644 help 1645 The kernel page allocator limits the size of maximal physically 1646 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1647 defines the maximal power of two of number of pages that can be 1648 allocated as a single contiguous block. This option allows 1649 overriding the default setting when ability to allocate very 1650 large blocks of physically contiguous memory is required. 1651 1652 The maximal size of allocation cannot exceed the size of the 1653 section, so the value of MAX_PAGE_ORDER should satisfy 1654 1655 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1656 1657 Don't change if unsure. 1658 1659config UNMAP_KERNEL_AT_EL0 1660 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1661 default y 1662 help 1663 Speculation attacks against some high-performance processors can 1664 be used to bypass MMU permission checks and leak kernel data to 1665 userspace. This can be defended against by unmapping the kernel 1666 when running in userspace, mapping it back in on exception entry 1667 via a trampoline page in the vector table. 1668 1669 If unsure, say Y. 1670 1671config MITIGATE_SPECTRE_BRANCH_HISTORY 1672 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1673 default y 1674 help 1675 Speculation attacks against some high-performance processors can 1676 make use of branch history to influence future speculation. 1677 When taking an exception from user-space, a sequence of branches 1678 or a firmware call overwrites the branch history. 1679 1680config ARM64_SW_TTBR0_PAN 1681 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1682 depends on !KCSAN 1683 select ARM64_PAN 1684 help 1685 Enabling this option prevents the kernel from accessing 1686 user-space memory directly by pointing TTBR0_EL1 to a reserved 1687 zeroed area and reserved ASID. The user access routines 1688 restore the valid TTBR0_EL1 temporarily. 1689 1690config ARM64_TAGGED_ADDR_ABI 1691 bool "Enable the tagged user addresses syscall ABI" 1692 default y 1693 help 1694 When this option is enabled, user applications can opt in to a 1695 relaxed ABI via prctl() allowing tagged addresses to be passed 1696 to system calls as pointer arguments. For details, see 1697 Documentation/arch/arm64/tagged-address-abi.rst. 1698 1699menuconfig COMPAT 1700 bool "Kernel support for 32-bit EL0" 1701 depends on ARM64_4K_PAGES || EXPERT 1702 select HAVE_UID16 1703 select OLD_SIGSUSPEND3 1704 select COMPAT_OLD_SIGACTION 1705 help 1706 This option enables support for a 32-bit EL0 running under a 64-bit 1707 kernel at EL1. AArch32-specific components such as system calls, 1708 the user helper functions, VFP support and the ptrace interface are 1709 handled appropriately by the kernel. 1710 1711 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1712 that you will only be able to execute AArch32 binaries that were compiled 1713 with page size aligned segments. 1714 1715 If you want to execute 32-bit userspace applications, say Y. 1716 1717if COMPAT 1718 1719config KUSER_HELPERS 1720 bool "Enable kuser helpers page for 32-bit applications" 1721 default y 1722 help 1723 Warning: disabling this option may break 32-bit user programs. 1724 1725 Provide kuser helpers to compat tasks. The kernel provides 1726 helper code to userspace in read only form at a fixed location 1727 to allow userspace to be independent of the CPU type fitted to 1728 the system. This permits binaries to be run on ARMv4 through 1729 to ARMv8 without modification. 1730 1731 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1732 1733 However, the fixed address nature of these helpers can be used 1734 by ROP (return orientated programming) authors when creating 1735 exploits. 1736 1737 If all of the binaries and libraries which run on your platform 1738 are built specifically for your platform, and make no use of 1739 these helpers, then you can turn this option off to hinder 1740 such exploits. However, in that case, if a binary or library 1741 relying on those helpers is run, it will not function correctly. 1742 1743 Say N here only if you are absolutely certain that you do not 1744 need these helpers; otherwise, the safe option is to say Y. 1745 1746config COMPAT_VDSO 1747 bool "Enable vDSO for 32-bit applications" 1748 depends on !CPU_BIG_ENDIAN 1749 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1750 default y 1751 help 1752 Place in the process address space of 32-bit applications an 1753 ELF shared object providing fast implementations of gettimeofday 1754 and clock_gettime. 1755 1756 You must have a 32-bit build of glibc 2.22 or later for programs 1757 to seamlessly take advantage of this. 1758 1759config THUMB2_COMPAT_VDSO 1760 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1761 depends on COMPAT_VDSO 1762 default y 1763 help 1764 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1765 otherwise with '-marm'. 1766 1767config COMPAT_ALIGNMENT_FIXUPS 1768 bool "Fix up misaligned multi-word loads and stores in user space" 1769 1770menuconfig ARMV8_DEPRECATED 1771 bool "Emulate deprecated/obsolete ARMv8 instructions" 1772 depends on SYSCTL 1773 help 1774 Legacy software support may require certain instructions 1775 that have been deprecated or obsoleted in the architecture. 1776 1777 Enable this config to enable selective emulation of these 1778 features. 1779 1780 If unsure, say Y 1781 1782if ARMV8_DEPRECATED 1783 1784config SWP_EMULATION 1785 bool "Emulate SWP/SWPB instructions" 1786 help 1787 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1788 they are always undefined. Say Y here to enable software 1789 emulation of these instructions for userspace using LDXR/STXR. 1790 This feature can be controlled at runtime with the abi.swp 1791 sysctl which is disabled by default. 1792 1793 In some older versions of glibc [<=2.8] SWP is used during futex 1794 trylock() operations with the assumption that the code will not 1795 be preempted. This invalid assumption may be more likely to fail 1796 with SWP emulation enabled, leading to deadlock of the user 1797 application. 1798 1799 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1800 on an external transaction monitoring block called a global 1801 monitor to maintain update atomicity. If your system does not 1802 implement a global monitor, this option can cause programs that 1803 perform SWP operations to uncached memory to deadlock. 1804 1805 If unsure, say Y 1806 1807config CP15_BARRIER_EMULATION 1808 bool "Emulate CP15 Barrier instructions" 1809 help 1810 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1811 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1812 strongly recommended to use the ISB, DSB, and DMB 1813 instructions instead. 1814 1815 Say Y here to enable software emulation of these 1816 instructions for AArch32 userspace code. When this option is 1817 enabled, CP15 barrier usage is traced which can help 1818 identify software that needs updating. This feature can be 1819 controlled at runtime with the abi.cp15_barrier sysctl. 1820 1821 If unsure, say Y 1822 1823config SETEND_EMULATION 1824 bool "Emulate SETEND instruction" 1825 help 1826 The SETEND instruction alters the data-endianness of the 1827 AArch32 EL0, and is deprecated in ARMv8. 1828 1829 Say Y here to enable software emulation of the instruction 1830 for AArch32 userspace code. This feature can be controlled 1831 at runtime with the abi.setend sysctl. 1832 1833 Note: All the cpus on the system must have mixed endian support at EL0 1834 for this feature to be enabled. If a new CPU - which doesn't support mixed 1835 endian - is hotplugged in after this feature has been enabled, there could 1836 be unexpected results in the applications. 1837 1838 If unsure, say Y 1839endif # ARMV8_DEPRECATED 1840 1841endif # COMPAT 1842 1843menu "ARMv8.1 architectural features" 1844 1845config ARM64_HW_AFDBM 1846 bool "Support for hardware updates of the Access and Dirty page flags" 1847 default y 1848 help 1849 The ARMv8.1 architecture extensions introduce support for 1850 hardware updates of the access and dirty information in page 1851 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1852 capable processors, accesses to pages with PTE_AF cleared will 1853 set this bit instead of raising an access flag fault. 1854 Similarly, writes to read-only pages with the DBM bit set will 1855 clear the read-only bit (AP[2]) instead of raising a 1856 permission fault. 1857 1858 Kernels built with this configuration option enabled continue 1859 to work on pre-ARMv8.1 hardware and the performance impact is 1860 minimal. If unsure, say Y. 1861 1862config ARM64_PAN 1863 bool "Enable support for Privileged Access Never (PAN)" 1864 default y 1865 help 1866 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1867 prevents the kernel or hypervisor from accessing user-space (EL0) 1868 memory directly. 1869 1870 Choosing this option will cause any unprotected (not using 1871 copy_to_user et al) memory access to fail with a permission fault. 1872 1873 The feature is detected at runtime, and will remain as a 'nop' 1874 instruction if the cpu does not implement the feature. 1875 1876config ARM64_LSE_ATOMICS 1877 bool 1878 default ARM64_USE_LSE_ATOMICS 1879 1880config ARM64_USE_LSE_ATOMICS 1881 bool "Atomic instructions" 1882 default y 1883 help 1884 As part of the Large System Extensions, ARMv8.1 introduces new 1885 atomic instructions that are designed specifically to scale in 1886 very large systems. 1887 1888 Say Y here to make use of these instructions for the in-kernel 1889 atomic routines. This incurs a small overhead on CPUs that do 1890 not support these instructions. 1891 1892endmenu # "ARMv8.1 architectural features" 1893 1894menu "ARMv8.2 architectural features" 1895 1896config ARM64_PMEM 1897 bool "Enable support for persistent memory" 1898 select ARCH_HAS_PMEM_API 1899 select ARCH_HAS_UACCESS_FLUSHCACHE 1900 help 1901 Say Y to enable support for the persistent memory API based on the 1902 ARMv8.2 DCPoP feature. 1903 1904 The feature is detected at runtime, and the kernel will use DC CVAC 1905 operations if DC CVAP is not supported (following the behaviour of 1906 DC CVAP itself if the system does not define a point of persistence). 1907 1908config ARM64_RAS_EXTN 1909 bool "Enable support for RAS CPU Extensions" 1910 default y 1911 help 1912 CPUs that support the Reliability, Availability and Serviceability 1913 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1914 errors, classify them and report them to software. 1915 1916 On CPUs with these extensions system software can use additional 1917 barriers to determine if faults are pending and read the 1918 classification from a new set of registers. 1919 1920 Selecting this feature will allow the kernel to use these barriers 1921 and access the new registers if the system supports the extension. 1922 Platform RAS features may additionally depend on firmware support. 1923 1924config ARM64_CNP 1925 bool "Enable support for Common Not Private (CNP) translations" 1926 default y 1927 help 1928 Common Not Private (CNP) allows translation table entries to 1929 be shared between different PEs in the same inner shareable 1930 domain, so the hardware can use this fact to optimise the 1931 caching of such entries in the TLB. 1932 1933 Selecting this option allows the CNP feature to be detected 1934 at runtime, and does not affect PEs that do not implement 1935 this feature. 1936 1937endmenu # "ARMv8.2 architectural features" 1938 1939menu "ARMv8.3 architectural features" 1940 1941config ARM64_PTR_AUTH 1942 bool "Enable support for pointer authentication" 1943 default y 1944 help 1945 Pointer authentication (part of the ARMv8.3 Extensions) provides 1946 instructions for signing and authenticating pointers against secret 1947 keys, which can be used to mitigate Return Oriented Programming (ROP) 1948 and other attacks. 1949 1950 This option enables these instructions at EL0 (i.e. for userspace). 1951 Choosing this option will cause the kernel to initialise secret keys 1952 for each process at exec() time, with these keys being 1953 context-switched along with the process. 1954 1955 The feature is detected at runtime. If the feature is not present in 1956 hardware it will not be advertised to userspace/KVM guest nor will it 1957 be enabled. 1958 1959 If the feature is present on the boot CPU but not on a late CPU, then 1960 the late CPU will be parked. Also, if the boot CPU does not have 1961 address auth and the late CPU has then the late CPU will still boot 1962 but with the feature disabled. On such a system, this option should 1963 not be selected. 1964 1965config ARM64_PTR_AUTH_KERNEL 1966 bool "Use pointer authentication for kernel" 1967 default y 1968 depends on ARM64_PTR_AUTH 1969 # Modern compilers insert a .note.gnu.property section note for PAC 1970 # which is only understood by binutils starting with version 2.33.1. 1971 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1972 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1973 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1974 help 1975 If the compiler supports the -mbranch-protection or 1976 -msign-return-address flag (e.g. GCC 7 or later), then this option 1977 will cause the kernel itself to be compiled with return address 1978 protection. In this case, and if the target hardware is known to 1979 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1980 disabled with minimal loss of protection. 1981 1982 This feature works with FUNCTION_GRAPH_TRACER option only if 1983 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1984 1985config CC_HAS_BRANCH_PROT_PAC_RET 1986 # GCC 9 or later, clang 8 or later 1987 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1988 1989config AS_HAS_CFI_NEGATE_RA_STATE 1990 # binutils 2.34+ 1991 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1992 1993endmenu # "ARMv8.3 architectural features" 1994 1995menu "ARMv8.4 architectural features" 1996 1997config ARM64_AMU_EXTN 1998 bool "Enable support for the Activity Monitors Unit CPU extension" 1999 default y 2000 help 2001 The activity monitors extension is an optional extension introduced 2002 by the ARMv8.4 CPU architecture. This enables support for version 1 2003 of the activity monitors architecture, AMUv1. 2004 2005 To enable the use of this extension on CPUs that implement it, say Y. 2006 2007 Note that for architectural reasons, firmware _must_ implement AMU 2008 support when running on CPUs that present the activity monitors 2009 extension. The required support is present in: 2010 * Version 1.5 and later of the ARM Trusted Firmware 2011 2012 For kernels that have this configuration enabled but boot with broken 2013 firmware, you may need to say N here until the firmware is fixed. 2014 Otherwise you may experience firmware panics or lockups when 2015 accessing the counter registers. Even if you are not observing these 2016 symptoms, the values returned by the register reads might not 2017 correctly reflect reality. Most commonly, the value read will be 0, 2018 indicating that the counter is not enabled. 2019 2020config ARM64_TLB_RANGE 2021 bool "Enable support for tlbi range feature" 2022 default y 2023 help 2024 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2025 range of input addresses. 2026 2027config ARM64_MPAM 2028 bool "Enable support for MPAM" 2029 select ARM64_MPAM_DRIVER if EXPERT # does nothing yet 2030 select ACPI_MPAM if ACPI 2031 help 2032 Memory System Resource Partitioning and Monitoring (MPAM) is an 2033 optional extension to the Arm architecture that allows each 2034 transaction issued to the memory system to be labelled with a 2035 Partition identifier (PARTID) and Performance Monitoring Group 2036 identifier (PMG). 2037 2038 Memory system components, such as the caches, can be configured with 2039 policies to control how much of various physical resources (such as 2040 memory bandwidth or cache memory) the transactions labelled with each 2041 PARTID can consume. Depending on the capabilities of the hardware, 2042 the PARTID and PMG can also be used as filtering criteria to measure 2043 the memory system resource consumption of different parts of a 2044 workload. 2045 2046 Use of this extension requires CPU support, support in the 2047 Memory System Components (MSC), and a description from firmware 2048 of where the MSCs are in the address space. 2049 2050 MPAM is exposed to user-space via the resctrl pseudo filesystem. 2051 2052endmenu # "ARMv8.4 architectural features" 2053 2054menu "ARMv8.5 architectural features" 2055 2056config AS_HAS_ARMV8_5 2057 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2058 2059config ARM64_BTI 2060 bool "Branch Target Identification support" 2061 default y 2062 help 2063 Branch Target Identification (part of the ARMv8.5 Extensions) 2064 provides a mechanism to limit the set of locations to which computed 2065 branch instructions such as BR or BLR can jump. 2066 2067 To make use of BTI on CPUs that support it, say Y. 2068 2069 BTI is intended to provide complementary protection to other control 2070 flow integrity protection mechanisms, such as the Pointer 2071 authentication mechanism provided as part of the ARMv8.3 Extensions. 2072 For this reason, it does not make sense to enable this option without 2073 also enabling support for pointer authentication. Thus, when 2074 enabling this option you should also select ARM64_PTR_AUTH=y. 2075 2076 Userspace binaries must also be specifically compiled to make use of 2077 this mechanism. If you say N here or the hardware does not support 2078 BTI, such binaries can still run, but you get no additional 2079 enforcement of branch destinations. 2080 2081config ARM64_BTI_KERNEL 2082 bool "Use Branch Target Identification for kernel" 2083 default y 2084 depends on ARM64_BTI 2085 depends on ARM64_PTR_AUTH_KERNEL 2086 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2087 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2088 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2089 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2090 depends on !CC_IS_GCC 2091 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2092 help 2093 Build the kernel with Branch Target Identification annotations 2094 and enable enforcement of this for kernel code. When this option 2095 is enabled and the system supports BTI all kernel code including 2096 modular code must have BTI enabled. 2097 2098config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2099 # GCC 9 or later, clang 8 or later 2100 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2101 2102config ARM64_E0PD 2103 bool "Enable support for E0PD" 2104 default y 2105 help 2106 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2107 that EL0 accesses made via TTBR1 always fault in constant time, 2108 providing similar benefits to KASLR as those provided by KPTI, but 2109 with lower overhead and without disrupting legitimate access to 2110 kernel memory such as SPE. 2111 2112 This option enables E0PD for TTBR1 where available. 2113 2114config ARM64_AS_HAS_MTE 2115 # Initial support for MTE went in binutils 2.32.0, checked with 2116 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2117 # as a late addition to the final architecture spec (LDGM/STGM) 2118 # is only supported in the newer 2.32.x and 2.33 binutils 2119 # versions, hence the extra "stgm" instruction check below. 2120 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2121 2122config ARM64_MTE 2123 bool "Memory Tagging Extension support" 2124 default y 2125 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2126 depends on AS_HAS_ARMV8_5 2127 # Required for tag checking in the uaccess routines 2128 select ARM64_PAN 2129 select ARCH_HAS_SUBPAGE_FAULTS 2130 select ARCH_USES_HIGH_VMA_FLAGS 2131 select ARCH_USES_PG_ARCH_2 2132 select ARCH_USES_PG_ARCH_3 2133 help 2134 Memory Tagging (part of the ARMv8.5 Extensions) provides 2135 architectural support for run-time, always-on detection of 2136 various classes of memory error to aid with software debugging 2137 to eliminate vulnerabilities arising from memory-unsafe 2138 languages. 2139 2140 This option enables the support for the Memory Tagging 2141 Extension at EL0 (i.e. for userspace). 2142 2143 Selecting this option allows the feature to be detected at 2144 runtime. Any secondary CPU not implementing this feature will 2145 not be allowed a late bring-up. 2146 2147 Userspace binaries that want to use this feature must 2148 explicitly opt in. The mechanism for the userspace is 2149 described in: 2150 2151 Documentation/arch/arm64/memory-tagging-extension.rst. 2152 2153endmenu # "ARMv8.5 architectural features" 2154 2155menu "ARMv8.7 architectural features" 2156 2157config ARM64_EPAN 2158 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2159 default y 2160 depends on ARM64_PAN 2161 help 2162 Enhanced Privileged Access Never (EPAN) allows Privileged 2163 Access Never to be used with Execute-only mappings. 2164 2165 The feature is detected at runtime, and will remain disabled 2166 if the cpu does not implement the feature. 2167endmenu # "ARMv8.7 architectural features" 2168 2169config AS_HAS_MOPS 2170 def_bool $(as-instr,.arch_extension mops) 2171 2172menu "ARMv8.9 architectural features" 2173 2174config ARM64_POE 2175 prompt "Permission Overlay Extension" 2176 def_bool y 2177 select ARCH_USES_HIGH_VMA_FLAGS 2178 select ARCH_HAS_PKEYS 2179 help 2180 The Permission Overlay Extension is used to implement Memory 2181 Protection Keys. Memory Protection Keys provides a mechanism for 2182 enforcing page-based protections, but without requiring modification 2183 of the page tables when an application changes protection domains. 2184 2185 For details, see Documentation/core-api/protection-keys.rst 2186 2187 If unsure, say y. 2188 2189config ARCH_PKEY_BITS 2190 int 2191 default 3 2192 2193config ARM64_HAFT 2194 bool "Support for Hardware managed Access Flag for Table Descriptors" 2195 depends on ARM64_HW_AFDBM 2196 default y 2197 help 2198 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2199 Flag for Table descriptors. When enabled an architectural executed 2200 memory access will update the Access Flag in each Table descriptor 2201 which is accessed during the translation table walk and for which 2202 the Access Flag is 0. The Access Flag of the Table descriptor use 2203 the same bit of PTE_AF. 2204 2205 The feature will only be enabled if all the CPUs in the system 2206 support this feature. If unsure, say Y. 2207 2208endmenu # "ARMv8.9 architectural features" 2209 2210menu "ARMv9.4 architectural features" 2211 2212config ARM64_GCS 2213 bool "Enable support for Guarded Control Stack (GCS)" 2214 default y 2215 select ARCH_HAS_USER_SHADOW_STACK 2216 select ARCH_USES_HIGH_VMA_FLAGS 2217 help 2218 Guarded Control Stack (GCS) provides support for a separate 2219 stack with restricted access which contains only return 2220 addresses. This can be used to harden against some attacks 2221 by comparing return address used by the program with what is 2222 stored in the GCS, and may also be used to efficiently obtain 2223 the call stack for applications such as profiling. 2224 2225 The feature is detected at runtime, and will remain disabled 2226 if the system does not implement the feature. 2227 2228endmenu # "ARMv9.4 architectural features" 2229 2230config ARM64_SVE 2231 bool "ARM Scalable Vector Extension support" 2232 default y 2233 help 2234 The Scalable Vector Extension (SVE) is an extension to the AArch64 2235 execution state which complements and extends the SIMD functionality 2236 of the base architecture to support much larger vectors and to enable 2237 additional vectorisation opportunities. 2238 2239 To enable use of this extension on CPUs that implement it, say Y. 2240 2241 On CPUs that support the SVE2 extensions, this option will enable 2242 those too. 2243 2244 Note that for architectural reasons, firmware _must_ implement SVE 2245 support when running on SVE capable hardware. The required support 2246 is present in: 2247 2248 * version 1.5 and later of the ARM Trusted Firmware 2249 * the AArch64 boot wrapper since commit 5e1261e08abf 2250 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2251 2252 For other firmware implementations, consult the firmware documentation 2253 or vendor. 2254 2255 If you need the kernel to boot on SVE-capable hardware with broken 2256 firmware, you may need to say N here until you get your firmware 2257 fixed. Otherwise, you may experience firmware panics or lockups when 2258 booting the kernel. If unsure and you are not observing these 2259 symptoms, you should assume that it is safe to say Y. 2260 2261config ARM64_SME 2262 bool "ARM Scalable Matrix Extension support" 2263 default y 2264 depends on ARM64_SVE 2265 help 2266 The Scalable Matrix Extension (SME) is an extension to the AArch64 2267 execution state which utilises a substantial subset of the SVE 2268 instruction set, together with the addition of new architectural 2269 register state capable of holding two dimensional matrix tiles to 2270 enable various matrix operations. 2271 2272config ARM64_PSEUDO_NMI 2273 bool "Support for NMI-like interrupts" 2274 select ARM_GIC_V3 2275 help 2276 Adds support for mimicking Non-Maskable Interrupts through the use of 2277 GIC interrupt priority. This support requires version 3 or later of 2278 ARM GIC. 2279 2280 This high priority configuration for interrupts needs to be 2281 explicitly enabled by setting the kernel parameter 2282 "irqchip.gicv3_pseudo_nmi" to 1. 2283 2284 If unsure, say N 2285 2286if ARM64_PSEUDO_NMI 2287config ARM64_DEBUG_PRIORITY_MASKING 2288 bool "Debug interrupt priority masking" 2289 help 2290 This adds runtime checks to functions enabling/disabling 2291 interrupts when using priority masking. The additional checks verify 2292 the validity of ICC_PMR_EL1 when calling concerned functions. 2293 2294 If unsure, say N 2295endif # ARM64_PSEUDO_NMI 2296 2297config RELOCATABLE 2298 bool "Build a relocatable kernel image" if EXPERT 2299 select ARCH_HAS_RELR 2300 default y 2301 help 2302 This builds the kernel as a Position Independent Executable (PIE), 2303 which retains all relocation metadata required to relocate the 2304 kernel binary at runtime to a different virtual address than the 2305 address it was linked at. 2306 Since AArch64 uses the RELA relocation format, this requires a 2307 relocation pass at runtime even if the kernel is loaded at the 2308 same address it was linked at. 2309 2310config RANDOMIZE_BASE 2311 bool "Randomize the address of the kernel image" 2312 select RELOCATABLE 2313 help 2314 Randomizes the virtual address at which the kernel image is 2315 loaded, as a security feature that deters exploit attempts 2316 relying on knowledge of the location of kernel internals. 2317 2318 It is the bootloader's job to provide entropy, by passing a 2319 random u64 value in /chosen/kaslr-seed at kernel entry. 2320 2321 When booting via the UEFI stub, it will invoke the firmware's 2322 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2323 to the kernel proper. In addition, it will randomise the physical 2324 location of the kernel Image as well. 2325 2326 If unsure, say N. 2327 2328config RANDOMIZE_MODULE_REGION_FULL 2329 bool "Randomize the module region over a 2 GB range" 2330 depends on RANDOMIZE_BASE 2331 default y 2332 help 2333 Randomizes the location of the module region inside a 2 GB window 2334 covering the core kernel. This way, it is less likely for modules 2335 to leak information about the location of core kernel data structures 2336 but it does imply that function calls between modules and the core 2337 kernel will need to be resolved via veneers in the module PLT. 2338 2339 When this option is not set, the module region will be randomized over 2340 a limited range that contains the [_stext, _etext] interval of the 2341 core kernel, so branch relocations are almost always in range unless 2342 the region is exhausted. In this particular case of region 2343 exhaustion, modules might be able to fall back to a larger 2GB area. 2344 2345config CC_HAVE_STACKPROTECTOR_SYSREG 2346 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2347 2348config STACKPROTECTOR_PER_TASK 2349 def_bool y 2350 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2351 2352config UNWIND_PATCH_PAC_INTO_SCS 2353 bool "Enable shadow call stack dynamically using code patching" 2354 depends on CC_IS_CLANG 2355 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2356 depends on SHADOW_CALL_STACK 2357 select UNWIND_TABLES 2358 select DYNAMIC_SCS 2359 2360config ARM64_CONTPTE 2361 bool "Contiguous PTE mappings for user memory" if EXPERT 2362 depends on TRANSPARENT_HUGEPAGE 2363 default y 2364 help 2365 When enabled, user mappings are configured using the PTE contiguous 2366 bit, for any mappings that meet the size and alignment requirements. 2367 This reduces TLB pressure and improves performance. 2368 2369endmenu # "Kernel Features" 2370 2371menu "Boot options" 2372 2373config ARM64_ACPI_PARKING_PROTOCOL 2374 bool "Enable support for the ARM64 ACPI parking protocol" 2375 depends on ACPI 2376 help 2377 Enable support for the ARM64 ACPI parking protocol. If disabled 2378 the kernel will not allow booting through the ARM64 ACPI parking 2379 protocol even if the corresponding data is present in the ACPI 2380 MADT table. 2381 2382config CMDLINE 2383 string "Default kernel command string" 2384 default "" 2385 help 2386 Provide a set of default command-line options at build time by 2387 entering them here. As a minimum, you should specify the the 2388 root device (e.g. root=/dev/nfs). 2389 2390choice 2391 prompt "Kernel command line type" 2392 depends on CMDLINE != "" 2393 default CMDLINE_FROM_BOOTLOADER 2394 help 2395 Choose how the kernel will handle the provided default kernel 2396 command line string. 2397 2398config CMDLINE_FROM_BOOTLOADER 2399 bool "Use bootloader kernel arguments if available" 2400 help 2401 Uses the command-line options passed by the boot loader. If 2402 the boot loader doesn't provide any, the default kernel command 2403 string provided in CMDLINE will be used. 2404 2405config CMDLINE_FORCE 2406 bool "Always use the default kernel command string" 2407 help 2408 Always use the default kernel command string, even if the boot 2409 loader passes other arguments to the kernel. 2410 This is useful if you cannot or don't want to change the 2411 command-line options your boot loader passes to the kernel. 2412 2413endchoice 2414 2415config EFI_STUB 2416 bool 2417 2418config EFI 2419 bool "UEFI runtime support" 2420 depends on OF && !CPU_BIG_ENDIAN 2421 depends on KERNEL_MODE_NEON 2422 select ARCH_SUPPORTS_ACPI 2423 select LIBFDT 2424 select UCS2_STRING 2425 select EFI_PARAMS_FROM_FDT 2426 select EFI_RUNTIME_WRAPPERS 2427 select EFI_STUB 2428 select EFI_GENERIC_STUB 2429 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2430 default y 2431 help 2432 This option provides support for runtime services provided 2433 by UEFI firmware (such as non-volatile variables, realtime 2434 clock, and platform reset). A UEFI stub is also provided to 2435 allow the kernel to be booted as an EFI application. This 2436 is only useful on systems that have UEFI firmware. 2437 2438config COMPRESSED_INSTALL 2439 bool "Install compressed image by default" 2440 help 2441 This makes the regular "make install" install the compressed 2442 image we built, not the legacy uncompressed one. 2443 2444 You can check that a compressed image works for you by doing 2445 "make zinstall" first, and verifying that everything is fine 2446 in your environment before making "make install" do this for 2447 you. 2448 2449config DMI 2450 bool "Enable support for SMBIOS (DMI) tables" 2451 depends on EFI 2452 default y 2453 help 2454 This enables SMBIOS/DMI feature for systems. 2455 2456 This option is only useful on systems that have UEFI firmware. 2457 However, even with this option, the resultant kernel should 2458 continue to boot on existing non-UEFI platforms. 2459 2460endmenu # "Boot options" 2461 2462menu "Power management options" 2463 2464source "kernel/power/Kconfig" 2465 2466config ARCH_HIBERNATION_POSSIBLE 2467 def_bool y 2468 depends on CPU_PM 2469 2470config ARCH_HIBERNATION_HEADER 2471 def_bool y 2472 depends on HIBERNATION 2473 2474config ARCH_SUSPEND_POSSIBLE 2475 def_bool y 2476 2477endmenu # "Power management options" 2478 2479menu "CPU Power Management" 2480 2481source "drivers/cpuidle/Kconfig" 2482 2483source "drivers/cpufreq/Kconfig" 2484 2485endmenu # "CPU Power Management" 2486 2487source "drivers/acpi/Kconfig" 2488 2489source "arch/arm64/kvm/Kconfig" 2490 2491source "kernel/livepatch/Kconfig" 2492