xref: /linux/arch/arm64/Kconfig (revision f69f5aab1fad379bbef9339f66bc8323daffe56e)
1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3	def_bool y
4	select ACPI_APMT if ACPI
5	select ACPI_CCA_REQUIRED if ACPI
6	select ACPI_GENERIC_GSI if ACPI
7	select ACPI_GTDT if ACPI
8	select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU
9	select ACPI_IORT if ACPI
10	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
11	select ACPI_MCFG if (ACPI && PCI)
12	select ACPI_SPCR_TABLE if ACPI
13	select ACPI_PPTT if ACPI
14	select ARCH_HAS_DEBUG_WX
15	select ARCH_BINFMT_ELF_EXTRA_PHDRS
16	select ARCH_BINFMT_ELF_STATE
17	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18	select ARCH_ENABLE_MEMORY_HOTPLUG
19	select ARCH_ENABLE_MEMORY_HOTREMOVE
20	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22	select ARCH_HAS_CACHE_LINE_SIZE
23	select ARCH_HAS_CC_PLATFORM
24	select ARCH_HAS_CRC32
25	select ARCH_HAS_CRC_T10DIF if KERNEL_MODE_NEON
26	select ARCH_HAS_CURRENT_STACK_POINTER
27	select ARCH_HAS_DEBUG_VIRTUAL
28	select ARCH_HAS_DEBUG_VM_PGTABLE
29	select ARCH_HAS_DMA_OPS if XEN
30	select ARCH_HAS_DMA_PREP_COHERENT
31	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
32	select ARCH_HAS_FAST_MULTIPLIER
33	select ARCH_HAS_FORTIFY_SOURCE
34	select ARCH_HAS_GCOV_PROFILE_ALL
35	select ARCH_HAS_GIGANTIC_PAGE
36	select ARCH_HAS_KCOV
37	select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON
38	select ARCH_HAS_KEEPINITRD
39	select ARCH_HAS_MEMBARRIER_SYNC_CORE
40	select ARCH_HAS_MEM_ENCRYPT
41	select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS
42	select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
43	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
44	select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT
45	select ARCH_HAS_PREEMPT_LAZY
46	select ARCH_HAS_PTDUMP
47	select ARCH_HAS_PTE_DEVMAP
48	select ARCH_HAS_PTE_SPECIAL
49	select ARCH_HAS_HW_PTE_YOUNG
50	select ARCH_HAS_SETUP_DMA_OPS
51	select ARCH_HAS_SET_DIRECT_MAP
52	select ARCH_HAS_SET_MEMORY
53	select ARCH_HAS_MEM_ENCRYPT
54	select ARCH_HAS_FORCE_DMA_UNENCRYPTED
55	select ARCH_STACKWALK
56	select ARCH_HAS_STRICT_KERNEL_RWX
57	select ARCH_HAS_STRICT_MODULE_RWX
58	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
59	select ARCH_HAS_SYNC_DMA_FOR_CPU
60	select ARCH_HAS_SYSCALL_WRAPPER
61	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
62	select ARCH_HAS_ZONE_DMA_SET if EXPERT
63	select ARCH_HAVE_ELF_PROT
64	select ARCH_HAVE_NMI_SAFE_CMPXCHG
65	select ARCH_HAVE_TRACE_MMIO_ACCESS
66	select ARCH_INLINE_READ_LOCK if !PREEMPTION
67	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
68	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
69	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
70	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
71	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
72	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
73	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
74	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
75	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
76	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
77	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
78	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
79	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
80	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
81	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
82	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
83	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
84	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
85	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
86	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
87	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
88	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
89	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
90	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
91	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
92	select ARCH_KEEP_MEMBLOCK
93	select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
94	select ARCH_USE_CMPXCHG_LOCKREF
95	select ARCH_USE_GNU_PROPERTY
96	select ARCH_USE_MEMTEST
97	select ARCH_USE_QUEUED_RWLOCKS
98	select ARCH_USE_QUEUED_SPINLOCKS
99	select ARCH_USE_SYM_ANNOTATIONS
100	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
101	select ARCH_SUPPORTS_HUGETLBFS
102	select ARCH_SUPPORTS_MEMORY_FAILURE
103	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
104	select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
105	select ARCH_SUPPORTS_LTO_CLANG_THIN
106	select ARCH_SUPPORTS_CFI_CLANG
107	select ARCH_SUPPORTS_ATOMIC_RMW
108	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
109	select ARCH_SUPPORTS_NUMA_BALANCING
110	select ARCH_SUPPORTS_PAGE_TABLE_CHECK
111	select ARCH_SUPPORTS_PER_VMA_LOCK
112	select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE
113	select ARCH_SUPPORTS_RT
114	select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH
115	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
116	select ARCH_WANT_DEFAULT_BPF_JIT
117	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
118	select ARCH_WANT_FRAME_POINTERS
119	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
120	select ARCH_WANT_LD_ORPHAN_WARN
121	select ARCH_WANTS_EXECMEM_LATE
122	select ARCH_WANTS_NO_INSTR
123	select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
124	select ARCH_HAS_UBSAN
125	select ARM_AMBA
126	select ARM_ARCH_TIMER
127	select ARM_GIC
128	select AUDIT_ARCH_COMPAT_GENERIC
129	select ARM_GIC_V2M if PCI
130	select ARM_GIC_V3
131	select ARM_GIC_V3_ITS if PCI
132	select ARM_PSCI_FW
133	select BUILDTIME_TABLE_SORT
134	select CLONE_BACKWARDS
135	select COMMON_CLK
136	select CPU_PM if (SUSPEND || CPU_IDLE)
137	select CPUMASK_OFFSTACK if NR_CPUS > 256
138	select DCACHE_WORD_ACCESS
139	select DYNAMIC_FTRACE if FUNCTION_TRACER
140	select DMA_BOUNCE_UNALIGNED_KMALLOC
141	select DMA_DIRECT_REMAP
142	select EDAC_SUPPORT
143	select FRAME_POINTER
144	select FUNCTION_ALIGNMENT_4B
145	select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
146	select GENERIC_ALLOCATOR
147	select GENERIC_ARCH_TOPOLOGY
148	select GENERIC_CLOCKEVENTS_BROADCAST
149	select GENERIC_CPU_AUTOPROBE
150	select GENERIC_CPU_DEVICES
151	select GENERIC_CPU_VULNERABILITIES
152	select GENERIC_EARLY_IOREMAP
153	select GENERIC_IDLE_POLL_SETUP
154	select GENERIC_IOREMAP
155	select GENERIC_IRQ_IPI
156	select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD
157	select GENERIC_IRQ_PROBE
158	select GENERIC_IRQ_SHOW
159	select GENERIC_IRQ_SHOW_LEVEL
160	select GENERIC_LIB_DEVMEM_IS_ALLOWED
161	select GENERIC_PCI_IOMAP
162	select GENERIC_SCHED_CLOCK
163	select GENERIC_SMP_IDLE_THREAD
164	select GENERIC_TIME_VSYSCALL
165	select GENERIC_GETTIMEOFDAY
166	select GENERIC_VDSO_DATA_STORE
167	select GENERIC_VDSO_TIME_NS
168	select HARDIRQS_SW_RESEND
169	select HAS_IOPORT
170	select HAVE_MOVE_PMD
171	select HAVE_MOVE_PUD
172	select HAVE_PCI
173	select HAVE_ACPI_APEI if (ACPI && EFI)
174	select HAVE_ALIGNED_STRUCT_PAGE
175	select HAVE_ARCH_AUDITSYSCALL
176	select HAVE_ARCH_BITREVERSE
177	select HAVE_ARCH_COMPILER_H
178	select HAVE_ARCH_HUGE_VMALLOC
179	select HAVE_ARCH_HUGE_VMAP
180	select HAVE_ARCH_JUMP_LABEL
181	select HAVE_ARCH_JUMP_LABEL_RELATIVE
182	select HAVE_ARCH_KASAN
183	select HAVE_ARCH_KASAN_VMALLOC
184	select HAVE_ARCH_KASAN_SW_TAGS
185	select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE
186	# Some instrumentation may be unsound, hence EXPERT
187	select HAVE_ARCH_KCSAN if EXPERT
188	select HAVE_ARCH_KFENCE
189	select HAVE_ARCH_KGDB
190	select HAVE_ARCH_MMAP_RND_BITS
191	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
192	select HAVE_ARCH_PREL32_RELOCATIONS
193	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
194	select HAVE_ARCH_SECCOMP_FILTER
195	select HAVE_ARCH_STACKLEAK
196	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
197	select HAVE_ARCH_TRACEHOOK
198	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
199	select HAVE_ARCH_VMAP_STACK
200	select HAVE_ARM_SMCCC
201	select HAVE_ASM_MODVERSIONS
202	select HAVE_EBPF_JIT
203	select HAVE_C_RECORDMCOUNT
204	select HAVE_CMPXCHG_DOUBLE
205	select HAVE_CMPXCHG_LOCAL
206	select HAVE_CONTEXT_TRACKING_USER
207	select HAVE_DEBUG_KMEMLEAK
208	select HAVE_DMA_CONTIGUOUS
209	select HAVE_DYNAMIC_FTRACE
210	select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
211		if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \
212		    CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS)
213	select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
214		if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
215	select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
216		if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
217		    (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE))
218	select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
219		if DYNAMIC_FTRACE_WITH_ARGS
220	select HAVE_SAMPLE_FTRACE_DIRECT
221	select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
222	select HAVE_BUILDTIME_MCOUNT_SORT
223	select HAVE_EFFICIENT_UNALIGNED_ACCESS
224	select HAVE_GUP_FAST
225	select HAVE_FTRACE_GRAPH_FUNC
226	select HAVE_FTRACE_MCOUNT_RECORD
227	select HAVE_FUNCTION_TRACER
228	select HAVE_FUNCTION_ERROR_INJECTION
229	select HAVE_FUNCTION_GRAPH_FREGS
230	select HAVE_FUNCTION_GRAPH_TRACER
231	select HAVE_GCC_PLUGINS
232	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \
233		HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI
234	select HAVE_HW_BREAKPOINT if PERF_EVENTS
235	select HAVE_IOREMAP_PROT
236	select HAVE_IRQ_TIME_ACCOUNTING
237	select HAVE_MOD_ARCH_SPECIFIC
238	select HAVE_NMI
239	select HAVE_PERF_EVENTS
240	select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI
241	select HAVE_PERF_REGS
242	select HAVE_PERF_USER_STACK_DUMP
243	select HAVE_PREEMPT_DYNAMIC_KEY
244	select HAVE_REGS_AND_STACK_ACCESS_API
245	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
246	select HAVE_FUNCTION_ARG_ACCESS_API
247	select MMU_GATHER_RCU_TABLE_FREE
248	select HAVE_RSEQ
249	select HAVE_RUST if RUSTC_SUPPORTS_ARM64
250	select HAVE_STACKPROTECTOR
251	select HAVE_SYSCALL_TRACEPOINTS
252	select HAVE_KPROBES
253	select HAVE_KRETPROBES
254	select HAVE_GENERIC_VDSO
255	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
256	select HOTPLUG_SMT if HOTPLUG_CPU
257	select IRQ_DOMAIN
258	select IRQ_FORCED_THREADING
259	select JUMP_LABEL
260	select KASAN_VMALLOC if KASAN
261	select LOCK_MM_AND_FIND_VMA
262	select MODULES_USE_ELF_RELA
263	select NEED_DMA_MAP_STATE
264	select NEED_SG_DMA_LENGTH
265	select OF
266	select OF_EARLY_FLATTREE
267	select PCI_DOMAINS_GENERIC if PCI
268	select PCI_ECAM if (ACPI && PCI)
269	select PCI_SYSCALL if PCI
270	select POWER_RESET
271	select POWER_SUPPLY
272	select SPARSE_IRQ
273	select SWIOTLB
274	select SYSCTL_EXCEPTION_TRACE
275	select THREAD_INFO_IN_TASK
276	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
277	select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD
278	select TRACE_IRQFLAGS_SUPPORT
279	select TRACE_IRQFLAGS_NMI_SUPPORT
280	select HAVE_SOFTIRQ_ON_OWN_STACK
281	select USER_STACKTRACE_SUPPORT
282	select VDSO_GETRANDOM
283	help
284	  ARM 64-bit (AArch64) Linux support.
285
286config RUSTC_SUPPORTS_ARM64
287	def_bool y
288	depends on CPU_LITTLE_ENDIAN
289	# Shadow call stack is only supported on certain rustc versions.
290	#
291	# When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is
292	# required due to use of the -Zfixed-x18 flag.
293	#
294	# Otherwise, rustc version 1.82+ is required due to use of the
295	# -Zsanitizer=shadow-call-stack flag.
296	depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS
297
298config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
299	def_bool CC_IS_CLANG
300	# https://github.com/ClangBuiltLinux/linux/issues/1507
301	depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
302
303config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
304	def_bool CC_IS_GCC
305	depends on $(cc-option,-fpatchable-function-entry=2)
306
307config 64BIT
308	def_bool y
309
310config MMU
311	def_bool y
312
313config ARM64_CONT_PTE_SHIFT
314	int
315	default 5 if PAGE_SIZE_64KB
316	default 7 if PAGE_SIZE_16KB
317	default 4
318
319config ARM64_CONT_PMD_SHIFT
320	int
321	default 5 if PAGE_SIZE_64KB
322	default 5 if PAGE_SIZE_16KB
323	default 4
324
325config ARCH_MMAP_RND_BITS_MIN
326	default 14 if PAGE_SIZE_64KB
327	default 16 if PAGE_SIZE_16KB
328	default 18
329
330# max bits determined by the following formula:
331#  VA_BITS - PTDESC_TABLE_SHIFT
332config ARCH_MMAP_RND_BITS_MAX
333	default 19 if ARM64_VA_BITS=36
334	default 24 if ARM64_VA_BITS=39
335	default 27 if ARM64_VA_BITS=42
336	default 30 if ARM64_VA_BITS=47
337	default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES
338	default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES
339	default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52)
340	default 14 if ARM64_64K_PAGES
341	default 16 if ARM64_16K_PAGES
342	default 18
343
344config ARCH_MMAP_RND_COMPAT_BITS_MIN
345	default 7 if ARM64_64K_PAGES
346	default 9 if ARM64_16K_PAGES
347	default 11
348
349config ARCH_MMAP_RND_COMPAT_BITS_MAX
350	default 16
351
352config NO_IOPORT_MAP
353	def_bool y if !PCI
354
355config STACKTRACE_SUPPORT
356	def_bool y
357
358config ILLEGAL_POINTER_VALUE
359	hex
360	default 0xdead000000000000
361
362config LOCKDEP_SUPPORT
363	def_bool y
364
365config GENERIC_BUG
366	def_bool y
367	depends on BUG
368
369config GENERIC_BUG_RELATIVE_POINTERS
370	def_bool y
371	depends on GENERIC_BUG
372
373config GENERIC_HWEIGHT
374	def_bool y
375
376config GENERIC_CSUM
377	def_bool y
378
379config GENERIC_CALIBRATE_DELAY
380	def_bool y
381
382config SMP
383	def_bool y
384
385config KERNEL_MODE_NEON
386	def_bool y
387
388config FIX_EARLYCON_MEM
389	def_bool y
390
391config PGTABLE_LEVELS
392	int
393	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
394	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
395	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
396	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
397	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
398	default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
399	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
400	default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52
401
402config ARCH_SUPPORTS_UPROBES
403	def_bool y
404
405config ARCH_PROC_KCORE_TEXT
406	def_bool y
407
408config BROKEN_GAS_INST
409	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
410
411config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
412	bool
413	# Clang's __builtin_return_address() strips the PAC since 12.0.0
414	# https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
415	default y if CC_IS_CLANG
416	# GCC's __builtin_return_address() strips the PAC since 11.1.0,
417	# and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
418	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
419	default y if CC_IS_GCC && (GCC_VERSION >= 110100)
420	default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
421	default y if CC_IS_GCC && (GCC_VERSION >=  90400) && (GCC_VERSION < 100000)
422	default y if CC_IS_GCC && (GCC_VERSION >=  80500) && (GCC_VERSION <  90000)
423	default n
424
425config KASAN_SHADOW_OFFSET
426	hex
427	depends on KASAN_GENERIC || KASAN_SW_TAGS
428	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS
429	default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS
430	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
431	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
432	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
433	default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS
434	default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS
435	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
436	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
437	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
438	default 0xffffffffffffffff
439
440config UNWIND_TABLES
441	bool
442
443source "arch/arm64/Kconfig.platforms"
444
445menu "Kernel Features"
446
447menu "ARM errata workarounds via the alternatives framework"
448
449config AMPERE_ERRATUM_AC03_CPU_38
450        bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
451	default y
452	help
453	  This option adds an alternative code sequence to work around Ampere
454	  errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne.
455
456	  The affected design reports FEAT_HAFDBS as not implemented in
457	  ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
458	  as required by the architecture. The unadvertised HAFDBS
459	  implementation suffers from an additional erratum where hardware
460	  A/D updates can occur after a PTE has been marked invalid.
461
462	  The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
463	  which avoids enabling unadvertised hardware Access Flag management
464	  at stage-2.
465
466	  If unsure, say Y.
467
468config AMPERE_ERRATUM_AC04_CPU_23
469        bool "AmpereOne: AC04_CPU_23:  Failure to synchronize writes to HCR_EL2 may corrupt address translations."
470	default y
471	help
472	  This option adds an alternative code sequence to work around Ampere
473	  errata AC04_CPU_23 on AmpereOne.
474
475	  Updates to HCR_EL2 can rarely corrupt simultaneous translations for
476	  data addresses initiated by load/store instructions. Only
477	  instruction initiated translations are vulnerable, not translations
478	  from prefetches for example. A DSB before the store to HCR_EL2 is
479	  sufficient to prevent older instructions from hitting the window
480	  for corruption, and an ISB after is sufficient to prevent younger
481	  instructions from hitting the window for corruption.
482
483	  If unsure, say Y.
484
485config ARM64_WORKAROUND_CLEAN_CACHE
486	bool
487
488config ARM64_ERRATUM_826319
489	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
490	default y
491	select ARM64_WORKAROUND_CLEAN_CACHE
492	help
493	  This option adds an alternative code sequence to work around ARM
494	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
495	  AXI master interface and an L2 cache.
496
497	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
498	  and is unable to accept a certain write via this interface, it will
499	  not progress on read data presented on the read data channel and the
500	  system can deadlock.
501
502	  The workaround promotes data cache clean instructions to
503	  data cache clean-and-invalidate.
504	  Please note that this does not necessarily enable the workaround,
505	  as it depends on the alternative framework, which will only patch
506	  the kernel if an affected CPU is detected.
507
508	  If unsure, say Y.
509
510config ARM64_ERRATUM_827319
511	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
512	default y
513	select ARM64_WORKAROUND_CLEAN_CACHE
514	help
515	  This option adds an alternative code sequence to work around ARM
516	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
517	  master interface and an L2 cache.
518
519	  Under certain conditions this erratum can cause a clean line eviction
520	  to occur at the same time as another transaction to the same address
521	  on the AMBA 5 CHI interface, which can cause data corruption if the
522	  interconnect reorders the two transactions.
523
524	  The workaround promotes data cache clean instructions to
525	  data cache clean-and-invalidate.
526	  Please note that this does not necessarily enable the workaround,
527	  as it depends on the alternative framework, which will only patch
528	  the kernel if an affected CPU is detected.
529
530	  If unsure, say Y.
531
532config ARM64_ERRATUM_824069
533	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
534	default y
535	select ARM64_WORKAROUND_CLEAN_CACHE
536	help
537	  This option adds an alternative code sequence to work around ARM
538	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
539	  to a coherent interconnect.
540
541	  If a Cortex-A53 processor is executing a store or prefetch for
542	  write instruction at the same time as a processor in another
543	  cluster is executing a cache maintenance operation to the same
544	  address, then this erratum might cause a clean cache line to be
545	  incorrectly marked as dirty.
546
547	  The workaround promotes data cache clean instructions to
548	  data cache clean-and-invalidate.
549	  Please note that this option does not necessarily enable the
550	  workaround, as it depends on the alternative framework, which will
551	  only patch the kernel if an affected CPU is detected.
552
553	  If unsure, say Y.
554
555config ARM64_ERRATUM_819472
556	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
557	default y
558	select ARM64_WORKAROUND_CLEAN_CACHE
559	help
560	  This option adds an alternative code sequence to work around ARM
561	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
562	  present when it is connected to a coherent interconnect.
563
564	  If the processor is executing a load and store exclusive sequence at
565	  the same time as a processor in another cluster is executing a cache
566	  maintenance operation to the same address, then this erratum might
567	  cause data corruption.
568
569	  The workaround promotes data cache clean instructions to
570	  data cache clean-and-invalidate.
571	  Please note that this does not necessarily enable the workaround,
572	  as it depends on the alternative framework, which will only patch
573	  the kernel if an affected CPU is detected.
574
575	  If unsure, say Y.
576
577config ARM64_ERRATUM_832075
578	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
579	default y
580	help
581	  This option adds an alternative code sequence to work around ARM
582	  erratum 832075 on Cortex-A57 parts up to r1p2.
583
584	  Affected Cortex-A57 parts might deadlock when exclusive load/store
585	  instructions to Write-Back memory are mixed with Device loads.
586
587	  The workaround is to promote device loads to use Load-Acquire
588	  semantics.
589	  Please note that this does not necessarily enable the workaround,
590	  as it depends on the alternative framework, which will only patch
591	  the kernel if an affected CPU is detected.
592
593	  If unsure, say Y.
594
595config ARM64_ERRATUM_834220
596	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)"
597	depends on KVM
598	help
599	  This option adds an alternative code sequence to work around ARM
600	  erratum 834220 on Cortex-A57 parts up to r1p2.
601
602	  Affected Cortex-A57 parts might report a Stage 2 translation
603	  fault as the result of a Stage 1 fault for load crossing a
604	  page boundary when there is a permission or device memory
605	  alignment fault at Stage 1 and a translation fault at Stage 2.
606
607	  The workaround is to verify that the Stage 1 translation
608	  doesn't generate a fault before handling the Stage 2 fault.
609	  Please note that this does not necessarily enable the workaround,
610	  as it depends on the alternative framework, which will only patch
611	  the kernel if an affected CPU is detected.
612
613	  If unsure, say N.
614
615config ARM64_ERRATUM_1742098
616	bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
617	depends on COMPAT
618	default y
619	help
620	  This option removes the AES hwcap for aarch32 user-space to
621	  workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
622
623	  Affected parts may corrupt the AES state if an interrupt is
624	  taken between a pair of AES instructions. These instructions
625	  are only present if the cryptography extensions are present.
626	  All software should have a fallback implementation for CPUs
627	  that don't implement the cryptography extensions.
628
629	  If unsure, say Y.
630
631config ARM64_ERRATUM_845719
632	bool "Cortex-A53: 845719: a load might read incorrect data"
633	depends on COMPAT
634	default y
635	help
636	  This option adds an alternative code sequence to work around ARM
637	  erratum 845719 on Cortex-A53 parts up to r0p4.
638
639	  When running a compat (AArch32) userspace on an affected Cortex-A53
640	  part, a load at EL0 from a virtual address that matches the bottom 32
641	  bits of the virtual address used by a recent load at (AArch64) EL1
642	  might return incorrect data.
643
644	  The workaround is to write the contextidr_el1 register on exception
645	  return to a 32-bit task.
646	  Please note that this does not necessarily enable the workaround,
647	  as it depends on the alternative framework, which will only patch
648	  the kernel if an affected CPU is detected.
649
650	  If unsure, say Y.
651
652config ARM64_ERRATUM_843419
653	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
654	default y
655	help
656	  This option links the kernel with '--fix-cortex-a53-843419' and
657	  enables PLT support to replace certain ADRP instructions, which can
658	  cause subsequent memory accesses to use an incorrect address on
659	  Cortex-A53 parts up to r0p4.
660
661	  If unsure, say Y.
662
663config ARM64_ERRATUM_1024718
664	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
665	default y
666	help
667	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
668
669	  Affected Cortex-A55 cores (all revisions) could cause incorrect
670	  update of the hardware dirty bit when the DBM/AP bits are updated
671	  without a break-before-make. The workaround is to disable the usage
672	  of hardware DBM locally on the affected cores. CPUs not affected by
673	  this erratum will continue to use the feature.
674
675	  If unsure, say Y.
676
677config ARM64_ERRATUM_1418040
678	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
679	default y
680	depends on COMPAT
681	help
682	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
683	  errata 1188873 and 1418040.
684
685	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
686	  cause register corruption when accessing the timer registers
687	  from AArch32 userspace.
688
689	  If unsure, say Y.
690
691config ARM64_WORKAROUND_SPECULATIVE_AT
692	bool
693
694config ARM64_ERRATUM_1165522
695	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
696	default y
697	select ARM64_WORKAROUND_SPECULATIVE_AT
698	help
699	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
700
701	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
702	  corrupted TLBs by speculating an AT instruction during a guest
703	  context switch.
704
705	  If unsure, say Y.
706
707config ARM64_ERRATUM_1319367
708	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
709	default y
710	select ARM64_WORKAROUND_SPECULATIVE_AT
711	help
712	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
713	  and A72 erratum 1319367
714
715	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
716	  speculating an AT instruction during a guest context switch.
717
718	  If unsure, say Y.
719
720config ARM64_ERRATUM_1530923
721	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
722	default y
723	select ARM64_WORKAROUND_SPECULATIVE_AT
724	help
725	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
726
727	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
728	  corrupted TLBs by speculating an AT instruction during a guest
729	  context switch.
730
731	  If unsure, say Y.
732
733config ARM64_WORKAROUND_REPEAT_TLBI
734	bool
735
736config ARM64_ERRATUM_2441007
737	bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
738	select ARM64_WORKAROUND_REPEAT_TLBI
739	help
740	  This option adds a workaround for ARM Cortex-A55 erratum #2441007.
741
742	  Under very rare circumstances, affected Cortex-A55 CPUs
743	  may not handle a race between a break-before-make sequence on one
744	  CPU, and another CPU accessing the same page. This could allow a
745	  store to a page that has been unmapped.
746
747	  Work around this by adding the affected CPUs to the list that needs
748	  TLB sequences to be done twice.
749
750	  If unsure, say N.
751
752config ARM64_ERRATUM_1286807
753	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)"
754	select ARM64_WORKAROUND_REPEAT_TLBI
755	help
756	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
757
758	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
759	  address for a cacheable mapping of a location is being
760	  accessed by a core while another core is remapping the virtual
761	  address to a new physical page using the recommended
762	  break-before-make sequence, then under very rare circumstances
763	  TLBI+DSB completes before a read using the translation being
764	  invalidated has been observed by other observers. The
765	  workaround repeats the TLBI+DSB operation.
766
767	  If unsure, say N.
768
769config ARM64_ERRATUM_1463225
770	bool "Cortex-A76: Software Step might prevent interrupt recognition"
771	default y
772	help
773	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
774
775	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
776	  of a system call instruction (SVC) can prevent recognition of
777	  subsequent interrupts when software stepping is disabled in the
778	  exception handler of the system call and either kernel debugging
779	  is enabled or VHE is in use.
780
781	  Work around the erratum by triggering a dummy step exception
782	  when handling a system call from a task that is being stepped
783	  in a VHE configuration of the kernel.
784
785	  If unsure, say Y.
786
787config ARM64_ERRATUM_1542419
788	bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
789	help
790	  This option adds a workaround for ARM Neoverse-N1 erratum
791	  1542419.
792
793	  Affected Neoverse-N1 cores could execute a stale instruction when
794	  modified by another CPU. The workaround depends on a firmware
795	  counterpart.
796
797	  Workaround the issue by hiding the DIC feature from EL0. This
798	  forces user-space to perform cache maintenance.
799
800	  If unsure, say N.
801
802config ARM64_ERRATUM_1508412
803	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
804	default y
805	help
806	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
807
808	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
809	  of a store-exclusive or read of PAR_EL1 and a load with device or
810	  non-cacheable memory attributes. The workaround depends on a firmware
811	  counterpart.
812
813	  KVM guests must also have the workaround implemented or they can
814	  deadlock the system.
815
816	  Work around the issue by inserting DMB SY barriers around PAR_EL1
817	  register reads and warning KVM users. The DMB barrier is sufficient
818	  to prevent a speculative PAR_EL1 read.
819
820	  If unsure, say Y.
821
822config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
823	bool
824
825config ARM64_ERRATUM_2051678
826	bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
827	default y
828	help
829	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
830	  Affected Cortex-A510 might not respect the ordering rules for
831	  hardware update of the page table's dirty bit. The workaround
832	  is to not enable the feature on affected CPUs.
833
834	  If unsure, say Y.
835
836config ARM64_ERRATUM_2077057
837	bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
838	default y
839	help
840	  This option adds the workaround for ARM Cortex-A510 erratum 2077057.
841	  Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
842	  expected, but a Pointer Authentication trap is taken instead. The
843	  erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
844	  EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
845
846	  This can only happen when EL2 is stepping EL1.
847
848	  When these conditions occur, the SPSR_EL2 value is unchanged from the
849	  previous guest entry, and can be restored from the in-memory copy.
850
851	  If unsure, say Y.
852
853config ARM64_ERRATUM_2658417
854	bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
855	default y
856	help
857	  This option adds the workaround for ARM Cortex-A510 erratum 2658417.
858	  Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
859	  BFMMLA or VMMLA instructions in rare circumstances when a pair of
860	  A510 CPUs are using shared neon hardware. As the sharing is not
861	  discoverable by the kernel, hide the BF16 HWCAP to indicate that
862	  user-space should not be using these instructions.
863
864	  If unsure, say Y.
865
866config ARM64_ERRATUM_2119858
867	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
868	default y
869	depends on CORESIGHT_TRBE
870	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
871	help
872	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
873
874	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
875	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
876	  the event of a WRAP event.
877
878	  Work around the issue by always making sure we move the TRBPTR_EL1 by
879	  256 bytes before enabling the buffer and filling the first 256 bytes of
880	  the buffer with ETM ignore packets upon disabling.
881
882	  If unsure, say Y.
883
884config ARM64_ERRATUM_2139208
885	bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
886	default y
887	depends on CORESIGHT_TRBE
888	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
889	help
890	  This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
891
892	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
893	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
894	  the event of a WRAP event.
895
896	  Work around the issue by always making sure we move the TRBPTR_EL1 by
897	  256 bytes before enabling the buffer and filling the first 256 bytes of
898	  the buffer with ETM ignore packets upon disabling.
899
900	  If unsure, say Y.
901
902config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
903	bool
904
905config ARM64_ERRATUM_2054223
906	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
907	default y
908	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
909	help
910	  Enable workaround for ARM Cortex-A710 erratum 2054223
911
912	  Affected cores may fail to flush the trace data on a TSB instruction, when
913	  the PE is in trace prohibited state. This will cause losing a few bytes
914	  of the trace cached.
915
916	  Workaround is to issue two TSB consecutively on affected cores.
917
918	  If unsure, say Y.
919
920config ARM64_ERRATUM_2067961
921	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
922	default y
923	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
924	help
925	  Enable workaround for ARM Neoverse-N2 erratum 2067961
926
927	  Affected cores may fail to flush the trace data on a TSB instruction, when
928	  the PE is in trace prohibited state. This will cause losing a few bytes
929	  of the trace cached.
930
931	  Workaround is to issue two TSB consecutively on affected cores.
932
933	  If unsure, say Y.
934
935config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
936	bool
937
938config ARM64_ERRATUM_2253138
939	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
940	depends on CORESIGHT_TRBE
941	default y
942	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
943	help
944	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
945
946	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
947	  for TRBE. Under some conditions, the TRBE might generate a write to the next
948	  virtually addressed page following the last page of the TRBE address space
949	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
950
951	  Work around this in the driver by always making sure that there is a
952	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
953
954	  If unsure, say Y.
955
956config ARM64_ERRATUM_2224489
957	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
958	depends on CORESIGHT_TRBE
959	default y
960	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
961	help
962	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
963
964	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
965	  for TRBE. Under some conditions, the TRBE might generate a write to the next
966	  virtually addressed page following the last page of the TRBE address space
967	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
968
969	  Work around this in the driver by always making sure that there is a
970	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
971
972	  If unsure, say Y.
973
974config ARM64_ERRATUM_2441009
975	bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
976	select ARM64_WORKAROUND_REPEAT_TLBI
977	help
978	  This option adds a workaround for ARM Cortex-A510 erratum #2441009.
979
980	  Under very rare circumstances, affected Cortex-A510 CPUs
981	  may not handle a race between a break-before-make sequence on one
982	  CPU, and another CPU accessing the same page. This could allow a
983	  store to a page that has been unmapped.
984
985	  Work around this by adding the affected CPUs to the list that needs
986	  TLB sequences to be done twice.
987
988	  If unsure, say N.
989
990config ARM64_ERRATUM_2064142
991	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
992	depends on CORESIGHT_TRBE
993	default y
994	help
995	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.
996
997	  Affected Cortex-A510 core might fail to write into system registers after the
998	  TRBE has been disabled. Under some conditions after the TRBE has been disabled
999	  writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
1000	  and TRBTRG_EL1 will be ignored and will not be effected.
1001
1002	  Work around this in the driver by executing TSB CSYNC and DSB after collection
1003	  is stopped and before performing a system register write to one of the affected
1004	  registers.
1005
1006	  If unsure, say Y.
1007
1008config ARM64_ERRATUM_2038923
1009	bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
1010	depends on CORESIGHT_TRBE
1011	default y
1012	help
1013	  This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1014
1015	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1016	  prohibited within the CPU. As a result, the trace buffer or trace buffer state
1017	  might be corrupted. This happens after TRBE buffer has been enabled by setting
1018	  TRBLIMITR_EL1.E, followed by just a single context synchronization event before
1019	  execution changes from a context, in which trace is prohibited to one where it
1020	  isn't, or vice versa. In these mentioned conditions, the view of whether trace
1021	  is prohibited is inconsistent between parts of the CPU, and the trace buffer or
1022	  the trace buffer state might be corrupted.
1023
1024	  Work around this in the driver by preventing an inconsistent view of whether the
1025	  trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
1026	  change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
1027	  two ISB instructions if no ERET is to take place.
1028
1029	  If unsure, say Y.
1030
1031config ARM64_ERRATUM_1902691
1032	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1033	depends on CORESIGHT_TRBE
1034	default y
1035	help
1036	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1037
1038	  Affected Cortex-A510 core might cause trace data corruption, when being written
1039	  into the memory. Effectively TRBE is broken and hence cannot be used to capture
1040	  trace data.
1041
1042	  Work around this problem in the driver by just preventing TRBE initialization on
1043	  affected cpus. The firmware must have disabled the access to TRBE for the kernel
1044	  on such implementations. This will cover the kernel for any firmware that doesn't
1045	  do this already.
1046
1047	  If unsure, say Y.
1048
1049config ARM64_ERRATUM_2457168
1050	bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1051	depends on ARM64_AMU_EXTN
1052	default y
1053	help
1054	  This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1055
1056	  The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
1057	  as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1058	  incorrectly giving a significantly higher output value.
1059
1060	  Work around this problem by returning 0 when reading the affected counter in
1061	  key locations that results in disabling all users of this counter. This effect
1062	  is the same to firmware disabling affected counters.
1063
1064	  If unsure, say Y.
1065
1066config ARM64_ERRATUM_2645198
1067	bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1068	default y
1069	help
1070	  This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1071
1072	  If a Cortex-A715 cpu sees a page mapping permissions change from executable
1073	  to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1074	  next instruction abort caused by permission fault.
1075
1076	  Only user-space does executable to non-executable permission transition via
1077	  mprotect() system call. Workaround the problem by doing a break-before-make
1078	  TLB invalidation, for all changes to executable user space mappings.
1079
1080	  If unsure, say Y.
1081
1082config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1083	bool
1084
1085config ARM64_ERRATUM_2966298
1086	bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1087	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1088	default y
1089	help
1090	  This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1091
1092	  On an affected Cortex-A520 core, a speculatively executed unprivileged
1093	  load might leak data from a privileged level via a cache side channel.
1094
1095	  Work around this problem by executing a TLBI before returning to EL0.
1096
1097	  If unsure, say Y.
1098
1099config ARM64_ERRATUM_3117295
1100	bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1101	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1102	default y
1103	help
1104	  This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1105
1106	  On an affected Cortex-A510 core, a speculatively executed unprivileged
1107	  load might leak data from a privileged level via a cache side channel.
1108
1109	  Work around this problem by executing a TLBI before returning to EL0.
1110
1111	  If unsure, say Y.
1112
1113config ARM64_ERRATUM_3194386
1114	bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1115	default y
1116	help
1117	  This option adds the workaround for the following errata:
1118
1119	  * ARM Cortex-A76 erratum 3324349
1120	  * ARM Cortex-A77 erratum 3324348
1121	  * ARM Cortex-A78 erratum 3324344
1122	  * ARM Cortex-A78C erratum 3324346
1123	  * ARM Cortex-A78C erratum 3324347
1124	  * ARM Cortex-A710 erratam 3324338
1125	  * ARM Cortex-A715 errartum 3456084
1126	  * ARM Cortex-A720 erratum 3456091
1127	  * ARM Cortex-A725 erratum 3456106
1128	  * ARM Cortex-X1 erratum 3324344
1129	  * ARM Cortex-X1C erratum 3324346
1130	  * ARM Cortex-X2 erratum 3324338
1131	  * ARM Cortex-X3 erratum 3324335
1132	  * ARM Cortex-X4 erratum 3194386
1133	  * ARM Cortex-X925 erratum 3324334
1134	  * ARM Neoverse-N1 erratum 3324349
1135	  * ARM Neoverse N2 erratum 3324339
1136	  * ARM Neoverse-N3 erratum 3456111
1137	  * ARM Neoverse-V1 erratum 3324341
1138	  * ARM Neoverse V2 erratum 3324336
1139	  * ARM Neoverse-V3 erratum 3312417
1140
1141	  On affected cores "MSR SSBS, #0" instructions may not affect
1142	  subsequent speculative instructions, which may permit unexepected
1143	  speculative store bypassing.
1144
1145	  Work around this problem by placing a Speculation Barrier (SB) or
1146	  Instruction Synchronization Barrier (ISB) after kernel changes to
1147	  SSBS. The presence of the SSBS special-purpose register is hidden
1148	  from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
1149	  will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
1150
1151	  If unsure, say Y.
1152
1153config CAVIUM_ERRATUM_22375
1154	bool "Cavium erratum 22375, 24313"
1155	default y
1156	help
1157	  Enable workaround for errata 22375 and 24313.
1158
1159	  This implements two gicv3-its errata workarounds for ThunderX. Both
1160	  with a small impact affecting only ITS table allocation.
1161
1162	    erratum 22375: only alloc 8MB table size
1163	    erratum 24313: ignore memory access type
1164
1165	  The fixes are in ITS initialization and basically ignore memory access
1166	  type and table size provided by the TYPER and BASER registers.
1167
1168	  If unsure, say Y.
1169
1170config CAVIUM_ERRATUM_23144
1171	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1172	depends on NUMA
1173	default y
1174	help
1175	  ITS SYNC command hang for cross node io and collections/cpu mapping.
1176
1177	  If unsure, say Y.
1178
1179config CAVIUM_ERRATUM_23154
1180	bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1181	default y
1182	help
1183	  The ThunderX GICv3 implementation requires a modified version for
1184	  reading the IAR status to ensure data synchronization
1185	  (access to icc_iar1_el1 is not sync'ed before and after).
1186
1187	  It also suffers from erratum 38545 (also present on Marvell's
1188	  OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1189	  spuriously presented to the CPU interface.
1190
1191	  If unsure, say Y.
1192
1193config CAVIUM_ERRATUM_27456
1194	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1195	default y
1196	help
1197	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1198	  instructions may cause the icache to become corrupted if it
1199	  contains data for a non-current ASID.  The fix is to
1200	  invalidate the icache when changing the mm context.
1201
1202	  If unsure, say Y.
1203
1204config CAVIUM_ERRATUM_30115
1205	bool "Cavium erratum 30115: Guest may disable interrupts in host"
1206	default y
1207	help
1208	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1209	  1.2, and T83 Pass 1.0, KVM guest execution may disable
1210	  interrupts in host. Trapping both GICv3 group-0 and group-1
1211	  accesses sidesteps the issue.
1212
1213	  If unsure, say Y.
1214
1215config CAVIUM_TX2_ERRATUM_219
1216	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1217	default y
1218	help
1219	  On Cavium ThunderX2, a load, store or prefetch instruction between a
1220	  TTBR update and the corresponding context synchronizing operation can
1221	  cause a spurious Data Abort to be delivered to any hardware thread in
1222	  the CPU core.
1223
1224	  Work around the issue by avoiding the problematic code sequence and
1225	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1226	  trap handler performs the corresponding register access, skips the
1227	  instruction and ensures context synchronization by virtue of the
1228	  exception return.
1229
1230	  If unsure, say Y.
1231
1232config FUJITSU_ERRATUM_010001
1233	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1234	default y
1235	help
1236	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1237	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1238	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
1239	  This fault occurs under a specific hardware condition when a
1240	  load/store instruction performs an address translation using:
1241	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1242	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1243	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1244	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1245
1246	  The workaround is to ensure these bits are clear in TCR_ELx.
1247	  The workaround only affects the Fujitsu-A64FX.
1248
1249	  If unsure, say Y.
1250
1251config HISILICON_ERRATUM_161600802
1252	bool "Hip07 161600802: Erroneous redistributor VLPI base"
1253	default y
1254	help
1255	  The HiSilicon Hip07 SoC uses the wrong redistributor base
1256	  when issued ITS commands such as VMOVP and VMAPP, and requires
1257	  a 128kB offset to be applied to the target address in this commands.
1258
1259	  If unsure, say Y.
1260
1261config HISILICON_ERRATUM_162100801
1262	bool "Hip09 162100801 erratum support"
1263	default y
1264	help
1265	  When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches
1266	  during unmapping operation, which will cause some vSGIs lost.
1267	  To fix the issue, invalidate related vPE cache through GICR_INVALLR
1268	  after VMOVP.
1269
1270	  If unsure, say Y.
1271
1272config QCOM_FALKOR_ERRATUM_1003
1273	bool "Falkor E1003: Incorrect translation due to ASID change"
1274	default y
1275	help
1276	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1277	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1278	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
1279	  then only for entries in the walk cache, since the leaf translation
1280	  is unchanged. Work around the erratum by invalidating the walk cache
1281	  entries for the trampoline before entering the kernel proper.
1282
1283config QCOM_FALKOR_ERRATUM_1009
1284	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1285	default y
1286	select ARM64_WORKAROUND_REPEAT_TLBI
1287	help
1288	  On Falkor v1, the CPU may prematurely complete a DSB following a
1289	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1290	  one more time to fix the issue.
1291
1292	  If unsure, say Y.
1293
1294config QCOM_QDF2400_ERRATUM_0065
1295	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1296	default y
1297	help
1298	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1299	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1300	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1301
1302	  If unsure, say Y.
1303
1304config QCOM_FALKOR_ERRATUM_E1041
1305	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1306	default y
1307	help
1308	  Falkor CPU may speculatively fetch instructions from an improper
1309	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
1310	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1311
1312	  If unsure, say Y.
1313
1314config NVIDIA_CARMEL_CNP_ERRATUM
1315	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1316	default y
1317	help
1318	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1319	  invalidate shared TLB entries installed by a different core, as it would
1320	  on standard ARM cores.
1321
1322	  If unsure, say Y.
1323
1324config ROCKCHIP_ERRATUM_3568002
1325	bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"
1326	default y
1327	help
1328	  The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI
1329	  addressing limited to the first 32bit of physical address space.
1330
1331	  If unsure, say Y.
1332
1333config ROCKCHIP_ERRATUM_3588001
1334	bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1335	default y
1336	help
1337	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1338	  This means, that its sharability feature may not be used, even though it
1339	  is supported by the IP itself.
1340
1341	  If unsure, say Y.
1342
1343config SOCIONEXT_SYNQUACER_PREITS
1344	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1345	default y
1346	help
1347	  Socionext Synquacer SoCs implement a separate h/w block to generate
1348	  MSI doorbell writes with non-zero values for the device ID.
1349
1350	  If unsure, say Y.
1351
1352endmenu # "ARM errata workarounds via the alternatives framework"
1353
1354choice
1355	prompt "Page size"
1356	default ARM64_4K_PAGES
1357	help
1358	  Page size (translation granule) configuration.
1359
1360config ARM64_4K_PAGES
1361	bool "4KB"
1362	select HAVE_PAGE_SIZE_4KB
1363	help
1364	  This feature enables 4KB pages support.
1365
1366config ARM64_16K_PAGES
1367	bool "16KB"
1368	select HAVE_PAGE_SIZE_16KB
1369	help
1370	  The system will use 16KB pages support. AArch32 emulation
1371	  requires applications compiled with 16K (or a multiple of 16K)
1372	  aligned segments.
1373
1374config ARM64_64K_PAGES
1375	bool "64KB"
1376	select HAVE_PAGE_SIZE_64KB
1377	help
1378	  This feature enables 64KB pages support (4KB by default)
1379	  allowing only two levels of page tables and faster TLB
1380	  look-up. AArch32 emulation requires applications compiled
1381	  with 64K aligned segments.
1382
1383endchoice
1384
1385choice
1386	prompt "Virtual address space size"
1387	default ARM64_VA_BITS_52
1388	help
1389	  Allows choosing one of multiple possible virtual address
1390	  space sizes. The level of translation table is determined by
1391	  a combination of page size and virtual address space size.
1392
1393config ARM64_VA_BITS_36
1394	bool "36-bit" if EXPERT
1395	depends on PAGE_SIZE_16KB
1396
1397config ARM64_VA_BITS_39
1398	bool "39-bit"
1399	depends on PAGE_SIZE_4KB
1400
1401config ARM64_VA_BITS_42
1402	bool "42-bit"
1403	depends on PAGE_SIZE_64KB
1404
1405config ARM64_VA_BITS_47
1406	bool "47-bit"
1407	depends on PAGE_SIZE_16KB
1408
1409config ARM64_VA_BITS_48
1410	bool "48-bit"
1411
1412config ARM64_VA_BITS_52
1413	bool "52-bit"
1414	help
1415	  Enable 52-bit virtual addressing for userspace when explicitly
1416	  requested via a hint to mmap(). The kernel will also use 52-bit
1417	  virtual addresses for its own mappings (provided HW support for
1418	  this feature is available, otherwise it reverts to 48-bit).
1419
1420	  NOTE: Enabling 52-bit virtual addressing in conjunction with
1421	  ARMv8.3 Pointer Authentication will result in the PAC being
1422	  reduced from 7 bits to 3 bits, which may have a significant
1423	  impact on its susceptibility to brute-force attacks.
1424
1425	  If unsure, select 48-bit virtual addressing instead.
1426
1427endchoice
1428
1429config ARM64_FORCE_52BIT
1430	bool "Force 52-bit virtual addresses for userspace"
1431	depends on ARM64_VA_BITS_52 && EXPERT
1432	help
1433	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
1434	  to maintain compatibility with older software by providing 48-bit VAs
1435	  unless a hint is supplied to mmap.
1436
1437	  This configuration option disables the 48-bit compatibility logic, and
1438	  forces all userspace addresses to be 52-bit on HW that supports it. One
1439	  should only enable this configuration option for stress testing userspace
1440	  memory management code. If unsure say N here.
1441
1442config ARM64_VA_BITS
1443	int
1444	default 36 if ARM64_VA_BITS_36
1445	default 39 if ARM64_VA_BITS_39
1446	default 42 if ARM64_VA_BITS_42
1447	default 47 if ARM64_VA_BITS_47
1448	default 48 if ARM64_VA_BITS_48
1449	default 52 if ARM64_VA_BITS_52
1450
1451choice
1452	prompt "Physical address space size"
1453	default ARM64_PA_BITS_48
1454	help
1455	  Choose the maximum physical address range that the kernel will
1456	  support.
1457
1458config ARM64_PA_BITS_48
1459	bool "48-bit"
1460	depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52
1461
1462config ARM64_PA_BITS_52
1463	bool "52-bit"
1464	depends on ARM64_64K_PAGES || ARM64_VA_BITS_52
1465	help
1466	  Enable support for a 52-bit physical address space, introduced as
1467	  part of the ARMv8.2-LPA extension.
1468
1469	  With this enabled, the kernel will also continue to work on CPUs that
1470	  do not support ARMv8.2-LPA, but with some added memory overhead (and
1471	  minor performance overhead).
1472
1473endchoice
1474
1475config ARM64_PA_BITS
1476	int
1477	default 48 if ARM64_PA_BITS_48
1478	default 52 if ARM64_PA_BITS_52
1479
1480config ARM64_LPA2
1481	def_bool y
1482	depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES
1483
1484choice
1485	prompt "Endianness"
1486	default CPU_LITTLE_ENDIAN
1487	help
1488	  Select the endianness of data accesses performed by the CPU. Userspace
1489	  applications will need to be compiled and linked for the endianness
1490	  that is selected here.
1491
1492config CPU_BIG_ENDIAN
1493	bool "Build big-endian kernel"
1494	# https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1495	depends on AS_IS_GNU || AS_VERSION >= 150000
1496	help
1497	  Say Y if you plan on running a kernel with a big-endian userspace.
1498
1499config CPU_LITTLE_ENDIAN
1500	bool "Build little-endian kernel"
1501	help
1502	  Say Y if you plan on running a kernel with a little-endian userspace.
1503	  This is usually the case for distributions targeting arm64.
1504
1505endchoice
1506
1507config SCHED_MC
1508	bool "Multi-core scheduler support"
1509	help
1510	  Multi-core scheduler support improves the CPU scheduler's decision
1511	  making when dealing with multi-core CPU chips at a cost of slightly
1512	  increased overhead in some places. If unsure say N here.
1513
1514config SCHED_CLUSTER
1515	bool "Cluster scheduler support"
1516	help
1517	  Cluster scheduler support improves the CPU scheduler's decision
1518	  making when dealing with machines that have clusters of CPUs.
1519	  Cluster usually means a couple of CPUs which are placed closely
1520	  by sharing mid-level caches, last-level cache tags or internal
1521	  busses.
1522
1523config SCHED_SMT
1524	bool "SMT scheduler support"
1525	help
1526	  Improves the CPU scheduler's decision making when dealing with
1527	  MultiThreading at a cost of slightly increased overhead in some
1528	  places. If unsure say N here.
1529
1530config NR_CPUS
1531	int "Maximum number of CPUs (2-4096)"
1532	range 2 4096
1533	default "512"
1534
1535config HOTPLUG_CPU
1536	bool "Support for hot-pluggable CPUs"
1537	select GENERIC_IRQ_MIGRATION
1538	help
1539	  Say Y here to experiment with turning CPUs off and on.  CPUs
1540	  can be controlled through /sys/devices/system/cpu.
1541
1542# Common NUMA Features
1543config NUMA
1544	bool "NUMA Memory Allocation and Scheduler Support"
1545	select GENERIC_ARCH_NUMA
1546	select OF_NUMA
1547	select HAVE_SETUP_PER_CPU_AREA
1548	select NEED_PER_CPU_EMBED_FIRST_CHUNK
1549	select NEED_PER_CPU_PAGE_FIRST_CHUNK
1550	select USE_PERCPU_NUMA_NODE_ID
1551	help
1552	  Enable NUMA (Non-Uniform Memory Access) support.
1553
1554	  The kernel will try to allocate memory used by a CPU on the
1555	  local memory of the CPU and add some more
1556	  NUMA awareness to the kernel.
1557
1558config NODES_SHIFT
1559	int "Maximum NUMA Nodes (as a power of 2)"
1560	range 1 10
1561	default "4"
1562	depends on NUMA
1563	help
1564	  Specify the maximum number of NUMA Nodes available on the target
1565	  system.  Increases memory reserved to accommodate various tables.
1566
1567source "kernel/Kconfig.hz"
1568
1569config ARCH_SPARSEMEM_ENABLE
1570	def_bool y
1571	select SPARSEMEM_VMEMMAP_ENABLE
1572	select SPARSEMEM_VMEMMAP
1573
1574config HW_PERF_EVENTS
1575	def_bool y
1576	depends on ARM_PMU
1577
1578# Supported by clang >= 7.0 or GCC >= 12.0.0
1579config CC_HAVE_SHADOW_CALL_STACK
1580	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1581
1582config PARAVIRT
1583	bool "Enable paravirtualization code"
1584	help
1585	  This changes the kernel so it can modify itself when it is run
1586	  under a hypervisor, potentially improving performance significantly
1587	  over full virtualization.
1588
1589config PARAVIRT_TIME_ACCOUNTING
1590	bool "Paravirtual steal time accounting"
1591	select PARAVIRT
1592	help
1593	  Select this option to enable fine granularity task steal time
1594	  accounting. Time spent executing other tasks in parallel with
1595	  the current vCPU is discounted from the vCPU power. To account for
1596	  that, there can be a small performance impact.
1597
1598	  If in doubt, say N here.
1599
1600config ARCH_SUPPORTS_KEXEC
1601	def_bool PM_SLEEP_SMP
1602
1603config ARCH_SUPPORTS_KEXEC_FILE
1604	def_bool y
1605
1606config ARCH_SELECTS_KEXEC_FILE
1607	def_bool y
1608	depends on KEXEC_FILE
1609	select HAVE_IMA_KEXEC if IMA
1610
1611config ARCH_SUPPORTS_KEXEC_SIG
1612	def_bool y
1613
1614config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG
1615	def_bool y
1616
1617config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG
1618	def_bool y
1619
1620config ARCH_SUPPORTS_KEXEC_HANDOVER
1621	def_bool y
1622
1623config ARCH_SUPPORTS_CRASH_DUMP
1624	def_bool y
1625
1626config ARCH_DEFAULT_CRASH_DUMP
1627	def_bool y
1628
1629config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
1630	def_bool CRASH_RESERVE
1631
1632config TRANS_TABLE
1633	def_bool y
1634	depends on HIBERNATION || KEXEC_CORE
1635
1636config XEN_DOM0
1637	def_bool y
1638	depends on XEN
1639
1640config XEN
1641	bool "Xen guest support on ARM64"
1642	depends on ARM64 && OF
1643	select SWIOTLB_XEN
1644	select PARAVIRT
1645	help
1646	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1647
1648# include/linux/mmzone.h requires the following to be true:
1649#
1650#   MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1651#
1652# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1653#
1654#     | SECTION_SIZE_BITS |  PAGE_SHIFT  |  max MAX_PAGE_ORDER  |  default MAX_PAGE_ORDER |
1655# ----+-------------------+--------------+----------------------+-------------------------+
1656# 4K  |       27          |      12      |       15             |         10              |
1657# 16K |       27          |      14      |       13             |         11              |
1658# 64K |       29          |      16      |       13             |         13              |
1659config ARCH_FORCE_MAX_ORDER
1660	int
1661	default "13" if ARM64_64K_PAGES
1662	default "11" if ARM64_16K_PAGES
1663	default "10"
1664	help
1665	  The kernel page allocator limits the size of maximal physically
1666	  contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1667	  defines the maximal power of two of number of pages that can be
1668	  allocated as a single contiguous block. This option allows
1669	  overriding the default setting when ability to allocate very
1670	  large blocks of physically contiguous memory is required.
1671
1672	  The maximal size of allocation cannot exceed the size of the
1673	  section, so the value of MAX_PAGE_ORDER should satisfy
1674
1675	    MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1676
1677	  Don't change if unsure.
1678
1679config UNMAP_KERNEL_AT_EL0
1680	bool "Unmap kernel when running in userspace (KPTI)" if EXPERT
1681	default y
1682	help
1683	  Speculation attacks against some high-performance processors can
1684	  be used to bypass MMU permission checks and leak kernel data to
1685	  userspace. This can be defended against by unmapping the kernel
1686	  when running in userspace, mapping it back in on exception entry
1687	  via a trampoline page in the vector table.
1688
1689	  If unsure, say Y.
1690
1691config MITIGATE_SPECTRE_BRANCH_HISTORY
1692	bool "Mitigate Spectre style attacks against branch history" if EXPERT
1693	default y
1694	help
1695	  Speculation attacks against some high-performance processors can
1696	  make use of branch history to influence future speculation.
1697	  When taking an exception from user-space, a sequence of branches
1698	  or a firmware call overwrites the branch history.
1699
1700config RODATA_FULL_DEFAULT_ENABLED
1701	bool "Apply r/o permissions of VM areas also to their linear aliases"
1702	default y
1703	help
1704	  Apply read-only attributes of VM areas to the linear alias of
1705	  the backing pages as well. This prevents code or read-only data
1706	  from being modified (inadvertently or intentionally) via another
1707	  mapping of the same memory page. This additional enhancement can
1708	  be turned off at runtime by passing rodata=[off|on] (and turned on
1709	  with rodata=full if this option is set to 'n')
1710
1711	  This requires the linear region to be mapped down to pages,
1712	  which may adversely affect performance in some cases.
1713
1714config ARM64_SW_TTBR0_PAN
1715	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1716	depends on !KCSAN
1717	select ARM64_PAN
1718	help
1719	  Enabling this option prevents the kernel from accessing
1720	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1721	  zeroed area and reserved ASID. The user access routines
1722	  restore the valid TTBR0_EL1 temporarily.
1723
1724config ARM64_TAGGED_ADDR_ABI
1725	bool "Enable the tagged user addresses syscall ABI"
1726	default y
1727	help
1728	  When this option is enabled, user applications can opt in to a
1729	  relaxed ABI via prctl() allowing tagged addresses to be passed
1730	  to system calls as pointer arguments. For details, see
1731	  Documentation/arch/arm64/tagged-address-abi.rst.
1732
1733menuconfig COMPAT
1734	bool "Kernel support for 32-bit EL0"
1735	depends on ARM64_4K_PAGES || EXPERT
1736	select HAVE_UID16
1737	select OLD_SIGSUSPEND3
1738	select COMPAT_OLD_SIGACTION
1739	help
1740	  This option enables support for a 32-bit EL0 running under a 64-bit
1741	  kernel at EL1. AArch32-specific components such as system calls,
1742	  the user helper functions, VFP support and the ptrace interface are
1743	  handled appropriately by the kernel.
1744
1745	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1746	  that you will only be able to execute AArch32 binaries that were compiled
1747	  with page size aligned segments.
1748
1749	  If you want to execute 32-bit userspace applications, say Y.
1750
1751if COMPAT
1752
1753config KUSER_HELPERS
1754	bool "Enable kuser helpers page for 32-bit applications"
1755	default y
1756	help
1757	  Warning: disabling this option may break 32-bit user programs.
1758
1759	  Provide kuser helpers to compat tasks. The kernel provides
1760	  helper code to userspace in read only form at a fixed location
1761	  to allow userspace to be independent of the CPU type fitted to
1762	  the system. This permits binaries to be run on ARMv4 through
1763	  to ARMv8 without modification.
1764
1765	  See Documentation/arch/arm/kernel_user_helpers.rst for details.
1766
1767	  However, the fixed address nature of these helpers can be used
1768	  by ROP (return orientated programming) authors when creating
1769	  exploits.
1770
1771	  If all of the binaries and libraries which run on your platform
1772	  are built specifically for your platform, and make no use of
1773	  these helpers, then you can turn this option off to hinder
1774	  such exploits. However, in that case, if a binary or library
1775	  relying on those helpers is run, it will not function correctly.
1776
1777	  Say N here only if you are absolutely certain that you do not
1778	  need these helpers; otherwise, the safe option is to say Y.
1779
1780config COMPAT_VDSO
1781	bool "Enable vDSO for 32-bit applications"
1782	depends on !CPU_BIG_ENDIAN
1783	depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1784	select GENERIC_COMPAT_VDSO
1785	default y
1786	help
1787	  Place in the process address space of 32-bit applications an
1788	  ELF shared object providing fast implementations of gettimeofday
1789	  and clock_gettime.
1790
1791	  You must have a 32-bit build of glibc 2.22 or later for programs
1792	  to seamlessly take advantage of this.
1793
1794config THUMB2_COMPAT_VDSO
1795	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1796	depends on COMPAT_VDSO
1797	default y
1798	help
1799	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1800	  otherwise with '-marm'.
1801
1802config COMPAT_ALIGNMENT_FIXUPS
1803	bool "Fix up misaligned multi-word loads and stores in user space"
1804
1805menuconfig ARMV8_DEPRECATED
1806	bool "Emulate deprecated/obsolete ARMv8 instructions"
1807	depends on SYSCTL
1808	help
1809	  Legacy software support may require certain instructions
1810	  that have been deprecated or obsoleted in the architecture.
1811
1812	  Enable this config to enable selective emulation of these
1813	  features.
1814
1815	  If unsure, say Y
1816
1817if ARMV8_DEPRECATED
1818
1819config SWP_EMULATION
1820	bool "Emulate SWP/SWPB instructions"
1821	help
1822	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1823	  they are always undefined. Say Y here to enable software
1824	  emulation of these instructions for userspace using LDXR/STXR.
1825	  This feature can be controlled at runtime with the abi.swp
1826	  sysctl which is disabled by default.
1827
1828	  In some older versions of glibc [<=2.8] SWP is used during futex
1829	  trylock() operations with the assumption that the code will not
1830	  be preempted. This invalid assumption may be more likely to fail
1831	  with SWP emulation enabled, leading to deadlock of the user
1832	  application.
1833
1834	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1835	  on an external transaction monitoring block called a global
1836	  monitor to maintain update atomicity. If your system does not
1837	  implement a global monitor, this option can cause programs that
1838	  perform SWP operations to uncached memory to deadlock.
1839
1840	  If unsure, say Y
1841
1842config CP15_BARRIER_EMULATION
1843	bool "Emulate CP15 Barrier instructions"
1844	help
1845	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1846	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1847	  strongly recommended to use the ISB, DSB, and DMB
1848	  instructions instead.
1849
1850	  Say Y here to enable software emulation of these
1851	  instructions for AArch32 userspace code. When this option is
1852	  enabled, CP15 barrier usage is traced which can help
1853	  identify software that needs updating. This feature can be
1854	  controlled at runtime with the abi.cp15_barrier sysctl.
1855
1856	  If unsure, say Y
1857
1858config SETEND_EMULATION
1859	bool "Emulate SETEND instruction"
1860	help
1861	  The SETEND instruction alters the data-endianness of the
1862	  AArch32 EL0, and is deprecated in ARMv8.
1863
1864	  Say Y here to enable software emulation of the instruction
1865	  for AArch32 userspace code. This feature can be controlled
1866	  at runtime with the abi.setend sysctl.
1867
1868	  Note: All the cpus on the system must have mixed endian support at EL0
1869	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1870	  endian - is hotplugged in after this feature has been enabled, there could
1871	  be unexpected results in the applications.
1872
1873	  If unsure, say Y
1874endif # ARMV8_DEPRECATED
1875
1876endif # COMPAT
1877
1878menu "ARMv8.1 architectural features"
1879
1880config ARM64_HW_AFDBM
1881	bool "Support for hardware updates of the Access and Dirty page flags"
1882	default y
1883	help
1884	  The ARMv8.1 architecture extensions introduce support for
1885	  hardware updates of the access and dirty information in page
1886	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1887	  capable processors, accesses to pages with PTE_AF cleared will
1888	  set this bit instead of raising an access flag fault.
1889	  Similarly, writes to read-only pages with the DBM bit set will
1890	  clear the read-only bit (AP[2]) instead of raising a
1891	  permission fault.
1892
1893	  Kernels built with this configuration option enabled continue
1894	  to work on pre-ARMv8.1 hardware and the performance impact is
1895	  minimal. If unsure, say Y.
1896
1897config ARM64_PAN
1898	bool "Enable support for Privileged Access Never (PAN)"
1899	default y
1900	help
1901	  Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1902	  prevents the kernel or hypervisor from accessing user-space (EL0)
1903	  memory directly.
1904
1905	  Choosing this option will cause any unprotected (not using
1906	  copy_to_user et al) memory access to fail with a permission fault.
1907
1908	  The feature is detected at runtime, and will remain as a 'nop'
1909	  instruction if the cpu does not implement the feature.
1910
1911config ARM64_LSE_ATOMICS
1912	bool
1913	default ARM64_USE_LSE_ATOMICS
1914
1915config ARM64_USE_LSE_ATOMICS
1916	bool "Atomic instructions"
1917	default y
1918	help
1919	  As part of the Large System Extensions, ARMv8.1 introduces new
1920	  atomic instructions that are designed specifically to scale in
1921	  very large systems.
1922
1923	  Say Y here to make use of these instructions for the in-kernel
1924	  atomic routines. This incurs a small overhead on CPUs that do
1925	  not support these instructions.
1926
1927endmenu # "ARMv8.1 architectural features"
1928
1929menu "ARMv8.2 architectural features"
1930
1931config ARM64_PMEM
1932	bool "Enable support for persistent memory"
1933	select ARCH_HAS_PMEM_API
1934	select ARCH_HAS_UACCESS_FLUSHCACHE
1935	help
1936	  Say Y to enable support for the persistent memory API based on the
1937	  ARMv8.2 DCPoP feature.
1938
1939	  The feature is detected at runtime, and the kernel will use DC CVAC
1940	  operations if DC CVAP is not supported (following the behaviour of
1941	  DC CVAP itself if the system does not define a point of persistence).
1942
1943config ARM64_RAS_EXTN
1944	bool "Enable support for RAS CPU Extensions"
1945	default y
1946	help
1947	  CPUs that support the Reliability, Availability and Serviceability
1948	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1949	  errors, classify them and report them to software.
1950
1951	  On CPUs with these extensions system software can use additional
1952	  barriers to determine if faults are pending and read the
1953	  classification from a new set of registers.
1954
1955	  Selecting this feature will allow the kernel to use these barriers
1956	  and access the new registers if the system supports the extension.
1957	  Platform RAS features may additionally depend on firmware support.
1958
1959config ARM64_CNP
1960	bool "Enable support for Common Not Private (CNP) translations"
1961	default y
1962	help
1963	  Common Not Private (CNP) allows translation table entries to
1964	  be shared between different PEs in the same inner shareable
1965	  domain, so the hardware can use this fact to optimise the
1966	  caching of such entries in the TLB.
1967
1968	  Selecting this option allows the CNP feature to be detected
1969	  at runtime, and does not affect PEs that do not implement
1970	  this feature.
1971
1972endmenu # "ARMv8.2 architectural features"
1973
1974menu "ARMv8.3 architectural features"
1975
1976config ARM64_PTR_AUTH
1977	bool "Enable support for pointer authentication"
1978	default y
1979	help
1980	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1981	  instructions for signing and authenticating pointers against secret
1982	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1983	  and other attacks.
1984
1985	  This option enables these instructions at EL0 (i.e. for userspace).
1986	  Choosing this option will cause the kernel to initialise secret keys
1987	  for each process at exec() time, with these keys being
1988	  context-switched along with the process.
1989
1990	  The feature is detected at runtime. If the feature is not present in
1991	  hardware it will not be advertised to userspace/KVM guest nor will it
1992	  be enabled.
1993
1994	  If the feature is present on the boot CPU but not on a late CPU, then
1995	  the late CPU will be parked. Also, if the boot CPU does not have
1996	  address auth and the late CPU has then the late CPU will still boot
1997	  but with the feature disabled. On such a system, this option should
1998	  not be selected.
1999
2000config ARM64_PTR_AUTH_KERNEL
2001	bool "Use pointer authentication for kernel"
2002	default y
2003	depends on ARM64_PTR_AUTH
2004	# Modern compilers insert a .note.gnu.property section note for PAC
2005	# which is only understood by binutils starting with version 2.33.1.
2006	depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
2007	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
2008	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2009	help
2010	  If the compiler supports the -mbranch-protection or
2011	  -msign-return-address flag (e.g. GCC 7 or later), then this option
2012	  will cause the kernel itself to be compiled with return address
2013	  protection. In this case, and if the target hardware is known to
2014	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
2015	  disabled with minimal loss of protection.
2016
2017	  This feature works with FUNCTION_GRAPH_TRACER option only if
2018	  DYNAMIC_FTRACE_WITH_ARGS is enabled.
2019
2020config CC_HAS_BRANCH_PROT_PAC_RET
2021	# GCC 9 or later, clang 8 or later
2022	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
2023
2024config AS_HAS_CFI_NEGATE_RA_STATE
2025	# binutils 2.34+
2026	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2027
2028endmenu # "ARMv8.3 architectural features"
2029
2030menu "ARMv8.4 architectural features"
2031
2032config ARM64_AMU_EXTN
2033	bool "Enable support for the Activity Monitors Unit CPU extension"
2034	default y
2035	help
2036	  The activity monitors extension is an optional extension introduced
2037	  by the ARMv8.4 CPU architecture. This enables support for version 1
2038	  of the activity monitors architecture, AMUv1.
2039
2040	  To enable the use of this extension on CPUs that implement it, say Y.
2041
2042	  Note that for architectural reasons, firmware _must_ implement AMU
2043	  support when running on CPUs that present the activity monitors
2044	  extension. The required support is present in:
2045	    * Version 1.5 and later of the ARM Trusted Firmware
2046
2047	  For kernels that have this configuration enabled but boot with broken
2048	  firmware, you may need to say N here until the firmware is fixed.
2049	  Otherwise you may experience firmware panics or lockups when
2050	  accessing the counter registers. Even if you are not observing these
2051	  symptoms, the values returned by the register reads might not
2052	  correctly reflect reality. Most commonly, the value read will be 0,
2053	  indicating that the counter is not enabled.
2054
2055config ARM64_TLB_RANGE
2056	bool "Enable support for tlbi range feature"
2057	default y
2058	help
2059	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2060	  range of input addresses.
2061
2062endmenu # "ARMv8.4 architectural features"
2063
2064menu "ARMv8.5 architectural features"
2065
2066config AS_HAS_ARMV8_5
2067	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2068
2069config ARM64_BTI
2070	bool "Branch Target Identification support"
2071	default y
2072	help
2073	  Branch Target Identification (part of the ARMv8.5 Extensions)
2074	  provides a mechanism to limit the set of locations to which computed
2075	  branch instructions such as BR or BLR can jump.
2076
2077	  To make use of BTI on CPUs that support it, say Y.
2078
2079	  BTI is intended to provide complementary protection to other control
2080	  flow integrity protection mechanisms, such as the Pointer
2081	  authentication mechanism provided as part of the ARMv8.3 Extensions.
2082	  For this reason, it does not make sense to enable this option without
2083	  also enabling support for pointer authentication.  Thus, when
2084	  enabling this option you should also select ARM64_PTR_AUTH=y.
2085
2086	  Userspace binaries must also be specifically compiled to make use of
2087	  this mechanism.  If you say N here or the hardware does not support
2088	  BTI, such binaries can still run, but you get no additional
2089	  enforcement of branch destinations.
2090
2091config ARM64_BTI_KERNEL
2092	bool "Use Branch Target Identification for kernel"
2093	default y
2094	depends on ARM64_BTI
2095	depends on ARM64_PTR_AUTH_KERNEL
2096	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
2097	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
2098	depends on !CC_IS_GCC || GCC_VERSION >= 100100
2099	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
2100	depends on !CC_IS_GCC
2101	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2102	help
2103	  Build the kernel with Branch Target Identification annotations
2104	  and enable enforcement of this for kernel code. When this option
2105	  is enabled and the system supports BTI all kernel code including
2106	  modular code must have BTI enabled.
2107
2108config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2109	# GCC 9 or later, clang 8 or later
2110	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2111
2112config ARM64_E0PD
2113	bool "Enable support for E0PD"
2114	default y
2115	help
2116	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
2117	  that EL0 accesses made via TTBR1 always fault in constant time,
2118	  providing similar benefits to KASLR as those provided by KPTI, but
2119	  with lower overhead and without disrupting legitimate access to
2120	  kernel memory such as SPE.
2121
2122	  This option enables E0PD for TTBR1 where available.
2123
2124config ARM64_AS_HAS_MTE
2125	# Initial support for MTE went in binutils 2.32.0, checked with
2126	# ".arch armv8.5-a+memtag" below. However, this was incomplete
2127	# as a late addition to the final architecture spec (LDGM/STGM)
2128	# is only supported in the newer 2.32.x and 2.33 binutils
2129	# versions, hence the extra "stgm" instruction check below.
2130	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2131
2132config ARM64_MTE
2133	bool "Memory Tagging Extension support"
2134	default y
2135	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2136	depends on AS_HAS_ARMV8_5
2137	# Required for tag checking in the uaccess routines
2138	select ARM64_PAN
2139	select ARCH_HAS_SUBPAGE_FAULTS
2140	select ARCH_USES_HIGH_VMA_FLAGS
2141	select ARCH_USES_PG_ARCH_2
2142	select ARCH_USES_PG_ARCH_3
2143	help
2144	  Memory Tagging (part of the ARMv8.5 Extensions) provides
2145	  architectural support for run-time, always-on detection of
2146	  various classes of memory error to aid with software debugging
2147	  to eliminate vulnerabilities arising from memory-unsafe
2148	  languages.
2149
2150	  This option enables the support for the Memory Tagging
2151	  Extension at EL0 (i.e. for userspace).
2152
2153	  Selecting this option allows the feature to be detected at
2154	  runtime. Any secondary CPU not implementing this feature will
2155	  not be allowed a late bring-up.
2156
2157	  Userspace binaries that want to use this feature must
2158	  explicitly opt in. The mechanism for the userspace is
2159	  described in:
2160
2161	  Documentation/arch/arm64/memory-tagging-extension.rst.
2162
2163endmenu # "ARMv8.5 architectural features"
2164
2165menu "ARMv8.7 architectural features"
2166
2167config ARM64_EPAN
2168	bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2169	default y
2170	depends on ARM64_PAN
2171	help
2172	  Enhanced Privileged Access Never (EPAN) allows Privileged
2173	  Access Never to be used with Execute-only mappings.
2174
2175	  The feature is detected at runtime, and will remain disabled
2176	  if the cpu does not implement the feature.
2177endmenu # "ARMv8.7 architectural features"
2178
2179config AS_HAS_MOPS
2180	def_bool $(as-instr,.arch_extension mops)
2181
2182menu "ARMv8.9 architectural features"
2183
2184config ARM64_POE
2185	prompt "Permission Overlay Extension"
2186	def_bool y
2187	select ARCH_USES_HIGH_VMA_FLAGS
2188	select ARCH_HAS_PKEYS
2189	help
2190	  The Permission Overlay Extension is used to implement Memory
2191	  Protection Keys. Memory Protection Keys provides a mechanism for
2192	  enforcing page-based protections, but without requiring modification
2193	  of the page tables when an application changes protection domains.
2194
2195	  For details, see Documentation/core-api/protection-keys.rst
2196
2197	  If unsure, say y.
2198
2199config ARCH_PKEY_BITS
2200	int
2201	default 3
2202
2203config ARM64_HAFT
2204	bool "Support for Hardware managed Access Flag for Table Descriptors"
2205	depends on ARM64_HW_AFDBM
2206	default y
2207	help
2208	  The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access
2209	  Flag for Table descriptors. When enabled an architectural executed
2210	  memory access will update the Access Flag in each Table descriptor
2211	  which is accessed during the translation table walk and for which
2212	  the Access Flag is 0. The Access Flag of the Table descriptor use
2213	  the same bit of PTE_AF.
2214
2215	  The feature will only be enabled if all the CPUs in the system
2216	  support this feature. If unsure, say Y.
2217
2218endmenu # "ARMv8.9 architectural features"
2219
2220menu "v9.4 architectural features"
2221
2222config ARM64_GCS
2223	bool "Enable support for Guarded Control Stack (GCS)"
2224	default y
2225	select ARCH_HAS_USER_SHADOW_STACK
2226	select ARCH_USES_HIGH_VMA_FLAGS
2227	depends on !UPROBES
2228	help
2229	  Guarded Control Stack (GCS) provides support for a separate
2230	  stack with restricted access which contains only return
2231	  addresses.  This can be used to harden against some attacks
2232	  by comparing return address used by the program with what is
2233	  stored in the GCS, and may also be used to efficiently obtain
2234	  the call stack for applications such as profiling.
2235
2236	  The feature is detected at runtime, and will remain disabled
2237	  if the system does not implement the feature.
2238
2239endmenu # "v9.4 architectural features"
2240
2241config ARM64_SVE
2242	bool "ARM Scalable Vector Extension support"
2243	default y
2244	help
2245	  The Scalable Vector Extension (SVE) is an extension to the AArch64
2246	  execution state which complements and extends the SIMD functionality
2247	  of the base architecture to support much larger vectors and to enable
2248	  additional vectorisation opportunities.
2249
2250	  To enable use of this extension on CPUs that implement it, say Y.
2251
2252	  On CPUs that support the SVE2 extensions, this option will enable
2253	  those too.
2254
2255	  Note that for architectural reasons, firmware _must_ implement SVE
2256	  support when running on SVE capable hardware.  The required support
2257	  is present in:
2258
2259	    * version 1.5 and later of the ARM Trusted Firmware
2260	    * the AArch64 boot wrapper since commit 5e1261e08abf
2261	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
2262
2263	  For other firmware implementations, consult the firmware documentation
2264	  or vendor.
2265
2266	  If you need the kernel to boot on SVE-capable hardware with broken
2267	  firmware, you may need to say N here until you get your firmware
2268	  fixed.  Otherwise, you may experience firmware panics or lockups when
2269	  booting the kernel.  If unsure and you are not observing these
2270	  symptoms, you should assume that it is safe to say Y.
2271
2272config ARM64_SME
2273	bool "ARM Scalable Matrix Extension support"
2274	default y
2275	depends on ARM64_SVE
2276	help
2277	  The Scalable Matrix Extension (SME) is an extension to the AArch64
2278	  execution state which utilises a substantial subset of the SVE
2279	  instruction set, together with the addition of new architectural
2280	  register state capable of holding two dimensional matrix tiles to
2281	  enable various matrix operations.
2282
2283config ARM64_PSEUDO_NMI
2284	bool "Support for NMI-like interrupts"
2285	select ARM_GIC_V3
2286	help
2287	  Adds support for mimicking Non-Maskable Interrupts through the use of
2288	  GIC interrupt priority. This support requires version 3 or later of
2289	  ARM GIC.
2290
2291	  This high priority configuration for interrupts needs to be
2292	  explicitly enabled by setting the kernel parameter
2293	  "irqchip.gicv3_pseudo_nmi" to 1.
2294
2295	  If unsure, say N
2296
2297if ARM64_PSEUDO_NMI
2298config ARM64_DEBUG_PRIORITY_MASKING
2299	bool "Debug interrupt priority masking"
2300	help
2301	  This adds runtime checks to functions enabling/disabling
2302	  interrupts when using priority masking. The additional checks verify
2303	  the validity of ICC_PMR_EL1 when calling concerned functions.
2304
2305	  If unsure, say N
2306endif # ARM64_PSEUDO_NMI
2307
2308config RELOCATABLE
2309	bool "Build a relocatable kernel image" if EXPERT
2310	select ARCH_HAS_RELR
2311	default y
2312	help
2313	  This builds the kernel as a Position Independent Executable (PIE),
2314	  which retains all relocation metadata required to relocate the
2315	  kernel binary at runtime to a different virtual address than the
2316	  address it was linked at.
2317	  Since AArch64 uses the RELA relocation format, this requires a
2318	  relocation pass at runtime even if the kernel is loaded at the
2319	  same address it was linked at.
2320
2321config RANDOMIZE_BASE
2322	bool "Randomize the address of the kernel image"
2323	select RELOCATABLE
2324	help
2325	  Randomizes the virtual address at which the kernel image is
2326	  loaded, as a security feature that deters exploit attempts
2327	  relying on knowledge of the location of kernel internals.
2328
2329	  It is the bootloader's job to provide entropy, by passing a
2330	  random u64 value in /chosen/kaslr-seed at kernel entry.
2331
2332	  When booting via the UEFI stub, it will invoke the firmware's
2333	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2334	  to the kernel proper. In addition, it will randomise the physical
2335	  location of the kernel Image as well.
2336
2337	  If unsure, say N.
2338
2339config RANDOMIZE_MODULE_REGION_FULL
2340	bool "Randomize the module region over a 2 GB range"
2341	depends on RANDOMIZE_BASE
2342	default y
2343	help
2344	  Randomizes the location of the module region inside a 2 GB window
2345	  covering the core kernel. This way, it is less likely for modules
2346	  to leak information about the location of core kernel data structures
2347	  but it does imply that function calls between modules and the core
2348	  kernel will need to be resolved via veneers in the module PLT.
2349
2350	  When this option is not set, the module region will be randomized over
2351	  a limited range that contains the [_stext, _etext] interval of the
2352	  core kernel, so branch relocations are almost always in range unless
2353	  the region is exhausted. In this particular case of region
2354	  exhaustion, modules might be able to fall back to a larger 2GB area.
2355
2356config CC_HAVE_STACKPROTECTOR_SYSREG
2357	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2358
2359config STACKPROTECTOR_PER_TASK
2360	def_bool y
2361	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2362
2363config UNWIND_PATCH_PAC_INTO_SCS
2364	bool "Enable shadow call stack dynamically using code patching"
2365	# needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated
2366	depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2367	depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2368	depends on SHADOW_CALL_STACK
2369	select UNWIND_TABLES
2370	select DYNAMIC_SCS
2371
2372config ARM64_CONTPTE
2373	bool "Contiguous PTE mappings for user memory" if EXPERT
2374	depends on TRANSPARENT_HUGEPAGE
2375	default y
2376	help
2377	  When enabled, user mappings are configured using the PTE contiguous
2378	  bit, for any mappings that meet the size and alignment requirements.
2379	  This reduces TLB pressure and improves performance.
2380
2381endmenu # "Kernel Features"
2382
2383menu "Boot options"
2384
2385config ARM64_ACPI_PARKING_PROTOCOL
2386	bool "Enable support for the ARM64 ACPI parking protocol"
2387	depends on ACPI
2388	help
2389	  Enable support for the ARM64 ACPI parking protocol. If disabled
2390	  the kernel will not allow booting through the ARM64 ACPI parking
2391	  protocol even if the corresponding data is present in the ACPI
2392	  MADT table.
2393
2394config CMDLINE
2395	string "Default kernel command string"
2396	default ""
2397	help
2398	  Provide a set of default command-line options at build time by
2399	  entering them here. As a minimum, you should specify the the
2400	  root device (e.g. root=/dev/nfs).
2401
2402choice
2403	prompt "Kernel command line type"
2404	depends on CMDLINE != ""
2405	default CMDLINE_FROM_BOOTLOADER
2406	help
2407	  Choose how the kernel will handle the provided default kernel
2408	  command line string.
2409
2410config CMDLINE_FROM_BOOTLOADER
2411	bool "Use bootloader kernel arguments if available"
2412	help
2413	  Uses the command-line options passed by the boot loader. If
2414	  the boot loader doesn't provide any, the default kernel command
2415	  string provided in CMDLINE will be used.
2416
2417config CMDLINE_FORCE
2418	bool "Always use the default kernel command string"
2419	help
2420	  Always use the default kernel command string, even if the boot
2421	  loader passes other arguments to the kernel.
2422	  This is useful if you cannot or don't want to change the
2423	  command-line options your boot loader passes to the kernel.
2424
2425endchoice
2426
2427config EFI_STUB
2428	bool
2429
2430config EFI
2431	bool "UEFI runtime support"
2432	depends on OF && !CPU_BIG_ENDIAN
2433	depends on KERNEL_MODE_NEON
2434	select ARCH_SUPPORTS_ACPI
2435	select LIBFDT
2436	select UCS2_STRING
2437	select EFI_PARAMS_FROM_FDT
2438	select EFI_RUNTIME_WRAPPERS
2439	select EFI_STUB
2440	select EFI_GENERIC_STUB
2441	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2442	default y
2443	help
2444	  This option provides support for runtime services provided
2445	  by UEFI firmware (such as non-volatile variables, realtime
2446	  clock, and platform reset). A UEFI stub is also provided to
2447	  allow the kernel to be booted as an EFI application. This
2448	  is only useful on systems that have UEFI firmware.
2449
2450config COMPRESSED_INSTALL
2451	bool "Install compressed image by default"
2452	help
2453	  This makes the regular "make install" install the compressed
2454	  image we built, not the legacy uncompressed one.
2455
2456	  You can check that a compressed image works for you by doing
2457	  "make zinstall" first, and verifying that everything is fine
2458	  in your environment before making "make install" do this for
2459	  you.
2460
2461config DMI
2462	bool "Enable support for SMBIOS (DMI) tables"
2463	depends on EFI
2464	default y
2465	help
2466	  This enables SMBIOS/DMI feature for systems.
2467
2468	  This option is only useful on systems that have UEFI firmware.
2469	  However, even with this option, the resultant kernel should
2470	  continue to boot on existing non-UEFI platforms.
2471
2472endmenu # "Boot options"
2473
2474menu "Power management options"
2475
2476source "kernel/power/Kconfig"
2477
2478config ARCH_HIBERNATION_POSSIBLE
2479	def_bool y
2480	depends on CPU_PM
2481
2482config ARCH_HIBERNATION_HEADER
2483	def_bool y
2484	depends on HIBERNATION
2485
2486config ARCH_SUSPEND_POSSIBLE
2487	def_bool y
2488
2489endmenu # "Power management options"
2490
2491menu "CPU Power Management"
2492
2493source "drivers/cpuidle/Kconfig"
2494
2495source "drivers/cpufreq/Kconfig"
2496
2497endmenu # "CPU Power Management"
2498
2499source "drivers/acpi/Kconfig"
2500
2501source "arch/arm64/kvm/Kconfig"
2502
2503