1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/V2H(P) CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 32 /* Internal Core Clocks */ 33 CLK_PLLCM33_DIV16, 34 CLK_PLLCLN_DIV2, 35 CLK_PLLCLN_DIV8, 36 CLK_PLLCLN_DIV16, 37 CLK_PLLDTY_ACPU, 38 CLK_PLLDTY_ACPU_DIV4, 39 40 /* Module Clocks */ 41 MOD_CLK_BASE, 42 }; 43 44 static const struct clk_div_table dtable_1_8[] = { 45 {0, 1}, 46 {1, 2}, 47 {2, 4}, 48 {3, 8}, 49 {0, 0}, 50 }; 51 52 static const struct clk_div_table dtable_2_64[] = { 53 {0, 2}, 54 {1, 4}, 55 {2, 8}, 56 {3, 16}, 57 {4, 64}, 58 {0, 0}, 59 }; 60 61 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 62 /* External Clock Inputs */ 63 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 64 DEF_INPUT("rtxin", CLK_RTXIN), 65 DEF_INPUT("qextal", CLK_QEXTAL), 66 67 /* PLL Clocks */ 68 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 69 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 70 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 71 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), 72 73 /* Internal Core Clocks */ 74 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 75 76 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 77 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 78 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 79 80 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 81 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 82 83 /* Core Clocks */ 84 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 85 DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55, 86 CDDIV1_DIVCTL0, dtable_1_8), 87 DEF_DDIV("ca55_0_coreclk1", R9A09G057_CA55_0_CORE_CLK1, CLK_PLLCA55, 88 CDDIV1_DIVCTL1, dtable_1_8), 89 DEF_DDIV("ca55_0_coreclk2", R9A09G057_CA55_0_CORE_CLK2, CLK_PLLCA55, 90 CDDIV1_DIVCTL2, dtable_1_8), 91 DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55, 92 CDDIV1_DIVCTL3, dtable_1_8), 93 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 94 }; 95 96 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 97 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5), 98 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3), 99 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4), 100 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5), 101 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6), 102 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7), 103 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8), 104 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9), 105 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10), 106 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11), 107 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12), 108 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13), 109 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14), 110 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15), 111 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16), 112 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17), 113 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18), 114 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), 115 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19), 116 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20), 117 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21), 118 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22), 119 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23), 120 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24), 121 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25), 122 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26), 123 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27), 124 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3), 125 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4), 126 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5), 127 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6), 128 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7), 129 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8), 130 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9), 131 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10), 132 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11), 133 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12), 134 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13), 135 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14), 136 }; 137 138 static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 139 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 140 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ 141 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ 142 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ 143 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */ 144 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */ 145 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ 146 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 147 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 148 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */ 149 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 150 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 151 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 152 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 153 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 154 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 155 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 156 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 157 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 158 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 159 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 160 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 161 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 162 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 163 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 164 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 165 }; 166 167 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { 168 /* Core Clocks */ 169 .core_clks = r9a09g057_core_clks, 170 .num_core_clks = ARRAY_SIZE(r9a09g057_core_clks), 171 .last_dt_core_clk = LAST_DT_CORE_CLK, 172 .num_total_core_clks = MOD_CLK_BASE, 173 174 /* Module Clocks */ 175 .mod_clks = r9a09g057_mod_clks, 176 .num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks), 177 .num_hw_mod_clks = 25 * 16, 178 179 /* Resets */ 180 .resets = r9a09g057_resets, 181 .num_resets = ARRAY_SIZE(r9a09g057_resets), 182 }; 183