1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
6 *
7 * This code was implemented by Mocean Laboratories AB when porting linux
8 * to the automotive development board Russellville. The copyright holder
9 * as seen in the header is Intel corporation.
10 * Mocean Laboratories forked off the GNU/Linux platform work into a
11 * separate company called Pelagicore AB, which committed the code to the
12 * kernel.
13 */
14
15 /* Supports:
16 * Xilinx IIC
17 */
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/completion.h>
27 #include <linux/platform_data/i2c-xiic.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/iopoll.h>
33 #include <linux/spinlock.h>
34
35 #define DRIVER_NAME "xiic-i2c"
36 #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0)
37 #define SMBUS_BLOCK_READ_MIN_LEN 3
38
39 enum xilinx_i2c_state {
40 STATE_DONE,
41 STATE_ERROR,
42 STATE_START
43 };
44
45 enum xiic_endian {
46 LITTLE,
47 BIG
48 };
49
50 enum i2c_scl_freq {
51 REG_VALUES_100KHZ = 0,
52 REG_VALUES_400KHZ = 1,
53 REG_VALUES_1MHZ = 2
54 };
55
56 /**
57 * struct xiic_i2c - Internal representation of the XIIC I2C bus
58 * @dev: Pointer to device structure
59 * @base: Memory base of the HW registers
60 * @completion: Completion for callers
61 * @adap: Kernel adapter representation
62 * @tx_msg: Messages from above to be sent
63 * @lock: Mutual exclusion
64 * @tx_pos: Current pos in TX message
65 * @nmsgs: Number of messages in tx_msg
66 * @rx_msg: Current RX message
67 * @rx_pos: Position within current RX message
68 * @endianness: big/little-endian byte order
69 * @clk: Pointer to AXI4-lite input clock
70 * @irq: Interrupt number
71 * @state: See STATE_
72 * @singlemaster: Indicates bus is single master
73 * @dynamic: Mode of controller
74 * @prev_msg_tx: Previous message is Tx
75 * @quirks: To hold platform specific bug info
76 * @smbus_block_read: Flag to handle block read
77 * @smbus_actual_len: Valid byte count (length + payload + optional PEC) of a
78 * padded SMBus block read. msg->len is trimmed to this on completion.
79 * Zero when no trimming is needed.
80 * @input_clk: Input clock to I2C controller
81 * @i2c_clk: I2C SCL frequency
82 * @atomic: Mode of transfer
83 * @atomic_lock: Lock for atomic transfer mode
84 * @atomic_xfer_state: See STATE_
85 */
86 struct xiic_i2c {
87 struct device *dev;
88 void __iomem *base;
89 struct completion completion;
90 struct i2c_adapter adap;
91 struct i2c_msg *tx_msg;
92 struct mutex lock;
93 unsigned int tx_pos;
94 unsigned int nmsgs;
95 struct i2c_msg *rx_msg;
96 int rx_pos;
97 enum xiic_endian endianness;
98 struct clk *clk;
99 int irq;
100 enum xilinx_i2c_state state;
101 bool singlemaster;
102 bool dynamic;
103 bool prev_msg_tx;
104 u32 quirks;
105 bool smbus_block_read;
106 unsigned int smbus_actual_len;
107 unsigned long input_clk;
108 unsigned int i2c_clk;
109 bool atomic;
110 spinlock_t atomic_lock; /* Lock for atomic transfer mode */
111 enum xilinx_i2c_state atomic_xfer_state;
112 };
113
114 struct xiic_version_data {
115 u32 quirks;
116 };
117
118 /**
119 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
120 * @tsusta: setup time for a repeated START condition
121 * @tsusto: setup time for a STOP condition
122 * @thdsta: hold time for a repeated START condition
123 * @tsudat: setup time for data
124 * @tbuf: bus free time between STOP and START
125 */
126 struct timing_regs {
127 unsigned int tsusta;
128 unsigned int tsusto;
129 unsigned int thdsta;
130 unsigned int tsudat;
131 unsigned int tbuf;
132 };
133
134 /* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
135 static const struct timing_regs timing_reg_values[] = {
136 { 5700, 5000, 4300, 550, 5000 }, /* Reg values for 100KHz */
137 { 900, 900, 900, 400, 1600 }, /* Reg values for 400KHz */
138 { 380, 380, 380, 170, 620 }, /* Reg values for 1MHz */
139 };
140
141 #define XIIC_MSB_OFFSET 0
142 #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET)
143
144 /*
145 * Register offsets in bytes from RegisterBase. Three is added to the
146 * base offset to access LSB (IBM style) of the word
147 */
148 #define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */
149 #define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */
150 #define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */
151 #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */
152 #define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */
153 #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
154 #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
155 #define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */
156 #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
157 #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */
158
159 /*
160 * Timing register offsets from RegisterBase. These are used only for
161 * setting i2c clock frequency for the line.
162 */
163 #define XIIC_TSUSTA_REG_OFFSET (0x28 + XIIC_REG_OFFSET) /* TSUSTA Register */
164 #define XIIC_TSUSTO_REG_OFFSET (0x2C + XIIC_REG_OFFSET) /* TSUSTO Register */
165 #define XIIC_THDSTA_REG_OFFSET (0x30 + XIIC_REG_OFFSET) /* THDSTA Register */
166 #define XIIC_TSUDAT_REG_OFFSET (0x34 + XIIC_REG_OFFSET) /* TSUDAT Register */
167 #define XIIC_TBUF_REG_OFFSET (0x38 + XIIC_REG_OFFSET) /* TBUF Register */
168 #define XIIC_THIGH_REG_OFFSET (0x3C + XIIC_REG_OFFSET) /* THIGH Register */
169 #define XIIC_TLOW_REG_OFFSET (0x40 + XIIC_REG_OFFSET) /* TLOW Register */
170 #define XIIC_THDDAT_REG_OFFSET (0x44 + XIIC_REG_OFFSET) /* THDDAT Register */
171
172 /* Control Register masks */
173 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
174 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
175 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
176 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
177 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
178 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
179 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
180
181 /* Status Register masks */
182 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
183 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
184 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
185 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
186 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
187 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
188 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
189 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
190
191 /* Interrupt Status Register masks Interrupt occurs when... */
192 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
193 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
194 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
195 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
196 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
197 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
198 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
199 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
200
201 /* The following constants specify the depth of the FIFOs */
202 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
203 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
204
205 /* The following constants specify groups of interrupts that are typically
206 * enabled or disables at the same time
207 */
208 #define XIIC_TX_INTERRUPTS \
209 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
210
211 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
212
213 /*
214 * Tx Fifo upper bit masks.
215 */
216 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
217 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
218
219 /* Dynamic mode constants */
220 #define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */
221
222 /*
223 * The following constants define the register offsets for the Interrupt
224 * registers. There are some holes in the memory map for reserved addresses
225 * to allow other registers to be added and still match the memory map of the
226 * interrupt controller registers
227 */
228 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
229 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
230 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
231 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
232
233 #define XIIC_RESET_MASK 0xAUL
234
235 #define XIIC_PM_TIMEOUT 1000 /* ms */
236 /* timeout waiting for the controller to respond */
237 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000))
238 /* timeout waiting for the controller finish transfers */
239 #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000))
240 /* timeout waiting for the controller finish transfers in micro seconds */
241 #define XIIC_XFER_TIMEOUT_US 10000000
242
243 /*
244 * The following constant is used for the device global interrupt enable
245 * register, to enable all interrupts for the device, this is the only bit
246 * in the register
247 */
248 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
249
250 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
251 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
252
253 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
254 static void __xiic_start_xfer(struct xiic_i2c *i2c);
255
xiic_i2c_runtime_suspend(struct device * dev)256 static int xiic_i2c_runtime_suspend(struct device *dev)
257 {
258 struct xiic_i2c *i2c = dev_get_drvdata(dev);
259
260 clk_disable(i2c->clk);
261
262 return 0;
263 }
264
xiic_i2c_runtime_resume(struct device * dev)265 static int xiic_i2c_runtime_resume(struct device *dev)
266 {
267 struct xiic_i2c *i2c = dev_get_drvdata(dev);
268 int ret;
269
270 ret = clk_enable(i2c->clk);
271 if (ret) {
272 dev_err(dev, "Cannot enable clock.\n");
273 return ret;
274 }
275
276 return 0;
277 }
278
279 /*
280 * For the register read and write functions, a little-endian and big-endian
281 * version are necessary. Endianness is detected during the probe function.
282 * Only the least significant byte [doublet] of the register are ever
283 * accessed. This requires an offset of 3 [2] from the base address for
284 * big-endian systems.
285 */
286
xiic_setreg8(struct xiic_i2c * i2c,int reg,u8 value)287 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
288 {
289 if (i2c->endianness == LITTLE)
290 iowrite8(value, i2c->base + reg);
291 else
292 iowrite8(value, i2c->base + reg + 3);
293 }
294
xiic_getreg8(struct xiic_i2c * i2c,int reg)295 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
296 {
297 u8 ret;
298
299 if (i2c->endianness == LITTLE)
300 ret = ioread8(i2c->base + reg);
301 else
302 ret = ioread8(i2c->base + reg + 3);
303 return ret;
304 }
305
xiic_setreg16(struct xiic_i2c * i2c,int reg,u16 value)306 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
307 {
308 if (i2c->endianness == LITTLE)
309 iowrite16(value, i2c->base + reg);
310 else
311 iowrite16be(value, i2c->base + reg + 2);
312 }
313
xiic_setreg32(struct xiic_i2c * i2c,int reg,int value)314 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
315 {
316 if (i2c->endianness == LITTLE)
317 iowrite32(value, i2c->base + reg);
318 else
319 iowrite32be(value, i2c->base + reg);
320 }
321
xiic_getreg32(struct xiic_i2c * i2c,int reg)322 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
323 {
324 u32 ret;
325
326 if (i2c->endianness == LITTLE)
327 ret = ioread32(i2c->base + reg);
328 else
329 ret = ioread32be(i2c->base + reg);
330 return ret;
331 }
332
xiic_irq_dis(struct xiic_i2c * i2c,u32 mask)333 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
334 {
335 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
336
337 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
338 }
339
xiic_irq_en(struct xiic_i2c * i2c,u32 mask)340 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
341 {
342 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
343
344 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
345 }
346
xiic_irq_clr(struct xiic_i2c * i2c,u32 mask)347 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
348 {
349 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
350
351 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
352 }
353
xiic_irq_clr_en(struct xiic_i2c * i2c,u32 mask)354 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
355 {
356 xiic_irq_clr(i2c, mask);
357 xiic_irq_en(i2c, mask);
358 }
359
xiic_clear_rx_fifo(struct xiic_i2c * i2c)360 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
361 {
362 u8 sr;
363 unsigned long timeout;
364
365 timeout = jiffies + XIIC_I2C_TIMEOUT;
366 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
367 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
368 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
369 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
370 if (time_after(jiffies, timeout)) {
371 dev_err(i2c->dev, "Failed to clear rx fifo\n");
372 return -ETIMEDOUT;
373 }
374 }
375
376 return 0;
377 }
378
xiic_wait_tx_empty(struct xiic_i2c * i2c)379 static int xiic_wait_tx_empty(struct xiic_i2c *i2c)
380 {
381 u8 isr;
382 unsigned long timeout;
383
384 timeout = jiffies + XIIC_I2C_TIMEOUT;
385 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
386 !(isr & XIIC_INTR_TX_EMPTY_MASK);
387 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) {
388 if (time_after(jiffies, timeout)) {
389 dev_err(i2c->dev, "Timeout waiting at Tx empty\n");
390 return -ETIMEDOUT;
391 }
392 }
393
394 return 0;
395 }
396
397 /**
398 * xiic_setclk - Sets the configured clock rate
399 * @i2c: Pointer to the xiic device structure
400 *
401 * The timing register values are calculated according to the input clock
402 * frequency and configured scl frequency. For details, please refer the
403 * AXI I2C PG and NXP I2C Spec.
404 * Supported frequencies are 100KHz, 400KHz and 1MHz.
405 *
406 * Return: 0 on success (Supported frequency selected or not configurable in SW)
407 * -EINVAL on failure (scl frequency not supported or THIGH is 0)
408 */
xiic_setclk(struct xiic_i2c * i2c)409 static int xiic_setclk(struct xiic_i2c *i2c)
410 {
411 unsigned int clk_in_mhz;
412 unsigned int index = 0;
413 u32 reg_val;
414
415 if (!i2c->atomic)
416 dev_dbg(i2c->adap.dev.parent,
417 "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
418 __func__, i2c->input_clk, i2c->i2c_clk);
419
420 /* If not specified in DT, do not configure in SW. Rely only on Vivado design */
421 if (!i2c->i2c_clk || !i2c->input_clk)
422 return 0;
423
424 clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000);
425
426 switch (i2c->i2c_clk) {
427 case I2C_MAX_FAST_MODE_PLUS_FREQ:
428 index = REG_VALUES_1MHZ;
429 break;
430 case I2C_MAX_FAST_MODE_FREQ:
431 index = REG_VALUES_400KHZ;
432 break;
433 case I2C_MAX_STANDARD_MODE_FREQ:
434 index = REG_VALUES_100KHZ;
435 break;
436 default:
437 dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n");
438 return -EINVAL;
439 }
440
441 /*
442 * Value to be stored in a register is the number of clock cycles required
443 * for the time duration. So the time is divided by the input clock time
444 * period to get the number of clock cycles required. Refer Xilinx AXI I2C
445 * PG document and I2C specification for further details.
446 */
447
448 /* THIGH - Depends on SCL clock frequency(i2c_clk) as below */
449 reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7;
450 if (reg_val == 0)
451 return -EINVAL;
452
453 xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);
454
455 /* TLOW - Value same as THIGH */
456 xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);
457
458 /* TSUSTA */
459 reg_val = (timing_reg_values[index].tsusta * clk_in_mhz) / 1000;
460 xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);
461
462 /* TSUSTO */
463 reg_val = (timing_reg_values[index].tsusto * clk_in_mhz) / 1000;
464 xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);
465
466 /* THDSTA */
467 reg_val = (timing_reg_values[index].thdsta * clk_in_mhz) / 1000;
468 xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);
469
470 /* TSUDAT */
471 reg_val = (timing_reg_values[index].tsudat * clk_in_mhz) / 1000;
472 xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);
473
474 /* TBUF */
475 reg_val = (timing_reg_values[index].tbuf * clk_in_mhz) / 1000;
476 xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);
477
478 /* THDDAT */
479 xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1);
480
481 return 0;
482 }
483
xiic_reinit(struct xiic_i2c * i2c)484 static int xiic_reinit(struct xiic_i2c *i2c)
485 {
486 int ret;
487
488 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
489
490 ret = xiic_setclk(i2c);
491 if (ret)
492 return ret;
493
494 /* Set receive Fifo depth to maximum (zero based). */
495 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
496
497 /* Reset Tx Fifo. */
498 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
499
500 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
501 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
502
503 /* make sure RX fifo is empty */
504 ret = xiic_clear_rx_fifo(i2c);
505 if (ret)
506 return ret;
507
508 /* Enable interrupts */
509 if (!i2c->atomic)
510 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
511
512 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
513
514 return 0;
515 }
516
xiic_deinit(struct xiic_i2c * i2c)517 static void xiic_deinit(struct xiic_i2c *i2c)
518 {
519 u8 cr;
520
521 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
522
523 /* Disable IIC Device. */
524 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
525 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
526 }
527
xiic_smbus_block_read_setup(struct xiic_i2c * i2c)528 static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c)
529 {
530 u8 rxmsg_len, rfd_set = 0;
531
532 /*
533 * Clear the I2C_M_RECV_LEN flag to avoid setting
534 * message length again
535 */
536 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN;
537
538 /* Set smbus_block_read flag to identify in isr */
539 i2c->smbus_block_read = true;
540
541 /* Read byte from rx fifo and set message length */
542 rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
543
544 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len;
545
546 /* Check if received length is valid */
547 if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) {
548 unsigned int pec_len = i2c->rx_msg->len - 1;
549
550 /* Set Receive fifo depth */
551 if (rxmsg_len + pec_len > IIC_RX_FIFO_DEPTH) {
552 /*
553 * Trailing bytes (payload plus any PEC) exceed Rx FIFO
554 * capacity, so drain in chunks. This also keeps the
555 * else branch below from pushing rfd_set past the
556 * 4-bit XIIC_RFD_REG_OFFSET field.
557 */
558 rfd_set = IIC_RX_FIFO_DEPTH - 1;
559 i2c->rx_msg->len = rxmsg_len + 1 + pec_len;
560 } else if (1 + rxmsg_len + pec_len < SMBUS_BLOCK_READ_MIN_LEN) {
561 /*
562 * The HW needs SMBUS_BLOCK_READ_MIN_LEN bytes on the
563 * bus to exit cleanly: by the time the ISR reads the
564 * length byte the second byte is already being clocked
565 * in, too late to NACK. Pad the drain target and record
566 * the real length, trimmed back on completion so the
567 * PEC check sees the right byte.
568 */
569 rfd_set = 0;
570 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN;
571 i2c->smbus_actual_len = 1 + rxmsg_len + pec_len;
572 } else {
573 /*
574 * All trailing bytes fit in the Rx FIFO. Defer RX_FULL
575 * until every one of them is buffered, so the drain
576 * takes xiic_read_rx()'s bytes_rem == 0 path.
577 */
578 rfd_set = rxmsg_len + pec_len - 1;
579 i2c->rx_msg->len = rxmsg_len + 1 + pec_len;
580 }
581 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
582
583 return;
584 }
585
586 /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */
587 i2c->tx_msg->len = 3;
588 i2c->smbus_block_read = false;
589 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n");
590 }
591
592 /*
593 * Undo the setup-time padding of a short SMBus block read before rx_msg is
594 * cleared, so the PEC check sees the right byte.
595 */
xiic_smbus_trim_len(struct xiic_i2c * i2c)596 static void xiic_smbus_trim_len(struct xiic_i2c *i2c)
597 {
598 if (i2c->rx_msg && i2c->smbus_actual_len)
599 i2c->rx_msg->len = i2c->smbus_actual_len;
600 }
601
xiic_read_rx(struct xiic_i2c * i2c)602 static void xiic_read_rx(struct xiic_i2c *i2c)
603 {
604 u8 bytes_in_fifo, cr = 0, bytes_to_read = 0;
605 u32 bytes_rem = 0;
606 int i;
607
608 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
609
610 if (!i2c->atomic)
611 dev_dbg(i2c->adap.dev.parent,
612 "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n",
613 __func__, bytes_in_fifo, xiic_rx_space(i2c),
614 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
615 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
616
617 if (bytes_in_fifo > xiic_rx_space(i2c))
618 bytes_in_fifo = xiic_rx_space(i2c);
619
620 bytes_to_read = bytes_in_fifo;
621
622 if (!i2c->dynamic) {
623 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo;
624
625 /* Set msg length if smbus_block_read */
626 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) {
627 xiic_smbus_block_read_setup(i2c);
628 return;
629 }
630
631 if (bytes_rem > IIC_RX_FIFO_DEPTH) {
632 bytes_to_read = bytes_in_fifo;
633 } else if (bytes_rem > 1) {
634 bytes_to_read = bytes_rem - 1;
635 } else if (bytes_rem == 1) {
636 bytes_to_read = 1;
637 /* Set NACK in CR to indicate slave transmitter */
638 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
639 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
640 XIIC_CR_NO_ACK_MASK);
641 } else if (bytes_rem == 0) {
642 bytes_to_read = bytes_in_fifo;
643
644 /* Generate stop on the bus if it is last message */
645 if (i2c->nmsgs == 1) {
646 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
647 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
648 ~XIIC_CR_MSMS_MASK);
649 }
650
651 /* Make TXACK=0, clean up for next transaction */
652 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
653 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
654 ~XIIC_CR_NO_ACK_MASK);
655 }
656 }
657
658 /* Read the fifo */
659 for (i = 0; i < bytes_to_read; i++) {
660 i2c->rx_msg->buf[i2c->rx_pos++] =
661 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
662 }
663
664 if (i2c->dynamic) {
665 u8 bytes;
666
667 /* Receive remaining bytes if less than fifo depth */
668 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH);
669 bytes--;
670 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
671 }
672 }
673
xiic_error_check(struct xiic_i2c * i2c)674 static bool xiic_error_check(struct xiic_i2c *i2c)
675 {
676 bool status = false;
677 u32 pend, isr, ier;
678
679 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
680 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
681 pend = isr & ier;
682
683 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
684 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
685 !(pend & XIIC_INTR_RX_FULL_MASK))) {
686 xiic_reinit(i2c);
687 status = true;
688 if (i2c->tx_msg || i2c->rx_msg)
689 i2c->atomic_xfer_state = STATE_ERROR;
690 }
691 return status;
692 }
693
xiic_tx_fifo_space(struct xiic_i2c * i2c)694 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
695 {
696 /* return the actual space left in the FIFO */
697 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
698 }
699
xiic_fill_tx_fifo(struct xiic_i2c * i2c)700 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
701 {
702 u8 fifo_space = xiic_tx_fifo_space(i2c);
703 int len = xiic_tx_space(i2c);
704
705 len = (len > fifo_space) ? fifo_space : len;
706
707 if (!i2c->atomic)
708 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
709 __func__, len, fifo_space);
710
711 while (len--) {
712 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
713
714 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
715 /* last message in transfer -> STOP */
716 if (i2c->dynamic) {
717 data |= XIIC_TX_DYN_STOP_MASK;
718 } else {
719 u8 cr;
720 int status;
721
722 /* Wait till FIFO is empty so STOP is sent last */
723 status = xiic_wait_tx_empty(i2c);
724 if (status)
725 return;
726
727 /* Write to CR to stop */
728 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
729 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
730 ~XIIC_CR_MSMS_MASK);
731 }
732 if (!i2c->atomic)
733 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
734 }
735 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
736
737 if (i2c->atomic && xiic_error_check(i2c))
738 return;
739 }
740 }
741
xiic_wakeup(struct xiic_i2c * i2c,enum xilinx_i2c_state code)742 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code)
743 {
744 i2c->tx_msg = NULL;
745 i2c->rx_msg = NULL;
746 i2c->nmsgs = 0;
747 i2c->state = code;
748 complete(&i2c->completion);
749 }
750
xiic_process(int irq,void * dev_id)751 static irqreturn_t xiic_process(int irq, void *dev_id)
752 {
753 struct xiic_i2c *i2c = dev_id;
754 u32 pend, isr, ier;
755 u32 clr = 0;
756 int xfer_more = 0;
757 int wakeup_req = 0;
758 enum xilinx_i2c_state wakeup_code = STATE_DONE;
759 int ret;
760
761 /* Get the interrupt Status from the IPIF. There is no clearing of
762 * interrupts in the IPIF. Interrupts must be cleared at the source.
763 * To find which interrupts are pending; AND interrupts pending with
764 * interrupts masked.
765 */
766 mutex_lock(&i2c->lock);
767 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
768 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
769 pend = isr & ier;
770
771 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
772 __func__, ier, isr, pend);
773 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
774 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
775 i2c->tx_msg, i2c->nmsgs);
776 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n",
777 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
778 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
779
780 /* Service requesting interrupt */
781 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
782 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
783 !(pend & XIIC_INTR_RX_FULL_MASK))) {
784 /* bus arbritration lost, or...
785 * Transmit error _OR_ RX completed
786 * if this happens when RX_FULL is not set
787 * this is probably a TX error
788 */
789
790 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
791
792 /* dynamic mode seem to suffer from problems if we just flushes
793 * fifos and the next message is a TX with len 0 (only addr)
794 * reset the IP instead of just flush fifos
795 */
796 ret = xiic_reinit(i2c);
797 if (ret < 0)
798 dev_dbg(i2c->adap.dev.parent, "reinit failed\n");
799
800 if (i2c->rx_msg) {
801 wakeup_req = 1;
802 wakeup_code = STATE_ERROR;
803 }
804 if (i2c->tx_msg) {
805 wakeup_req = 1;
806 wakeup_code = STATE_ERROR;
807 }
808 /* don't try to handle other events */
809 goto out;
810 }
811 if (pend & XIIC_INTR_RX_FULL_MASK) {
812 /* Receive register/FIFO is full */
813
814 clr |= XIIC_INTR_RX_FULL_MASK;
815 if (!i2c->rx_msg) {
816 dev_dbg(i2c->adap.dev.parent,
817 "%s unexpected RX IRQ\n", __func__);
818 xiic_clear_rx_fifo(i2c);
819 goto out;
820 }
821
822 xiic_read_rx(i2c);
823 if (xiic_rx_space(i2c) == 0) {
824 xiic_smbus_trim_len(i2c);
825
826 /* this is the last part of the message */
827 i2c->rx_msg = NULL;
828
829 /* also clear TX error if there (RX complete) */
830 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
831
832 dev_dbg(i2c->adap.dev.parent,
833 "%s end of message, nmsgs: %d\n",
834 __func__, i2c->nmsgs);
835
836 /* send next message if this wasn't the last,
837 * otherwise the transfer will be finialise when
838 * receiving the bus not busy interrupt
839 */
840 if (i2c->nmsgs > 1) {
841 i2c->nmsgs--;
842 i2c->tx_msg++;
843 dev_dbg(i2c->adap.dev.parent,
844 "%s will start next...\n", __func__);
845 xfer_more = 1;
846 }
847 }
848 }
849 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
850 /* Transmit register/FIFO is empty or ½ empty */
851
852 clr |= (pend &
853 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
854
855 if (!i2c->tx_msg) {
856 dev_dbg(i2c->adap.dev.parent,
857 "%s unexpected TX IRQ\n", __func__);
858 goto out;
859 }
860
861 if (xiic_tx_space(i2c)) {
862 xiic_fill_tx_fifo(i2c);
863 } else {
864 /* current message fully written */
865 dev_dbg(i2c->adap.dev.parent,
866 "%s end of message sent, nmsgs: %d\n",
867 __func__, i2c->nmsgs);
868 /* Don't move onto the next message until the TX FIFO empties,
869 * to ensure that a NAK is not missed.
870 */
871 if (i2c->nmsgs > 1 && (pend & XIIC_INTR_TX_EMPTY_MASK)) {
872 i2c->nmsgs--;
873 i2c->tx_msg++;
874 xfer_more = 1;
875 } else {
876 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
877
878 dev_dbg(i2c->adap.dev.parent,
879 "%s Got TX IRQ but no more to do...\n",
880 __func__);
881 }
882 }
883 }
884
885 if (pend & XIIC_INTR_BNB_MASK) {
886 /* IIC bus has transitioned to not busy */
887 clr |= XIIC_INTR_BNB_MASK;
888
889 /* The bus is not busy, disable BusNotBusy interrupt */
890 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
891
892 if (i2c->tx_msg && i2c->smbus_block_read) {
893 i2c->smbus_block_read = false;
894 /*
895 * Drive xiic_tx_space() to 0 to signal STATE_DONE
896 * without truncating the rx_msg length.
897 */
898 i2c->tx_pos = i2c->tx_msg->len;
899 }
900
901 if (!i2c->tx_msg)
902 goto out;
903
904 wakeup_req = 1;
905
906 if (i2c->nmsgs == 1 && !i2c->rx_msg &&
907 xiic_tx_space(i2c) == 0)
908 wakeup_code = STATE_DONE;
909 else
910 wakeup_code = STATE_ERROR;
911 }
912
913 out:
914 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
915
916 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
917 if (xfer_more)
918 __xiic_start_xfer(i2c);
919 if (wakeup_req)
920 xiic_wakeup(i2c, wakeup_code);
921
922 WARN_ON(xfer_more && wakeup_req);
923
924 mutex_unlock(&i2c->lock);
925 return IRQ_HANDLED;
926 }
927
xiic_bus_busy(struct xiic_i2c * i2c)928 static int xiic_bus_busy(struct xiic_i2c *i2c)
929 {
930 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
931
932 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
933 }
934
xiic_wait_not_busy(struct xiic_i2c * i2c)935 static int xiic_wait_not_busy(struct xiic_i2c *i2c)
936 {
937 int tries = 3;
938 int err;
939
940 /* for instance if previous transfer was terminated due to TX error
941 * it might be that the bus is on it's way to become available
942 * give it at most 3 ms to wake
943 */
944 err = xiic_bus_busy(i2c);
945 while (err && tries--) {
946 if (i2c->atomic)
947 udelay(1000);
948 else
949 usleep_range(1000, 1100);
950 err = xiic_bus_busy(i2c);
951 }
952
953 return err;
954 }
955
xiic_recv_atomic(struct xiic_i2c * i2c)956 static void xiic_recv_atomic(struct xiic_i2c *i2c)
957 {
958 while (xiic_rx_space(i2c)) {
959 if (xiic_getreg32(i2c, XIIC_IISR_OFFSET) & XIIC_INTR_RX_FULL_MASK) {
960 xiic_read_rx(i2c);
961
962 /* Clear Rx full and Tx error interrupts. */
963 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
964 XIIC_INTR_TX_ERROR_MASK);
965 }
966 if (xiic_error_check(i2c))
967 return;
968 }
969
970 xiic_smbus_trim_len(i2c);
971 i2c->rx_msg = NULL;
972 xiic_irq_clr_en(i2c, XIIC_INTR_TX_ERROR_MASK);
973
974 /* send next message if this wasn't the last. */
975 if (i2c->nmsgs > 1) {
976 i2c->nmsgs--;
977 i2c->tx_msg++;
978 __xiic_start_xfer(i2c);
979 }
980 }
981
xiic_start_recv(struct xiic_i2c * i2c)982 static void xiic_start_recv(struct xiic_i2c *i2c)
983 {
984 u16 rx_watermark;
985 u8 cr = 0, rfd_set = 0;
986 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
987
988 /* A stale value from an aborted block read would truncate this msg. */
989 i2c->smbus_actual_len = 0;
990
991 if (!i2c->atomic)
992 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
993 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
994 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
995
996 /* Disable Tx interrupts */
997 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK);
998
999 if (i2c->dynamic) {
1000 u8 bytes;
1001 u16 val;
1002
1003 /* Clear and enable Rx full interrupt. */
1004 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
1005 XIIC_INTR_TX_ERROR_MASK);
1006
1007 /*
1008 * We want to get all but last byte, because the TX_ERROR IRQ
1009 * is used to indicate error ACK on the address, and
1010 * negative ack on the last received byte, so to not mix
1011 * them receive all but last.
1012 * In the case where there is only one byte to receive
1013 * we can check if ERROR and RX full is set at the same time
1014 */
1015 rx_watermark = msg->len;
1016 bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH);
1017
1018 if (rx_watermark > 0)
1019 bytes--;
1020 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
1021
1022 /* write the address */
1023 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
1024 i2c_8bit_addr_from_msg(msg) |
1025 XIIC_TX_DYN_START_MASK);
1026
1027 /* If last message, include dynamic stop bit with length */
1028 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0;
1029 val |= msg->len;
1030
1031 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
1032
1033 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
1034 } else {
1035 /*
1036 * If previous message is Tx, make sure that Tx FIFO is empty
1037 * before starting a new transfer as the repeated start in
1038 * standard mode can corrupt the transaction if there are
1039 * still bytes to be transmitted in FIFO
1040 */
1041 if (i2c->prev_msg_tx) {
1042 int status;
1043
1044 status = xiic_wait_tx_empty(i2c);
1045 if (status)
1046 return;
1047 }
1048
1049 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1050
1051 /* Set Receive fifo depth */
1052 rx_watermark = msg->len;
1053 if (rx_watermark > IIC_RX_FIFO_DEPTH) {
1054 rfd_set = IIC_RX_FIFO_DEPTH - 1;
1055 } else if (rx_watermark == 1) {
1056 rfd_set = rx_watermark - 1;
1057
1058 /* Set No_ACK, except for smbus_block_read */
1059 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) {
1060 /* Handle single byte transfer separately */
1061 cr |= XIIC_CR_NO_ACK_MASK;
1062 }
1063 } else if (rx_watermark == 0) {
1064 rfd_set = rx_watermark;
1065 } else {
1066 rfd_set = rx_watermark - 2;
1067 }
1068 /* Check if RSTA should be set */
1069 if (cr & XIIC_CR_MSMS_MASK) {
1070 /* Already a master, RSTA should be set */
1071 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1072 XIIC_CR_REPEATED_START_MASK) &
1073 ~(XIIC_CR_DIR_IS_TX_MASK));
1074 }
1075
1076 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
1077
1078 /* Clear and enable Rx full and transmit complete interrupts */
1079 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
1080 XIIC_INTR_TX_ERROR_MASK);
1081
1082 /* Write the address */
1083 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
1084 i2c_8bit_addr_from_msg(msg));
1085
1086 /* Write to Control Register,to start transaction in Rx mode */
1087 if ((cr & XIIC_CR_MSMS_MASK) == 0) {
1088 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1089 XIIC_CR_MSMS_MASK)
1090 & ~(XIIC_CR_DIR_IS_TX_MASK));
1091 }
1092 if (!i2c->atomic)
1093 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n",
1094 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
1095 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
1096 }
1097
1098 if (i2c->nmsgs == 1)
1099 /* very last, enable bus not busy as well */
1100 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
1101
1102 /* the message is tx:ed */
1103 i2c->tx_pos = msg->len;
1104
1105 i2c->prev_msg_tx = false;
1106
1107 /* Enable interrupts */
1108 if (!i2c->atomic)
1109 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
1110 else
1111 xiic_recv_atomic(i2c);
1112 }
1113
xiic_send_rem_atomic(struct xiic_i2c * i2c)1114 static void xiic_send_rem_atomic(struct xiic_i2c *i2c)
1115 {
1116 while (xiic_tx_space(i2c)) {
1117 if (xiic_tx_fifo_space(i2c)) {
1118 u16 data;
1119
1120 data = i2c->tx_msg->buf[i2c->tx_pos];
1121 i2c->tx_pos++;
1122 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
1123 /* last message in transfer -> STOP */
1124 if (i2c->dynamic) {
1125 data |= XIIC_TX_DYN_STOP_MASK;
1126 } else {
1127 u8 cr;
1128 int status;
1129
1130 /* Wait till FIFO is empty so STOP is sent last */
1131 status = xiic_wait_tx_empty(i2c);
1132 if (status)
1133 return;
1134
1135 /* Write to CR to stop */
1136 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1137 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
1138 ~XIIC_CR_MSMS_MASK);
1139 }
1140 }
1141 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1142 }
1143 if (xiic_error_check(i2c))
1144 return;
1145 }
1146
1147 if (i2c->nmsgs > 1) {
1148 i2c->nmsgs--;
1149 i2c->tx_msg++;
1150 __xiic_start_xfer(i2c);
1151 } else {
1152 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
1153 }
1154 }
1155
xiic_start_send(struct xiic_i2c * i2c)1156 static void xiic_start_send(struct xiic_i2c *i2c)
1157 {
1158 u8 cr = 0;
1159 u16 data;
1160 struct i2c_msg *msg = i2c->tx_msg;
1161
1162 if (!i2c->atomic) {
1163 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
1164 __func__, msg, msg->len);
1165 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
1166 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
1167 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
1168 }
1169
1170 if (i2c->dynamic) {
1171 /* write the address */
1172 data = i2c_8bit_addr_from_msg(msg) |
1173 XIIC_TX_DYN_START_MASK;
1174
1175 if (i2c->nmsgs == 1 && msg->len == 0)
1176 /* no data and last message -> add STOP */
1177 data |= XIIC_TX_DYN_STOP_MASK;
1178
1179 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1180
1181 /* Clear any pending Tx empty, Tx Error and then enable them */
1182 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1183 XIIC_INTR_TX_ERROR_MASK |
1184 XIIC_INTR_BNB_MASK |
1185 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ?
1186 XIIC_INTR_TX_HALF_MASK : 0));
1187
1188 xiic_fill_tx_fifo(i2c);
1189 } else {
1190 /*
1191 * If previous message is Tx, make sure that Tx FIFO is empty
1192 * before starting a new transfer as the repeated start in
1193 * standard mode can corrupt the transaction if there are
1194 * still bytes to be transmitted in FIFO
1195 */
1196 if (i2c->prev_msg_tx) {
1197 int status;
1198
1199 status = xiic_wait_tx_empty(i2c);
1200 if (status)
1201 return;
1202 }
1203 /* Check if RSTA should be set */
1204 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1205 if (cr & XIIC_CR_MSMS_MASK) {
1206 /* Already a master, RSTA should be set */
1207 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1208 XIIC_CR_REPEATED_START_MASK |
1209 XIIC_CR_DIR_IS_TX_MASK) &
1210 ~(XIIC_CR_NO_ACK_MASK));
1211 }
1212
1213 /* Write address to FIFO */
1214 data = i2c_8bit_addr_from_msg(msg);
1215 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1216
1217 /* Fill fifo */
1218 xiic_fill_tx_fifo(i2c);
1219
1220 if ((cr & XIIC_CR_MSMS_MASK) == 0) {
1221 /* Start Tx by writing to CR */
1222 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1223 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
1224 XIIC_CR_MSMS_MASK |
1225 XIIC_CR_DIR_IS_TX_MASK);
1226 }
1227
1228 /* Clear any pending Tx empty, Tx Error and then enable them */
1229 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1230 XIIC_INTR_TX_ERROR_MASK |
1231 XIIC_INTR_BNB_MASK);
1232 }
1233
1234 i2c->prev_msg_tx = true;
1235
1236 if (i2c->atomic && !i2c->atomic_xfer_state)
1237 xiic_send_rem_atomic(i2c);
1238 }
1239
__xiic_start_xfer(struct xiic_i2c * i2c)1240 static void __xiic_start_xfer(struct xiic_i2c *i2c)
1241 {
1242 int fifo_space = xiic_tx_fifo_space(i2c);
1243
1244 if (!i2c->atomic)
1245 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
1246 __func__, i2c->tx_msg, fifo_space);
1247
1248 if (!i2c->tx_msg)
1249 return;
1250
1251 if (i2c->atomic && xiic_error_check(i2c))
1252 return;
1253
1254 i2c->rx_pos = 0;
1255 i2c->tx_pos = 0;
1256 i2c->state = STATE_START;
1257 if (i2c->tx_msg->flags & I2C_M_RD) {
1258 /* we dont date putting several reads in the FIFO */
1259 xiic_start_recv(i2c);
1260 } else {
1261 xiic_start_send(i2c);
1262 }
1263 }
1264
xiic_start_xfer(struct xiic_i2c * i2c,struct i2c_msg * msgs,int num)1265 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
1266 {
1267 bool broken_read, max_read_len, smbus_blk_read;
1268 int ret, count;
1269
1270 if (i2c->atomic)
1271 spin_lock(&i2c->atomic_lock);
1272 else
1273 mutex_lock(&i2c->lock);
1274
1275 if (i2c->tx_msg || i2c->rx_msg) {
1276 dev_err(i2c->adap.dev.parent,
1277 "cannot start a transfer while busy\n");
1278 ret = -EBUSY;
1279 goto out;
1280 }
1281
1282 i2c->atomic_xfer_state = STATE_DONE;
1283
1284 /* In single master mode bus can only be busy, when in use by this
1285 * driver. If the register indicates bus being busy for some reason we
1286 * should ignore it, since bus will never be released and i2c will be
1287 * stuck forever.
1288 */
1289 if (!i2c->singlemaster) {
1290 ret = xiic_wait_not_busy(i2c);
1291 if (ret) {
1292 /* If the bus is stuck in a busy state, such as due to spurious low
1293 * pulses on the bus causing a false start condition to be detected,
1294 * then try to recover by re-initializing the controller and check
1295 * again if the bus is still busy.
1296 */
1297 dev_warn(i2c->adap.dev.parent, "I2C bus busy timeout, reinitializing\n");
1298 ret = xiic_reinit(i2c);
1299 if (ret)
1300 goto out;
1301 ret = xiic_wait_not_busy(i2c);
1302 if (ret)
1303 goto out;
1304 }
1305 }
1306
1307 i2c->tx_msg = msgs;
1308 i2c->rx_msg = NULL;
1309 i2c->nmsgs = num;
1310
1311 if (!i2c->atomic)
1312 init_completion(&i2c->completion);
1313
1314 /* Decide standard mode or Dynamic mode */
1315 i2c->dynamic = true;
1316
1317 /* Initialize prev message type */
1318 i2c->prev_msg_tx = false;
1319
1320 /*
1321 * Scan through nmsgs, use dynamic mode when none of the below three
1322 * conditions occur. We need standard mode even if one condition holds
1323 * true in the entire array of messages in a single transfer.
1324 * If read transaction as dynamic mode is broken for delayed reads
1325 * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions.
1326 * If read length is > 255 bytes.
1327 * If smbus_block_read transaction.
1328 */
1329 for (count = 0; count < i2c->nmsgs; count++) {
1330 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) &&
1331 (i2c->tx_msg[count].flags & I2C_M_RD);
1332 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) &&
1333 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC);
1334 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN);
1335
1336 if (broken_read || max_read_len || smbus_blk_read) {
1337 i2c->dynamic = false;
1338 break;
1339 }
1340 }
1341
1342 ret = xiic_reinit(i2c);
1343 if (!ret)
1344 __xiic_start_xfer(i2c);
1345
1346 out:
1347 if (i2c->atomic)
1348 spin_unlock(&i2c->atomic_lock);
1349 else
1350 mutex_unlock(&i2c->lock);
1351
1352 return ret;
1353 }
1354
xiic_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1355 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1356 {
1357 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
1358 int err;
1359
1360 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
1361 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
1362
1363 err = pm_runtime_resume_and_get(i2c->dev);
1364 if (err < 0)
1365 return err;
1366
1367 err = xiic_start_xfer(i2c, msgs, num);
1368 if (err < 0)
1369 goto out;
1370
1371 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT);
1372 mutex_lock(&i2c->lock);
1373 if (err == 0) { /* Timeout */
1374 i2c->tx_msg = NULL;
1375 i2c->rx_msg = NULL;
1376 i2c->nmsgs = 0;
1377 err = -ETIMEDOUT;
1378 } else {
1379 err = (i2c->state == STATE_DONE) ? num : -EIO;
1380 }
1381 mutex_unlock(&i2c->lock);
1382
1383 out:
1384 pm_runtime_put_autosuspend(i2c->dev);
1385 return err;
1386 }
1387
xiic_xfer_atomic(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1388 static int xiic_xfer_atomic(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1389 {
1390 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
1391 u32 status_reg;
1392 int err;
1393
1394 err = xiic_i2c_runtime_resume(i2c->dev);
1395 if (err)
1396 return err;
1397
1398 i2c->atomic = true;
1399 err = xiic_start_xfer(i2c, msgs, num);
1400 if (err < 0)
1401 return err;
1402
1403 err = readl_poll_timeout_atomic(i2c->base + XIIC_SR_REG_OFFSET,
1404 status_reg, !(status_reg & XIIC_SR_BUS_BUSY_MASK),
1405 1, XIIC_XFER_TIMEOUT_US);
1406
1407 if (err) /* Timeout */
1408 err = -ETIMEDOUT;
1409
1410 spin_lock(&i2c->atomic_lock);
1411 if (err || i2c->state) {
1412 i2c->tx_msg = NULL;
1413 i2c->rx_msg = NULL;
1414 i2c->nmsgs = 0;
1415 }
1416
1417 err = (i2c->atomic_xfer_state == STATE_DONE) ? num : -EIO;
1418 spin_unlock(&i2c->atomic_lock);
1419
1420 i2c->atomic = false;
1421 xiic_i2c_runtime_suspend(i2c->dev);
1422
1423 return err;
1424 }
1425
xiic_func(struct i2c_adapter * adap)1426 static u32 xiic_func(struct i2c_adapter *adap)
1427 {
1428 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
1429 }
1430
1431 static const struct i2c_algorithm xiic_algorithm = {
1432 .xfer = xiic_xfer,
1433 .xfer_atomic = xiic_xfer_atomic,
1434 .functionality = xiic_func,
1435 };
1436
1437 static const struct i2c_adapter xiic_adapter = {
1438 .owner = THIS_MODULE,
1439 .class = I2C_CLASS_DEPRECATED,
1440 .algo = &xiic_algorithm,
1441 };
1442
1443 static const struct xiic_version_data xiic_2_00 = {
1444 .quirks = DYNAMIC_MODE_READ_BROKEN_BIT,
1445 };
1446
1447 static const struct of_device_id xiic_of_match[] = {
1448 { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 },
1449 { .compatible = "xlnx,axi-iic-2.1", },
1450 {},
1451 };
1452 MODULE_DEVICE_TABLE(of, xiic_of_match);
1453
xiic_i2c_probe(struct platform_device * pdev)1454 static int xiic_i2c_probe(struct platform_device *pdev)
1455 {
1456 struct device *dev = &pdev->dev;
1457 struct fwnode_handle *fwnode = dev_fwnode(dev);
1458 struct xiic_i2c *i2c;
1459 struct xiic_i2c_platform_data *pdata;
1460 const struct xiic_version_data *data;
1461 struct resource *res;
1462 int ret, irq;
1463 u8 i;
1464 u32 sr;
1465
1466 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
1467 if (!i2c)
1468 return -ENOMEM;
1469
1470 data = device_get_match_data(dev);
1471 if (data)
1472 i2c->quirks = data->quirks;
1473
1474 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1475 if (IS_ERR(i2c->base))
1476 return PTR_ERR(i2c->base);
1477
1478 irq = platform_get_irq(pdev, 0);
1479 if (irq < 0)
1480 return irq;
1481
1482 pdata = dev_get_platdata(dev);
1483
1484 /* hook up driver to tree */
1485 platform_set_drvdata(pdev, i2c);
1486 i2c->adap = xiic_adapter;
1487 i2c->adap.nr = pdev->id;
1488 i2c_set_adapdata(&i2c->adap, i2c);
1489 i2c->adap.dev.parent = &pdev->dev;
1490 device_set_node(&i2c->adap.dev, fwnode);
1491 snprintf(i2c->adap.name, sizeof(i2c->adap.name),
1492 DRIVER_NAME " %s", pdev->name);
1493
1494 ret = devm_mutex_init(dev, &i2c->lock);
1495 if (ret)
1496 return ret;
1497
1498 spin_lock_init(&i2c->atomic_lock);
1499
1500 if (is_of_node(fwnode)) {
1501 i2c->clk = devm_clk_get_enabled(dev, NULL);
1502 if (IS_ERR(i2c->clk))
1503 return dev_err_probe(dev, PTR_ERR(i2c->clk),
1504 "failed to enable input clock.\n");
1505 }
1506
1507 i2c->dev = dev;
1508
1509 pm_runtime_set_autosuspend_delay(dev, XIIC_PM_TIMEOUT);
1510 pm_runtime_use_autosuspend(dev);
1511 /*
1512 * Enable runtime PM by hand: devm_pm_runtime_set_active_enabled()
1513 * tears down in an order that races the devm-enabled clock release and
1514 * makes clk_core_disable() WARN (see xiic_i2c_remove()).
1515 */
1516 ret = pm_runtime_set_active(dev);
1517 if (ret) {
1518 pm_runtime_dont_use_autosuspend(dev);
1519 return ret;
1520 }
1521 pm_runtime_enable(dev);
1522
1523 /* SCL frequency configuration */
1524 i2c->input_clk = clk_get_rate(i2c->clk);
1525 ret = device_property_read_u32(dev, "clock-frequency", &i2c->i2c_clk);
1526 /* If clock-frequency not specified in DT, do not configure in SW */
1527 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ)
1528 i2c->i2c_clk = 0;
1529
1530 /*
1531 * Request the IRQ non-managed: later probe steps unwind manually via
1532 * goto, so a devm handler could still be live after that teardown runs.
1533 */
1534 i2c->irq = irq;
1535 ret = request_threaded_irq(irq, NULL, xiic_process, IRQF_ONESHOT,
1536 pdev->name, i2c);
1537 if (ret)
1538 goto err_pm_disable;
1539
1540 i2c->singlemaster = device_property_read_bool(dev, "single-master");
1541
1542 /*
1543 * Detect endianness
1544 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
1545 * set, assume that the endianness was wrong and swap.
1546 */
1547 i2c->endianness = LITTLE;
1548 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
1549 /* Reset is cleared in xiic_reinit */
1550 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
1551 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
1552 i2c->endianness = BIG;
1553
1554 ret = xiic_reinit(i2c);
1555 if (ret) {
1556 dev_err_probe(dev, ret, "Cannot xiic_reinit\n");
1557 goto err_free_irq;
1558 }
1559
1560 /* add i2c adapter to i2c tree */
1561 ret = i2c_add_numbered_adapter(&i2c->adap);
1562 if (ret) {
1563 xiic_deinit(i2c);
1564 goto err_free_irq;
1565 }
1566
1567 if (pdata) {
1568 /* add in known devices to the bus */
1569 for (i = 0; i < pdata->num_devices; i++)
1570 i2c_new_client_device(&i2c->adap, pdata->devices + i);
1571 }
1572
1573 dev_dbg(dev, "mmio %pR irq %d scl clock frequency %d\n",
1574 res, irq, i2c->i2c_clk);
1575
1576 return 0;
1577
1578 err_free_irq:
1579 free_irq(irq, i2c);
1580 err_pm_disable:
1581 pm_runtime_disable(dev);
1582 pm_runtime_set_suspended(dev);
1583 pm_runtime_dont_use_autosuspend(dev);
1584
1585 return ret;
1586 }
1587
xiic_i2c_remove(struct platform_device * pdev)1588 static void xiic_i2c_remove(struct platform_device *pdev)
1589 {
1590 struct device *dev = &pdev->dev;
1591 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
1592 int ret;
1593
1594 /* remove adapter & data */
1595 i2c_del_adapter(&i2c->adap);
1596
1597 free_irq(i2c->irq, i2c);
1598
1599 ret = pm_runtime_get_sync(dev);
1600 if (ret < 0)
1601 dev_warn(dev, "Failed to activate device for removal (%pe)\n",
1602 ERR_PTR(ret));
1603 else
1604 xiic_deinit(i2c);
1605
1606 pm_runtime_disable(dev);
1607 pm_runtime_put_noidle(dev);
1608 pm_runtime_set_suspended(dev);
1609 pm_runtime_dont_use_autosuspend(dev);
1610 }
1611
1612 static const struct dev_pm_ops xiic_dev_pm_ops = {
1613 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
1614 xiic_i2c_runtime_resume, NULL)
1615 };
1616
1617 static struct platform_driver xiic_i2c_driver = {
1618 .probe = xiic_i2c_probe,
1619 .remove = xiic_i2c_remove,
1620 .driver = {
1621 .name = DRIVER_NAME,
1622 .of_match_table = of_match_ptr(xiic_of_match),
1623 .pm = &xiic_dev_pm_ops,
1624 },
1625 };
1626
1627 module_platform_driver(xiic_i2c_driver);
1628
1629 MODULE_ALIAS("platform:" DRIVER_NAME);
1630 MODULE_AUTHOR("info@mocean-labs.com");
1631 MODULE_DESCRIPTION("Xilinx I2C bus driver");
1632 MODULE_LICENSE("GPL v2");
1633