1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CRC32 25 select ARCH_HAS_CRC_T10DIF if KERNEL_MODE_NEON 26 select ARCH_HAS_CURRENT_STACK_POINTER 27 select ARCH_HAS_DEBUG_VIRTUAL 28 select ARCH_HAS_DEBUG_VM_PGTABLE 29 select ARCH_HAS_DMA_OPS if XEN 30 select ARCH_HAS_DMA_PREP_COHERENT 31 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 32 select ARCH_HAS_FAST_MULTIPLIER 33 select ARCH_HAS_FORTIFY_SOURCE 34 select ARCH_HAS_GCOV_PROFILE_ALL 35 select ARCH_HAS_GIGANTIC_PAGE 36 select ARCH_HAS_KCOV 37 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 38 select ARCH_HAS_KEEPINITRD 39 select ARCH_HAS_MEMBARRIER_SYNC_CORE 40 select ARCH_HAS_MEM_ENCRYPT 41 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 42 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 43 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 44 select ARCH_HAS_PTE_DEVMAP 45 select ARCH_HAS_PTE_SPECIAL 46 select ARCH_HAS_HW_PTE_YOUNG 47 select ARCH_HAS_SETUP_DMA_OPS 48 select ARCH_HAS_SET_DIRECT_MAP 49 select ARCH_HAS_SET_MEMORY 50 select ARCH_HAS_MEM_ENCRYPT 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_SYSCALL_WRAPPER 58 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 59 select ARCH_HAS_ZONE_DMA_SET if EXPERT 60 select ARCH_HAVE_ELF_PROT 61 select ARCH_HAVE_NMI_SAFE_CMPXCHG 62 select ARCH_HAVE_TRACE_MMIO_ACCESS 63 select ARCH_INLINE_READ_LOCK if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 65 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 70 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 73 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 74 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 77 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 78 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 79 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 83 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 84 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 87 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 88 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 89 select ARCH_KEEP_MEMBLOCK 90 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 91 select ARCH_USE_CMPXCHG_LOCKREF 92 select ARCH_USE_GNU_PROPERTY 93 select ARCH_USE_MEMTEST 94 select ARCH_USE_QUEUED_RWLOCKS 95 select ARCH_USE_QUEUED_SPINLOCKS 96 select ARCH_USE_SYM_ANNOTATIONS 97 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 98 select ARCH_SUPPORTS_HUGETLBFS 99 select ARCH_SUPPORTS_MEMORY_FAILURE 100 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 101 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 102 select ARCH_SUPPORTS_LTO_CLANG_THIN 103 select ARCH_SUPPORTS_CFI_CLANG 104 select ARCH_SUPPORTS_ATOMIC_RMW 105 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 106 select ARCH_SUPPORTS_NUMA_BALANCING 107 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 108 select ARCH_SUPPORTS_PER_VMA_LOCK 109 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 110 select ARCH_SUPPORTS_RT 111 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 112 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 113 select ARCH_WANT_DEFAULT_BPF_JIT 114 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 115 select ARCH_WANT_FRAME_POINTERS 116 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 117 select ARCH_WANT_LD_ORPHAN_WARN 118 select ARCH_WANTS_EXECMEM_LATE 119 select ARCH_WANTS_NO_INSTR 120 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 121 select ARCH_HAS_UBSAN 122 select ARM_AMBA 123 select ARM_ARCH_TIMER 124 select ARM_GIC 125 select AUDIT_ARCH_COMPAT_GENERIC 126 select ARM_GIC_V2M if PCI 127 select ARM_GIC_V3 128 select ARM_GIC_V3_ITS if PCI 129 select ARM_PSCI_FW 130 select BUILDTIME_TABLE_SORT 131 select CLONE_BACKWARDS 132 select COMMON_CLK 133 select CPU_PM if (SUSPEND || CPU_IDLE) 134 select CPUMASK_OFFSTACK if NR_CPUS > 256 135 select CRC32 136 select DCACHE_WORD_ACCESS 137 select DYNAMIC_FTRACE if FUNCTION_TRACER 138 select DMA_BOUNCE_UNALIGNED_KMALLOC 139 select DMA_DIRECT_REMAP 140 select EDAC_SUPPORT 141 select FRAME_POINTER 142 select FUNCTION_ALIGNMENT_4B 143 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 144 select GENERIC_ALLOCATOR 145 select GENERIC_ARCH_TOPOLOGY 146 select GENERIC_CLOCKEVENTS_BROADCAST 147 select GENERIC_CPU_AUTOPROBE 148 select GENERIC_CPU_DEVICES 149 select GENERIC_CPU_VULNERABILITIES 150 select GENERIC_EARLY_IOREMAP 151 select GENERIC_IDLE_POLL_SETUP 152 select GENERIC_IOREMAP 153 select GENERIC_IRQ_IPI 154 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 155 select GENERIC_IRQ_PROBE 156 select GENERIC_IRQ_SHOW 157 select GENERIC_IRQ_SHOW_LEVEL 158 select GENERIC_LIB_DEVMEM_IS_ALLOWED 159 select GENERIC_PCI_IOMAP 160 select GENERIC_PTDUMP 161 select GENERIC_SCHED_CLOCK 162 select GENERIC_SMP_IDLE_THREAD 163 select GENERIC_TIME_VSYSCALL 164 select GENERIC_GETTIMEOFDAY 165 select GENERIC_VDSO_TIME_NS 166 select HARDIRQS_SW_RESEND 167 select HAS_IOPORT 168 select HAVE_MOVE_PMD 169 select HAVE_MOVE_PUD 170 select HAVE_PCI 171 select HAVE_ACPI_APEI if (ACPI && EFI) 172 select HAVE_ALIGNED_STRUCT_PAGE 173 select HAVE_ARCH_AUDITSYSCALL 174 select HAVE_ARCH_BITREVERSE 175 select HAVE_ARCH_COMPILER_H 176 select HAVE_ARCH_HUGE_VMALLOC 177 select HAVE_ARCH_HUGE_VMAP 178 select HAVE_ARCH_JUMP_LABEL 179 select HAVE_ARCH_JUMP_LABEL_RELATIVE 180 select HAVE_ARCH_KASAN 181 select HAVE_ARCH_KASAN_VMALLOC 182 select HAVE_ARCH_KASAN_SW_TAGS 183 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 184 # Some instrumentation may be unsound, hence EXPERT 185 select HAVE_ARCH_KCSAN if EXPERT 186 select HAVE_ARCH_KFENCE 187 select HAVE_ARCH_KGDB 188 select HAVE_ARCH_MMAP_RND_BITS 189 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 190 select HAVE_ARCH_PREL32_RELOCATIONS 191 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 192 select HAVE_ARCH_SECCOMP_FILTER 193 select HAVE_ARCH_STACKLEAK 194 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 195 select HAVE_ARCH_TRACEHOOK 196 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 197 select HAVE_ARCH_VMAP_STACK 198 select HAVE_ARM_SMCCC 199 select HAVE_ASM_MODVERSIONS 200 select HAVE_EBPF_JIT 201 select HAVE_C_RECORDMCOUNT 202 select HAVE_CMPXCHG_DOUBLE 203 select HAVE_CMPXCHG_LOCAL 204 select HAVE_CONTEXT_TRACKING_USER 205 select HAVE_DEBUG_KMEMLEAK 206 select HAVE_DMA_CONTIGUOUS 207 select HAVE_DYNAMIC_FTRACE 208 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 209 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 210 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 211 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 212 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 213 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 214 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 215 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 216 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 217 if DYNAMIC_FTRACE_WITH_ARGS 218 select HAVE_SAMPLE_FTRACE_DIRECT 219 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 220 select HAVE_EFFICIENT_UNALIGNED_ACCESS 221 select HAVE_GUP_FAST 222 select HAVE_FTRACE_GRAPH_FUNC 223 select HAVE_FTRACE_MCOUNT_RECORD 224 select HAVE_FUNCTION_TRACER 225 select HAVE_FUNCTION_ERROR_INJECTION 226 select HAVE_FUNCTION_GRAPH_FREGS 227 select HAVE_FUNCTION_GRAPH_TRACER 228 select HAVE_GCC_PLUGINS 229 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 230 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 231 select HAVE_HW_BREAKPOINT if PERF_EVENTS 232 select HAVE_IOREMAP_PROT 233 select HAVE_IRQ_TIME_ACCOUNTING 234 select HAVE_MOD_ARCH_SPECIFIC 235 select HAVE_NMI 236 select HAVE_PERF_EVENTS 237 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 238 select HAVE_PERF_REGS 239 select HAVE_PERF_USER_STACK_DUMP 240 select HAVE_PREEMPT_DYNAMIC_KEY 241 select HAVE_REGS_AND_STACK_ACCESS_API 242 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 243 select HAVE_FUNCTION_ARG_ACCESS_API 244 select MMU_GATHER_RCU_TABLE_FREE 245 select HAVE_RSEQ 246 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 247 select HAVE_STACKPROTECTOR 248 select HAVE_SYSCALL_TRACEPOINTS 249 select HAVE_KPROBES 250 select HAVE_KRETPROBES 251 select HAVE_GENERIC_VDSO 252 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 253 select IRQ_DOMAIN 254 select IRQ_FORCED_THREADING 255 select KASAN_VMALLOC if KASAN 256 select LOCK_MM_AND_FIND_VMA 257 select MODULES_USE_ELF_RELA 258 select NEED_DMA_MAP_STATE 259 select NEED_SG_DMA_LENGTH 260 select OF 261 select OF_EARLY_FLATTREE 262 select PCI_DOMAINS_GENERIC if PCI 263 select PCI_ECAM if (ACPI && PCI) 264 select PCI_SYSCALL if PCI 265 select POWER_RESET 266 select POWER_SUPPLY 267 select SPARSE_IRQ 268 select SWIOTLB 269 select SYSCTL_EXCEPTION_TRACE 270 select THREAD_INFO_IN_TASK 271 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 272 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 273 select TRACE_IRQFLAGS_SUPPORT 274 select TRACE_IRQFLAGS_NMI_SUPPORT 275 select HAVE_SOFTIRQ_ON_OWN_STACK 276 select USER_STACKTRACE_SUPPORT 277 select VDSO_GETRANDOM 278 help 279 ARM 64-bit (AArch64) Linux support. 280 281config RUSTC_SUPPORTS_ARM64 282 def_bool y 283 depends on CPU_LITTLE_ENDIAN 284 # Shadow call stack is only supported on certain rustc versions. 285 # 286 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 287 # required due to use of the -Zfixed-x18 flag. 288 # 289 # Otherwise, rustc version 1.82+ is required due to use of the 290 # -Zsanitizer=shadow-call-stack flag. 291 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 292 293config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 294 def_bool CC_IS_CLANG 295 # https://github.com/ClangBuiltLinux/linux/issues/1507 296 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 297 298config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 299 def_bool CC_IS_GCC 300 depends on $(cc-option,-fpatchable-function-entry=2) 301 302config 64BIT 303 def_bool y 304 305config MMU 306 def_bool y 307 308config ARM64_CONT_PTE_SHIFT 309 int 310 default 5 if PAGE_SIZE_64KB 311 default 7 if PAGE_SIZE_16KB 312 default 4 313 314config ARM64_CONT_PMD_SHIFT 315 int 316 default 5 if PAGE_SIZE_64KB 317 default 5 if PAGE_SIZE_16KB 318 default 4 319 320config ARCH_MMAP_RND_BITS_MIN 321 default 14 if PAGE_SIZE_64KB 322 default 16 if PAGE_SIZE_16KB 323 default 18 324 325# max bits determined by the following formula: 326# VA_BITS - PAGE_SHIFT - 3 327config ARCH_MMAP_RND_BITS_MAX 328 default 19 if ARM64_VA_BITS=36 329 default 24 if ARM64_VA_BITS=39 330 default 27 if ARM64_VA_BITS=42 331 default 30 if ARM64_VA_BITS=47 332 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 333 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 334 default 33 if ARM64_VA_BITS=48 335 default 14 if ARM64_64K_PAGES 336 default 16 if ARM64_16K_PAGES 337 default 18 338 339config ARCH_MMAP_RND_COMPAT_BITS_MIN 340 default 7 if ARM64_64K_PAGES 341 default 9 if ARM64_16K_PAGES 342 default 11 343 344config ARCH_MMAP_RND_COMPAT_BITS_MAX 345 default 16 346 347config NO_IOPORT_MAP 348 def_bool y if !PCI 349 350config STACKTRACE_SUPPORT 351 def_bool y 352 353config ILLEGAL_POINTER_VALUE 354 hex 355 default 0xdead000000000000 356 357config LOCKDEP_SUPPORT 358 def_bool y 359 360config GENERIC_BUG 361 def_bool y 362 depends on BUG 363 364config GENERIC_BUG_RELATIVE_POINTERS 365 def_bool y 366 depends on GENERIC_BUG 367 368config GENERIC_HWEIGHT 369 def_bool y 370 371config GENERIC_CSUM 372 def_bool y 373 374config GENERIC_CALIBRATE_DELAY 375 def_bool y 376 377config SMP 378 def_bool y 379 380config KERNEL_MODE_NEON 381 def_bool y 382 383config FIX_EARLYCON_MEM 384 def_bool y 385 386config PGTABLE_LEVELS 387 int 388 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 389 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 390 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 391 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 392 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 393 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 394 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 395 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 396 397config ARCH_SUPPORTS_UPROBES 398 def_bool y 399 400config ARCH_PROC_KCORE_TEXT 401 def_bool y 402 403config BROKEN_GAS_INST 404 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 405 406config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 407 bool 408 # Clang's __builtin_return_address() strips the PAC since 12.0.0 409 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 410 default y if CC_IS_CLANG 411 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 412 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 413 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 414 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 415 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 416 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 417 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 418 default n 419 420config KASAN_SHADOW_OFFSET 421 hex 422 depends on KASAN_GENERIC || KASAN_SW_TAGS 423 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 424 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 425 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 426 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 427 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 428 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 429 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 430 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 431 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 432 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 433 default 0xffffffffffffffff 434 435config UNWIND_TABLES 436 bool 437 438source "arch/arm64/Kconfig.platforms" 439 440menu "Kernel Features" 441 442menu "ARM errata workarounds via the alternatives framework" 443 444config AMPERE_ERRATUM_AC03_CPU_38 445 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 446 default y 447 help 448 This option adds an alternative code sequence to work around Ampere 449 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 450 451 The affected design reports FEAT_HAFDBS as not implemented in 452 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 453 as required by the architecture. The unadvertised HAFDBS 454 implementation suffers from an additional erratum where hardware 455 A/D updates can occur after a PTE has been marked invalid. 456 457 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 458 which avoids enabling unadvertised hardware Access Flag management 459 at stage-2. 460 461 If unsure, say Y. 462 463config ARM64_WORKAROUND_CLEAN_CACHE 464 bool 465 466config ARM64_ERRATUM_826319 467 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 468 default y 469 select ARM64_WORKAROUND_CLEAN_CACHE 470 help 471 This option adds an alternative code sequence to work around ARM 472 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 473 AXI master interface and an L2 cache. 474 475 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 476 and is unable to accept a certain write via this interface, it will 477 not progress on read data presented on the read data channel and the 478 system can deadlock. 479 480 The workaround promotes data cache clean instructions to 481 data cache clean-and-invalidate. 482 Please note that this does not necessarily enable the workaround, 483 as it depends on the alternative framework, which will only patch 484 the kernel if an affected CPU is detected. 485 486 If unsure, say Y. 487 488config ARM64_ERRATUM_827319 489 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 490 default y 491 select ARM64_WORKAROUND_CLEAN_CACHE 492 help 493 This option adds an alternative code sequence to work around ARM 494 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 495 master interface and an L2 cache. 496 497 Under certain conditions this erratum can cause a clean line eviction 498 to occur at the same time as another transaction to the same address 499 on the AMBA 5 CHI interface, which can cause data corruption if the 500 interconnect reorders the two transactions. 501 502 The workaround promotes data cache clean instructions to 503 data cache clean-and-invalidate. 504 Please note that this does not necessarily enable the workaround, 505 as it depends on the alternative framework, which will only patch 506 the kernel if an affected CPU is detected. 507 508 If unsure, say Y. 509 510config ARM64_ERRATUM_824069 511 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 512 default y 513 select ARM64_WORKAROUND_CLEAN_CACHE 514 help 515 This option adds an alternative code sequence to work around ARM 516 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 517 to a coherent interconnect. 518 519 If a Cortex-A53 processor is executing a store or prefetch for 520 write instruction at the same time as a processor in another 521 cluster is executing a cache maintenance operation to the same 522 address, then this erratum might cause a clean cache line to be 523 incorrectly marked as dirty. 524 525 The workaround promotes data cache clean instructions to 526 data cache clean-and-invalidate. 527 Please note that this option does not necessarily enable the 528 workaround, as it depends on the alternative framework, which will 529 only patch the kernel if an affected CPU is detected. 530 531 If unsure, say Y. 532 533config ARM64_ERRATUM_819472 534 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 535 default y 536 select ARM64_WORKAROUND_CLEAN_CACHE 537 help 538 This option adds an alternative code sequence to work around ARM 539 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 540 present when it is connected to a coherent interconnect. 541 542 If the processor is executing a load and store exclusive sequence at 543 the same time as a processor in another cluster is executing a cache 544 maintenance operation to the same address, then this erratum might 545 cause data corruption. 546 547 The workaround promotes data cache clean instructions to 548 data cache clean-and-invalidate. 549 Please note that this does not necessarily enable the workaround, 550 as it depends on the alternative framework, which will only patch 551 the kernel if an affected CPU is detected. 552 553 If unsure, say Y. 554 555config ARM64_ERRATUM_832075 556 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 557 default y 558 help 559 This option adds an alternative code sequence to work around ARM 560 erratum 832075 on Cortex-A57 parts up to r1p2. 561 562 Affected Cortex-A57 parts might deadlock when exclusive load/store 563 instructions to Write-Back memory are mixed with Device loads. 564 565 The workaround is to promote device loads to use Load-Acquire 566 semantics. 567 Please note that this does not necessarily enable the workaround, 568 as it depends on the alternative framework, which will only patch 569 the kernel if an affected CPU is detected. 570 571 If unsure, say Y. 572 573config ARM64_ERRATUM_834220 574 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 575 depends on KVM 576 help 577 This option adds an alternative code sequence to work around ARM 578 erratum 834220 on Cortex-A57 parts up to r1p2. 579 580 Affected Cortex-A57 parts might report a Stage 2 translation 581 fault as the result of a Stage 1 fault for load crossing a 582 page boundary when there is a permission or device memory 583 alignment fault at Stage 1 and a translation fault at Stage 2. 584 585 The workaround is to verify that the Stage 1 translation 586 doesn't generate a fault before handling the Stage 2 fault. 587 Please note that this does not necessarily enable the workaround, 588 as it depends on the alternative framework, which will only patch 589 the kernel if an affected CPU is detected. 590 591 If unsure, say N. 592 593config ARM64_ERRATUM_1742098 594 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 595 depends on COMPAT 596 default y 597 help 598 This option removes the AES hwcap for aarch32 user-space to 599 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 600 601 Affected parts may corrupt the AES state if an interrupt is 602 taken between a pair of AES instructions. These instructions 603 are only present if the cryptography extensions are present. 604 All software should have a fallback implementation for CPUs 605 that don't implement the cryptography extensions. 606 607 If unsure, say Y. 608 609config ARM64_ERRATUM_845719 610 bool "Cortex-A53: 845719: a load might read incorrect data" 611 depends on COMPAT 612 default y 613 help 614 This option adds an alternative code sequence to work around ARM 615 erratum 845719 on Cortex-A53 parts up to r0p4. 616 617 When running a compat (AArch32) userspace on an affected Cortex-A53 618 part, a load at EL0 from a virtual address that matches the bottom 32 619 bits of the virtual address used by a recent load at (AArch64) EL1 620 might return incorrect data. 621 622 The workaround is to write the contextidr_el1 register on exception 623 return to a 32-bit task. 624 Please note that this does not necessarily enable the workaround, 625 as it depends on the alternative framework, which will only patch 626 the kernel if an affected CPU is detected. 627 628 If unsure, say Y. 629 630config ARM64_ERRATUM_843419 631 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 632 default y 633 help 634 This option links the kernel with '--fix-cortex-a53-843419' and 635 enables PLT support to replace certain ADRP instructions, which can 636 cause subsequent memory accesses to use an incorrect address on 637 Cortex-A53 parts up to r0p4. 638 639 If unsure, say Y. 640 641config ARM64_LD_HAS_FIX_ERRATUM_843419 642 def_bool $(ld-option,--fix-cortex-a53-843419) 643 644config ARM64_ERRATUM_1024718 645 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 646 default y 647 help 648 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 649 650 Affected Cortex-A55 cores (all revisions) could cause incorrect 651 update of the hardware dirty bit when the DBM/AP bits are updated 652 without a break-before-make. The workaround is to disable the usage 653 of hardware DBM locally on the affected cores. CPUs not affected by 654 this erratum will continue to use the feature. 655 656 If unsure, say Y. 657 658config ARM64_ERRATUM_1418040 659 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 660 default y 661 depends on COMPAT 662 help 663 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 664 errata 1188873 and 1418040. 665 666 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 667 cause register corruption when accessing the timer registers 668 from AArch32 userspace. 669 670 If unsure, say Y. 671 672config ARM64_WORKAROUND_SPECULATIVE_AT 673 bool 674 675config ARM64_ERRATUM_1165522 676 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 677 default y 678 select ARM64_WORKAROUND_SPECULATIVE_AT 679 help 680 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 681 682 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 683 corrupted TLBs by speculating an AT instruction during a guest 684 context switch. 685 686 If unsure, say Y. 687 688config ARM64_ERRATUM_1319367 689 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 690 default y 691 select ARM64_WORKAROUND_SPECULATIVE_AT 692 help 693 This option adds work arounds for ARM Cortex-A57 erratum 1319537 694 and A72 erratum 1319367 695 696 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 697 speculating an AT instruction during a guest context switch. 698 699 If unsure, say Y. 700 701config ARM64_ERRATUM_1530923 702 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 703 default y 704 select ARM64_WORKAROUND_SPECULATIVE_AT 705 help 706 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 707 708 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 709 corrupted TLBs by speculating an AT instruction during a guest 710 context switch. 711 712 If unsure, say Y. 713 714config ARM64_WORKAROUND_REPEAT_TLBI 715 bool 716 717config ARM64_ERRATUM_2441007 718 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 719 select ARM64_WORKAROUND_REPEAT_TLBI 720 help 721 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 722 723 Under very rare circumstances, affected Cortex-A55 CPUs 724 may not handle a race between a break-before-make sequence on one 725 CPU, and another CPU accessing the same page. This could allow a 726 store to a page that has been unmapped. 727 728 Work around this by adding the affected CPUs to the list that needs 729 TLB sequences to be done twice. 730 731 If unsure, say N. 732 733config ARM64_ERRATUM_1286807 734 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 735 select ARM64_WORKAROUND_REPEAT_TLBI 736 help 737 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 738 739 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 740 address for a cacheable mapping of a location is being 741 accessed by a core while another core is remapping the virtual 742 address to a new physical page using the recommended 743 break-before-make sequence, then under very rare circumstances 744 TLBI+DSB completes before a read using the translation being 745 invalidated has been observed by other observers. The 746 workaround repeats the TLBI+DSB operation. 747 748 If unsure, say N. 749 750config ARM64_ERRATUM_1463225 751 bool "Cortex-A76: Software Step might prevent interrupt recognition" 752 default y 753 help 754 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 755 756 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 757 of a system call instruction (SVC) can prevent recognition of 758 subsequent interrupts when software stepping is disabled in the 759 exception handler of the system call and either kernel debugging 760 is enabled or VHE is in use. 761 762 Work around the erratum by triggering a dummy step exception 763 when handling a system call from a task that is being stepped 764 in a VHE configuration of the kernel. 765 766 If unsure, say Y. 767 768config ARM64_ERRATUM_1542419 769 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 770 help 771 This option adds a workaround for ARM Neoverse-N1 erratum 772 1542419. 773 774 Affected Neoverse-N1 cores could execute a stale instruction when 775 modified by another CPU. The workaround depends on a firmware 776 counterpart. 777 778 Workaround the issue by hiding the DIC feature from EL0. This 779 forces user-space to perform cache maintenance. 780 781 If unsure, say N. 782 783config ARM64_ERRATUM_1508412 784 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 785 default y 786 help 787 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 788 789 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 790 of a store-exclusive or read of PAR_EL1 and a load with device or 791 non-cacheable memory attributes. The workaround depends on a firmware 792 counterpart. 793 794 KVM guests must also have the workaround implemented or they can 795 deadlock the system. 796 797 Work around the issue by inserting DMB SY barriers around PAR_EL1 798 register reads and warning KVM users. The DMB barrier is sufficient 799 to prevent a speculative PAR_EL1 read. 800 801 If unsure, say Y. 802 803config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 804 bool 805 806config ARM64_ERRATUM_2051678 807 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 808 default y 809 help 810 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 811 Affected Cortex-A510 might not respect the ordering rules for 812 hardware update of the page table's dirty bit. The workaround 813 is to not enable the feature on affected CPUs. 814 815 If unsure, say Y. 816 817config ARM64_ERRATUM_2077057 818 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 819 default y 820 help 821 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 822 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 823 expected, but a Pointer Authentication trap is taken instead. The 824 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 825 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 826 827 This can only happen when EL2 is stepping EL1. 828 829 When these conditions occur, the SPSR_EL2 value is unchanged from the 830 previous guest entry, and can be restored from the in-memory copy. 831 832 If unsure, say Y. 833 834config ARM64_ERRATUM_2658417 835 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 836 default y 837 help 838 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 839 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 840 BFMMLA or VMMLA instructions in rare circumstances when a pair of 841 A510 CPUs are using shared neon hardware. As the sharing is not 842 discoverable by the kernel, hide the BF16 HWCAP to indicate that 843 user-space should not be using these instructions. 844 845 If unsure, say Y. 846 847config ARM64_ERRATUM_2119858 848 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 849 default y 850 depends on CORESIGHT_TRBE 851 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 852 help 853 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 854 855 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 856 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 857 the event of a WRAP event. 858 859 Work around the issue by always making sure we move the TRBPTR_EL1 by 860 256 bytes before enabling the buffer and filling the first 256 bytes of 861 the buffer with ETM ignore packets upon disabling. 862 863 If unsure, say Y. 864 865config ARM64_ERRATUM_2139208 866 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 867 default y 868 depends on CORESIGHT_TRBE 869 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 870 help 871 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 872 873 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 874 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 875 the event of a WRAP event. 876 877 Work around the issue by always making sure we move the TRBPTR_EL1 by 878 256 bytes before enabling the buffer and filling the first 256 bytes of 879 the buffer with ETM ignore packets upon disabling. 880 881 If unsure, say Y. 882 883config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 884 bool 885 886config ARM64_ERRATUM_2054223 887 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 888 default y 889 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 890 help 891 Enable workaround for ARM Cortex-A710 erratum 2054223 892 893 Affected cores may fail to flush the trace data on a TSB instruction, when 894 the PE is in trace prohibited state. This will cause losing a few bytes 895 of the trace cached. 896 897 Workaround is to issue two TSB consecutively on affected cores. 898 899 If unsure, say Y. 900 901config ARM64_ERRATUM_2067961 902 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 903 default y 904 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 905 help 906 Enable workaround for ARM Neoverse-N2 erratum 2067961 907 908 Affected cores may fail to flush the trace data on a TSB instruction, when 909 the PE is in trace prohibited state. This will cause losing a few bytes 910 of the trace cached. 911 912 Workaround is to issue two TSB consecutively on affected cores. 913 914 If unsure, say Y. 915 916config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 917 bool 918 919config ARM64_ERRATUM_2253138 920 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 921 depends on CORESIGHT_TRBE 922 default y 923 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 924 help 925 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 926 927 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 928 for TRBE. Under some conditions, the TRBE might generate a write to the next 929 virtually addressed page following the last page of the TRBE address space 930 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 931 932 Work around this in the driver by always making sure that there is a 933 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 934 935 If unsure, say Y. 936 937config ARM64_ERRATUM_2224489 938 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 939 depends on CORESIGHT_TRBE 940 default y 941 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 942 help 943 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 944 945 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 946 for TRBE. Under some conditions, the TRBE might generate a write to the next 947 virtually addressed page following the last page of the TRBE address space 948 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 949 950 Work around this in the driver by always making sure that there is a 951 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 952 953 If unsure, say Y. 954 955config ARM64_ERRATUM_2441009 956 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 957 select ARM64_WORKAROUND_REPEAT_TLBI 958 help 959 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 960 961 Under very rare circumstances, affected Cortex-A510 CPUs 962 may not handle a race between a break-before-make sequence on one 963 CPU, and another CPU accessing the same page. This could allow a 964 store to a page that has been unmapped. 965 966 Work around this by adding the affected CPUs to the list that needs 967 TLB sequences to be done twice. 968 969 If unsure, say N. 970 971config ARM64_ERRATUM_2064142 972 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 973 depends on CORESIGHT_TRBE 974 default y 975 help 976 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 977 978 Affected Cortex-A510 core might fail to write into system registers after the 979 TRBE has been disabled. Under some conditions after the TRBE has been disabled 980 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 981 and TRBTRG_EL1 will be ignored and will not be effected. 982 983 Work around this in the driver by executing TSB CSYNC and DSB after collection 984 is stopped and before performing a system register write to one of the affected 985 registers. 986 987 If unsure, say Y. 988 989config ARM64_ERRATUM_2038923 990 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 991 depends on CORESIGHT_TRBE 992 default y 993 help 994 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 995 996 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 997 prohibited within the CPU. As a result, the trace buffer or trace buffer state 998 might be corrupted. This happens after TRBE buffer has been enabled by setting 999 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 1000 execution changes from a context, in which trace is prohibited to one where it 1001 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1002 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1003 the trace buffer state might be corrupted. 1004 1005 Work around this in the driver by preventing an inconsistent view of whether the 1006 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1007 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1008 two ISB instructions if no ERET is to take place. 1009 1010 If unsure, say Y. 1011 1012config ARM64_ERRATUM_1902691 1013 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1014 depends on CORESIGHT_TRBE 1015 default y 1016 help 1017 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1018 1019 Affected Cortex-A510 core might cause trace data corruption, when being written 1020 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1021 trace data. 1022 1023 Work around this problem in the driver by just preventing TRBE initialization on 1024 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1025 on such implementations. This will cover the kernel for any firmware that doesn't 1026 do this already. 1027 1028 If unsure, say Y. 1029 1030config ARM64_ERRATUM_2457168 1031 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1032 depends on ARM64_AMU_EXTN 1033 default y 1034 help 1035 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1036 1037 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1038 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1039 incorrectly giving a significantly higher output value. 1040 1041 Work around this problem by returning 0 when reading the affected counter in 1042 key locations that results in disabling all users of this counter. This effect 1043 is the same to firmware disabling affected counters. 1044 1045 If unsure, say Y. 1046 1047config ARM64_ERRATUM_2645198 1048 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1049 default y 1050 help 1051 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1052 1053 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1054 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1055 next instruction abort caused by permission fault. 1056 1057 Only user-space does executable to non-executable permission transition via 1058 mprotect() system call. Workaround the problem by doing a break-before-make 1059 TLB invalidation, for all changes to executable user space mappings. 1060 1061 If unsure, say Y. 1062 1063config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1064 bool 1065 1066config ARM64_ERRATUM_2966298 1067 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1068 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1069 default y 1070 help 1071 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1072 1073 On an affected Cortex-A520 core, a speculatively executed unprivileged 1074 load might leak data from a privileged level via a cache side channel. 1075 1076 Work around this problem by executing a TLBI before returning to EL0. 1077 1078 If unsure, say Y. 1079 1080config ARM64_ERRATUM_3117295 1081 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1082 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1083 default y 1084 help 1085 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1086 1087 On an affected Cortex-A510 core, a speculatively executed unprivileged 1088 load might leak data from a privileged level via a cache side channel. 1089 1090 Work around this problem by executing a TLBI before returning to EL0. 1091 1092 If unsure, say Y. 1093 1094config ARM64_ERRATUM_3194386 1095 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1096 default y 1097 help 1098 This option adds the workaround for the following errata: 1099 1100 * ARM Cortex-A76 erratum 3324349 1101 * ARM Cortex-A77 erratum 3324348 1102 * ARM Cortex-A78 erratum 3324344 1103 * ARM Cortex-A78C erratum 3324346 1104 * ARM Cortex-A78C erratum 3324347 1105 * ARM Cortex-A710 erratam 3324338 1106 * ARM Cortex-A715 errartum 3456084 1107 * ARM Cortex-A720 erratum 3456091 1108 * ARM Cortex-A725 erratum 3456106 1109 * ARM Cortex-X1 erratum 3324344 1110 * ARM Cortex-X1C erratum 3324346 1111 * ARM Cortex-X2 erratum 3324338 1112 * ARM Cortex-X3 erratum 3324335 1113 * ARM Cortex-X4 erratum 3194386 1114 * ARM Cortex-X925 erratum 3324334 1115 * ARM Neoverse-N1 erratum 3324349 1116 * ARM Neoverse N2 erratum 3324339 1117 * ARM Neoverse-N3 erratum 3456111 1118 * ARM Neoverse-V1 erratum 3324341 1119 * ARM Neoverse V2 erratum 3324336 1120 * ARM Neoverse-V3 erratum 3312417 1121 1122 On affected cores "MSR SSBS, #0" instructions may not affect 1123 subsequent speculative instructions, which may permit unexepected 1124 speculative store bypassing. 1125 1126 Work around this problem by placing a Speculation Barrier (SB) or 1127 Instruction Synchronization Barrier (ISB) after kernel changes to 1128 SSBS. The presence of the SSBS special-purpose register is hidden 1129 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1130 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1131 1132 If unsure, say Y. 1133 1134config CAVIUM_ERRATUM_22375 1135 bool "Cavium erratum 22375, 24313" 1136 default y 1137 help 1138 Enable workaround for errata 22375 and 24313. 1139 1140 This implements two gicv3-its errata workarounds for ThunderX. Both 1141 with a small impact affecting only ITS table allocation. 1142 1143 erratum 22375: only alloc 8MB table size 1144 erratum 24313: ignore memory access type 1145 1146 The fixes are in ITS initialization and basically ignore memory access 1147 type and table size provided by the TYPER and BASER registers. 1148 1149 If unsure, say Y. 1150 1151config CAVIUM_ERRATUM_23144 1152 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1153 depends on NUMA 1154 default y 1155 help 1156 ITS SYNC command hang for cross node io and collections/cpu mapping. 1157 1158 If unsure, say Y. 1159 1160config CAVIUM_ERRATUM_23154 1161 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1162 default y 1163 help 1164 The ThunderX GICv3 implementation requires a modified version for 1165 reading the IAR status to ensure data synchronization 1166 (access to icc_iar1_el1 is not sync'ed before and after). 1167 1168 It also suffers from erratum 38545 (also present on Marvell's 1169 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1170 spuriously presented to the CPU interface. 1171 1172 If unsure, say Y. 1173 1174config CAVIUM_ERRATUM_27456 1175 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1176 default y 1177 help 1178 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1179 instructions may cause the icache to become corrupted if it 1180 contains data for a non-current ASID. The fix is to 1181 invalidate the icache when changing the mm context. 1182 1183 If unsure, say Y. 1184 1185config CAVIUM_ERRATUM_30115 1186 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1187 default y 1188 help 1189 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1190 1.2, and T83 Pass 1.0, KVM guest execution may disable 1191 interrupts in host. Trapping both GICv3 group-0 and group-1 1192 accesses sidesteps the issue. 1193 1194 If unsure, say Y. 1195 1196config CAVIUM_TX2_ERRATUM_219 1197 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1198 default y 1199 help 1200 On Cavium ThunderX2, a load, store or prefetch instruction between a 1201 TTBR update and the corresponding context synchronizing operation can 1202 cause a spurious Data Abort to be delivered to any hardware thread in 1203 the CPU core. 1204 1205 Work around the issue by avoiding the problematic code sequence and 1206 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1207 trap handler performs the corresponding register access, skips the 1208 instruction and ensures context synchronization by virtue of the 1209 exception return. 1210 1211 If unsure, say Y. 1212 1213config FUJITSU_ERRATUM_010001 1214 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1215 default y 1216 help 1217 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1218 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1219 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1220 This fault occurs under a specific hardware condition when a 1221 load/store instruction performs an address translation using: 1222 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1223 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1224 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1225 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1226 1227 The workaround is to ensure these bits are clear in TCR_ELx. 1228 The workaround only affects the Fujitsu-A64FX. 1229 1230 If unsure, say Y. 1231 1232config HISILICON_ERRATUM_161600802 1233 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1234 default y 1235 help 1236 The HiSilicon Hip07 SoC uses the wrong redistributor base 1237 when issued ITS commands such as VMOVP and VMAPP, and requires 1238 a 128kB offset to be applied to the target address in this commands. 1239 1240 If unsure, say Y. 1241 1242config HISILICON_ERRATUM_162100801 1243 bool "Hip09 162100801 erratum support" 1244 default y 1245 help 1246 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1247 during unmapping operation, which will cause some vSGIs lost. 1248 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1249 after VMOVP. 1250 1251 If unsure, say Y. 1252 1253config QCOM_FALKOR_ERRATUM_1003 1254 bool "Falkor E1003: Incorrect translation due to ASID change" 1255 default y 1256 help 1257 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1258 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1259 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1260 then only for entries in the walk cache, since the leaf translation 1261 is unchanged. Work around the erratum by invalidating the walk cache 1262 entries for the trampoline before entering the kernel proper. 1263 1264config QCOM_FALKOR_ERRATUM_1009 1265 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1266 default y 1267 select ARM64_WORKAROUND_REPEAT_TLBI 1268 help 1269 On Falkor v1, the CPU may prematurely complete a DSB following a 1270 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1271 one more time to fix the issue. 1272 1273 If unsure, say Y. 1274 1275config QCOM_QDF2400_ERRATUM_0065 1276 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1277 default y 1278 help 1279 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1280 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1281 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1282 1283 If unsure, say Y. 1284 1285config QCOM_FALKOR_ERRATUM_E1041 1286 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1287 default y 1288 help 1289 Falkor CPU may speculatively fetch instructions from an improper 1290 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1291 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1292 1293 If unsure, say Y. 1294 1295config NVIDIA_CARMEL_CNP_ERRATUM 1296 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1297 default y 1298 help 1299 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1300 invalidate shared TLB entries installed by a different core, as it would 1301 on standard ARM cores. 1302 1303 If unsure, say Y. 1304 1305config ROCKCHIP_ERRATUM_3588001 1306 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1307 default y 1308 help 1309 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1310 This means, that its sharability feature may not be used, even though it 1311 is supported by the IP itself. 1312 1313 If unsure, say Y. 1314 1315config SOCIONEXT_SYNQUACER_PREITS 1316 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1317 default y 1318 help 1319 Socionext Synquacer SoCs implement a separate h/w block to generate 1320 MSI doorbell writes with non-zero values for the device ID. 1321 1322 If unsure, say Y. 1323 1324endmenu # "ARM errata workarounds via the alternatives framework" 1325 1326choice 1327 prompt "Page size" 1328 default ARM64_4K_PAGES 1329 help 1330 Page size (translation granule) configuration. 1331 1332config ARM64_4K_PAGES 1333 bool "4KB" 1334 select HAVE_PAGE_SIZE_4KB 1335 help 1336 This feature enables 4KB pages support. 1337 1338config ARM64_16K_PAGES 1339 bool "16KB" 1340 select HAVE_PAGE_SIZE_16KB 1341 help 1342 The system will use 16KB pages support. AArch32 emulation 1343 requires applications compiled with 16K (or a multiple of 16K) 1344 aligned segments. 1345 1346config ARM64_64K_PAGES 1347 bool "64KB" 1348 select HAVE_PAGE_SIZE_64KB 1349 help 1350 This feature enables 64KB pages support (4KB by default) 1351 allowing only two levels of page tables and faster TLB 1352 look-up. AArch32 emulation requires applications compiled 1353 with 64K aligned segments. 1354 1355endchoice 1356 1357choice 1358 prompt "Virtual address space size" 1359 default ARM64_VA_BITS_52 1360 help 1361 Allows choosing one of multiple possible virtual address 1362 space sizes. The level of translation table is determined by 1363 a combination of page size and virtual address space size. 1364 1365config ARM64_VA_BITS_36 1366 bool "36-bit" if EXPERT 1367 depends on PAGE_SIZE_16KB 1368 1369config ARM64_VA_BITS_39 1370 bool "39-bit" 1371 depends on PAGE_SIZE_4KB 1372 1373config ARM64_VA_BITS_42 1374 bool "42-bit" 1375 depends on PAGE_SIZE_64KB 1376 1377config ARM64_VA_BITS_47 1378 bool "47-bit" 1379 depends on PAGE_SIZE_16KB 1380 1381config ARM64_VA_BITS_48 1382 bool "48-bit" 1383 1384config ARM64_VA_BITS_52 1385 bool "52-bit" 1386 help 1387 Enable 52-bit virtual addressing for userspace when explicitly 1388 requested via a hint to mmap(). The kernel will also use 52-bit 1389 virtual addresses for its own mappings (provided HW support for 1390 this feature is available, otherwise it reverts to 48-bit). 1391 1392 NOTE: Enabling 52-bit virtual addressing in conjunction with 1393 ARMv8.3 Pointer Authentication will result in the PAC being 1394 reduced from 7 bits to 3 bits, which may have a significant 1395 impact on its susceptibility to brute-force attacks. 1396 1397 If unsure, select 48-bit virtual addressing instead. 1398 1399endchoice 1400 1401config ARM64_FORCE_52BIT 1402 bool "Force 52-bit virtual addresses for userspace" 1403 depends on ARM64_VA_BITS_52 && EXPERT 1404 help 1405 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1406 to maintain compatibility with older software by providing 48-bit VAs 1407 unless a hint is supplied to mmap. 1408 1409 This configuration option disables the 48-bit compatibility logic, and 1410 forces all userspace addresses to be 52-bit on HW that supports it. One 1411 should only enable this configuration option for stress testing userspace 1412 memory management code. If unsure say N here. 1413 1414config ARM64_VA_BITS 1415 int 1416 default 36 if ARM64_VA_BITS_36 1417 default 39 if ARM64_VA_BITS_39 1418 default 42 if ARM64_VA_BITS_42 1419 default 47 if ARM64_VA_BITS_47 1420 default 48 if ARM64_VA_BITS_48 1421 default 52 if ARM64_VA_BITS_52 1422 1423choice 1424 prompt "Physical address space size" 1425 default ARM64_PA_BITS_48 1426 help 1427 Choose the maximum physical address range that the kernel will 1428 support. 1429 1430config ARM64_PA_BITS_48 1431 bool "48-bit" 1432 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1433 1434config ARM64_PA_BITS_52 1435 bool "52-bit" 1436 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1437 help 1438 Enable support for a 52-bit physical address space, introduced as 1439 part of the ARMv8.2-LPA extension. 1440 1441 With this enabled, the kernel will also continue to work on CPUs that 1442 do not support ARMv8.2-LPA, but with some added memory overhead (and 1443 minor performance overhead). 1444 1445endchoice 1446 1447config ARM64_PA_BITS 1448 int 1449 default 48 if ARM64_PA_BITS_48 1450 default 52 if ARM64_PA_BITS_52 1451 1452config ARM64_LPA2 1453 def_bool y 1454 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1455 1456choice 1457 prompt "Endianness" 1458 default CPU_LITTLE_ENDIAN 1459 help 1460 Select the endianness of data accesses performed by the CPU. Userspace 1461 applications will need to be compiled and linked for the endianness 1462 that is selected here. 1463 1464config CPU_BIG_ENDIAN 1465 bool "Build big-endian kernel" 1466 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1467 depends on AS_IS_GNU || AS_VERSION >= 150000 1468 help 1469 Say Y if you plan on running a kernel with a big-endian userspace. 1470 1471config CPU_LITTLE_ENDIAN 1472 bool "Build little-endian kernel" 1473 help 1474 Say Y if you plan on running a kernel with a little-endian userspace. 1475 This is usually the case for distributions targeting arm64. 1476 1477endchoice 1478 1479config SCHED_MC 1480 bool "Multi-core scheduler support" 1481 help 1482 Multi-core scheduler support improves the CPU scheduler's decision 1483 making when dealing with multi-core CPU chips at a cost of slightly 1484 increased overhead in some places. If unsure say N here. 1485 1486config SCHED_CLUSTER 1487 bool "Cluster scheduler support" 1488 help 1489 Cluster scheduler support improves the CPU scheduler's decision 1490 making when dealing with machines that have clusters of CPUs. 1491 Cluster usually means a couple of CPUs which are placed closely 1492 by sharing mid-level caches, last-level cache tags or internal 1493 busses. 1494 1495config SCHED_SMT 1496 bool "SMT scheduler support" 1497 help 1498 Improves the CPU scheduler's decision making when dealing with 1499 MultiThreading at a cost of slightly increased overhead in some 1500 places. If unsure say N here. 1501 1502config NR_CPUS 1503 int "Maximum number of CPUs (2-4096)" 1504 range 2 4096 1505 default "512" 1506 1507config HOTPLUG_CPU 1508 bool "Support for hot-pluggable CPUs" 1509 select GENERIC_IRQ_MIGRATION 1510 help 1511 Say Y here to experiment with turning CPUs off and on. CPUs 1512 can be controlled through /sys/devices/system/cpu. 1513 1514# Common NUMA Features 1515config NUMA 1516 bool "NUMA Memory Allocation and Scheduler Support" 1517 select GENERIC_ARCH_NUMA 1518 select OF_NUMA 1519 select HAVE_SETUP_PER_CPU_AREA 1520 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1521 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1522 select USE_PERCPU_NUMA_NODE_ID 1523 help 1524 Enable NUMA (Non-Uniform Memory Access) support. 1525 1526 The kernel will try to allocate memory used by a CPU on the 1527 local memory of the CPU and add some more 1528 NUMA awareness to the kernel. 1529 1530config NODES_SHIFT 1531 int "Maximum NUMA Nodes (as a power of 2)" 1532 range 1 10 1533 default "4" 1534 depends on NUMA 1535 help 1536 Specify the maximum number of NUMA Nodes available on the target 1537 system. Increases memory reserved to accommodate various tables. 1538 1539source "kernel/Kconfig.hz" 1540 1541config ARCH_SPARSEMEM_ENABLE 1542 def_bool y 1543 select SPARSEMEM_VMEMMAP_ENABLE 1544 select SPARSEMEM_VMEMMAP 1545 1546config HW_PERF_EVENTS 1547 def_bool y 1548 depends on ARM_PMU 1549 1550# Supported by clang >= 7.0 or GCC >= 12.0.0 1551config CC_HAVE_SHADOW_CALL_STACK 1552 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1553 1554config PARAVIRT 1555 bool "Enable paravirtualization code" 1556 help 1557 This changes the kernel so it can modify itself when it is run 1558 under a hypervisor, potentially improving performance significantly 1559 over full virtualization. 1560 1561config PARAVIRT_TIME_ACCOUNTING 1562 bool "Paravirtual steal time accounting" 1563 select PARAVIRT 1564 help 1565 Select this option to enable fine granularity task steal time 1566 accounting. Time spent executing other tasks in parallel with 1567 the current vCPU is discounted from the vCPU power. To account for 1568 that, there can be a small performance impact. 1569 1570 If in doubt, say N here. 1571 1572config ARCH_SUPPORTS_KEXEC 1573 def_bool PM_SLEEP_SMP 1574 1575config ARCH_SUPPORTS_KEXEC_FILE 1576 def_bool y 1577 1578config ARCH_SELECTS_KEXEC_FILE 1579 def_bool y 1580 depends on KEXEC_FILE 1581 select HAVE_IMA_KEXEC if IMA 1582 1583config ARCH_SUPPORTS_KEXEC_SIG 1584 def_bool y 1585 1586config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1587 def_bool y 1588 1589config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1590 def_bool y 1591 1592config ARCH_SUPPORTS_CRASH_DUMP 1593 def_bool y 1594 1595config ARCH_DEFAULT_CRASH_DUMP 1596 def_bool y 1597 1598config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1599 def_bool CRASH_RESERVE 1600 1601config TRANS_TABLE 1602 def_bool y 1603 depends on HIBERNATION || KEXEC_CORE 1604 1605config XEN_DOM0 1606 def_bool y 1607 depends on XEN 1608 1609config XEN 1610 bool "Xen guest support on ARM64" 1611 depends on ARM64 && OF 1612 select SWIOTLB_XEN 1613 select PARAVIRT 1614 help 1615 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1616 1617# include/linux/mmzone.h requires the following to be true: 1618# 1619# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1620# 1621# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1622# 1623# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1624# ----+-------------------+--------------+----------------------+-------------------------+ 1625# 4K | 27 | 12 | 15 | 10 | 1626# 16K | 27 | 14 | 13 | 11 | 1627# 64K | 29 | 16 | 13 | 13 | 1628config ARCH_FORCE_MAX_ORDER 1629 int 1630 default "13" if ARM64_64K_PAGES 1631 default "11" if ARM64_16K_PAGES 1632 default "10" 1633 help 1634 The kernel page allocator limits the size of maximal physically 1635 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1636 defines the maximal power of two of number of pages that can be 1637 allocated as a single contiguous block. This option allows 1638 overriding the default setting when ability to allocate very 1639 large blocks of physically contiguous memory is required. 1640 1641 The maximal size of allocation cannot exceed the size of the 1642 section, so the value of MAX_PAGE_ORDER should satisfy 1643 1644 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1645 1646 Don't change if unsure. 1647 1648config UNMAP_KERNEL_AT_EL0 1649 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1650 default y 1651 help 1652 Speculation attacks against some high-performance processors can 1653 be used to bypass MMU permission checks and leak kernel data to 1654 userspace. This can be defended against by unmapping the kernel 1655 when running in userspace, mapping it back in on exception entry 1656 via a trampoline page in the vector table. 1657 1658 If unsure, say Y. 1659 1660config MITIGATE_SPECTRE_BRANCH_HISTORY 1661 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1662 default y 1663 help 1664 Speculation attacks against some high-performance processors can 1665 make use of branch history to influence future speculation. 1666 When taking an exception from user-space, a sequence of branches 1667 or a firmware call overwrites the branch history. 1668 1669config RODATA_FULL_DEFAULT_ENABLED 1670 bool "Apply r/o permissions of VM areas also to their linear aliases" 1671 default y 1672 help 1673 Apply read-only attributes of VM areas to the linear alias of 1674 the backing pages as well. This prevents code or read-only data 1675 from being modified (inadvertently or intentionally) via another 1676 mapping of the same memory page. This additional enhancement can 1677 be turned off at runtime by passing rodata=[off|on] (and turned on 1678 with rodata=full if this option is set to 'n') 1679 1680 This requires the linear region to be mapped down to pages, 1681 which may adversely affect performance in some cases. 1682 1683config ARM64_SW_TTBR0_PAN 1684 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1685 depends on !KCSAN 1686 select ARM64_PAN 1687 help 1688 Enabling this option prevents the kernel from accessing 1689 user-space memory directly by pointing TTBR0_EL1 to a reserved 1690 zeroed area and reserved ASID. The user access routines 1691 restore the valid TTBR0_EL1 temporarily. 1692 1693config ARM64_TAGGED_ADDR_ABI 1694 bool "Enable the tagged user addresses syscall ABI" 1695 default y 1696 help 1697 When this option is enabled, user applications can opt in to a 1698 relaxed ABI via prctl() allowing tagged addresses to be passed 1699 to system calls as pointer arguments. For details, see 1700 Documentation/arch/arm64/tagged-address-abi.rst. 1701 1702menuconfig COMPAT 1703 bool "Kernel support for 32-bit EL0" 1704 depends on ARM64_4K_PAGES || EXPERT 1705 select HAVE_UID16 1706 select OLD_SIGSUSPEND3 1707 select COMPAT_OLD_SIGACTION 1708 help 1709 This option enables support for a 32-bit EL0 running under a 64-bit 1710 kernel at EL1. AArch32-specific components such as system calls, 1711 the user helper functions, VFP support and the ptrace interface are 1712 handled appropriately by the kernel. 1713 1714 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1715 that you will only be able to execute AArch32 binaries that were compiled 1716 with page size aligned segments. 1717 1718 If you want to execute 32-bit userspace applications, say Y. 1719 1720if COMPAT 1721 1722config KUSER_HELPERS 1723 bool "Enable kuser helpers page for 32-bit applications" 1724 default y 1725 help 1726 Warning: disabling this option may break 32-bit user programs. 1727 1728 Provide kuser helpers to compat tasks. The kernel provides 1729 helper code to userspace in read only form at a fixed location 1730 to allow userspace to be independent of the CPU type fitted to 1731 the system. This permits binaries to be run on ARMv4 through 1732 to ARMv8 without modification. 1733 1734 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1735 1736 However, the fixed address nature of these helpers can be used 1737 by ROP (return orientated programming) authors when creating 1738 exploits. 1739 1740 If all of the binaries and libraries which run on your platform 1741 are built specifically for your platform, and make no use of 1742 these helpers, then you can turn this option off to hinder 1743 such exploits. However, in that case, if a binary or library 1744 relying on those helpers is run, it will not function correctly. 1745 1746 Say N here only if you are absolutely certain that you do not 1747 need these helpers; otherwise, the safe option is to say Y. 1748 1749config COMPAT_VDSO 1750 bool "Enable vDSO for 32-bit applications" 1751 depends on !CPU_BIG_ENDIAN 1752 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1753 select GENERIC_COMPAT_VDSO 1754 default y 1755 help 1756 Place in the process address space of 32-bit applications an 1757 ELF shared object providing fast implementations of gettimeofday 1758 and clock_gettime. 1759 1760 You must have a 32-bit build of glibc 2.22 or later for programs 1761 to seamlessly take advantage of this. 1762 1763config THUMB2_COMPAT_VDSO 1764 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1765 depends on COMPAT_VDSO 1766 default y 1767 help 1768 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1769 otherwise with '-marm'. 1770 1771config COMPAT_ALIGNMENT_FIXUPS 1772 bool "Fix up misaligned multi-word loads and stores in user space" 1773 1774menuconfig ARMV8_DEPRECATED 1775 bool "Emulate deprecated/obsolete ARMv8 instructions" 1776 depends on SYSCTL 1777 help 1778 Legacy software support may require certain instructions 1779 that have been deprecated or obsoleted in the architecture. 1780 1781 Enable this config to enable selective emulation of these 1782 features. 1783 1784 If unsure, say Y 1785 1786if ARMV8_DEPRECATED 1787 1788config SWP_EMULATION 1789 bool "Emulate SWP/SWPB instructions" 1790 help 1791 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1792 they are always undefined. Say Y here to enable software 1793 emulation of these instructions for userspace using LDXR/STXR. 1794 This feature can be controlled at runtime with the abi.swp 1795 sysctl which is disabled by default. 1796 1797 In some older versions of glibc [<=2.8] SWP is used during futex 1798 trylock() operations with the assumption that the code will not 1799 be preempted. This invalid assumption may be more likely to fail 1800 with SWP emulation enabled, leading to deadlock of the user 1801 application. 1802 1803 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1804 on an external transaction monitoring block called a global 1805 monitor to maintain update atomicity. If your system does not 1806 implement a global monitor, this option can cause programs that 1807 perform SWP operations to uncached memory to deadlock. 1808 1809 If unsure, say Y 1810 1811config CP15_BARRIER_EMULATION 1812 bool "Emulate CP15 Barrier instructions" 1813 help 1814 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1815 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1816 strongly recommended to use the ISB, DSB, and DMB 1817 instructions instead. 1818 1819 Say Y here to enable software emulation of these 1820 instructions for AArch32 userspace code. When this option is 1821 enabled, CP15 barrier usage is traced which can help 1822 identify software that needs updating. This feature can be 1823 controlled at runtime with the abi.cp15_barrier sysctl. 1824 1825 If unsure, say Y 1826 1827config SETEND_EMULATION 1828 bool "Emulate SETEND instruction" 1829 help 1830 The SETEND instruction alters the data-endianness of the 1831 AArch32 EL0, and is deprecated in ARMv8. 1832 1833 Say Y here to enable software emulation of the instruction 1834 for AArch32 userspace code. This feature can be controlled 1835 at runtime with the abi.setend sysctl. 1836 1837 Note: All the cpus on the system must have mixed endian support at EL0 1838 for this feature to be enabled. If a new CPU - which doesn't support mixed 1839 endian - is hotplugged in after this feature has been enabled, there could 1840 be unexpected results in the applications. 1841 1842 If unsure, say Y 1843endif # ARMV8_DEPRECATED 1844 1845endif # COMPAT 1846 1847menu "ARMv8.1 architectural features" 1848 1849config ARM64_HW_AFDBM 1850 bool "Support for hardware updates of the Access and Dirty page flags" 1851 default y 1852 help 1853 The ARMv8.1 architecture extensions introduce support for 1854 hardware updates of the access and dirty information in page 1855 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1856 capable processors, accesses to pages with PTE_AF cleared will 1857 set this bit instead of raising an access flag fault. 1858 Similarly, writes to read-only pages with the DBM bit set will 1859 clear the read-only bit (AP[2]) instead of raising a 1860 permission fault. 1861 1862 Kernels built with this configuration option enabled continue 1863 to work on pre-ARMv8.1 hardware and the performance impact is 1864 minimal. If unsure, say Y. 1865 1866config ARM64_PAN 1867 bool "Enable support for Privileged Access Never (PAN)" 1868 default y 1869 help 1870 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1871 prevents the kernel or hypervisor from accessing user-space (EL0) 1872 memory directly. 1873 1874 Choosing this option will cause any unprotected (not using 1875 copy_to_user et al) memory access to fail with a permission fault. 1876 1877 The feature is detected at runtime, and will remain as a 'nop' 1878 instruction if the cpu does not implement the feature. 1879 1880config AS_HAS_LSE_ATOMICS 1881 def_bool $(as-instr,.arch_extension lse) 1882 1883config ARM64_LSE_ATOMICS 1884 bool 1885 default ARM64_USE_LSE_ATOMICS 1886 depends on AS_HAS_LSE_ATOMICS 1887 1888config ARM64_USE_LSE_ATOMICS 1889 bool "Atomic instructions" 1890 default y 1891 help 1892 As part of the Large System Extensions, ARMv8.1 introduces new 1893 atomic instructions that are designed specifically to scale in 1894 very large systems. 1895 1896 Say Y here to make use of these instructions for the in-kernel 1897 atomic routines. This incurs a small overhead on CPUs that do 1898 not support these instructions and requires the kernel to be 1899 built with binutils >= 2.25 in order for the new instructions 1900 to be used. 1901 1902endmenu # "ARMv8.1 architectural features" 1903 1904menu "ARMv8.2 architectural features" 1905 1906config AS_HAS_ARMV8_2 1907 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1908 1909config AS_HAS_SHA3 1910 def_bool $(as-instr,.arch armv8.2-a+sha3) 1911 1912config ARM64_PMEM 1913 bool "Enable support for persistent memory" 1914 select ARCH_HAS_PMEM_API 1915 select ARCH_HAS_UACCESS_FLUSHCACHE 1916 help 1917 Say Y to enable support for the persistent memory API based on the 1918 ARMv8.2 DCPoP feature. 1919 1920 The feature is detected at runtime, and the kernel will use DC CVAC 1921 operations if DC CVAP is not supported (following the behaviour of 1922 DC CVAP itself if the system does not define a point of persistence). 1923 1924config ARM64_RAS_EXTN 1925 bool "Enable support for RAS CPU Extensions" 1926 default y 1927 help 1928 CPUs that support the Reliability, Availability and Serviceability 1929 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1930 errors, classify them and report them to software. 1931 1932 On CPUs with these extensions system software can use additional 1933 barriers to determine if faults are pending and read the 1934 classification from a new set of registers. 1935 1936 Selecting this feature will allow the kernel to use these barriers 1937 and access the new registers if the system supports the extension. 1938 Platform RAS features may additionally depend on firmware support. 1939 1940config ARM64_CNP 1941 bool "Enable support for Common Not Private (CNP) translations" 1942 default y 1943 help 1944 Common Not Private (CNP) allows translation table entries to 1945 be shared between different PEs in the same inner shareable 1946 domain, so the hardware can use this fact to optimise the 1947 caching of such entries in the TLB. 1948 1949 Selecting this option allows the CNP feature to be detected 1950 at runtime, and does not affect PEs that do not implement 1951 this feature. 1952 1953endmenu # "ARMv8.2 architectural features" 1954 1955menu "ARMv8.3 architectural features" 1956 1957config ARM64_PTR_AUTH 1958 bool "Enable support for pointer authentication" 1959 default y 1960 help 1961 Pointer authentication (part of the ARMv8.3 Extensions) provides 1962 instructions for signing and authenticating pointers against secret 1963 keys, which can be used to mitigate Return Oriented Programming (ROP) 1964 and other attacks. 1965 1966 This option enables these instructions at EL0 (i.e. for userspace). 1967 Choosing this option will cause the kernel to initialise secret keys 1968 for each process at exec() time, with these keys being 1969 context-switched along with the process. 1970 1971 The feature is detected at runtime. If the feature is not present in 1972 hardware it will not be advertised to userspace/KVM guest nor will it 1973 be enabled. 1974 1975 If the feature is present on the boot CPU but not on a late CPU, then 1976 the late CPU will be parked. Also, if the boot CPU does not have 1977 address auth and the late CPU has then the late CPU will still boot 1978 but with the feature disabled. On such a system, this option should 1979 not be selected. 1980 1981config ARM64_PTR_AUTH_KERNEL 1982 bool "Use pointer authentication for kernel" 1983 default y 1984 depends on ARM64_PTR_AUTH 1985 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1986 # Modern compilers insert a .note.gnu.property section note for PAC 1987 # which is only understood by binutils starting with version 2.33.1. 1988 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1989 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1990 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1991 help 1992 If the compiler supports the -mbranch-protection or 1993 -msign-return-address flag (e.g. GCC 7 or later), then this option 1994 will cause the kernel itself to be compiled with return address 1995 protection. In this case, and if the target hardware is known to 1996 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1997 disabled with minimal loss of protection. 1998 1999 This feature works with FUNCTION_GRAPH_TRACER option only if 2000 DYNAMIC_FTRACE_WITH_ARGS is enabled. 2001 2002config CC_HAS_BRANCH_PROT_PAC_RET 2003 # GCC 9 or later, clang 8 or later 2004 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 2005 2006config CC_HAS_SIGN_RETURN_ADDRESS 2007 # GCC 7, 8 2008 def_bool $(cc-option,-msign-return-address=all) 2009 2010config AS_HAS_ARMV8_3 2011 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 2012 2013config AS_HAS_CFI_NEGATE_RA_STATE 2014 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2015 2016config AS_HAS_LDAPR 2017 def_bool $(as-instr,.arch_extension rcpc) 2018 2019endmenu # "ARMv8.3 architectural features" 2020 2021menu "ARMv8.4 architectural features" 2022 2023config ARM64_AMU_EXTN 2024 bool "Enable support for the Activity Monitors Unit CPU extension" 2025 default y 2026 help 2027 The activity monitors extension is an optional extension introduced 2028 by the ARMv8.4 CPU architecture. This enables support for version 1 2029 of the activity monitors architecture, AMUv1. 2030 2031 To enable the use of this extension on CPUs that implement it, say Y. 2032 2033 Note that for architectural reasons, firmware _must_ implement AMU 2034 support when running on CPUs that present the activity monitors 2035 extension. The required support is present in: 2036 * Version 1.5 and later of the ARM Trusted Firmware 2037 2038 For kernels that have this configuration enabled but boot with broken 2039 firmware, you may need to say N here until the firmware is fixed. 2040 Otherwise you may experience firmware panics or lockups when 2041 accessing the counter registers. Even if you are not observing these 2042 symptoms, the values returned by the register reads might not 2043 correctly reflect reality. Most commonly, the value read will be 0, 2044 indicating that the counter is not enabled. 2045 2046config AS_HAS_ARMV8_4 2047 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2048 2049config ARM64_TLB_RANGE 2050 bool "Enable support for tlbi range feature" 2051 default y 2052 depends on AS_HAS_ARMV8_4 2053 help 2054 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2055 range of input addresses. 2056 2057 The feature introduces new assembly instructions, and they were 2058 support when binutils >= 2.30. 2059 2060endmenu # "ARMv8.4 architectural features" 2061 2062menu "ARMv8.5 architectural features" 2063 2064config AS_HAS_ARMV8_5 2065 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2066 2067config ARM64_BTI 2068 bool "Branch Target Identification support" 2069 default y 2070 help 2071 Branch Target Identification (part of the ARMv8.5 Extensions) 2072 provides a mechanism to limit the set of locations to which computed 2073 branch instructions such as BR or BLR can jump. 2074 2075 To make use of BTI on CPUs that support it, say Y. 2076 2077 BTI is intended to provide complementary protection to other control 2078 flow integrity protection mechanisms, such as the Pointer 2079 authentication mechanism provided as part of the ARMv8.3 Extensions. 2080 For this reason, it does not make sense to enable this option without 2081 also enabling support for pointer authentication. Thus, when 2082 enabling this option you should also select ARM64_PTR_AUTH=y. 2083 2084 Userspace binaries must also be specifically compiled to make use of 2085 this mechanism. If you say N here or the hardware does not support 2086 BTI, such binaries can still run, but you get no additional 2087 enforcement of branch destinations. 2088 2089config ARM64_BTI_KERNEL 2090 bool "Use Branch Target Identification for kernel" 2091 default y 2092 depends on ARM64_BTI 2093 depends on ARM64_PTR_AUTH_KERNEL 2094 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2095 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2096 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2097 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2098 depends on !CC_IS_GCC 2099 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2100 help 2101 Build the kernel with Branch Target Identification annotations 2102 and enable enforcement of this for kernel code. When this option 2103 is enabled and the system supports BTI all kernel code including 2104 modular code must have BTI enabled. 2105 2106config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2107 # GCC 9 or later, clang 8 or later 2108 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2109 2110config ARM64_E0PD 2111 bool "Enable support for E0PD" 2112 default y 2113 help 2114 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2115 that EL0 accesses made via TTBR1 always fault in constant time, 2116 providing similar benefits to KASLR as those provided by KPTI, but 2117 with lower overhead and without disrupting legitimate access to 2118 kernel memory such as SPE. 2119 2120 This option enables E0PD for TTBR1 where available. 2121 2122config ARM64_AS_HAS_MTE 2123 # Initial support for MTE went in binutils 2.32.0, checked with 2124 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2125 # as a late addition to the final architecture spec (LDGM/STGM) 2126 # is only supported in the newer 2.32.x and 2.33 binutils 2127 # versions, hence the extra "stgm" instruction check below. 2128 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2129 2130config ARM64_MTE 2131 bool "Memory Tagging Extension support" 2132 default y 2133 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2134 depends on AS_HAS_ARMV8_5 2135 depends on AS_HAS_LSE_ATOMICS 2136 # Required for tag checking in the uaccess routines 2137 select ARM64_PAN 2138 select ARCH_HAS_SUBPAGE_FAULTS 2139 select ARCH_USES_HIGH_VMA_FLAGS 2140 select ARCH_USES_PG_ARCH_2 2141 select ARCH_USES_PG_ARCH_3 2142 help 2143 Memory Tagging (part of the ARMv8.5 Extensions) provides 2144 architectural support for run-time, always-on detection of 2145 various classes of memory error to aid with software debugging 2146 to eliminate vulnerabilities arising from memory-unsafe 2147 languages. 2148 2149 This option enables the support for the Memory Tagging 2150 Extension at EL0 (i.e. for userspace). 2151 2152 Selecting this option allows the feature to be detected at 2153 runtime. Any secondary CPU not implementing this feature will 2154 not be allowed a late bring-up. 2155 2156 Userspace binaries that want to use this feature must 2157 explicitly opt in. The mechanism for the userspace is 2158 described in: 2159 2160 Documentation/arch/arm64/memory-tagging-extension.rst. 2161 2162endmenu # "ARMv8.5 architectural features" 2163 2164menu "ARMv8.7 architectural features" 2165 2166config ARM64_EPAN 2167 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2168 default y 2169 depends on ARM64_PAN 2170 help 2171 Enhanced Privileged Access Never (EPAN) allows Privileged 2172 Access Never to be used with Execute-only mappings. 2173 2174 The feature is detected at runtime, and will remain disabled 2175 if the cpu does not implement the feature. 2176endmenu # "ARMv8.7 architectural features" 2177 2178config AS_HAS_MOPS 2179 def_bool $(as-instr,.arch_extension mops) 2180 2181menu "ARMv8.9 architectural features" 2182 2183config ARM64_POE 2184 prompt "Permission Overlay Extension" 2185 def_bool y 2186 select ARCH_USES_HIGH_VMA_FLAGS 2187 select ARCH_HAS_PKEYS 2188 help 2189 The Permission Overlay Extension is used to implement Memory 2190 Protection Keys. Memory Protection Keys provides a mechanism for 2191 enforcing page-based protections, but without requiring modification 2192 of the page tables when an application changes protection domains. 2193 2194 For details, see Documentation/core-api/protection-keys.rst 2195 2196 If unsure, say y. 2197 2198config ARCH_PKEY_BITS 2199 int 2200 default 3 2201 2202config ARM64_HAFT 2203 bool "Support for Hardware managed Access Flag for Table Descriptors" 2204 depends on ARM64_HW_AFDBM 2205 default y 2206 help 2207 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2208 Flag for Table descriptors. When enabled an architectural executed 2209 memory access will update the Access Flag in each Table descriptor 2210 which is accessed during the translation table walk and for which 2211 the Access Flag is 0. The Access Flag of the Table descriptor use 2212 the same bit of PTE_AF. 2213 2214 The feature will only be enabled if all the CPUs in the system 2215 support this feature. If unsure, say Y. 2216 2217endmenu # "ARMv8.9 architectural features" 2218 2219menu "v9.4 architectural features" 2220 2221config ARM64_GCS 2222 bool "Enable support for Guarded Control Stack (GCS)" 2223 default y 2224 select ARCH_HAS_USER_SHADOW_STACK 2225 select ARCH_USES_HIGH_VMA_FLAGS 2226 depends on !UPROBES 2227 help 2228 Guarded Control Stack (GCS) provides support for a separate 2229 stack with restricted access which contains only return 2230 addresses. This can be used to harden against some attacks 2231 by comparing return address used by the program with what is 2232 stored in the GCS, and may also be used to efficiently obtain 2233 the call stack for applications such as profiling. 2234 2235 The feature is detected at runtime, and will remain disabled 2236 if the system does not implement the feature. 2237 2238endmenu # "v9.4 architectural features" 2239 2240config ARM64_SVE 2241 bool "ARM Scalable Vector Extension support" 2242 default y 2243 help 2244 The Scalable Vector Extension (SVE) is an extension to the AArch64 2245 execution state which complements and extends the SIMD functionality 2246 of the base architecture to support much larger vectors and to enable 2247 additional vectorisation opportunities. 2248 2249 To enable use of this extension on CPUs that implement it, say Y. 2250 2251 On CPUs that support the SVE2 extensions, this option will enable 2252 those too. 2253 2254 Note that for architectural reasons, firmware _must_ implement SVE 2255 support when running on SVE capable hardware. The required support 2256 is present in: 2257 2258 * version 1.5 and later of the ARM Trusted Firmware 2259 * the AArch64 boot wrapper since commit 5e1261e08abf 2260 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2261 2262 For other firmware implementations, consult the firmware documentation 2263 or vendor. 2264 2265 If you need the kernel to boot on SVE-capable hardware with broken 2266 firmware, you may need to say N here until you get your firmware 2267 fixed. Otherwise, you may experience firmware panics or lockups when 2268 booting the kernel. If unsure and you are not observing these 2269 symptoms, you should assume that it is safe to say Y. 2270 2271config ARM64_SME 2272 bool "ARM Scalable Matrix Extension support" 2273 default y 2274 depends on ARM64_SVE 2275 depends on BROKEN 2276 help 2277 The Scalable Matrix Extension (SME) is an extension to the AArch64 2278 execution state which utilises a substantial subset of the SVE 2279 instruction set, together with the addition of new architectural 2280 register state capable of holding two dimensional matrix tiles to 2281 enable various matrix operations. 2282 2283config ARM64_PSEUDO_NMI 2284 bool "Support for NMI-like interrupts" 2285 select ARM_GIC_V3 2286 help 2287 Adds support for mimicking Non-Maskable Interrupts through the use of 2288 GIC interrupt priority. This support requires version 3 or later of 2289 ARM GIC. 2290 2291 This high priority configuration for interrupts needs to be 2292 explicitly enabled by setting the kernel parameter 2293 "irqchip.gicv3_pseudo_nmi" to 1. 2294 2295 If unsure, say N 2296 2297if ARM64_PSEUDO_NMI 2298config ARM64_DEBUG_PRIORITY_MASKING 2299 bool "Debug interrupt priority masking" 2300 help 2301 This adds runtime checks to functions enabling/disabling 2302 interrupts when using priority masking. The additional checks verify 2303 the validity of ICC_PMR_EL1 when calling concerned functions. 2304 2305 If unsure, say N 2306endif # ARM64_PSEUDO_NMI 2307 2308config RELOCATABLE 2309 bool "Build a relocatable kernel image" if EXPERT 2310 select ARCH_HAS_RELR 2311 default y 2312 help 2313 This builds the kernel as a Position Independent Executable (PIE), 2314 which retains all relocation metadata required to relocate the 2315 kernel binary at runtime to a different virtual address than the 2316 address it was linked at. 2317 Since AArch64 uses the RELA relocation format, this requires a 2318 relocation pass at runtime even if the kernel is loaded at the 2319 same address it was linked at. 2320 2321config RANDOMIZE_BASE 2322 bool "Randomize the address of the kernel image" 2323 select RELOCATABLE 2324 help 2325 Randomizes the virtual address at which the kernel image is 2326 loaded, as a security feature that deters exploit attempts 2327 relying on knowledge of the location of kernel internals. 2328 2329 It is the bootloader's job to provide entropy, by passing a 2330 random u64 value in /chosen/kaslr-seed at kernel entry. 2331 2332 When booting via the UEFI stub, it will invoke the firmware's 2333 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2334 to the kernel proper. In addition, it will randomise the physical 2335 location of the kernel Image as well. 2336 2337 If unsure, say N. 2338 2339config RANDOMIZE_MODULE_REGION_FULL 2340 bool "Randomize the module region over a 2 GB range" 2341 depends on RANDOMIZE_BASE 2342 default y 2343 help 2344 Randomizes the location of the module region inside a 2 GB window 2345 covering the core kernel. This way, it is less likely for modules 2346 to leak information about the location of core kernel data structures 2347 but it does imply that function calls between modules and the core 2348 kernel will need to be resolved via veneers in the module PLT. 2349 2350 When this option is not set, the module region will be randomized over 2351 a limited range that contains the [_stext, _etext] interval of the 2352 core kernel, so branch relocations are almost always in range unless 2353 the region is exhausted. In this particular case of region 2354 exhaustion, modules might be able to fall back to a larger 2GB area. 2355 2356config CC_HAVE_STACKPROTECTOR_SYSREG 2357 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2358 2359config STACKPROTECTOR_PER_TASK 2360 def_bool y 2361 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2362 2363config UNWIND_PATCH_PAC_INTO_SCS 2364 bool "Enable shadow call stack dynamically using code patching" 2365 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2366 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2367 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2368 depends on SHADOW_CALL_STACK 2369 select UNWIND_TABLES 2370 select DYNAMIC_SCS 2371 2372config ARM64_CONTPTE 2373 bool "Contiguous PTE mappings for user memory" if EXPERT 2374 depends on TRANSPARENT_HUGEPAGE 2375 default y 2376 help 2377 When enabled, user mappings are configured using the PTE contiguous 2378 bit, for any mappings that meet the size and alignment requirements. 2379 This reduces TLB pressure and improves performance. 2380 2381endmenu # "Kernel Features" 2382 2383menu "Boot options" 2384 2385config ARM64_ACPI_PARKING_PROTOCOL 2386 bool "Enable support for the ARM64 ACPI parking protocol" 2387 depends on ACPI 2388 help 2389 Enable support for the ARM64 ACPI parking protocol. If disabled 2390 the kernel will not allow booting through the ARM64 ACPI parking 2391 protocol even if the corresponding data is present in the ACPI 2392 MADT table. 2393 2394config CMDLINE 2395 string "Default kernel command string" 2396 default "" 2397 help 2398 Provide a set of default command-line options at build time by 2399 entering them here. As a minimum, you should specify the the 2400 root device (e.g. root=/dev/nfs). 2401 2402choice 2403 prompt "Kernel command line type" 2404 depends on CMDLINE != "" 2405 default CMDLINE_FROM_BOOTLOADER 2406 help 2407 Choose how the kernel will handle the provided default kernel 2408 command line string. 2409 2410config CMDLINE_FROM_BOOTLOADER 2411 bool "Use bootloader kernel arguments if available" 2412 help 2413 Uses the command-line options passed by the boot loader. If 2414 the boot loader doesn't provide any, the default kernel command 2415 string provided in CMDLINE will be used. 2416 2417config CMDLINE_FORCE 2418 bool "Always use the default kernel command string" 2419 help 2420 Always use the default kernel command string, even if the boot 2421 loader passes other arguments to the kernel. 2422 This is useful if you cannot or don't want to change the 2423 command-line options your boot loader passes to the kernel. 2424 2425endchoice 2426 2427config EFI_STUB 2428 bool 2429 2430config EFI 2431 bool "UEFI runtime support" 2432 depends on OF && !CPU_BIG_ENDIAN 2433 depends on KERNEL_MODE_NEON 2434 select ARCH_SUPPORTS_ACPI 2435 select LIBFDT 2436 select UCS2_STRING 2437 select EFI_PARAMS_FROM_FDT 2438 select EFI_RUNTIME_WRAPPERS 2439 select EFI_STUB 2440 select EFI_GENERIC_STUB 2441 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2442 default y 2443 help 2444 This option provides support for runtime services provided 2445 by UEFI firmware (such as non-volatile variables, realtime 2446 clock, and platform reset). A UEFI stub is also provided to 2447 allow the kernel to be booted as an EFI application. This 2448 is only useful on systems that have UEFI firmware. 2449 2450config COMPRESSED_INSTALL 2451 bool "Install compressed image by default" 2452 help 2453 This makes the regular "make install" install the compressed 2454 image we built, not the legacy uncompressed one. 2455 2456 You can check that a compressed image works for you by doing 2457 "make zinstall" first, and verifying that everything is fine 2458 in your environment before making "make install" do this for 2459 you. 2460 2461config DMI 2462 bool "Enable support for SMBIOS (DMI) tables" 2463 depends on EFI 2464 default y 2465 help 2466 This enables SMBIOS/DMI feature for systems. 2467 2468 This option is only useful on systems that have UEFI firmware. 2469 However, even with this option, the resultant kernel should 2470 continue to boot on existing non-UEFI platforms. 2471 2472endmenu # "Boot options" 2473 2474menu "Power management options" 2475 2476source "kernel/power/Kconfig" 2477 2478config ARCH_HIBERNATION_POSSIBLE 2479 def_bool y 2480 depends on CPU_PM 2481 2482config ARCH_HIBERNATION_HEADER 2483 def_bool y 2484 depends on HIBERNATION 2485 2486config ARCH_SUSPEND_POSSIBLE 2487 def_bool y 2488 2489endmenu # "Power management options" 2490 2491menu "CPU Power Management" 2492 2493source "drivers/cpuidle/Kconfig" 2494 2495source "drivers/cpufreq/Kconfig" 2496 2497endmenu # "CPU Power Management" 2498 2499source "drivers/acpi/Kconfig" 2500 2501source "arch/arm64/kvm/Kconfig" 2502 2503