xref: /linux/drivers/iio/imu/adis16480.c (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * ADIS16480 and similar IMUs driver
4  *
5  * Copyright 2012 Analog Devices Inc.
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/bitfield.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/math.h>
13 #include <linux/device.h>
14 #include <linux/kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/lcm.h>
19 #include <linux/property.h>
20 #include <linux/swab.h>
21 #include <linux/crc32.h>
22 
23 #include <linux/iio/iio.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/imu/adis.h>
26 #include <linux/iio/trigger_consumer.h>
27 
28 #include <linux/debugfs.h>
29 
30 #define ADIS16480_PAGE_SIZE 0x80
31 
32 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg))
33 
34 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */
35 #define ADIS16480_REG_SEQ_CNT			ADIS16480_REG(0x00, 0x06)
36 #define ADIS16480_REG_SYS_E_FLA			ADIS16480_REG(0x00, 0x08)
37 #define ADIS16480_REG_DIAG_STS			ADIS16480_REG(0x00, 0x0A)
38 #define ADIS16480_REG_ALM_STS			ADIS16480_REG(0x00, 0x0C)
39 #define ADIS16480_REG_TEMP_OUT			ADIS16480_REG(0x00, 0x0E)
40 #define ADIS16480_REG_X_GYRO_OUT		ADIS16480_REG(0x00, 0x10)
41 #define ADIS16480_REG_Y_GYRO_OUT		ADIS16480_REG(0x00, 0x14)
42 #define ADIS16480_REG_Z_GYRO_OUT		ADIS16480_REG(0x00, 0x18)
43 #define ADIS16480_REG_X_ACCEL_OUT		ADIS16480_REG(0x00, 0x1C)
44 #define ADIS16480_REG_Y_ACCEL_OUT		ADIS16480_REG(0x00, 0x20)
45 #define ADIS16480_REG_Z_ACCEL_OUT		ADIS16480_REG(0x00, 0x24)
46 #define ADIS16480_REG_X_MAGN_OUT		ADIS16480_REG(0x00, 0x28)
47 #define ADIS16480_REG_Y_MAGN_OUT		ADIS16480_REG(0x00, 0x2A)
48 #define ADIS16480_REG_Z_MAGN_OUT		ADIS16480_REG(0x00, 0x2C)
49 #define ADIS16480_REG_BAROM_OUT			ADIS16480_REG(0x00, 0x2E)
50 #define ADIS16480_REG_X_DELTAANG_OUT		ADIS16480_REG(0x00, 0x40)
51 #define ADIS16480_REG_Y_DELTAANG_OUT		ADIS16480_REG(0x00, 0x44)
52 #define ADIS16480_REG_Z_DELTAANG_OUT		ADIS16480_REG(0x00, 0x48)
53 #define ADIS16480_REG_X_DELTAVEL_OUT		ADIS16480_REG(0x00, 0x4C)
54 #define ADIS16480_REG_Y_DELTAVEL_OUT		ADIS16480_REG(0x00, 0x50)
55 #define ADIS16480_REG_Z_DELTAVEL_OUT		ADIS16480_REG(0x00, 0x54)
56 #define ADIS16480_REG_PROD_ID			ADIS16480_REG(0x00, 0x7E)
57 
58 #define ADIS16480_REG_X_GYRO_SCALE		ADIS16480_REG(0x02, 0x04)
59 #define ADIS16480_REG_Y_GYRO_SCALE		ADIS16480_REG(0x02, 0x06)
60 #define ADIS16480_REG_Z_GYRO_SCALE		ADIS16480_REG(0x02, 0x08)
61 #define ADIS16480_REG_X_ACCEL_SCALE		ADIS16480_REG(0x02, 0x0A)
62 #define ADIS16480_REG_Y_ACCEL_SCALE		ADIS16480_REG(0x02, 0x0C)
63 #define ADIS16480_REG_Z_ACCEL_SCALE		ADIS16480_REG(0x02, 0x0E)
64 #define ADIS16480_REG_X_GYRO_BIAS		ADIS16480_REG(0x02, 0x10)
65 #define ADIS16480_REG_Y_GYRO_BIAS		ADIS16480_REG(0x02, 0x14)
66 #define ADIS16480_REG_Z_GYRO_BIAS		ADIS16480_REG(0x02, 0x18)
67 #define ADIS16480_REG_X_ACCEL_BIAS		ADIS16480_REG(0x02, 0x1C)
68 #define ADIS16480_REG_Y_ACCEL_BIAS		ADIS16480_REG(0x02, 0x20)
69 #define ADIS16480_REG_Z_ACCEL_BIAS		ADIS16480_REG(0x02, 0x24)
70 #define ADIS16480_REG_X_HARD_IRON		ADIS16480_REG(0x02, 0x28)
71 #define ADIS16480_REG_Y_HARD_IRON		ADIS16480_REG(0x02, 0x2A)
72 #define ADIS16480_REG_Z_HARD_IRON		ADIS16480_REG(0x02, 0x2C)
73 #define ADIS16480_REG_BAROM_BIAS		ADIS16480_REG(0x02, 0x40)
74 #define ADIS16480_REG_FLASH_CNT			ADIS16480_REG(0x02, 0x7C)
75 
76 #define ADIS16480_REG_GLOB_CMD			ADIS16480_REG(0x03, 0x02)
77 #define ADIS16480_REG_FNCTIO_CTRL		ADIS16480_REG(0x03, 0x06)
78 #define ADIS16480_REG_GPIO_CTRL			ADIS16480_REG(0x03, 0x08)
79 #define ADIS16480_REG_CONFIG			ADIS16480_REG(0x03, 0x0A)
80 #define ADIS16480_REG_DEC_RATE			ADIS16480_REG(0x03, 0x0C)
81 #define ADIS16480_REG_SLP_CNT			ADIS16480_REG(0x03, 0x10)
82 #define ADIS16480_REG_FILTER_BNK0		ADIS16480_REG(0x03, 0x16)
83 #define ADIS16480_REG_FILTER_BNK1		ADIS16480_REG(0x03, 0x18)
84 #define ADIS16480_REG_ALM_CNFG0			ADIS16480_REG(0x03, 0x20)
85 #define ADIS16480_REG_ALM_CNFG1			ADIS16480_REG(0x03, 0x22)
86 #define ADIS16480_REG_ALM_CNFG2			ADIS16480_REG(0x03, 0x24)
87 #define ADIS16480_REG_XG_ALM_MAGN		ADIS16480_REG(0x03, 0x28)
88 #define ADIS16480_REG_YG_ALM_MAGN		ADIS16480_REG(0x03, 0x2A)
89 #define ADIS16480_REG_ZG_ALM_MAGN		ADIS16480_REG(0x03, 0x2C)
90 #define ADIS16480_REG_XA_ALM_MAGN		ADIS16480_REG(0x03, 0x2E)
91 #define ADIS16480_REG_YA_ALM_MAGN		ADIS16480_REG(0x03, 0x30)
92 #define ADIS16480_REG_ZA_ALM_MAGN		ADIS16480_REG(0x03, 0x32)
93 #define ADIS16480_REG_XM_ALM_MAGN		ADIS16480_REG(0x03, 0x34)
94 #define ADIS16480_REG_YM_ALM_MAGN		ADIS16480_REG(0x03, 0x36)
95 #define ADIS16480_REG_ZM_ALM_MAGN		ADIS16480_REG(0x03, 0x38)
96 #define ADIS16480_REG_BR_ALM_MAGN		ADIS16480_REG(0x03, 0x3A)
97 #define ADIS16480_REG_FIRM_REV			ADIS16480_REG(0x03, 0x78)
98 #define ADIS16480_REG_FIRM_DM			ADIS16480_REG(0x03, 0x7A)
99 #define ADIS16480_REG_FIRM_Y			ADIS16480_REG(0x03, 0x7C)
100 
101 /*
102  * External clock scaling in PPS mode.
103  * Available only for ADIS1649x devices
104  */
105 #define ADIS16495_REG_SYNC_SCALE		ADIS16480_REG(0x03, 0x10)
106 #define ADIS16495_REG_BURST_CMD			ADIS16480_REG(0x00, 0x7C)
107 #define ADIS16495_GYRO_ACCEL_BURST_ID		0xA5A5
108 #define ADIS16545_DELTA_ANG_VEL_BURST_ID	0xC3C3
109 /* total number of segments in burst */
110 #define ADIS16495_BURST_MAX_DATA		20
111 
112 #define ADIS16480_REG_SERIAL_NUM		ADIS16480_REG(0x04, 0x20)
113 
114 /* Each filter coefficent bank spans two pages */
115 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \
116 		ADIS16480_REG((page) + 1, (x) - 60 + 8))
117 #define ADIS16480_FIR_COEF_A(x)			ADIS16480_FIR_COEF(0x05, (x))
118 #define ADIS16480_FIR_COEF_B(x)			ADIS16480_FIR_COEF(0x07, (x))
119 #define ADIS16480_FIR_COEF_C(x)			ADIS16480_FIR_COEF(0x09, (x))
120 #define ADIS16480_FIR_COEF_D(x)			ADIS16480_FIR_COEF(0x0B, (x))
121 
122 /* ADIS16480_REG_FNCTIO_CTRL */
123 #define ADIS16480_DRDY_SEL_MSK		GENMASK(1, 0)
124 #define ADIS16480_DRDY_SEL(x)		FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x)
125 #define ADIS16480_DRDY_POL_MSK		BIT(2)
126 #define ADIS16480_DRDY_POL(x)		FIELD_PREP(ADIS16480_DRDY_POL_MSK, x)
127 #define ADIS16480_DRDY_EN_MSK		BIT(3)
128 #define ADIS16480_DRDY_EN(x)		FIELD_PREP(ADIS16480_DRDY_EN_MSK, x)
129 #define ADIS16480_SYNC_SEL_MSK		GENMASK(5, 4)
130 #define ADIS16480_SYNC_SEL(x)		FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x)
131 #define ADIS16480_SYNC_EN_MSK		BIT(7)
132 #define ADIS16480_SYNC_EN(x)		FIELD_PREP(ADIS16480_SYNC_EN_MSK, x)
133 #define ADIS16480_SYNC_MODE_MSK		BIT(8)
134 #define ADIS16480_SYNC_MODE(x)		FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x)
135 
136 #define ADIS16545_BURST_DATA_SEL_0_CHN_MASK	GENMASK(5, 0)
137 #define ADIS16545_BURST_DATA_SEL_1_CHN_MASK	GENMASK(16, 11)
138 #define ADIS16545_BURST_DATA_SEL_MASK		BIT(8)
139 
140 struct adis16480_chip_info {
141 	unsigned int num_channels;
142 	const struct iio_chan_spec *channels;
143 	unsigned int gyro_max_val;
144 	unsigned int gyro_max_scale;
145 	unsigned int accel_max_val;
146 	unsigned int accel_max_scale;
147 	unsigned int temp_scale;
148 	unsigned int deltang_max_val;
149 	unsigned int deltvel_max_val;
150 	unsigned int int_clk;
151 	unsigned int max_dec_rate;
152 	const unsigned int *filter_freqs;
153 	bool has_pps_clk_mode;
154 	bool has_sleep_cnt;
155 	bool has_burst_delta_data;
156 	const struct adis_data adis_data;
157 };
158 
159 enum adis16480_int_pin {
160 	ADIS16480_PIN_DIO1,
161 	ADIS16480_PIN_DIO2,
162 	ADIS16480_PIN_DIO3,
163 	ADIS16480_PIN_DIO4
164 };
165 
166 enum adis16480_clock_mode {
167 	ADIS16480_CLK_SYNC,
168 	ADIS16480_CLK_PPS,
169 	ADIS16480_CLK_INT
170 };
171 
172 struct adis16480 {
173 	const struct adis16480_chip_info *chip_info;
174 
175 	struct adis adis;
176 	struct clk *ext_clk;
177 	enum adis16480_clock_mode clk_mode;
178 	unsigned int clk_freq;
179 	u16 burst_id;
180 	/* Alignment needed for the timestamp */
181 	__be16 data[ADIS16495_BURST_MAX_DATA] __aligned(8);
182 };
183 
184 static const char * const adis16480_int_pin_names[4] = {
185 	[ADIS16480_PIN_DIO1] = "DIO1",
186 	[ADIS16480_PIN_DIO2] = "DIO2",
187 	[ADIS16480_PIN_DIO3] = "DIO3",
188 	[ADIS16480_PIN_DIO4] = "DIO4",
189 };
190 
191 static bool low_rate_allow;
192 module_param(low_rate_allow, bool, 0444);
193 MODULE_PARM_DESC(low_rate_allow,
194 		 "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)");
195 
adis16480_show_firmware_revision(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)196 static ssize_t adis16480_show_firmware_revision(struct file *file,
197 		char __user *userbuf, size_t count, loff_t *ppos)
198 {
199 	struct adis16480 *adis16480 = file->private_data;
200 	char buf[7];
201 	size_t len;
202 	u16 rev;
203 	int ret;
204 
205 	ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev);
206 	if (ret)
207 		return ret;
208 
209 	len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
210 
211 	return simple_read_from_buffer(userbuf, count, ppos, buf, len);
212 }
213 
214 static const struct file_operations adis16480_firmware_revision_fops = {
215 	.open = simple_open,
216 	.read = adis16480_show_firmware_revision,
217 	.llseek = default_llseek,
218 	.owner = THIS_MODULE,
219 };
220 
adis16480_show_firmware_date(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)221 static ssize_t adis16480_show_firmware_date(struct file *file,
222 		char __user *userbuf, size_t count, loff_t *ppos)
223 {
224 	struct adis16480 *adis16480 = file->private_data;
225 	u16 md, year;
226 	char buf[12];
227 	size_t len;
228 	int ret;
229 
230 	ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year);
231 	if (ret)
232 		return ret;
233 
234 	ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md);
235 	if (ret)
236 		return ret;
237 
238 	len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n",
239 			md >> 8, md & 0xff, year);
240 
241 	return simple_read_from_buffer(userbuf, count, ppos, buf, len);
242 }
243 
244 static const struct file_operations adis16480_firmware_date_fops = {
245 	.open = simple_open,
246 	.read = adis16480_show_firmware_date,
247 	.llseek = default_llseek,
248 	.owner = THIS_MODULE,
249 };
250 
adis16480_show_serial_number(void * arg,u64 * val)251 static int adis16480_show_serial_number(void *arg, u64 *val)
252 {
253 	struct adis16480 *adis16480 = arg;
254 	u16 serial;
255 	int ret;
256 
257 	ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM,
258 		&serial);
259 	if (ret)
260 		return ret;
261 
262 	*val = serial;
263 
264 	return 0;
265 }
266 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops,
267 	adis16480_show_serial_number, NULL, "0x%.4llx\n");
268 
adis16480_show_product_id(void * arg,u64 * val)269 static int adis16480_show_product_id(void *arg, u64 *val)
270 {
271 	struct adis16480 *adis16480 = arg;
272 	u16 prod_id;
273 	int ret;
274 
275 	ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID,
276 		&prod_id);
277 	if (ret)
278 		return ret;
279 
280 	*val = prod_id;
281 
282 	return 0;
283 }
284 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops,
285 	adis16480_show_product_id, NULL, "%llu\n");
286 
adis16480_show_flash_count(void * arg,u64 * val)287 static int adis16480_show_flash_count(void *arg, u64 *val)
288 {
289 	struct adis16480 *adis16480 = arg;
290 	u32 flash_count;
291 	int ret;
292 
293 	ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT,
294 		&flash_count);
295 	if (ret)
296 		return ret;
297 
298 	*val = flash_count;
299 
300 	return 0;
301 }
302 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops,
303 	adis16480_show_flash_count, NULL, "%lld\n");
304 
adis16480_debugfs_init(struct iio_dev * indio_dev)305 static void adis16480_debugfs_init(struct iio_dev *indio_dev)
306 {
307 	struct adis16480 *adis16480 = iio_priv(indio_dev);
308 	struct dentry *d = iio_get_debugfs_dentry(indio_dev);
309 
310 	if (!IS_ENABLED(CONFIG_DEBUG_FS))
311 		return;
312 
313 	debugfs_create_file_unsafe("firmware_revision", 0400,
314 		d, adis16480, &adis16480_firmware_revision_fops);
315 	debugfs_create_file_unsafe("firmware_date", 0400,
316 		d, adis16480, &adis16480_firmware_date_fops);
317 	debugfs_create_file_unsafe("serial_number", 0400,
318 		d, adis16480, &adis16480_serial_number_fops);
319 	debugfs_create_file_unsafe("product_id", 0400,
320 		d, adis16480, &adis16480_product_id_fops);
321 	debugfs_create_file_unsafe("flash_count", 0400,
322 		d, adis16480, &adis16480_flash_count_fops);
323 }
324 
adis16480_set_freq(struct iio_dev * indio_dev,int val,int val2)325 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2)
326 {
327 	struct adis16480 *st = iio_priv(indio_dev);
328 	unsigned int t, sample_rate = st->clk_freq;
329 	int ret;
330 
331 	if (val < 0 || val2 < 0)
332 		return -EINVAL;
333 
334 	t =  val * 1000 + val2 / 1000;
335 	if (t == 0)
336 		return -EINVAL;
337 
338 	adis_dev_auto_lock(&st->adis);
339 	/*
340 	 * When using PPS mode, the input clock needs to be scaled so that we have an IMU
341 	 * sample rate between (optimally) 4000 and 4250. After this, we can use the
342 	 * decimation filter to lower the sampling rate in order to get what the user wants.
343 	 * Optimally, the user sample rate is a multiple of both the IMU sample rate and
344 	 * the input clock. Hence, calculating the sync_scale dynamically gives us better
345 	 * chances of achieving a perfect/integer value for DEC_RATE. The math here is:
346 	 *	1. lcm of the input clock and the desired output rate.
347 	 *	2. get the highest multiple of the previous result lower than the adis max rate.
348 	 *	3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE
349 	 *	   and DEC_RATE (to get the user output rate)
350 	 */
351 	if (st->clk_mode == ADIS16480_CLK_PPS) {
352 		unsigned long scaled_rate = lcm(st->clk_freq, t);
353 		int sync_scale;
354 
355 		/*
356 		 * If lcm is bigger than the IMU maximum sampling rate there's no perfect
357 		 * solution. In this case, we get the highest multiple of the input clock
358 		 * lower than the IMU max sample rate.
359 		 */
360 		if (scaled_rate > st->chip_info->int_clk)
361 			scaled_rate = st->chip_info->int_clk / st->clk_freq * st->clk_freq;
362 		else
363 			scaled_rate = st->chip_info->int_clk / scaled_rate * scaled_rate;
364 
365 		/*
366 		 * This is not an hard requirement but it's not advised to run the IMU
367 		 * with a sample rate lower than 4000Hz due to possible undersampling
368 		 * issues. However, there are users that might really want to take the risk.
369 		 * Hence, we provide a module parameter for them. If set, we allow sample
370 		 * rates lower than 4KHz. By default, we won't allow this and we just roundup
371 		 * the rate to the next multiple of the input clock bigger than 4KHz. This
372 		 * is done like this as in some cases (when DEC_RATE is 0) might give
373 		 * us the closest value to the one desired by the user...
374 		 */
375 		if (scaled_rate < 4000000 && !low_rate_allow)
376 			scaled_rate = roundup(4000000, st->clk_freq);
377 
378 		sync_scale = scaled_rate / st->clk_freq;
379 		ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale);
380 		if (ret)
381 			return ret;
382 
383 		sample_rate = scaled_rate;
384 	}
385 
386 	t = DIV_ROUND_CLOSEST(sample_rate, t);
387 	if (t)
388 		t--;
389 
390 	if (t > st->chip_info->max_dec_rate)
391 		t = st->chip_info->max_dec_rate;
392 
393 	return __adis_write_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, t);
394 }
395 
adis16480_get_freq(struct iio_dev * indio_dev,int * val,int * val2)396 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2)
397 {
398 	struct adis16480 *st = iio_priv(indio_dev);
399 	uint16_t t;
400 	int ret;
401 	unsigned int freq, sample_rate = st->clk_freq;
402 
403 	adis_dev_auto_lock(&st->adis);
404 
405 	if (st->clk_mode == ADIS16480_CLK_PPS) {
406 		u16 sync_scale;
407 
408 		ret = __adis_read_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, &sync_scale);
409 		if (ret)
410 			return ret;
411 
412 		sample_rate = st->clk_freq * sync_scale;
413 	}
414 
415 	ret = __adis_read_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, &t);
416 	if (ret)
417 		return ret;
418 
419 	freq = DIV_ROUND_CLOSEST(sample_rate, (t + 1));
420 
421 	*val = freq / 1000;
422 	*val2 = (freq % 1000) * 1000;
423 
424 	return IIO_VAL_INT_PLUS_MICRO;
425 }
426 
427 enum {
428 	ADIS16480_SCAN_GYRO_X,
429 	ADIS16480_SCAN_GYRO_Y,
430 	ADIS16480_SCAN_GYRO_Z,
431 	ADIS16480_SCAN_ACCEL_X,
432 	ADIS16480_SCAN_ACCEL_Y,
433 	ADIS16480_SCAN_ACCEL_Z,
434 	ADIS16480_SCAN_MAGN_X,
435 	ADIS16480_SCAN_MAGN_Y,
436 	ADIS16480_SCAN_MAGN_Z,
437 	ADIS16480_SCAN_BARO,
438 	ADIS16480_SCAN_TEMP,
439 	ADIS16480_SCAN_DELTANG_X,
440 	ADIS16480_SCAN_DELTANG_Y,
441 	ADIS16480_SCAN_DELTANG_Z,
442 	ADIS16480_SCAN_DELTVEL_X,
443 	ADIS16480_SCAN_DELTVEL_Y,
444 	ADIS16480_SCAN_DELTVEL_Z,
445 };
446 
447 static const unsigned int adis16480_calibbias_regs[] = {
448 	[ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS,
449 	[ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS,
450 	[ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS,
451 	[ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS,
452 	[ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS,
453 	[ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS,
454 	[ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON,
455 	[ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON,
456 	[ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON,
457 	[ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS,
458 };
459 
460 static const unsigned int adis16480_calibscale_regs[] = {
461 	[ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE,
462 	[ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE,
463 	[ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE,
464 	[ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE,
465 	[ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE,
466 	[ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE,
467 };
468 
adis16480_set_calibbias(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int bias)469 static int adis16480_set_calibbias(struct iio_dev *indio_dev,
470 	const struct iio_chan_spec *chan, int bias)
471 {
472 	unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
473 	struct adis16480 *st = iio_priv(indio_dev);
474 
475 	switch (chan->type) {
476 	case IIO_MAGN:
477 	case IIO_PRESSURE:
478 		if (bias < -0x8000 || bias >= 0x8000)
479 			return -EINVAL;
480 		return adis_write_reg_16(&st->adis, reg, bias);
481 	case IIO_ANGL_VEL:
482 	case IIO_ACCEL:
483 		return adis_write_reg_32(&st->adis, reg, bias);
484 	default:
485 		break;
486 	}
487 
488 	return -EINVAL;
489 }
490 
adis16480_get_calibbias(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * bias)491 static int adis16480_get_calibbias(struct iio_dev *indio_dev,
492 	const struct iio_chan_spec *chan, int *bias)
493 {
494 	unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
495 	struct adis16480 *st = iio_priv(indio_dev);
496 	uint16_t val16;
497 	uint32_t val32;
498 	int ret;
499 
500 	switch (chan->type) {
501 	case IIO_MAGN:
502 	case IIO_PRESSURE:
503 		ret = adis_read_reg_16(&st->adis, reg, &val16);
504 		if (ret == 0)
505 			*bias = sign_extend32(val16, 15);
506 		break;
507 	case IIO_ANGL_VEL:
508 	case IIO_ACCEL:
509 		ret = adis_read_reg_32(&st->adis, reg, &val32);
510 		if (ret == 0)
511 			*bias = sign_extend32(val32, 31);
512 		break;
513 	default:
514 		ret = -EINVAL;
515 	}
516 
517 	if (ret)
518 		return ret;
519 
520 	return IIO_VAL_INT;
521 }
522 
adis16480_set_calibscale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int scale)523 static int adis16480_set_calibscale(struct iio_dev *indio_dev,
524 	const struct iio_chan_spec *chan, int scale)
525 {
526 	unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
527 	struct adis16480 *st = iio_priv(indio_dev);
528 
529 	if (scale < -0x8000 || scale >= 0x8000)
530 		return -EINVAL;
531 
532 	return adis_write_reg_16(&st->adis, reg, scale);
533 }
534 
adis16480_get_calibscale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * scale)535 static int adis16480_get_calibscale(struct iio_dev *indio_dev,
536 	const struct iio_chan_spec *chan, int *scale)
537 {
538 	unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
539 	struct adis16480 *st = iio_priv(indio_dev);
540 	uint16_t val16;
541 	int ret;
542 
543 	ret = adis_read_reg_16(&st->adis, reg, &val16);
544 	if (ret)
545 		return ret;
546 
547 	*scale = sign_extend32(val16, 15);
548 	return IIO_VAL_INT;
549 }
550 
551 static const unsigned int adis16480_def_filter_freqs[] = {
552 	310,
553 	55,
554 	275,
555 	63,
556 };
557 
558 static const unsigned int adis16495_def_filter_freqs[] = {
559 	300,
560 	100,
561 	300,
562 	100,
563 };
564 
565 static const unsigned int ad16480_filter_data[][2] = {
566 	[ADIS16480_SCAN_GYRO_X]		= { ADIS16480_REG_FILTER_BNK0, 0 },
567 	[ADIS16480_SCAN_GYRO_Y]		= { ADIS16480_REG_FILTER_BNK0, 3 },
568 	[ADIS16480_SCAN_GYRO_Z]		= { ADIS16480_REG_FILTER_BNK0, 6 },
569 	[ADIS16480_SCAN_ACCEL_X]	= { ADIS16480_REG_FILTER_BNK0, 9 },
570 	[ADIS16480_SCAN_ACCEL_Y]	= { ADIS16480_REG_FILTER_BNK0, 12 },
571 	[ADIS16480_SCAN_ACCEL_Z]	= { ADIS16480_REG_FILTER_BNK1, 0 },
572 	[ADIS16480_SCAN_MAGN_X]		= { ADIS16480_REG_FILTER_BNK1, 3 },
573 	[ADIS16480_SCAN_MAGN_Y]		= { ADIS16480_REG_FILTER_BNK1, 6 },
574 	[ADIS16480_SCAN_MAGN_Z]		= { ADIS16480_REG_FILTER_BNK1, 9 },
575 };
576 
adis16480_get_filter_freq(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * freq)577 static int adis16480_get_filter_freq(struct iio_dev *indio_dev,
578 	const struct iio_chan_spec *chan, int *freq)
579 {
580 	struct adis16480 *st = iio_priv(indio_dev);
581 	unsigned int enable_mask, offset, reg;
582 	uint16_t val;
583 	int ret;
584 
585 	reg = ad16480_filter_data[chan->scan_index][0];
586 	offset = ad16480_filter_data[chan->scan_index][1];
587 	enable_mask = BIT(offset + 2);
588 
589 	ret = adis_read_reg_16(&st->adis, reg, &val);
590 	if (ret)
591 		return ret;
592 
593 	if (!(val & enable_mask))
594 		*freq = 0;
595 	else
596 		*freq = st->chip_info->filter_freqs[(val >> offset) & 0x3];
597 
598 	return IIO_VAL_INT;
599 }
600 
adis16480_set_filter_freq(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int freq)601 static int adis16480_set_filter_freq(struct iio_dev *indio_dev,
602 	const struct iio_chan_spec *chan, unsigned int freq)
603 {
604 	struct adis16480 *st = iio_priv(indio_dev);
605 	unsigned int enable_mask, offset, reg;
606 	unsigned int diff, best_diff;
607 	unsigned int i, best_freq;
608 	uint16_t val;
609 	int ret;
610 
611 	reg = ad16480_filter_data[chan->scan_index][0];
612 	offset = ad16480_filter_data[chan->scan_index][1];
613 	enable_mask = BIT(offset + 2);
614 
615 	adis_dev_auto_lock(&st->adis);
616 
617 	ret = __adis_read_reg_16(&st->adis, reg, &val);
618 	if (ret)
619 		return ret;
620 
621 	if (freq == 0) {
622 		val &= ~enable_mask;
623 	} else {
624 		best_freq = 0;
625 		best_diff = st->chip_info->filter_freqs[0];
626 		for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) {
627 			if (st->chip_info->filter_freqs[i] >= freq) {
628 				diff = st->chip_info->filter_freqs[i] - freq;
629 				if (diff < best_diff) {
630 					best_diff = diff;
631 					best_freq = i;
632 				}
633 			}
634 		}
635 
636 		val &= ~(0x3 << offset);
637 		val |= best_freq << offset;
638 		val |= enable_mask;
639 	}
640 
641 	return __adis_write_reg_16(&st->adis, reg, val);
642 }
643 
adis16480_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)644 static int adis16480_read_raw(struct iio_dev *indio_dev,
645 	const struct iio_chan_spec *chan, int *val, int *val2, long info)
646 {
647 	struct adis16480 *st = iio_priv(indio_dev);
648 	unsigned int temp;
649 
650 	switch (info) {
651 	case IIO_CHAN_INFO_RAW:
652 		return adis_single_conversion(indio_dev, chan, 0, val);
653 	case IIO_CHAN_INFO_SCALE:
654 		switch (chan->type) {
655 		case IIO_ANGL_VEL:
656 			*val = st->chip_info->gyro_max_scale;
657 			*val2 = st->chip_info->gyro_max_val;
658 			return IIO_VAL_FRACTIONAL;
659 		case IIO_ACCEL:
660 			*val = st->chip_info->accel_max_scale;
661 			*val2 = st->chip_info->accel_max_val;
662 			return IIO_VAL_FRACTIONAL;
663 		case IIO_MAGN:
664 			*val = 0;
665 			*val2 = 100; /* 0.0001 gauss */
666 			return IIO_VAL_INT_PLUS_MICRO;
667 		case IIO_TEMP:
668 			/*
669 			 * +85 degrees Celsius = temp_max_scale
670 			 * +25 degrees Celsius = 0
671 			 * LSB, 25 degrees Celsius  = 60 / temp_max_scale
672 			 */
673 			*val = st->chip_info->temp_scale / 1000;
674 			*val2 = (st->chip_info->temp_scale % 1000) * 1000;
675 			return IIO_VAL_INT_PLUS_MICRO;
676 		case IIO_PRESSURE:
677 			/*
678 			 * max scale is 1310 mbar
679 			 * max raw value is 32767 shifted for 32bits
680 			 */
681 			*val = 131; /* 1310mbar = 131 kPa */
682 			*val2 = 32767 << 16;
683 			return IIO_VAL_FRACTIONAL;
684 		case IIO_DELTA_ANGL:
685 			*val = st->chip_info->deltang_max_val;
686 			*val2 = 31;
687 			return IIO_VAL_FRACTIONAL_LOG2;
688 		case IIO_DELTA_VELOCITY:
689 			*val = st->chip_info->deltvel_max_val;
690 			*val2 = 31;
691 			return IIO_VAL_FRACTIONAL_LOG2;
692 		default:
693 			return -EINVAL;
694 		}
695 	case IIO_CHAN_INFO_OFFSET:
696 		/* Only the temperature channel has a offset */
697 		temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */
698 		*val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale);
699 		return IIO_VAL_INT;
700 	case IIO_CHAN_INFO_CALIBBIAS:
701 		return adis16480_get_calibbias(indio_dev, chan, val);
702 	case IIO_CHAN_INFO_CALIBSCALE:
703 		return adis16480_get_calibscale(indio_dev, chan, val);
704 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
705 		return adis16480_get_filter_freq(indio_dev, chan, val);
706 	case IIO_CHAN_INFO_SAMP_FREQ:
707 		return adis16480_get_freq(indio_dev, val, val2);
708 	default:
709 		return -EINVAL;
710 	}
711 }
712 
adis16480_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long info)713 static int adis16480_write_raw(struct iio_dev *indio_dev,
714 	const struct iio_chan_spec *chan, int val, int val2, long info)
715 {
716 	switch (info) {
717 	case IIO_CHAN_INFO_CALIBBIAS:
718 		return adis16480_set_calibbias(indio_dev, chan, val);
719 	case IIO_CHAN_INFO_CALIBSCALE:
720 		return adis16480_set_calibscale(indio_dev, chan, val);
721 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
722 		return adis16480_set_filter_freq(indio_dev, chan, val);
723 	case IIO_CHAN_INFO_SAMP_FREQ:
724 		return adis16480_set_freq(indio_dev, val, val2);
725 
726 	default:
727 		return -EINVAL;
728 	}
729 }
730 
731 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \
732 	{ \
733 		.type = (_type), \
734 		.modified = 1, \
735 		.channel2 = (_mod), \
736 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
737 			BIT(IIO_CHAN_INFO_CALIBBIAS) | \
738 			_info_sep, \
739 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
740 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
741 		.address = (_address), \
742 		.scan_index = (_si), \
743 		.scan_type = { \
744 			.sign = 's', \
745 			.realbits = (_bits), \
746 			.storagebits = (_bits), \
747 			.endianness = IIO_BE, \
748 		}, \
749 	}
750 
751 #define ADIS16480_GYRO_CHANNEL(_mod) \
752 	ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
753 	ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \
754 	BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
755 	BIT(IIO_CHAN_INFO_CALIBSCALE), \
756 	32)
757 
758 #define ADIS16480_ACCEL_CHANNEL(_mod) \
759 	ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \
760 	ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \
761 	BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
762 	BIT(IIO_CHAN_INFO_CALIBSCALE), \
763 	32)
764 
765 #define ADIS16480_DELTANG_CHANNEL(_mod) \
766 	ADIS16480_MOD_CHANNEL(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
767 	ADIS16480_REG_ ## _mod ## _DELTAANG_OUT, ADIS16480_SCAN_DELTANG_ ## _mod, \
768 	0, 32)
769 
770 #define ADIS16480_DELTANG_CHANNEL_NO_SCAN(_mod) \
771 	ADIS16480_MOD_CHANNEL(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
772 	ADIS16480_REG_ ## _mod ## _DELTAANG_OUT, -1, 0, 32)
773 
774 #define ADIS16480_DELTVEL_CHANNEL(_mod) \
775 	ADIS16480_MOD_CHANNEL(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
776 	ADIS16480_REG_ ## _mod ## _DELTAVEL_OUT, ADIS16480_SCAN_DELTVEL_ ## _mod, \
777 	0, 32)
778 
779 #define ADIS16480_DELTVEL_CHANNEL_NO_SCAN(_mod) \
780 	ADIS16480_MOD_CHANNEL(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
781 	ADIS16480_REG_ ## _mod ## _DELTAVEL_OUT, -1, 0,	32)
782 
783 #define ADIS16480_MAGN_CHANNEL(_mod) \
784 	ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \
785 	ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \
786 	BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
787 	16)
788 
789 #define ADIS16480_PRESSURE_CHANNEL() \
790 	{ \
791 		.type = IIO_PRESSURE, \
792 		.indexed = 1, \
793 		.channel = 0, \
794 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
795 			BIT(IIO_CHAN_INFO_CALIBBIAS) | \
796 			BIT(IIO_CHAN_INFO_SCALE), \
797 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
798 		.address = ADIS16480_REG_BAROM_OUT, \
799 		.scan_index = ADIS16480_SCAN_BARO, \
800 		.scan_type = { \
801 			.sign = 's', \
802 			.realbits = 32, \
803 			.storagebits = 32, \
804 			.endianness = IIO_BE, \
805 		}, \
806 	}
807 
808 #define ADIS16480_TEMP_CHANNEL() { \
809 		.type = IIO_TEMP, \
810 		.indexed = 1, \
811 		.channel = 0, \
812 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
813 			BIT(IIO_CHAN_INFO_SCALE) | \
814 			BIT(IIO_CHAN_INFO_OFFSET), \
815 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
816 		.address = ADIS16480_REG_TEMP_OUT, \
817 		.scan_index = ADIS16480_SCAN_TEMP, \
818 		.scan_type = { \
819 			.sign = 's', \
820 			.realbits = 16, \
821 			.storagebits = 16, \
822 			.endianness = IIO_BE, \
823 		}, \
824 	}
825 
826 static const struct iio_chan_spec adis16480_channels[] = {
827 	ADIS16480_GYRO_CHANNEL(X),
828 	ADIS16480_GYRO_CHANNEL(Y),
829 	ADIS16480_GYRO_CHANNEL(Z),
830 	ADIS16480_ACCEL_CHANNEL(X),
831 	ADIS16480_ACCEL_CHANNEL(Y),
832 	ADIS16480_ACCEL_CHANNEL(Z),
833 	ADIS16480_MAGN_CHANNEL(X),
834 	ADIS16480_MAGN_CHANNEL(Y),
835 	ADIS16480_MAGN_CHANNEL(Z),
836 	ADIS16480_PRESSURE_CHANNEL(),
837 	ADIS16480_TEMP_CHANNEL(),
838 	IIO_CHAN_SOFT_TIMESTAMP(11),
839 	ADIS16480_DELTANG_CHANNEL_NO_SCAN(X),
840 	ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y),
841 	ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z),
842 	ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X),
843 	ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y),
844 	ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z),
845 };
846 
847 static const struct iio_chan_spec adis16485_channels[] = {
848 	ADIS16480_GYRO_CHANNEL(X),
849 	ADIS16480_GYRO_CHANNEL(Y),
850 	ADIS16480_GYRO_CHANNEL(Z),
851 	ADIS16480_ACCEL_CHANNEL(X),
852 	ADIS16480_ACCEL_CHANNEL(Y),
853 	ADIS16480_ACCEL_CHANNEL(Z),
854 	ADIS16480_TEMP_CHANNEL(),
855 	IIO_CHAN_SOFT_TIMESTAMP(7),
856 	ADIS16480_DELTANG_CHANNEL_NO_SCAN(X),
857 	ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y),
858 	ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z),
859 	ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X),
860 	ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y),
861 	ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z),
862 };
863 
864 static const struct iio_chan_spec adis16545_channels[] = {
865 	ADIS16480_GYRO_CHANNEL(X),
866 	ADIS16480_GYRO_CHANNEL(Y),
867 	ADIS16480_GYRO_CHANNEL(Z),
868 	ADIS16480_ACCEL_CHANNEL(X),
869 	ADIS16480_ACCEL_CHANNEL(Y),
870 	ADIS16480_ACCEL_CHANNEL(Z),
871 	ADIS16480_TEMP_CHANNEL(),
872 	ADIS16480_DELTANG_CHANNEL(X),
873 	ADIS16480_DELTANG_CHANNEL(Y),
874 	ADIS16480_DELTANG_CHANNEL(Z),
875 	ADIS16480_DELTVEL_CHANNEL(X),
876 	ADIS16480_DELTVEL_CHANNEL(Y),
877 	ADIS16480_DELTVEL_CHANNEL(Z),
878 	IIO_CHAN_SOFT_TIMESTAMP(17),
879 };
880 
881 static const struct iio_chan_spec adis16489_channels[] = {
882 	ADIS16480_GYRO_CHANNEL(X),
883 	ADIS16480_GYRO_CHANNEL(Y),
884 	ADIS16480_GYRO_CHANNEL(Z),
885 	ADIS16480_ACCEL_CHANNEL(X),
886 	ADIS16480_ACCEL_CHANNEL(Y),
887 	ADIS16480_ACCEL_CHANNEL(Z),
888 	ADIS16480_PRESSURE_CHANNEL(),
889 	ADIS16480_TEMP_CHANNEL(),
890 	IIO_CHAN_SOFT_TIMESTAMP(8),
891 	ADIS16480_DELTANG_CHANNEL_NO_SCAN(X),
892 	ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y),
893 	ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z),
894 	ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X),
895 	ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y),
896 	ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z),
897 };
898 
899 enum adis16480_variant {
900 	ADIS16375,
901 	ADIS16480,
902 	ADIS16485,
903 	ADIS16486,
904 	ADIS16487,
905 	ADIS16488,
906 	ADIS16489,
907 	ADIS16490,
908 	ADIS16495_1,
909 	ADIS16495_2,
910 	ADIS16495_3,
911 	ADIS16497_1,
912 	ADIS16497_2,
913 	ADIS16497_3,
914 	ADIS16545_1,
915 	ADIS16545_2,
916 	ADIS16545_3,
917 	ADIS16547_1,
918 	ADIS16547_2,
919 	ADIS16547_3
920 };
921 
922 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0
923 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1
924 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2
925 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3
926 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4
927 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5
928 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8
929 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9
930 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10
931 #define ADIS16480_DIAG_STAT_BARO_FAIL 11
932 
933 static const char * const adis16480_status_error_msgs[] = {
934 	[ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure",
935 	[ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure",
936 	[ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure",
937 	[ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure",
938 	[ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure",
939 	[ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure",
940 	[ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure",
941 	[ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure",
942 	[ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure",
943 	[ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure",
944 };
945 
946 static int adis16480_enable_irq(struct adis *adis, bool enable);
947 
948 #define ADIS16480_DATA(_prod_id, _timeouts, _burst_len, _burst_max_speed)	\
949 {										\
950 	.diag_stat_reg = ADIS16480_REG_DIAG_STS,				\
951 	.glob_cmd_reg = ADIS16480_REG_GLOB_CMD,					\
952 	.prod_id_reg = ADIS16480_REG_PROD_ID,					\
953 	.prod_id = (_prod_id),							\
954 	.has_paging = true,							\
955 	.read_delay = 5,							\
956 	.write_delay = 5,							\
957 	.self_test_mask = BIT(1),						\
958 	.self_test_reg = ADIS16480_REG_GLOB_CMD,				\
959 	.status_error_msgs = adis16480_status_error_msgs,			\
960 	.status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) |		\
961 		BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) |				\
962 		BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) |				\
963 		BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) |				\
964 		BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) |				\
965 		BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) |				\
966 		BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) |				\
967 		BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) |				\
968 		BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) |				\
969 		BIT(ADIS16480_DIAG_STAT_BARO_FAIL),				\
970 	.enable_irq = adis16480_enable_irq,					\
971 	.timeouts = (_timeouts),						\
972 	.burst_reg_cmd = ADIS16495_REG_BURST_CMD,				\
973 	.burst_len = (_burst_len),						\
974 	.burst_max_speed_hz = _burst_max_speed					\
975 }
976 
977 static const struct adis_timeout adis16485_timeouts = {
978 	.reset_ms = 560,
979 	.sw_reset_ms = 120,
980 	.self_test_ms = 12,
981 };
982 
983 static const struct adis_timeout adis16480_timeouts = {
984 	.reset_ms = 560,
985 	.sw_reset_ms = 560,
986 	.self_test_ms = 12,
987 };
988 
989 static const struct adis_timeout adis16495_timeouts = {
990 	.reset_ms = 170,
991 	.sw_reset_ms = 130,
992 	.self_test_ms = 40,
993 };
994 
995 static const struct adis_timeout adis16495_1_timeouts = {
996 	.reset_ms = 250,
997 	.sw_reset_ms = 210,
998 	.self_test_ms = 20,
999 };
1000 
1001 static const struct adis_timeout adis16545_timeouts = {
1002 	.reset_ms = 315,
1003 	.sw_reset_ms = 270,
1004 	.self_test_ms = 35,
1005 };
1006 
1007 static const struct adis16480_chip_info adis16480_chip_info[] = {
1008 	[ADIS16375] = {
1009 		.channels = adis16485_channels,
1010 		.num_channels = ARRAY_SIZE(adis16485_channels),
1011 		/*
1012 		 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which
1013 		 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since
1014 		 * it gives better approximation. However, in this case we
1015 		 * cannot do it since it would not fit in a 32bit variable.
1016 		 */
1017 		.gyro_max_val = 22887 << 16,
1018 		.gyro_max_scale = IIO_DEGREE_TO_RAD(300),
1019 		.accel_max_val = IIO_M_S_2_TO_G(21973 << 16),
1020 		.accel_max_scale = 18,
1021 		.temp_scale = 5650, /* 5.65 milli degree Celsius */
1022 		.deltang_max_val = IIO_DEGREE_TO_RAD(180),
1023 		.deltvel_max_val = 100,
1024 		.int_clk = 2460000,
1025 		.max_dec_rate = 2048,
1026 		.has_sleep_cnt = true,
1027 		.filter_freqs = adis16480_def_filter_freqs,
1028 		.adis_data = ADIS16480_DATA(16375, &adis16485_timeouts, 0, 0),
1029 	},
1030 	[ADIS16480] = {
1031 		.channels = adis16480_channels,
1032 		.num_channels = ARRAY_SIZE(adis16480_channels),
1033 		.gyro_max_val = 22500 << 16,
1034 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1035 		.accel_max_val = IIO_M_S_2_TO_G(12500 << 16),
1036 		.accel_max_scale = 10,
1037 		.temp_scale = 5650, /* 5.65 milli degree Celsius */
1038 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1039 		.deltvel_max_val = 200,
1040 		.int_clk = 2460000,
1041 		.max_dec_rate = 2048,
1042 		.has_sleep_cnt = true,
1043 		.filter_freqs = adis16480_def_filter_freqs,
1044 		.adis_data = ADIS16480_DATA(16480, &adis16480_timeouts, 0, 0),
1045 	},
1046 	[ADIS16485] = {
1047 		.channels = adis16485_channels,
1048 		.num_channels = ARRAY_SIZE(adis16485_channels),
1049 		.gyro_max_val = 22500 << 16,
1050 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1051 		.accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
1052 		.accel_max_scale = 5,
1053 		.temp_scale = 5650, /* 5.65 milli degree Celsius */
1054 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1055 		.deltvel_max_val = 50,
1056 		.int_clk = 2460000,
1057 		.max_dec_rate = 2048,
1058 		.has_sleep_cnt = true,
1059 		.filter_freqs = adis16480_def_filter_freqs,
1060 		.adis_data = ADIS16480_DATA(16485, &adis16485_timeouts, 0, 0),
1061 	},
1062 	[ADIS16486] = {
1063 		.channels = adis16485_channels,
1064 		.num_channels = ARRAY_SIZE(adis16485_channels),
1065 		.gyro_max_val = 22500 << 16,
1066 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1067 		.accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
1068 		.accel_max_scale = 18,
1069 		.temp_scale = 5650, /* 5.65 milli degree Celsius */
1070 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1071 		.deltvel_max_val = 200,
1072 		.int_clk = 2460000,
1073 		.max_dec_rate = 2048,
1074 		.has_sleep_cnt = true,
1075 		.filter_freqs = adis16480_def_filter_freqs,
1076 		.adis_data = ADIS16480_DATA(16486, &adis16480_timeouts, 0, 0),
1077 	},
1078 	[ADIS16487] = {
1079 		.channels = adis16485_channels,
1080 		.num_channels = ARRAY_SIZE(adis16485_channels),
1081 		.gyro_max_val = 22500 << 16,
1082 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1083 		.accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
1084 		.accel_max_scale = 5,
1085 		.temp_scale = 5650, /* 5.65 milli degree Celsius */
1086 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1087 		.deltvel_max_val = 50,
1088 		.int_clk = 2460000,
1089 		.max_dec_rate = 2048,
1090 		.has_sleep_cnt = true,
1091 		.filter_freqs = adis16480_def_filter_freqs,
1092 		.adis_data = ADIS16480_DATA(16487, &adis16485_timeouts, 0, 0),
1093 	},
1094 	[ADIS16488] = {
1095 		.channels = adis16480_channels,
1096 		.num_channels = ARRAY_SIZE(adis16480_channels),
1097 		.gyro_max_val = 22500 << 16,
1098 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1099 		.accel_max_val = IIO_M_S_2_TO_G(22500 << 16),
1100 		.accel_max_scale = 18,
1101 		.temp_scale = 5650, /* 5.65 milli degree Celsius */
1102 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1103 		.deltvel_max_val = 200,
1104 		.int_clk = 2460000,
1105 		.max_dec_rate = 2048,
1106 		.has_sleep_cnt = true,
1107 		.filter_freqs = adis16480_def_filter_freqs,
1108 		.adis_data = ADIS16480_DATA(16488, &adis16485_timeouts, 0, 0),
1109 	},
1110 	[ADIS16489] = {
1111 		.channels = adis16489_channels,
1112 		.num_channels = ARRAY_SIZE(adis16489_channels),
1113 		.gyro_max_val = 22500 << 16,
1114 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1115 		.accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
1116 		.accel_max_scale = 18,
1117 		.temp_scale = 5650, /* 5.65 milli degree Celsius */
1118 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1119 		.deltvel_max_val = 200,
1120 		.int_clk = 2460000,
1121 		.max_dec_rate = 2048,
1122 		.has_sleep_cnt = true,
1123 		.filter_freqs = adis16480_def_filter_freqs,
1124 		.adis_data = ADIS16480_DATA(16489, &adis16480_timeouts, 0, 0),
1125 	},
1126 	[ADIS16490] = {
1127 		.channels = adis16485_channels,
1128 		.num_channels = ARRAY_SIZE(adis16485_channels),
1129 		.gyro_max_val = 20000 << 16,
1130 		.gyro_max_scale = IIO_DEGREE_TO_RAD(100),
1131 		.accel_max_val = IIO_M_S_2_TO_G(16000 << 16),
1132 		.accel_max_scale = 8,
1133 		.temp_scale = 14285, /* 14.285 milli degree Celsius */
1134 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1135 		.deltvel_max_val = 200,
1136 		.int_clk = 4250000,
1137 		.max_dec_rate = 4250,
1138 		.filter_freqs = adis16495_def_filter_freqs,
1139 		.has_pps_clk_mode = true,
1140 		.adis_data = ADIS16480_DATA(16490, &adis16495_timeouts, 0, 0),
1141 	},
1142 	[ADIS16495_1] = {
1143 		.channels = adis16485_channels,
1144 		.num_channels = ARRAY_SIZE(adis16485_channels),
1145 		.gyro_max_val = 20000 << 16,
1146 		.gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1147 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1148 		.accel_max_scale = 8,
1149 		.temp_scale = 12500, /* 12.5 milli degree Celsius */
1150 		.deltang_max_val = IIO_DEGREE_TO_RAD(360),
1151 		.deltvel_max_val = 100,
1152 		.int_clk = 4250000,
1153 		.max_dec_rate = 4250,
1154 		.filter_freqs = adis16495_def_filter_freqs,
1155 		.has_pps_clk_mode = true,
1156 		/* 20 elements of 16bits */
1157 		.adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1158 					    ADIS16495_BURST_MAX_DATA * 2,
1159 					    6000000),
1160 	},
1161 	[ADIS16495_2] = {
1162 		.channels = adis16485_channels,
1163 		.num_channels = ARRAY_SIZE(adis16485_channels),
1164 		.gyro_max_val = 18000 << 16,
1165 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1166 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1167 		.accel_max_scale = 8,
1168 		.temp_scale = 12500, /* 12.5 milli degree Celsius */
1169 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1170 		.deltvel_max_val = 100,
1171 		.int_clk = 4250000,
1172 		.max_dec_rate = 4250,
1173 		.filter_freqs = adis16495_def_filter_freqs,
1174 		.has_pps_clk_mode = true,
1175 		/* 20 elements of 16bits */
1176 		.adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1177 					    ADIS16495_BURST_MAX_DATA * 2,
1178 					    6000000),
1179 	},
1180 	[ADIS16495_3] = {
1181 		.channels = adis16485_channels,
1182 		.num_channels = ARRAY_SIZE(adis16485_channels),
1183 		.gyro_max_val = 20000 << 16,
1184 		.gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1185 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1186 		.accel_max_scale = 8,
1187 		.temp_scale = 12500, /* 12.5 milli degree Celsius */
1188 		.deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1189 		.deltvel_max_val = 100,
1190 		.int_clk = 4250000,
1191 		.max_dec_rate = 4250,
1192 		.filter_freqs = adis16495_def_filter_freqs,
1193 		.has_pps_clk_mode = true,
1194 		/* 20 elements of 16bits */
1195 		.adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1196 					    ADIS16495_BURST_MAX_DATA * 2,
1197 					    6000000),
1198 	},
1199 	[ADIS16497_1] = {
1200 		.channels = adis16485_channels,
1201 		.num_channels = ARRAY_SIZE(adis16485_channels),
1202 		.gyro_max_val = 20000 << 16,
1203 		.gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1204 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1205 		.accel_max_scale = 40,
1206 		.temp_scale = 12500, /* 12.5 milli degree Celsius */
1207 		.deltang_max_val = IIO_DEGREE_TO_RAD(360),
1208 		.deltvel_max_val = 400,
1209 		.int_clk = 4250000,
1210 		.max_dec_rate = 4250,
1211 		.filter_freqs = adis16495_def_filter_freqs,
1212 		.has_pps_clk_mode = true,
1213 		/* 20 elements of 16bits */
1214 		.adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1215 					    ADIS16495_BURST_MAX_DATA * 2,
1216 					    6000000),
1217 	},
1218 	[ADIS16497_2] = {
1219 		.channels = adis16485_channels,
1220 		.num_channels = ARRAY_SIZE(adis16485_channels),
1221 		.gyro_max_val = 18000 << 16,
1222 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1223 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1224 		.accel_max_scale = 40,
1225 		.temp_scale = 12500, /* 12.5 milli degree Celsius */
1226 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1227 		.deltvel_max_val = 400,
1228 		.int_clk = 4250000,
1229 		.max_dec_rate = 4250,
1230 		.filter_freqs = adis16495_def_filter_freqs,
1231 		.has_pps_clk_mode = true,
1232 		/* 20 elements of 16bits */
1233 		.adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1234 					    ADIS16495_BURST_MAX_DATA * 2,
1235 					    6000000),
1236 	},
1237 	[ADIS16497_3] = {
1238 		.channels = adis16485_channels,
1239 		.num_channels = ARRAY_SIZE(adis16485_channels),
1240 		.gyro_max_val = 20000 << 16,
1241 		.gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1242 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1243 		.accel_max_scale = 40,
1244 		.temp_scale = 12500, /* 12.5 milli degree Celsius */
1245 		.deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1246 		.deltvel_max_val = 400,
1247 		.int_clk = 4250000,
1248 		.max_dec_rate = 4250,
1249 		.filter_freqs = adis16495_def_filter_freqs,
1250 		.has_pps_clk_mode = true,
1251 		/* 20 elements of 16bits */
1252 		.adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1253 					    ADIS16495_BURST_MAX_DATA * 2,
1254 					    6000000),
1255 	},
1256 	[ADIS16545_1] = {
1257 		.channels = adis16545_channels,
1258 		.num_channels = ARRAY_SIZE(adis16545_channels),
1259 		.gyro_max_val = 20000 << 16,
1260 		.gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1261 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1262 		.accel_max_scale = 8,
1263 		.temp_scale = 7000, /* 7 milli degree Celsius */
1264 		.deltang_max_val = IIO_DEGREE_TO_RAD(360),
1265 		.deltvel_max_val = 100,
1266 		.int_clk = 4250000,
1267 		.max_dec_rate = 4250,
1268 		.filter_freqs = adis16495_def_filter_freqs,
1269 		.has_pps_clk_mode = true,
1270 		.has_burst_delta_data = true,
1271 		/* 20 elements of 16bits */
1272 		.adis_data = ADIS16480_DATA(16545, &adis16545_timeouts,
1273 					    ADIS16495_BURST_MAX_DATA * 2,
1274 					    6500000),
1275 	},
1276 	[ADIS16545_2] = {
1277 		.channels = adis16545_channels,
1278 		.num_channels = ARRAY_SIZE(adis16545_channels),
1279 		.gyro_max_val = 18000 << 16,
1280 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1281 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1282 		.accel_max_scale = 8,
1283 		.temp_scale = 7000, /* 7 milli degree Celsius */
1284 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1285 		.deltvel_max_val = 100,
1286 		.int_clk = 4250000,
1287 		.max_dec_rate = 4250,
1288 		.filter_freqs = adis16495_def_filter_freqs,
1289 		.has_pps_clk_mode = true,
1290 		.has_burst_delta_data = true,
1291 		/* 20 elements of 16bits */
1292 		.adis_data = ADIS16480_DATA(16545, &adis16545_timeouts,
1293 					    ADIS16495_BURST_MAX_DATA * 2,
1294 					    6500000),
1295 	},
1296 	[ADIS16545_3] = {
1297 		.channels = adis16545_channels,
1298 		.num_channels = ARRAY_SIZE(adis16545_channels),
1299 		.gyro_max_val = 20000 << 16,
1300 		.gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1301 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1302 		.accel_max_scale = 8,
1303 		.temp_scale = 7000, /* 7 milli degree Celsius */
1304 		.deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1305 		.deltvel_max_val = 100,
1306 		.int_clk = 4250000,
1307 		.max_dec_rate = 4250,
1308 		.filter_freqs = adis16495_def_filter_freqs,
1309 		.has_pps_clk_mode = true,
1310 		.has_burst_delta_data = true,
1311 		/* 20 elements of 16bits */
1312 		.adis_data = ADIS16480_DATA(16545, &adis16545_timeouts,
1313 					    ADIS16495_BURST_MAX_DATA * 2,
1314 					    6500000),
1315 	},
1316 	[ADIS16547_1] = {
1317 		.channels = adis16545_channels,
1318 		.num_channels = ARRAY_SIZE(adis16545_channels),
1319 		.gyro_max_val = 20000 << 16,
1320 		.gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1321 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1322 		.accel_max_scale = 40,
1323 		.temp_scale = 7000, /* 7 milli degree Celsius */
1324 		.deltang_max_val = IIO_DEGREE_TO_RAD(360),
1325 		.deltvel_max_val = 400,
1326 		.int_clk = 4250000,
1327 		.max_dec_rate = 4250,
1328 		.filter_freqs = adis16495_def_filter_freqs,
1329 		.has_pps_clk_mode = true,
1330 		.has_burst_delta_data = true,
1331 		/* 20 elements of 16bits */
1332 		.adis_data = ADIS16480_DATA(16547, &adis16545_timeouts,
1333 					    ADIS16495_BURST_MAX_DATA * 2,
1334 					    6500000),
1335 	},
1336 	[ADIS16547_2] = {
1337 		.channels = adis16545_channels,
1338 		.num_channels = ARRAY_SIZE(adis16545_channels),
1339 		.gyro_max_val = 18000 << 16,
1340 		.gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1341 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1342 		.accel_max_scale = 40,
1343 		.temp_scale = 7000, /* 7 milli degree Celsius */
1344 		.deltang_max_val = IIO_DEGREE_TO_RAD(720),
1345 		.deltvel_max_val = 400,
1346 		.int_clk = 4250000,
1347 		.max_dec_rate = 4250,
1348 		.filter_freqs = adis16495_def_filter_freqs,
1349 		.has_pps_clk_mode = true,
1350 		.has_burst_delta_data = true,
1351 		/* 20 elements of 16bits */
1352 		.adis_data = ADIS16480_DATA(16547, &adis16545_timeouts,
1353 					    ADIS16495_BURST_MAX_DATA * 2,
1354 					    6500000),
1355 	},
1356 	[ADIS16547_3] = {
1357 		.channels = adis16545_channels,
1358 		.num_channels = ARRAY_SIZE(adis16545_channels),
1359 		.gyro_max_val = 20000 << 16,
1360 		.gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1361 		.accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1362 		.accel_max_scale = 40,
1363 		.temp_scale = 7000, /* 7 milli degree Celsius */
1364 		.deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1365 		.deltvel_max_val = 400,
1366 		.int_clk = 4250000,
1367 		.max_dec_rate = 4250,
1368 		.filter_freqs = adis16495_def_filter_freqs,
1369 		.has_pps_clk_mode = true,
1370 		.has_burst_delta_data = true,
1371 		/* 20 elements of 16bits */
1372 		.adis_data = ADIS16480_DATA(16547, &adis16545_timeouts,
1373 					    ADIS16495_BURST_MAX_DATA * 2,
1374 					    6500000),
1375 	},
1376 };
1377 
adis16480_validate_crc(const u16 * buf,const u8 n_elem,const u32 crc)1378 static bool adis16480_validate_crc(const u16 *buf, const u8 n_elem, const u32 crc)
1379 {
1380 	u32 crc_calc;
1381 	u16 crc_buf[15];
1382 	int j;
1383 
1384 	for (j = 0; j < n_elem; j++)
1385 		crc_buf[j] = swab16(buf[j]);
1386 
1387 	crc_calc = crc32(~0, crc_buf, n_elem * 2);
1388 	crc_calc ^= ~0;
1389 
1390 	return (crc == crc_calc);
1391 }
1392 
adis16480_trigger_handler(int irq,void * p)1393 static irqreturn_t adis16480_trigger_handler(int irq, void *p)
1394 {
1395 	struct iio_poll_func *pf = p;
1396 	struct iio_dev *indio_dev = pf->indio_dev;
1397 	struct adis16480 *st = iio_priv(indio_dev);
1398 	struct adis *adis = &st->adis;
1399 	struct device *dev = &adis->spi->dev;
1400 	int ret, bit, offset, i = 0, buff_offset = 0;
1401 	__be16 *buffer;
1402 	u32 crc;
1403 	bool valid;
1404 
1405 	adis_dev_auto_scoped_lock(adis) {
1406 		if (adis->current_page != 0) {
1407 			adis->tx[0] = ADIS_WRITE_REG(ADIS_REG_PAGE_ID);
1408 			adis->tx[1] = 0;
1409 			ret = spi_write(adis->spi, adis->tx, 2);
1410 			if (ret) {
1411 				dev_err(dev, "Failed to change device page: %d\n", ret);
1412 				goto irq_done;
1413 			}
1414 
1415 			adis->current_page = 0;
1416 		}
1417 
1418 		ret = spi_sync(adis->spi, &adis->msg);
1419 		if (ret) {
1420 			dev_err(dev, "Failed to read data: %d\n", ret);
1421 			goto irq_done;
1422 		}
1423 	}
1424 
1425 	/*
1426 	 * After making the burst request, the response can have one or two
1427 	 * 16-bit responses containing the BURST_ID depending on the sclk. If
1428 	 * clk > 3.6MHz, then we will have two BURST_ID in a row. If clk < 3MHZ,
1429 	 * we have only one. To manage that variation, we use the transition from the
1430 	 * BURST_ID to the SYS_E_FLAG register, which will not be equal to 0xA5A5/0xC3C3.
1431 	 * If we not find this variation in the first 4 segments, then the data should
1432 	 * not be valid.
1433 	 */
1434 	buffer = adis->buffer;
1435 	for (offset = 0; offset < 4; offset++) {
1436 		u16 curr = be16_to_cpu(buffer[offset]);
1437 		u16 next = be16_to_cpu(buffer[offset + 1]);
1438 
1439 		if (curr == st->burst_id && next != st->burst_id) {
1440 			offset++;
1441 			break;
1442 		}
1443 	}
1444 
1445 	if (offset == 4) {
1446 		dev_err(dev, "Invalid burst data\n");
1447 		goto irq_done;
1448 	}
1449 
1450 	crc = be16_to_cpu(buffer[offset + 16]) << 16 | be16_to_cpu(buffer[offset + 15]);
1451 	valid = adis16480_validate_crc((u16 *)&buffer[offset], 15, crc);
1452 	if (!valid) {
1453 		dev_err(dev, "Invalid crc\n");
1454 		goto irq_done;
1455 	}
1456 
1457 	iio_for_each_active_channel(indio_dev, bit) {
1458 		/*
1459 		 * When burst mode is used, temperature is the first data
1460 		 * channel in the sequence, but the temperature scan index
1461 		 * is 10.
1462 		 */
1463 		switch (bit) {
1464 		case ADIS16480_SCAN_TEMP:
1465 			st->data[i++] = buffer[offset + 1];
1466 			/*
1467 			 * The temperature channel has 16-bit storage size.
1468 			 * We need to perform the padding to have the buffer
1469 			 * elements naturally aligned in case there are any
1470 			 * 32-bit storage size channels enabled which are added
1471 			 * in the buffer after the temprature data. In case
1472 			 * there is no data being added after the temperature
1473 			 * data, the padding is harmless.
1474 			 */
1475 			st->data[i++] = 0;
1476 			break;
1477 		case ADIS16480_SCAN_DELTANG_X ... ADIS16480_SCAN_DELTVEL_Z:
1478 			buff_offset = ADIS16480_SCAN_DELTANG_X;
1479 			fallthrough;
1480 		case ADIS16480_SCAN_GYRO_X ... ADIS16480_SCAN_ACCEL_Z:
1481 			/* The lower register data is sequenced first */
1482 			st->data[i++] = buffer[2 * (bit - buff_offset) + offset + 3];
1483 			st->data[i++] = buffer[2 * (bit - buff_offset) + offset + 2];
1484 			break;
1485 		}
1486 	}
1487 
1488 	iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
1489 irq_done:
1490 	iio_trigger_notify_done(indio_dev->trig);
1491 
1492 	return IRQ_HANDLED;
1493 }
1494 
1495 static const unsigned long adis16545_channel_masks[] = {
1496 	ADIS16545_BURST_DATA_SEL_0_CHN_MASK | BIT(ADIS16480_SCAN_TEMP) | BIT(17),
1497 	ADIS16545_BURST_DATA_SEL_1_CHN_MASK | BIT(ADIS16480_SCAN_TEMP) | BIT(17),
1498 	0,
1499 };
1500 
adis16480_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1501 static int adis16480_update_scan_mode(struct iio_dev *indio_dev,
1502 				      const unsigned long *scan_mask)
1503 {
1504 	u16 en;
1505 	int ret;
1506 	struct adis16480 *st = iio_priv(indio_dev);
1507 
1508 	if (st->chip_info->has_burst_delta_data) {
1509 		if (*scan_mask & ADIS16545_BURST_DATA_SEL_0_CHN_MASK) {
1510 			en = FIELD_PREP(ADIS16545_BURST_DATA_SEL_MASK, 0);
1511 			st->burst_id = ADIS16495_GYRO_ACCEL_BURST_ID;
1512 		} else {
1513 			en = FIELD_PREP(ADIS16545_BURST_DATA_SEL_MASK, 1);
1514 			st->burst_id = ADIS16545_DELTA_ANG_VEL_BURST_ID;
1515 		}
1516 
1517 		ret = __adis_update_bits(&st->adis, ADIS16480_REG_CONFIG,
1518 					 ADIS16545_BURST_DATA_SEL_MASK, en);
1519 		if (ret)
1520 			return ret;
1521 	}
1522 
1523 	return adis_update_scan_mode(indio_dev, scan_mask);
1524 }
1525 
1526 static const struct iio_info adis16480_info = {
1527 	.read_raw = &adis16480_read_raw,
1528 	.write_raw = &adis16480_write_raw,
1529 	.update_scan_mode = &adis16480_update_scan_mode,
1530 	.debugfs_reg_access = adis_debugfs_reg_access,
1531 };
1532 
adis16480_stop_device(struct iio_dev * indio_dev)1533 static int adis16480_stop_device(struct iio_dev *indio_dev)
1534 {
1535 	struct adis16480 *st = iio_priv(indio_dev);
1536 	struct device *dev = &st->adis.spi->dev;
1537 	int ret;
1538 
1539 	ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9));
1540 	if (ret)
1541 		dev_err(dev, "Could not power down device: %d\n", ret);
1542 
1543 	return ret;
1544 }
1545 
adis16480_enable_irq(struct adis * adis,bool enable)1546 static int adis16480_enable_irq(struct adis *adis, bool enable)
1547 {
1548 	uint16_t val;
1549 	int ret;
1550 
1551 	ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1552 	if (ret)
1553 		return ret;
1554 
1555 	val &= ~ADIS16480_DRDY_EN_MSK;
1556 	val |= ADIS16480_DRDY_EN(enable);
1557 
1558 	return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val);
1559 }
1560 
adis16480_config_irq_pin(struct adis16480 * st)1561 static int adis16480_config_irq_pin(struct adis16480 *st)
1562 {
1563 	struct device *dev = &st->adis.spi->dev;
1564 	struct fwnode_handle *fwnode = dev_fwnode(dev);
1565 	enum adis16480_int_pin pin;
1566 	unsigned int irq_type;
1567 	uint16_t val;
1568 	int i, irq = 0;
1569 
1570 	/* Disable data ready since the default after reset is on */
1571 	val = ADIS16480_DRDY_EN(0);
1572 
1573 	/*
1574 	 * Get the interrupt from the devicetre by reading the interrupt-names
1575 	 * property. If it is not specified, use DIO1 pin as default.
1576 	 * According to the datasheet, the factory default assigns DIO2 as data
1577 	 * ready signal. However, in the previous versions of the driver, DIO1
1578 	 * pin was used. So, we should leave it as is since some devices might
1579 	 * be expecting the interrupt on the wrong physical pin.
1580 	 */
1581 	pin = ADIS16480_PIN_DIO1;
1582 	for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1583 		irq = fwnode_irq_get_byname(fwnode, adis16480_int_pin_names[i]);
1584 		if (irq > 0) {
1585 			pin = i;
1586 			break;
1587 		}
1588 	}
1589 
1590 	val |= ADIS16480_DRDY_SEL(pin);
1591 
1592 	/*
1593 	 * Get the interrupt line behaviour. The data ready polarity can be
1594 	 * configured as positive or negative, corresponding to
1595 	 * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively.
1596 	 */
1597 	irq_type = irq_get_trigger_type(st->adis.spi->irq);
1598 	if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */
1599 		val |= ADIS16480_DRDY_POL(1);
1600 	} else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
1601 		val |= ADIS16480_DRDY_POL(0);
1602 	} else {
1603 		dev_err(dev, "Invalid interrupt type 0x%x specified\n", irq_type);
1604 		return -EINVAL;
1605 	}
1606 	/* Write the data ready configuration to the FNCTIO_CTRL register */
1607 	return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1608 }
1609 
adis16480_fw_get_ext_clk_pin(struct adis16480 * st)1610 static int adis16480_fw_get_ext_clk_pin(struct adis16480 *st)
1611 {
1612 	struct device *dev = &st->adis.spi->dev;
1613 	const char *ext_clk_pin;
1614 	enum adis16480_int_pin pin;
1615 	int i;
1616 
1617 	pin = ADIS16480_PIN_DIO2;
1618 	if (device_property_read_string(dev, "adi,ext-clk-pin", &ext_clk_pin))
1619 		goto clk_input_not_found;
1620 
1621 	for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1622 		if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0)
1623 			return i;
1624 	}
1625 
1626 clk_input_not_found:
1627 	dev_info(dev, "clk input line not specified, using DIO2\n");
1628 	return pin;
1629 }
1630 
adis16480_ext_clk_config(struct adis16480 * st,bool enable)1631 static int adis16480_ext_clk_config(struct adis16480 *st, bool enable)
1632 {
1633 	struct device *dev = &st->adis.spi->dev;
1634 	unsigned int mode, mask;
1635 	enum adis16480_int_pin pin;
1636 	uint16_t val;
1637 	int ret;
1638 
1639 	ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1640 	if (ret)
1641 		return ret;
1642 
1643 	pin = adis16480_fw_get_ext_clk_pin(st);
1644 	/*
1645 	 * Each DIOx pin supports only one function at a time. When a single pin
1646 	 * has two assignments, the enable bit for a lower priority function
1647 	 * automatically resets to zero (disabling the lower priority function).
1648 	 */
1649 	if (pin == ADIS16480_DRDY_SEL(val))
1650 		dev_warn(dev, "DIO%x pin supports only one function at a time\n", pin + 1);
1651 
1652 	mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin);
1653 	mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK;
1654 	/* Only ADIS1649x devices support pps ext clock mode */
1655 	if (st->chip_info->has_pps_clk_mode) {
1656 		mode |= ADIS16480_SYNC_MODE(st->clk_mode);
1657 		mask |= ADIS16480_SYNC_MODE_MSK;
1658 	}
1659 
1660 	val &= ~mask;
1661 	val |= mode;
1662 
1663 	ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1664 	if (ret)
1665 		return ret;
1666 
1667 	return clk_prepare_enable(st->ext_clk);
1668 }
1669 
adis16480_get_ext_clocks(struct adis16480 * st)1670 static int adis16480_get_ext_clocks(struct adis16480 *st)
1671 {
1672 	struct device *dev = &st->adis.spi->dev;
1673 
1674 	st->ext_clk = devm_clk_get_optional(dev, "sync");
1675 	if (IS_ERR(st->ext_clk))
1676 		return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n");
1677 	if (st->ext_clk) {
1678 		st->clk_mode = ADIS16480_CLK_SYNC;
1679 		return 0;
1680 	}
1681 
1682 	if (st->chip_info->has_pps_clk_mode) {
1683 		st->ext_clk = devm_clk_get_optional(dev, "pps");
1684 		if (IS_ERR(st->ext_clk))
1685 			return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n");
1686 		if (st->ext_clk) {
1687 			st->clk_mode = ADIS16480_CLK_PPS;
1688 			return 0;
1689 		}
1690 	}
1691 
1692 	st->clk_mode = ADIS16480_CLK_INT;
1693 	return 0;
1694 }
1695 
adis16480_stop(void * data)1696 static void adis16480_stop(void *data)
1697 {
1698 	adis16480_stop_device(data);
1699 }
1700 
adis16480_clk_disable(void * data)1701 static void adis16480_clk_disable(void *data)
1702 {
1703 	clk_disable_unprepare(data);
1704 }
1705 
adis16480_probe(struct spi_device * spi)1706 static int adis16480_probe(struct spi_device *spi)
1707 {
1708 	const struct spi_device_id *id = spi_get_device_id(spi);
1709 	const struct adis_data *adis16480_data;
1710 	irq_handler_t trigger_handler = NULL;
1711 	struct device *dev = &spi->dev;
1712 	struct iio_dev *indio_dev;
1713 	struct adis16480 *st;
1714 	int ret;
1715 
1716 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1717 	if (indio_dev == NULL)
1718 		return -ENOMEM;
1719 
1720 	st = iio_priv(indio_dev);
1721 
1722 	st->chip_info = &adis16480_chip_info[id->driver_data];
1723 	indio_dev->name = spi_get_device_id(spi)->name;
1724 	indio_dev->channels = st->chip_info->channels;
1725 	indio_dev->num_channels = st->chip_info->num_channels;
1726 	if (st->chip_info->has_burst_delta_data)
1727 		indio_dev->available_scan_masks = adis16545_channel_masks;
1728 	indio_dev->info = &adis16480_info;
1729 	indio_dev->modes = INDIO_DIRECT_MODE;
1730 
1731 	adis16480_data = &st->chip_info->adis_data;
1732 
1733 	ret = adis_init(&st->adis, indio_dev, spi, adis16480_data);
1734 	if (ret)
1735 		return ret;
1736 
1737 	ret = __adis_initial_startup(&st->adis);
1738 	if (ret)
1739 		return ret;
1740 
1741 	/*
1742 	 * By default, use burst id for gyroscope and accelerometer data.
1743 	 * This is the only option for devices which do not offer delta angle
1744 	 * and delta velocity burst readings.
1745 	 */
1746 	st->burst_id = ADIS16495_GYRO_ACCEL_BURST_ID;
1747 
1748 	if (st->chip_info->has_sleep_cnt) {
1749 		ret = devm_add_action_or_reset(dev, adis16480_stop, indio_dev);
1750 		if (ret)
1751 			return ret;
1752 	}
1753 
1754 	ret = adis16480_config_irq_pin(st);
1755 	if (ret)
1756 		return ret;
1757 
1758 	ret = adis16480_get_ext_clocks(st);
1759 	if (ret)
1760 		return ret;
1761 
1762 	if (st->ext_clk) {
1763 		ret = adis16480_ext_clk_config(st, true);
1764 		if (ret)
1765 			return ret;
1766 
1767 		ret = devm_add_action_or_reset(dev, adis16480_clk_disable, st->ext_clk);
1768 		if (ret)
1769 			return ret;
1770 
1771 		st->clk_freq = clk_get_rate(st->ext_clk);
1772 		st->clk_freq *= 1000; /* micro */
1773 		if (st->clk_mode == ADIS16480_CLK_PPS) {
1774 			u16 sync_scale;
1775 
1776 			/*
1777 			 * In PPS mode, the IMU sample rate is the clk_freq * sync_scale. Hence,
1778 			 * default the IMU sample rate to the highest multiple of the input clock
1779 			 * lower than the IMU max sample rate. The internal sample rate is the
1780 			 * max...
1781 			 */
1782 			sync_scale = st->chip_info->int_clk / st->clk_freq;
1783 			ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale);
1784 			if (ret)
1785 				return ret;
1786 		}
1787 	} else {
1788 		st->clk_freq = st->chip_info->int_clk;
1789 	}
1790 
1791 	/* Only use our trigger handler if burst mode is supported */
1792 	if (adis16480_data->burst_len)
1793 		trigger_handler = adis16480_trigger_handler;
1794 
1795 	ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
1796 						 trigger_handler);
1797 	if (ret)
1798 		return ret;
1799 
1800 	ret = devm_iio_device_register(dev, indio_dev);
1801 	if (ret)
1802 		return ret;
1803 
1804 	adis16480_debugfs_init(indio_dev);
1805 
1806 	return 0;
1807 }
1808 
1809 static const struct spi_device_id adis16480_ids[] = {
1810 	{ "adis16375", ADIS16375 },
1811 	{ "adis16480", ADIS16480 },
1812 	{ "adis16485", ADIS16485 },
1813 	{ "adis16486", ADIS16486 },
1814 	{ "adis16487", ADIS16487 },
1815 	{ "adis16488", ADIS16488 },
1816 	{ "adis16489", ADIS16489 },
1817 	{ "adis16490", ADIS16490 },
1818 	{ "adis16495-1", ADIS16495_1 },
1819 	{ "adis16495-2", ADIS16495_2 },
1820 	{ "adis16495-3", ADIS16495_3 },
1821 	{ "adis16497-1", ADIS16497_1 },
1822 	{ "adis16497-2", ADIS16497_2 },
1823 	{ "adis16497-3", ADIS16497_3 },
1824 	{ "adis16545-1", ADIS16545_1 },
1825 	{ "adis16545-2", ADIS16545_2 },
1826 	{ "adis16545-3", ADIS16545_3 },
1827 	{ "adis16547-1", ADIS16547_1 },
1828 	{ "adis16547-2", ADIS16547_2 },
1829 	{ "adis16547-3", ADIS16547_3 },
1830 	{ }
1831 };
1832 MODULE_DEVICE_TABLE(spi, adis16480_ids);
1833 
1834 static const struct of_device_id adis16480_of_match[] = {
1835 	{ .compatible = "adi,adis16375" },
1836 	{ .compatible = "adi,adis16480" },
1837 	{ .compatible = "adi,adis16485" },
1838 	{ .compatible = "adi,adis16486" },
1839 	{ .compatible = "adi,adis16487" },
1840 	{ .compatible = "adi,adis16488" },
1841 	{ .compatible = "adi,adis16489" },
1842 	{ .compatible = "adi,adis16490" },
1843 	{ .compatible = "adi,adis16495-1" },
1844 	{ .compatible = "adi,adis16495-2" },
1845 	{ .compatible = "adi,adis16495-3" },
1846 	{ .compatible = "adi,adis16497-1" },
1847 	{ .compatible = "adi,adis16497-2" },
1848 	{ .compatible = "adi,adis16497-3" },
1849 	{ .compatible = "adi,adis16545-1" },
1850 	{ .compatible = "adi,adis16545-2" },
1851 	{ .compatible = "adi,adis16545-3" },
1852 	{ .compatible = "adi,adis16547-1" },
1853 	{ .compatible = "adi,adis16547-2" },
1854 	{ .compatible = "adi,adis16547-3" },
1855 	{ },
1856 };
1857 MODULE_DEVICE_TABLE(of, adis16480_of_match);
1858 
1859 static struct spi_driver adis16480_driver = {
1860 	.driver = {
1861 		.name = "adis16480",
1862 		.of_match_table = adis16480_of_match,
1863 	},
1864 	.id_table = adis16480_ids,
1865 	.probe = adis16480_probe,
1866 };
1867 module_spi_driver(adis16480_driver);
1868 
1869 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1870 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver");
1871 MODULE_LICENSE("GPL v2");
1872 MODULE_IMPORT_NS("IIO_ADISLIB");
1873