Lines Matching defs:bits
339 * clear all the bits from "clr" in "dst"
524 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
525 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
587 int tcc_offset_bits; /* TCC Offset bits in MSR_IA32_TEMPERATURE_TARGET */
8044 int bits = platform->tcc_offset_bits;
8047 if (bits && !get_msr(base_cpu, MSR_PLATFORM_INFO, &enabled))
8050 if (bits && enabled) {
8051 tcc_offset = (msr >> 24) & GENMASK(bits - 1, 0);
8230 * Decode the bits according to the Nehalem documentation
10960 * 1,2,4..6,8-10 and set bits in cpu_subset
11078 * multiple invocations simply clear more bits in enabled mask