Lines Matching +full:0 +full:x2a

4         "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0xc1",
7 …echnology) assists. the event also counts for Machine Ordering count. Available PDIST counters: 0",
9 "UMask": "0x4",
14 "Counter": "0,1,2,3,4,5,6,7",
15 "EventCode": "0xc1",
17 "PublicDescription": "ASSISTS.PAGE_FAULT Available PDIST counters: 0",
19 "UMask": "0x8",
24 "Counter": "0,1,2,3,4,5,6,7",
26 "EventCode": "0xe4",
29 "UMask": "0x1",
34 "Counter": "0,1,2,3,4,5,6,7",
35 "EventCode": "0xB7",
37 "MSRIndex": "0x1a6,0x1a7",
38 "MSRValue": "0x800000010000",
39 …which modify a full 64 byte cacheline that have any type of response. Available PDIST counters: 0",
41 "UMask": "0x1",
46 "Counter": "0,1,2,3,4,5,6,7",
47 "EventCode": "0xB7",
49 "MSRIndex": "0x1a6,0x1a7",
50 "MSRValue": "0x400000010000",
51 …dify only part of a 64 byte cacheline that have any type of response. Available PDIST counters: 0",
53 "UMask": "0x1",
58 "Counter": "0,1,2,3,4,5,6,7",
59 "EventCode": "0xB7",
61 "MSRIndex": "0x1a6,0x1a7",
62 "MSRValue": "0x10800",
63 …escription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
65 "UMask": "0x1",
70 "Counter": "0,1,2,3",
71 "EventCode": "0x2A,0x2B",
73 "MSRIndex": "0x1a6,0x1a7",
74 "MSRValue": "0x10800",
75 …escription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
77 "UMask": "0x1",
82 "Counter": "0,1,2,3",
84 "EventCode": "0x2d",
86 …tches, loads or stores initiated by the Core that miss the L2 cache). Available PDIST counters: 0",
88 "UMask": "0x1",